| author | Suman Anna <s-anna@ti.com> | |
| Tue, 25 May 2021 14:53:06 +0000 (09:53 -0500) | ||
| committer | Suman Anna <s-anna@ti.com> | |
| Tue, 25 May 2021 23:50:34 +0000 (18:50 -0500) | ||
| commit | c2ab821c54796edc01321193c94cb5c7fd8c6ae4 | |
| tree | 67672523423ebde057607808b54004d2ef370b76 | tree | snapshot (tar.xz tar.gz zip) |
| parent | 6e85299f6020ced37602ec8638fb3649199961bb | commit | diff |
dt-bindings: irqchip: Update pruss-intc binding for K3 AM64x SoCs
The K3 AM64x SoCs also have a ICSSG IP that is similar to existing K3
AM65x and J721E SoCs. The ICSSG interrupt controller is identical to
that of the INTC on J721E SoCs, and supports 20 host interrupts and
160 input events from various SoC interrupt sources. All the 8 output
host interrupts are routed to multiple entities though. Update the
PRUSS interrupt controller binding with this information, though the
same K3 compatible shall be used for the ICSSG INTC on AM64x SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
The K3 AM64x SoCs also have a ICSSG IP that is similar to existing K3
AM65x and J721E SoCs. The ICSSG interrupt controller is identical to
that of the INTC on J721E SoCs, and supports 20 host interrupts and
160 input events from various SoC interrupt sources. All the 8 output
host interrupts are routed to multiple entities though. Update the
PRUSS interrupt controller binding with this information, though the
same K3 compatible shall be used for the ICSSG INTC on AM64x SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
| Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml | diff | blob | history |