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raw | patch | inline | side by side (parent: 3011e60)
| author | Suman Anna <s-anna@ti.com> | |
| Mon, 18 Feb 2019 19:44:39 +0000 (13:44 -0600) | ||
| committer | Suman Anna <s-anna@ti.com> | |
| Sun, 24 Feb 2019 01:20:50 +0000 (19:20 -0600) |
Add the DT nodes for the PRU-ICSS0 and PRU-ICSS1 processor subsystems
that are present on the 66AK2G SoC. The two PRU-ICSSs are identical
to each other. Each PRU-ICSS instance is represented by a pruss-soc-bus
node and a child PRUSS subsystem node. These nodes are enabled by
default.
The PRU-ICSSs on 66AK2G are very similar to the PRUSS on the AM57xx
SoCs except for larger Shared Data RAM and the lack of a PRU-ICSS
crossbar. There are also few other minor integration differences
w.r.t IPC mechansims that can be attributed to the architecture
differences between Keystone and OMAP families.
The PRUSS subsystem node contains the entire address space and the
various interrupts generated towards the main MPU. The various
sub-modules of the PRU-ICSS are represented as individual child
nodes (so platform devices themselves) of the PRUSS subsystem node.
These include the two PRU cores and the interrupt controller. The
Industrial Ethernet Peripheral (IEP), the Real Time Media Independent
Interface controller (MII_RT), and the CFG sub-module are represented
as syscon nodes. All the Data RAMs are represented within a child
node of its own named 'memories' without any compatible.
The DT nodes use all standard properties. The regs property in the
PRU nodes define the addresses for the Instruction RAM, the Debug
and Control sub-modules for that PRU core. The firmware for each
PRU core is defined through a 'firmware-name' property.
The default names for the firmware images for each PRU core are
defined as follows (these can be adjusted either in derivative
board dts files or through sysfs at runtime if required):
PRU-ICSS0 PRU0 Core: k2g-pru0_0-fw
PRU-ICSS0 PRU1 Core: k2g-pru0_1-fw
PRU-ICSS1 PRU0 Core: k2g-pru1_0-fw
PRU-ICSS1 PRU1 Core: k2g-pru1_1-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
that are present on the 66AK2G SoC. The two PRU-ICSSs are identical
to each other. Each PRU-ICSS instance is represented by a pruss-soc-bus
node and a child PRUSS subsystem node. These nodes are enabled by
default.
The PRU-ICSSs on 66AK2G are very similar to the PRUSS on the AM57xx
SoCs except for larger Shared Data RAM and the lack of a PRU-ICSS
crossbar. There are also few other minor integration differences
w.r.t IPC mechansims that can be attributed to the architecture
differences between Keystone and OMAP families.
The PRUSS subsystem node contains the entire address space and the
various interrupts generated towards the main MPU. The various
sub-modules of the PRU-ICSS are represented as individual child
nodes (so platform devices themselves) of the PRUSS subsystem node.
These include the two PRU cores and the interrupt controller. The
Industrial Ethernet Peripheral (IEP), the Real Time Media Independent
Interface controller (MII_RT), and the CFG sub-module are represented
as syscon nodes. All the Data RAMs are represented within a child
node of its own named 'memories' without any compatible.
The DT nodes use all standard properties. The regs property in the
PRU nodes define the addresses for the Instruction RAM, the Debug
and Control sub-modules for that PRU core. The firmware for each
PRU core is defined through a 'firmware-name' property.
The default names for the firmware images for each PRU core are
defined as follows (these can be adjusted either in derivative
board dts files or through sysfs at runtime if required):
PRU-ICSS0 PRU0 Core: k2g-pru0_0-fw
PRU-ICSS0 PRU1 Core: k2g-pru0_1-fw
PRU-ICSS1 PRU0 Core: k2g-pru1_0-fw
PRU-ICSS1 PRU1 Core: k2g-pru1_1-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
| arch/arm/boot/dts/keystone-k2g.dtsi | patch | blob | history |
index b1b8ab43a9bf62ac1deb00c19779ecd4261b74b0..d3dd70d719a9c053cb72d937c60606be53273356 100644 (file)
interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>;
};
+ pruss_soc_bus0: pruss-soc-bus@20aa6004 {
+ compatible = "ti,k2g-pruss-soc-bus";
+ reg = <0x20aa6004 0x4>;
+ power-domains = <&k2g_pds 0x0014>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges;
+ dma-coherent;
+
+ pruss0: pruss@20a80000 {
+ compatible = "ti,k2g-pruss";
+ reg = <0x20a80000 0x40000>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "host2", "host3", "host4",
+ "host5", "host6", "host8",
+ "host9";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges;
+ dma-coherent;
+
+ pruss0_mem: memories@20a80000 {
+ reg = <0x20a80000 0x2000>,
+ <0x20a82000 0x2000>,
+ <0x20a90000 0x10000>;
+ reg-names = "dram0", "dram1",
+ "shrdram2";
+ };
+
+ pruss0_cfg: cfg@20aa6000 {
+ compatible = "syscon";
+ reg = <0x20aa6000 0x2000>;
+ };
+
+ pruss0_iep: iep@20aae000 {
+ compatible = "syscon";
+ reg = <0x20aae000 0x31c>;
+ };
+
+ pruss0_mii_rt: mii-rt@20ab2000 {
+ compatible = "syscon";
+ reg = <0x20ab2000 0x70>;
+ };
+
+ pruss0_intc: interrupt-controller@20aa0000 {
+ compatible = "ti,k2g-pruss-intc";
+ reg = <0x20aa0000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pru0_0: pru@20ab4000 {
+ compatible = "ti,k2g-pru";
+ reg = <0x20ab4000 0x3000>,
+ <0x20aa2000 0x400>,
+ <0x20aa2400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "k2g-pru0_0-fw";
+ };
+
+ pru0_1: pru@20ab8000 {
+ compatible = "ti,k2g-pru";
+ reg = <0x20ab8000 0x3000>,
+ <0x20aa4000 0x400>,
+ <0x20aa4400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "k2g-pru0_1-fw";
+ };
+ };
+ };
+
+ pruss_soc_bus1: pruss-soc-bus@20ae6004 {
+ compatible = "ti,k2g-pruss-soc-bus";
+ reg = <0x20ae6004 0x4>;
+ power-domains = <&k2g_pds 0x0015>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges;
+ dma-coherent;
+
+ pruss1: pruss@20ac0000 {
+ compatible = "ti,k2g-pruss";
+ reg = <0x20ac0000 0x40000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "host2", "host3", "host4",
+ "host5", "host6", "host8",
+ "host9";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges;
+ dma-coherent;
+
+ pruss1_mem: memories@20ac0000 {
+ reg = <0x20ac0000 0x2000>,
+ <0x20ac2000 0x2000>,
+ <0x20ad0000 0x10000>;
+ reg-names = "dram0", "dram1",
+ "shrdram2";
+ };
+
+ pruss1_cfg: cfg@20ae6000 {
+ compatible = "syscon";
+ reg = <0x20ae6000 0x2000>;
+ };
+
+ pruss1_iep: iep@20aee000 {
+ compatible = "syscon";
+ reg = <0x20aee000 0x31c>;
+ };
+
+ pruss1_mii_rt: mii-rt@20af2000 {
+ compatible = "syscon";
+ reg = <0x20af2000 0x70>;
+ };
+
+ pruss1_intc: interrupt-controller@20ae0000 {
+ compatible = "ti,k2g-pruss-intc";
+ reg = <0x20ae0000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pru1_0: pru@20af4000 {
+ compatible = "ti,k2g-pru";
+ reg = <0x20af4000 0x3000>,
+ <0x20ae2000 0x400>,
+ <0x20ae2400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "k2g-pru1_0-fw";
+ };
+
+ pru1_1: pru@20af8000 {
+ compatible = "ti,k2g-pru";
+ reg = <0x20af8000 0x3000>,
+ <0x20ae4000 0x400>,
+ <0x20ae4400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "k2g-pru1_1-fw";
+ };
+ };
+ };
+
mdio: mdio@4200f00 {
compatible = "ti,keystone_mdio", "ti,davinci_mdio";
reg = <0x04200f00 0x100>;