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raw | patch | inline | side by side (parent: ae398c4)
raw | patch | inline | side by side (parent: ae398c4)
| author | Suman Anna <s-anna@ti.com> | |
| Mon, 18 Feb 2019 19:43:45 +0000 (13:43 -0600) | ||
| committer | Suman Anna <s-anna@ti.com> | |
| Sun, 24 Feb 2019 01:20:50 +0000 (19:20 -0600) |
Add the DT nodes for the PRU-ICSS1 and PRU-ICSS2 processor subsystems
that are present on AM57xx family of SoCs. Each PRU-ICSS instance is
represented by a pruss-soc-bus node and a child PRUSS subsystem node.
The two PRU-ICSSs are identical to each other. They are not supported
on DRA7xx SoCs in general, so the nodes are added in disabled state
to the common dra7 DTS file. They should be enabled only in the AM57xx
related board files.
The PRU-ICSSs on AM57xx are very similar to the PRUSS in AM33xx and
AM437x except for variations in the RAM sizes and the number of
interrupts coming into the MPU INTC. The interrupt events into the
PRU-ICSS also requires programming of the corresponding crossbars
properly.
The PRUSS subsystem node contains the entire address space and the
various interrupts generated towards the main MPU. The various
sub-modules of the PRU-ICSS are represented as individual child
nodes (so platform devices themselves) of the PRUSS subsystem node.
These include the two PRU cores and the interrupt controller. The
Industrial Ethernet Peripheral (IEP), the Real Time Media Independent
Interface controller (MII_RT), and the CFG sub-module are represented
as syscon nodes. All the Data RAMs are represented within a child
node of its own named 'memories' without any compatible.
The DT nodes use all standard properties. The regs property in the
PRU nodes define the addresses for the Instruction RAM, the Debug
and Control sub-modules for that PRU core. The firmware for each
PRU core is defined through a 'firmware-name' property.
The default names for the firmware images for each PRU core are
defined as follows (these can be adjusted either in derivative
board dts files or through sysfs at runtime if required):
PRU-ICSS1 PRU0 Core: am57xx-pru1_0-fw
PRU-ICSS1 PRU1 Core: am57xx-pru1_1-fw
PRU-ICSS2 PRU0 Core: am57xx-pru2_0-fw
PRU-ICSS2 PRU1 Core: am57xx-pru2_1-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
that are present on AM57xx family of SoCs. Each PRU-ICSS instance is
represented by a pruss-soc-bus node and a child PRUSS subsystem node.
The two PRU-ICSSs are identical to each other. They are not supported
on DRA7xx SoCs in general, so the nodes are added in disabled state
to the common dra7 DTS file. They should be enabled only in the AM57xx
related board files.
The PRU-ICSSs on AM57xx are very similar to the PRUSS in AM33xx and
AM437x except for variations in the RAM sizes and the number of
interrupts coming into the MPU INTC. The interrupt events into the
PRU-ICSS also requires programming of the corresponding crossbars
properly.
The PRUSS subsystem node contains the entire address space and the
various interrupts generated towards the main MPU. The various
sub-modules of the PRU-ICSS are represented as individual child
nodes (so platform devices themselves) of the PRUSS subsystem node.
These include the two PRU cores and the interrupt controller. The
Industrial Ethernet Peripheral (IEP), the Real Time Media Independent
Interface controller (MII_RT), and the CFG sub-module are represented
as syscon nodes. All the Data RAMs are represented within a child
node of its own named 'memories' without any compatible.
The DT nodes use all standard properties. The regs property in the
PRU nodes define the addresses for the Instruction RAM, the Debug
and Control sub-modules for that PRU core. The firmware for each
PRU core is defined through a 'firmware-name' property.
The default names for the firmware images for each PRU core are
defined as follows (these can be adjusted either in derivative
board dts files or through sysfs at runtime if required):
PRU-ICSS1 PRU0 Core: am57xx-pru1_0-fw
PRU-ICSS1 PRU1 Core: am57xx-pru1_1-fw
PRU-ICSS2 PRU0 Core: am57xx-pru2_0-fw
PRU-ICSS2 PRU1 Core: am57xx-pru2_1-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
| arch/arm/boot/dts/dra7.dtsi | patch | blob | history |
index a0ddf497e8cddcd2fd1c906244167bc373be93e3..301f759cc0cc0a7877c77079ff8af6a90ecb0b95 100644 (file)
status = "disabled";
};
+ pruss_soc_bus1: pruss-soc-bus@4b226004 {
+ compatible = "ti,am5728-pruss-soc-bus";
+ reg = <0x4b226004 0x4>;
+ ti,hwmods = "pruss1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ pruss1: pruss@4b200000 {
+ compatible = "ti,am5728-pruss";
+ reg = <0x4b200000 0x80000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host2", "host3", "host4",
+ "host5", "host6", "host7",
+ "host8", "host9";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ pruss1_mem: memories@4b200000 {
+ reg = <0x4b200000 0x2000>,
+ <0x4b202000 0x2000>,
+ <0x4b210000 0x8000>;
+ reg-names = "dram0", "dram1",
+ "shrdram2";
+ };
+
+ pruss1_cfg: cfg@4b226000 {
+ compatible = "syscon";
+ reg = <0x4b226000 0x2000>;
+ };
+
+ pruss1_iep: iep@4b22e000 {
+ compatible = "syscon";
+ reg = <0x4b22e000 0x31c>;
+ };
+
+ pruss1_mii_rt: mii-rt@4b232000 {
+ compatible = "syscon";
+ reg = <0x4b232000 0x58>;
+ };
+
+ pruss1_intc: interrupt-controller@4b220000 {
+ compatible = "ti,am5728-pruss-intc";
+ reg = <0x4b220000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pru1_0: pru@4b234000 {
+ compatible = "ti,am5728-pru";
+ reg = <0x4b234000 0x3000>,
+ <0x4b222000 0x400>,
+ <0x4b222400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am57xx-pru1_0-fw";
+ };
+
+ pru1_1: pru@4b238000 {
+ compatible = "ti,am5728-pru";
+ reg = <0x4b238000 0x3000>,
+ <0x4b224000 0x400>,
+ <0x4b224400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am57xx-pru1_1-fw";
+ };
+ };
+ };
+
+ pruss_soc_bus2: pruss-soc-bus@4b2a6004 {
+ compatible = "ti,am5728-pruss-soc-bus";
+ reg = <0x4b2a6004 0x4>;
+ ti,hwmods = "pruss2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ pruss2: pruss@4b280000 {
+ compatible = "ti,am5728-pruss";
+ reg = <0x4b280000 0x80000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host2", "host3", "host4",
+ "host5", "host6", "host7",
+ "host8", "host9";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ pruss2_mem: memories@4b280000 {
+ reg = <0x4b280000 0x2000>,
+ <0x4b282000 0x2000>,
+ <0x4b290000 0x8000>;
+ reg-names = "dram0", "dram1",
+ "shrdram2";
+ };
+
+ pruss2_cfg: cfg@4b2a6000 {
+ compatible = "syscon";
+ reg = <0x4b2a6000 0x2000>;
+ };
+
+ pruss2_iep: iep@4b2ae000 {
+ compatible = "syscon";
+ reg = <0x4b2ae000 0x31c>;
+ };
+
+ pruss2_mii_rt: mii-rt@4b2b2000 {
+ compatible = "syscon";
+ reg = <0x4b2b2000 0x58>;
+ };
+
+ pruss2_intc: interrupt-controller@4b2a0000 {
+ compatible = "ti,am5728-pruss-intc";
+ reg = <0x4b2a0000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pru2_0: pru@4b2b4000 {
+ compatible = "ti,am5728-pru";
+ reg = <0x4b2b4000 0x3000>,
+ <0x4b2a2000 0x400>,
+ <0x4b2a2400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am57xx-pru2_0-fw";
+ };
+
+ pru2_1: pru@4b2b8000 {
+ compatible = "ti,am5728-pru";
+ reg = <0x4b2b8000 0x3000>,
+ <0x4b2a4000 0x400>,
+ <0x4b2a4400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am57xx-pru2_1-fw";
+ };
+ };
+ };
+
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v3";
regulator-name = "abb_mpu";