ARM: DRA7: hwmod_data: Add PRU-ICSS data for AM57xx variants

The AM57xx family of SoCs have two PRU-ICSS remote processor
subsystems, each supporting two PRU processor cores. These
subsystems are not supported on the DRA7 family of SOCs. They
are very similar to the respective processor subsystems on
AM33xx/AM43xx SoCs except for a few differences. The relevant
hwmod classes and data structures have been added for the
PRU-ICSS1 and PRU-ICSS2 subsystems to enable support for
these on the AM57xx SoC variants.

Do note that these subsystems do not have a programmable module
reset line unlike those present in AM33xx/AM43xx. The modules
are reset just like any other IP with the SoC's global cold/warm
resets.

Signed-off-by: Suman Anna <s-anna@ti.com>

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index e6c7061a8e73679695f7816c0461ccccf66151c6..ff3ab1e0622d34dee81eddbbe5a1028d96750d94 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1894,6 +1894,42 @@ static struct omap_hwmod dra7xx_pciess2_hwmod = {
        },
 };
 
+/*
+ * 'pru-icss' class
+ * Programmable Real-Time Unit and Industrial Communication Subsystem
+ */
+static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
+       .name   = "pruss",
+};
+
+/* pru-icss1 */
+static struct omap_hwmod dra7xx_pruss1_hwmod = {
+       .name           = "pruss1",
+       .class          = &dra7xx_pruss_hwmod_class,
+       .clkdm_name     = "l4per2_clkdm",
+       .prcm           = {
+               .omap4  = {
+                       .clkctrl_offs   = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
+                       .context_offs   = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
+                       .modulemode     = MODULEMODE_SWCTRL,
+               },
+       },
+};
+
+/* pru-icss2 */
+static struct omap_hwmod dra7xx_pruss2_hwmod = {
+       .name           = "pruss2",
+       .class          = &dra7xx_pruss_hwmod_class,
+       .clkdm_name     = "l4per2_clkdm",
+       .prcm           = {
+               .omap4  = {
+                       .clkctrl_offs   = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
+                       .context_offs   = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
+                       .modulemode     = MODULEMODE_SWCTRL,
+               },
+       },
+};
+
 /*
  * 'qspi' class
  *
@@ -3457,6 +3493,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> pruss1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss1 = {
+       .master         = &dra7xx_l4_cfg_hwmod,
+       .slave          = &dra7xx_pruss1_hwmod,
+       .clk            = "dpll_gmac_h13x2_ck",
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pruss2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss2 = {
+       .master         = &dra7xx_l4_cfg_hwmod,
+       .slave          = &dra7xx_pruss2_hwmod,
+       .clk            = "dpll_gmac_h13x2_ck",
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_1 -> qspi */
 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
        .master         = &dra7xx_l3_main_1_hwmod,
@@ -3909,6 +3961,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
        &dra7xx_l4_cfg__pciess1,
        &dra7xx_l3_main_1__pciess2,
        &dra7xx_l4_cfg__pciess2,
+       &dra7xx_l4_cfg__pruss1,
+       &dra7xx_l4_cfg__pruss2,
        &dra7xx_l3_main_1__qspi,
        &dra7xx_l4_cfg__sata,
        &dra7xx_l4_cfg__smartreflex_core,