author | Suman Anna <s-anna@ti.com> | |
Sun, 24 Feb 2019 03:15:13 +0000 (21:15 -0600) | ||
committer | Suman Anna <s-anna@ti.com> | |
Mon, 25 Feb 2019 19:11:51 +0000 (13:11 -0600) |
Pull in the mailbox feature branch into a new topic remoteproc branch
dedicated for adding remoteproc support patches for the remote processors
present on K3 AM65x SoCs. The merge brings in the base platform and board
support for K3 AM65x SoCs, including the support for the Mailbox IP present
within the Main NavSS sub-module on K3 AM65x SoCs.
* 'mailbox-linux-4.19.y' of git://git.ti.com/rpmsg/mailbox: (134 commits)
dt-bindings: mailbox: omap: Update example for TI K3 AM65x SoCs
arm64: dts: ti: k3-am65-main: Rename IPC sub-mailboxes
arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs
arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes
ti_config_fragments: v8_rpmsg: Enable OMAP Mailbox support
mailbox/omap: add support for TI K3 SoCs
dt-bindings: mailbox: omap: Update bindings for TI K3 AM65x SoCs
ti_config_fragments: v8_defconfig_map: Add v8 rpmsg config file
ti_config_fragments: v8_rpmsg: Add RPMsg domain config fragment file
ti_config_fragments: defconfig_map: Include RPMsg config fragment
ti_config_fragments: rpmsg: Add RPMsg domain config fragment file
dmaengine: ti: k3-udma: Try to use the highest TPL channels for MEM_TO_MEM
dmaengine: ti: k3-udma: Only allow MEM_TO_MEM transfer on the main UDMA
ti_config_fragments/defconfig_map.txt: add missing baseport.cfg entries
ti_config_fragments: v8_baseport: Forward port v8_baseport cfg from 4.14
arm64: dts: ti: k3-am6: Add NAVSS and PDMA nodes
dmaengine: ti: k3-udma: Add glue layer for non DMAengine users
dmaengine: ti: New driver for K3 UDMA
dmaengine: ti: Add cppi5 header for UDMA
dt-bindings: dma: ti: Add document for K3 UDMA
...
Signed-off-by: Suman Anna <s-anna@ti.com>
dedicated for adding remoteproc support patches for the remote processors
present on K3 AM65x SoCs. The merge brings in the base platform and board
support for K3 AM65x SoCs, including the support for the Mailbox IP present
within the Main NavSS sub-module on K3 AM65x SoCs.
* 'mailbox-linux-4.19.y' of git://git.ti.com/rpmsg/mailbox: (134 commits)
dt-bindings: mailbox: omap: Update example for TI K3 AM65x SoCs
arm64: dts: ti: k3-am65-main: Rename IPC sub-mailboxes
arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs
arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes
ti_config_fragments: v8_rpmsg: Enable OMAP Mailbox support
mailbox/omap: add support for TI K3 SoCs
dt-bindings: mailbox: omap: Update bindings for TI K3 AM65x SoCs
ti_config_fragments: v8_defconfig_map: Add v8 rpmsg config file
ti_config_fragments: v8_rpmsg: Add RPMsg domain config fragment file
ti_config_fragments: defconfig_map: Include RPMsg config fragment
ti_config_fragments: rpmsg: Add RPMsg domain config fragment file
dmaengine: ti: k3-udma: Try to use the highest TPL channels for MEM_TO_MEM
dmaengine: ti: k3-udma: Only allow MEM_TO_MEM transfer on the main UDMA
ti_config_fragments/defconfig_map.txt: add missing baseport.cfg entries
ti_config_fragments: v8_baseport: Forward port v8_baseport cfg from 4.14
arm64: dts: ti: k3-am6: Add NAVSS and PDMA nodes
dmaengine: ti: k3-udma: Add glue layer for non DMAengine users
dmaengine: ti: New driver for K3 UDMA
dmaengine: ti: Add cppi5 header for UDMA
dt-bindings: dma: ti: Add document for K3 UDMA
...
Signed-off-by: Suman Anna <s-anna@ti.com>
13 files changed:
index e279f0f33c0053203cd6a505c175e03d48b92ddf,63e7efb4760c376d0392ab4e9d9c2d5c82818dc5..362746729583f08fb389b85b4386baee15d3dfd2
&rtc {
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
+ system-power-controller;
+ };
+
+ &wkup_m3_ipc {
+ ti,scale-data-fw = "am335x-bone-scale-data.bin";
};
+
+&pruss_soc_bus {
+ status = "okay";
+
+ pruss: pruss@4a300000 {
+ status = "okay";
+ };
+};
diff --cc arch/arm/boot/dts/am335x-evm.dts
index f9578b10bbe7b2e355f2b08b98a0df7920e982bd,ca69ed2a5680ea5c93e18b2bff14be47a989300a..9f5e7d927f925c9799305747e5fa07807bfe95c6
clock-names = "ext-clk", "int-clk";
};
+ &wkup_m3_ipc {
+ ti,scale-data-fw = "am335x-evm-scale-data.bin";
+ };
++
+&pruss_soc_bus {
+ status = "okay";
+
+ pruss: pruss@4a300000 {
+ status = "okay";
+ };
+};
diff --cc arch/arm/boot/dts/am335x-evmsk.dts
Simple merge
diff --cc arch/arm/boot/dts/am33xx.dtsi
Simple merge
diff --cc arch/arm/boot/dts/am4372.dtsi
Simple merge
diff --cc arch/arm/boot/dts/am437x-gp-evm.dts
index b93a3c8282ca3df7c1bc5282b7f8477f678351a5,98a0907af26be2edb32e6a1b88b92a722e4c5373..9e34ce39c259754d6dd1117d7488e1f312581dd8
cpu0-supply = <&dcdc2>;
};
+ &wkup_m3_ipc {
+ ti,set-io-isolation;
+ ti,scale-data-fw = "am43x-evm-scale-data.bin";
+ };
++
+&pruss_soc_bus {
+ status = "okay";
+
+ pruss1: pruss@54400000 {
+ status = "okay";
+ };
+
+ pruss0: pruss@54440000 {
+ status = "okay";
+ };
+};
diff --cc arch/arm/boot/dts/am437x-sk-evm.dts
index 026a0f28f734fd973cc43c1b9228814ad8a584b2,55278aec469016dfc8cd2ca6efa75b53155d0ab1..ed2a2cafc2bade3f310e503d63ac9b54f1e7ae15
};
};
+ &wkup_m3_ipc {
+ ti,scale-data-fw = "am43x-evm-scale-data.bin";
+ };
++
+&pruss_soc_bus {
+ status = "okay";
+
+ pruss1: pruss@54400000 {
+ status = "okay";
+ };
+
+ pruss0: pruss@54440000 {
+ status = "okay";
+ };
+};
diff --cc arch/arm/boot/dts/am57xx-idk-common.dtsi
index e4c71080fba5fd06e8edd0dd2ea7d4cf7085def9,4c77a48ee9b0eaa116fc537792f03a5fb1f9f472..d23eb2667f42e6d2921881c2f43883aa2a740253
};
};
+ &cpu0 {
+ vdd-supply = <&smps12_reg>;
+ };
++
+&pruss_soc_bus1 {
+ status = "okay";
+
+ pruss1: pruss@4b200000 {
+ status = "okay";
+ };
+};
+
+&pruss_soc_bus2 {
+ status = "okay";
+
+ pruss2: pruss@4b280000 {
+ status = "okay";
+ };
+};
diff --cc arch/arm/boot/dts/keystone-k2g.dtsi
Simple merge
diff --cc drivers/irqchip/Makefile
index b49c2470fa94ad76df1be15c6b4ac7a969485772,11418eb9ac11bbf355192c7de62b944b6deb1e47..d4cd347a2c8505249959bce71c89475c269a927d
+++ b/drivers/irqchip/Makefile
obj-$(CONFIG_NDS32) += irq-ativic32.o
obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o
obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
+obj-$(CONFIG_TI_PRUSS) += irq-pruss-intc.o
+ obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
+ obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
diff --cc drivers/soc/ti/Kconfig
index 35574ecef8cae15b972a61d95842a885fff523f7,09d485acbce44b2108377fae274454295cdc010a..0b67bde174b584c5cf4ff148a9f591ab0bd3147e
+++ b/drivers/soc/ti/Kconfig
called ti_sci_pm_domains. Note this is needed early in boot before
rootfs may be available.
+config TI_PRUSS
+ tristate "TI PRU-ICSS Subsystem Platform drivers"
+ depends on SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE
+ select MFD_SYSCON
+ help
+ TI PRU-ICSS Subsystem platform specific support.
+
+ Say Y or M here to support the Programmable Realtime Unit (PRU)
+ processors on various TI SoCs. It's safe to say N here if you're
+ not interested in the PRU or if you are unsure.
+
+ config TI_K3_RINGACC
+ tristate "K3 Ring accelerator Sub System"
+ depends on ARCH_K3 || COMPILE_TEST
+ default y
+ help
+ Say y here to support the K3 Ring accelerator module.
+ The Ring Accelerator (RINGACC or RA) provides hardware acceleration
+ to enable straightforward passing of work between a producer
+ and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs
+ If unsure, say N.
+
+ config TI_K3_RINGACC_DEBUG
+ tristate "K3 Ring accelerator Sub System tests and debug"
+ depends on TI_K3_RINGACC
+ default n
+
endif # SOC_TI
diff --cc drivers/soc/ti/Makefile
index b69beb059b60721eeb219064754b67a0fe06dd95,5dc80fff924e27ca7d82bfaa024464c840d5c12b..ca5c2724f8c0a0de0a83035a0c4fa50578cef1a0
+++ b/drivers/soc/ti/Makefile
obj-$(CONFIG_AMX3_PM) += pm33xx.o
obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o
obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o
+obj-$(CONFIG_TI_PRUSS) += pruss_soc_bus.o pruss.o
+ obj-$(CONFIG_TI_K3_RINGACC) += k3-ringacc.o
diff --cc drivers/soc/ti/wkup_m3_ipc.c
index f5cb8c0af09f3ab8ade4443ada270bf1f1eefa92,eee4b8b737d63886f569f85d3945325d6e17051c..fda2741252d981754775d349ead8560b7d71df8e
{.irq_nr = 0, .src = "Unknown"},
};
- aux_data_addr = rproc_da_to_va(m3_ipc->rproc,
- aux_data_dev_addr,
- WKUP_M3_AUXDATA_SIZE);
+ /**
+ * wkup_m3_copy_aux_data - Copy auxiliary data to special region of m3 dmem
+ * @data - pointer to data
+ * @sz - size of data to copy (limit 256 bytes)
+ *
+ * Copies any additional blob of data to the wkup_m3 dmem to be used by the
+ * firmware
+ */
+ static unsigned long wkup_m3_copy_aux_data(struct wkup_m3_ipc *m3_ipc,
+ const void *data, int sz)
+ {
+ unsigned long aux_data_dev_addr;
+ void *aux_data_addr;
+
+ aux_data_dev_addr = WKUP_M3_DMEM_START + WKUP_M3_AUXDATA_OFFSET;
++ aux_data_addr = rproc_da_to_va(m3_ipc->rproc, aux_data_dev_addr,
++ WKUP_M3_AUXDATA_SIZE, RPROC_FLAGS_NONE);
+ memcpy(aux_data_addr, data, sz);
+
+ return WKUP_M3_AUXDATA_OFFSET;
+ }
+
+ static void wkup_m3_scale_data_fw_cb(const struct firmware *fw, void *context)
+ {
+ unsigned long val, aux_base;
+ struct wkup_m3_scale_data_header hdr;
+ struct wkup_m3_ipc *m3_ipc = context;
+ struct device *dev = m3_ipc->dev;
+
+ if (!fw) {
+ dev_err(dev, "Voltage scale fw name given but file missing.\n");
+ return;
+ }
+
+ memcpy(&hdr, fw->data, sizeof(hdr));
+
+ if (hdr.magic != WKUP_M3_SD_FW_MAGIC) {
+ dev_err(dev, "PM: Voltage Scale Data binary does not appear valid.\n");
+ goto release_sd_fw;
+ }
+
+ aux_base = wkup_m3_copy_aux_data(m3_ipc, fw->data + sizeof(hdr),
+ fw->size - sizeof(hdr));
+
+ val = (aux_base + hdr.sleep_offset);
+ val |= ((aux_base + hdr.wake_offset) << 16);
+
+ m3_ipc->volt_scale_offsets = val;
+
+ release_sd_fw:
+ release_firmware(fw);
+ };
+
+ static int wkup_m3_init_scale_data(struct wkup_m3_ipc *m3_ipc,
+ struct device *dev)
+ {
+ int ret = 0;
+
+ /*
+ * If no name is provided, user has already been warned, pm will
+ * still work so return 0
+ */
+
+ if (!m3_ipc->sd_fw_name)
+ return ret;
+
+ ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
+ m3_ipc->sd_fw_name, dev, GFP_ATOMIC,
+ m3_ipc, wkup_m3_scale_data_fw_cb);
+
+ return ret;
+ }
+
+ #ifdef CONFIG_DEBUG_FS
+ static void wkup_m3_set_halt_late(bool enabled)
+ {
+ if (enabled)
+ m3_ipc_state->halt = (1 << IPC_DBG_HALT_SHIFT);
+ else
+ m3_ipc_state->halt = 0;
+ }
+
+ static int option_get(void *data, u64 *val)
+ {
+ u32 *option = data;
+
+ *val = *option;
+
+ return 0;
+ }
+
+ static int option_set(void *data, u64 val)
+ {
+ u32 *option = data;
+
+ *option = val;
+
+ if (option == &m3_ipc_state->halt) {
+ if (val)
+ wkup_m3_set_halt_late(true);
+ else
+ wkup_m3_set_halt_late(false);
+ }
+
+ return 0;
+ }
+
+ DEFINE_SIMPLE_ATTRIBUTE(wkup_m3_ipc_option_fops, option_get, option_set,
+ "%llu\n");
+
+ static int wkup_m3_ipc_dbg_init(struct wkup_m3_ipc *m3_ipc)
+ {
+ m3_ipc->dbg_path = debugfs_create_dir("wkup_m3_ipc", NULL);
+
+ if (!m3_ipc->dbg_path)
+ return -EINVAL;
+
+ (void)debugfs_create_file("enable_late_halt", 0644,
+ m3_ipc->dbg_path,
+ &m3_ipc->halt,
+ &wkup_m3_ipc_option_fops);
+
+ return 0;
+ }
+
+ static inline void wkup_m3_ipc_dbg_destroy(struct wkup_m3_ipc *m3_ipc)
+ {
+ debugfs_remove_recursive(m3_ipc->dbg_path);
+ }
+ #else
+ static inline int wkup_m3_ipc_dbg_init(struct wkup_m3_ipc *m3_ipc)
+ {
+ return 0;
+ }
+
+ static inline void wkup_m3_ipc_dbg_destroy(struct wkup_m3_ipc *m3_ipc)
+ {
+ }
+ #endif /* CONFIG_DEBUG_FS */
+
static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
{
writel(AM33XX_M3_TXEV_ACK,