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dt-bindings: irqchip: Add PRUSS interrupt controller bindings
authorSuman Anna <s-anna@ti.com>
Fri, 15 Feb 2019 16:54:19 +0000 (10:54 -0600)
committerSuman Anna <s-anna@ti.com>
Sat, 23 Feb 2019 17:21:11 +0000 (11:21 -0600)
The Programmable Real-Time Unit Subsystem (PRUSS) contains an
interrupt controller (INTC) that can handle various system input
events and post interrupts back to the device-level initiators.
The INTC can support upto 64 input events with individual control
configuration and hardware prioritization. These events are mapped
onto 10 interrupt signals through two levels of many-to-one mapping
support. Different interrupt signals are routed to the individual
PRU cores or to the host CPU.

Add the bindings document for this interrupt controller. The binding
currently covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx;
and a Keystone 2 architecture based 66AK2G SoC. The Davinci based
OMAPL138 SoCs and K3 architecture based AM65x SoCs will be covered
in a subsequent patch.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt
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+PRU ICSS INTC on TI SoCs
+========================
+
+Each PRUSS has a single interrupt controller instance that is common to both
+the PRU cores. Each interrupt controller can detect 64 input events which are
+then mapped to 10 possible output interrupts through two levels of mapping. The
+input events can be triggered by either the PRUs and/or various other PRUSS
+internal and external peripherals. The first 2 output interrupts are fed
+exclusively to the internal PRU cores, with the remaining 8 connected to
+external interrupt controllers including the MPU.
+
+This interrupt-controller node should be defined as a child node of the
+corresponding PRUSS node. The node should be named "interrupt-controller".
+Please see the overall PRUSS bindings document for additional details
+including a complete example,
+    Documentation/devicetree/bindings/soc/ti/ti,pruss.txt
+
+Required Properties:
+--------------------
+- compatible           : should be one of,
+                             "ti,am3356-pruss-intc" for AM335x family of SoCs
+                             "ti,am4376-pruss-intc" for AM437x family of SoCs
+                             "ti,am5728-pruss-intc" for AM57xx family of SoCs
+                             "ti,k2g-pruss-intc" for 66AK2G family of SoCs
+- reg                  : base address and size for the PRUSS INTC sub-module
+- interrupt-controller : mark this node as an interrupt controller
+- #interrupt-cells     : should be 1. Client users shall use the PRU System
+                         event number (the interrupt source that the client
+                         is interested in) as the value of the interrupts
+                         property in their node
+
+Example:
+--------
+
+1.     /* AM33xx PRU-ICSS */
+       pruss_soc_bus: pruss-soc-bus@4a326004 {
+               compatible = "ti,am3356-pruss-soc-bus";
+               ...
+
+               pruss: pruss@4a300000 {
+                       compatible = "ti,am3356-pruss";
+                       reg = <0x4a300000 0x80000>;
+                       interrupts = <20 21 22 23 24 25 26 27>;
+                       interrupt-names = "host2", "host3", "host4",
+                                         "host5", "host6", "host7",
+                                         "host8", "host9";
+                       #address-cells = <1>;
+                       ...
+
+                       pruss_intc: interrupt-controller@4a320000 {
+                               compatible = "ti,am3356-pruss-intc";
+                               reg = <0x4a320000 0x2000>;
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+       };