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author | Suman Anna <s-anna@ti.com> | |
Fri, 15 Feb 2019 17:19:15 +0000 (11:19 -0600) | ||
committer | Suman Anna <s-anna@ti.com> | |
Sun, 24 Feb 2019 01:20:48 +0000 (19:20 -0600) |
The Programmable Real-Time Unit Subsystem (PRUSS) consists of dual
32-bit RISC cores (Programmable Real-Time Units, or PRUs) for program
execution. This patch adds the bindings for these PRU cores.
The binding currently covers the OMAP architecture SoCs - AM33xx,
AM437x and AM57xx; and a Keystone 2 architecture based 66AK2G SoC.
The Davinci based OMAPL138 SoCs and K3 architecture based AM65x SoCs
will be covered in a subsequent patch.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
32-bit RISC cores (Programmable Real-Time Units, or PRUs) for program
execution. This patch adds the bindings for these PRU cores.
The binding currently covers the OMAP architecture SoCs - AM33xx,
AM437x and AM57xx; and a Keystone 2 architecture based 66AK2G SoC.
The Davinci based OMAPL138 SoCs and K3 architecture based AM65x SoCs
will be covered in a subsequent patch.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.txt | [new file with mode: 0644] | patch | blob |
diff --git a/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.txt
--- /dev/null
@@ -0,0 +1,74 @@
+PRU Core on TI SoCs
+===================
+
+Each PRUSS has dual PRU cores, each represented by a PRU node. Each PRU core
+has a dedicated Instruction RAM, Control and Debug register sets, and use
+the Data RAMs present within the PRUSS for code execution.
+
+Each PRU core node should be defined as a child node of the corresponding PRUSS
+node. Each node can optionally be rendered inactive by using the standard DT
+string property, "status".
+
+Please see the overall PRUSS bindings document for additional details
+including a complete example,
+ Documentation/devicetree/bindings/soc/ti/ti,pruss.txt
+
+Required Properties:
+--------------------
+- compatible : should be
+ "ti,am3356-pru" for AM335x family of SoCs
+ "ti,am4376-pru" for AM437x family of SoCs
+ "ti,am5728-pru" for AM57xx family of SoCs
+ "ti,k2g-pru" for 66AK2G family of SoCs
+- reg : base address and size for each of the 3 sub-module address
+ spaces as mentioned in reg-names, and in the same order as
+ the reg-names
+- reg-names : should contain each of the following 3 names, the binding is
+ agnostic of the order of these reg-names, preferable to have
+ the "iram" entry as the first one
+ "iram" for Instruction RAM,
+ "control" for the CTRL sub-module registers,
+ "debug" for the Debug sub-module registers,
+- firmware-name : should contain the name of the default firmware image file
+ located on the firmware search path
+
+
+Example:
+--------
+
+1. /* AM33xx PRU-ICSS */
+ pruss_soc_bus: pruss-soc-bus@4a326004 {
+ compatible = "ti,am3356-pruss-soc-bus";
+ ...
+
+ pruss: pruss@4a300000 {
+ compatible = "ti,am3356-pruss";
+ reg = <0x4a300000 0x80000>;
+ ...
+
+ pruss_mem: memories@4a300000 {
+ reg = <0x4a300000 0x2000>,
+ <0x4a302000 0x2000>,
+ <0x4a310000 0x3000>;
+ reg-names = "dram0", "dram1", "shrdram2";
+ };
+
+ pru0: pru@4a334000 {
+ compatible = "ti,am3356-pru";
+ reg = <0x4a334000 0x2000>,
+ <0x4a322000 0x400>,
+ <0x4a322400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am335x-pru0-fw";
+ };
+
+ pru1: pru@4a338000 {
+ compatible = "ti,am3356-pru";
+ reg = <0x4a338000 0x2000>,
+ <0x4a324000 0x400>,
+ <0x4a324400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am335x-pru1-fw";
+ };
+ };
+ };