1 /*\r
2 * Copyright (c) 2006-2014, Texas Instruments Incorporated\r
3 * All rights reserved.\r
4 *\r
5 * Redistribution and use in source and binary forms, with or without\r
6 * modification, are permitted provided that the following conditions\r
7 * are met:\r
8 *\r
9 * * Redistributions of source code must retain the above copyright\r
10 * notice, this list of conditions and the following disclaimer.\r
11 *\r
12 * * Redistributions in binary form must reproduce the above copyright\r
13 * notice, this list of conditions and the following disclaimer in the\r
14 * documentation and/or other materials provided with the distribution.\r
15 *\r
16 * * Neither the name of Texas Instruments Incorporated nor the names of\r
17 * its contributors may be used to endorse or promote products derived\r
18 * from this software without specific prior written permission.\r
19 *\r
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
31 *\r
32 */\r
33 \r
34 function d2h(d) {return ("00000000" + (d).toString(16)).slice(-8);}\r
35 \r
36 var newline = "\n";\r
37 \r
38 function printRegisterValue(ds, name, addr)\r
39 {\r
40 value = debugSessionDAP.memory.readWord(0,addr,false);\r
41 value_string = d2h(value);\r
42 file.write(name + " = 0x" + value_string + newline);\r
43 return value; // return the register value for interrogation\r
44 }\r
45 \r
46 // Build a filename that includes date/time\r
47 var today = new Date();\r
48 var year4digit = today.getFullYear();\r
49 var month2digit = ("0" + (today.getMonth()+1)).slice(-2);\r
50 var day2digit = ("0" + today.getDate()).slice(-2);\r
51 var hour2digit = ("0" + today.getHours()).slice(-2);\r
52 var minutes2digit = ("0" + today.getMinutes()).slice(-2);\r
53 var seconds2digit = ("0" + today.getSeconds()).slice(-2);\r
54 var filename_date = '_' + year4digit + '-' + month2digit + '-' + day2digit + '_' + hour2digit + minutes2digit + seconds2digit; \r
55 var userHomeFolder = System.getProperty("user.home");\r
56 var filename = userHomeFolder + '/Desktop/' + 'am335x-boot-analysis' + filename_date + '.txt';\r
57 \r
58 file = new java.io.FileWriter(filename);\r
59 \r
60 debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS");\r
61 debugSessionDAP.target.connect();\r
62 \r
63 var reg_val;\r
64 \r
65 // CONTROL: device_id\r
66 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: device_id", 0x44E10600);\r
67 if ( (reg_val & 0x0FFFFFFF) == 0xb94402e ) {file.write(" * AM335x family" + newline);}\r
68 if ( (reg_val & 0xF0000000) == (0 << 28) ) {file.write(" * Silicon Revision 1.0" + newline);}\r
69 if ( (reg_val & 0xF0000000) == (1 << 28) ) {file.write(" * Silicon Revision 2.0" + newline);}\r
70 if ( (reg_val & 0xF0000000) == (2 << 28) ) {file.write(" * Silicon Revision 2.1" + newline);}\r
71 \r
72 // ROM: PRM_RSTST\r
73 file.write(newline);\r
74 reg_val = printRegisterValue(debugSessionDAP, "PRM_DEVICE: PRM_RSTST", 0x44E00F08);\r
75 if (reg_val & 1<<0 ) {file.write(" * Bit 0 : GLOBAL_COLD_RST" + newline);}\r
76 if (reg_val & 1<<1 ) {file.write(" * Bit 1 : GLOBAL_WARM_RST" + newline);}\r
77 if (reg_val & 1<<4 ) {file.write(" * Bit 4 : WDT1_RST" + newline);}\r
78 if (reg_val & 1<<5 ) {file.write(" * Bit 5 : EXTERNAL_WARM_RST" + newline);}\r
79 \r
80 // CONTROL: control_status\r
81 file.write(newline);\r
82 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: control_status", 0x44E10040);\r
83 boot_sequence = (reg_val & 0x1F);\r
84 if ( (reg_val & 3<<22 ) == 0<<22 ) {file.write(" * SYSBOOT[15:14] = 00b (19.2 MHz)" + newline);}\r
85 if ( (reg_val & 3<<22 ) == 1<<22 ) {file.write(" * SYSBOOT[15:14] = 01b (24 MHz)" + newline);}\r
86 if ( (reg_val & 3<<22 ) == 2<<22 ) {file.write(" * SYSBOOT[15:14] = 10b (25 MHz)" + newline);}\r
87 if ( (reg_val & 3<<22 ) == 3<<22 ) {file.write(" * SYSBOOT[15:14] = 11b (26 MHz)" + newline);}\r
88 if ( (reg_val & 3<<20 ) != 0<<20 ) {file.write(" * SYSBOOT[13:12] have been set improperly!" + newline);}\r
89 if ( (reg_val & 3<<18 ) == 0<<18 ) {file.write(" * SYSBOOT[11:10] = 00b No GPMC CS0 addr/data muxing" + newline);}\r
90 if ( (reg_val & 3<<18 ) == 1<<18 ) {file.write(" * SYSBOOT[11:10] = 01b GPMC CS0 addr/addr/data muxing" + newline);}\r
91 if ( (reg_val & 3<<18 ) == 2<<18 ) {file.write(" * SYSBOOT[11:10] = 10b GPMC CS0 addr/data muxing" + newline);}\r
92 if ( (reg_val & 3<<18 ) == 3<<18 ) {file.write(" * SYSBOOT[11:10] = 11b ILLEGAL VALUE!" + newline);}\r
93 if ( (reg_val & 1<<17 ) == 1<<17 ) {file.write(" * SYSBOOT[9] = 0 GPMC CS0 Ignore WAIT input" + newline);}\r
94 if ( (reg_val & 1<<17 ) == 1<<17 ) {file.write(" * SYSBOOT[9] = 1 GPMC CS0 Use WAIT input" + newline);}\r
95 if ( (reg_val & 1<<16 ) == 1<<16 ) {file.write(" * SYSBOOT[8] = 0 GPMC CS0 8-bit data bus" + newline);}\r
96 if ( (reg_val & 1<<16 ) == 1<<16 ) {file.write(" * SYSBOOT[8] = 1 GPMC CS0 16-bit data bus" + newline);}\r
97 if ( (reg_val & 7<<8 ) == 3<<8 ) {file.write(" * Device Type = General Purpose (GP)" + newline);}\r
98 else {file.write(" * Device Type is NOT GP" + newline);}\r
99 if ( (reg_val & 0xFF ) == 0x01 ) {file.write(" * SYSBOOT[8] = 1 GPMC CS0 16-bit data bus" + newline);}\r
100 if ( (reg_val & 3<<6 ) == 0<<6 ) {file.write(" * SYSBOOT[7:6] = 00b MII (EMAC boot modes only)" + newline);}\r
101 if ( (reg_val & 3<<6 ) == 1<<6 ) {file.write(" * SYSBOOT[7:6] = 01b RMII (EMAC boot modes only)" + newline);}\r
102 if ( (reg_val & 3<<6 ) == 2<<6 ) {file.write(" * SYSBOOT[7:6] = 10b ILLEGAL VALUE!" + newline);}\r
103 if ( (reg_val & 3<<6 ) == 3<<6 ) {file.write(" * SYSBOOT[7:6] = 11b RGMII no internal delay (EMAC boot modes only)" + newline);}\r
104 if ( (reg_val & 1<<5 ) == 0<<5 ) {file.write(" * SYSBOOT[5] = 0 CLKOUT1 disabled" + newline);}\r
105 if ( (reg_val & 1<<5 ) == 1<<5 ) {file.write(" * SYSBOOT[5] = 1 CLKOUT1 enabled" + newline);}\r
106 if (boot_sequence == 0x00) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);}\r
107 if (boot_sequence == 0x01) {file.write(" * Boot Sequence : UART0 -> XIP w/WAIT (MUX2) -> MMC0 -> SPI0" + newline);} \r
108 if (boot_sequence == 0x02) {file.write(" * Boot Sequence : UART0 -> SPI0 -> NAND -> NANDI2C" + newline);}\r
109 if (boot_sequence == 0x03) {file.write(" * Boot Sequence : UART0 -> SPI0 -> XIP (MUX2) -> MMC0" + newline);}\r
110 if (boot_sequence == 0x04) {file.write(" * Boot Sequence : UART0 -> XIP w/WAIT (MUX1) -> MMC0 -> NAND" + newline);}\r
111 if (boot_sequence == 0x05) {file.write(" * Boot Sequence : UART0 -> XIP (MUX1) -> SPI0 -> NANDI2C" + newline);}\r
112 if (boot_sequence == 0x06) {file.write(" * Boot Sequence : EMAC1 -> SPI0 -> NAND -> NANDI2C" + newline);}\r
113 if (boot_sequence == 0x07) {file.write(" * Boot Sequence : EMAC1 -> MMC0 -> XIP w/WAIT (MUX2) -> NAND" + newline);}\r
114 if (boot_sequence == 0x08) {file.write(" * Boot Sequence : EMAC1 -> MMC0 -> XIP (MUX2) -> NANDI2C" + newline);}\r
115 if (boot_sequence == 0x09) {file.write(" * Boot Sequence : EMAC1 -> XIP w/WAIT (MUX1) -> NAND -> MMC0" + newline);}\r
116 if (boot_sequence == 0x0A) {file.write(" * Boot Sequence : EMAC1 -> XIP (MUX1) -> SPI0 -> NANDI2C" + newline);}\r
117 if (boot_sequence == 0x0B) {file.write(" * Boot Sequence : USB0 -> NAND -> SPI0 -> MMC0" + newline);}\r
118 if (boot_sequence == 0x0C) {file.write(" * Boot Sequence : USB0 -> NAND -> XIP (MUX2) -> NANDI2C" + newline);}\r
119 if (boot_sequence == 0x0D) {file.write(" * Boot Sequence : USB0 -> NAND -> XIP (MUX1) -> SPI0" + newline);}\r
120 if (boot_sequence == 0x0E) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);}\r
121 if (boot_sequence == 0x0F) {file.write(" * Boot Sequence : UART0 -> EMAC1 -> Reserved -> Reserved" + newline);}\r
122 if (boot_sequence == 0x10) {file.write(" * Boot Sequence : XIP (MUX1) -> UART0 -> EMAC1 -> MMC0 " + newline);}\r
123 if (boot_sequence == 0x11) {file.write(" * Boot Sequence : XIP w/WAIT (MUX1) -> UART0 -> EMAC1 -> MMC0" + newline);} \r
124 if (boot_sequence == 0x12) {file.write(" * Boot Sequence : NAND -> NANDI2C -> USB0 -> UART0" + newline);}\r
125 if (boot_sequence == 0x13) {file.write(" * Boot Sequence : NAND -> NANDI2C -> MMC0 -> UART0" + newline);}\r
126 if (boot_sequence == 0x14) {file.write(" * Boot Sequence : NAND -> NANDI2C -> SPI0 -> EMAC1" + newline);}\r
127 if (boot_sequence == 0x15) {file.write(" * Boot Sequence : NANDI2C -> MMC0 -> EMAC1 -> UART0" + newline);}\r
128 if (boot_sequence == 0x16) {file.write(" * Boot Sequence : SPI0 -> MMC0 -> UART0 -> EMAC1" + newline);}\r
129 if (boot_sequence == 0x17) {file.write(" * Boot Sequence : MMC0 -> SPI0 -> UART0 -> USB0" + newline);}\r
130 if (boot_sequence == 0x18) {file.write(" * Boot Sequence : SPI0 -> MMC0 -> USB0 -> UART0" + newline);}\r
131 if (boot_sequence == 0x19) {file.write(" * Boot Sequence : SPI0 -> MMC0 -> EMAC1 -> UART0" + newline);}\r
132 if (boot_sequence == 0x1A) {file.write(" * Boot Sequence : XIP (MUX2) -> UART0 -> SPI0 -> MMC0" + newline);}\r
133 if (boot_sequence == 0x1B) {file.write(" * Boot Sequence : XIP w/WAIT (MUX2) -> UART0 -> SPI0 -> MMC0" + newline);}\r
134 if (boot_sequence == 0x1C) {file.write(" * Boot Sequence : MMC1 -> MMC0 -> UART0 -> USB0" + newline);}\r
135 if (boot_sequence == 0x1D) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);}\r
136 if (boot_sequence == 0x1E) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);}\r
137 if (boot_sequence == 0x1F) {file.write(" * Boot Sequence : Fast External Boot -> EMAC1 -> UART0 -> Reserved" + newline);}\r
138 \r
139 // ROM: Tracing Vector 1\r
140 file.write(newline);\r
141 reg_val = printRegisterValue(debugSessionDAP, "ROM: Current tracing vector, word 1", 0x4030CE40);\r
142 if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [General] Passed the public reset vector" + newline);}\r
143 if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [General] Entered main function" + newline);}\r
144 if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [General] Running after the cold reset" + newline);}\r
145 if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Boot] Main booting routine entered" + newline);}\r
146 if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Memory booting started" + newline);}\r
147 if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Peripheral Boot] Peripheral booting started" + newline);}\r
148 if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [Boot] Booting loop reached last device" + newline);}\r
149 if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Boot] GP header found" + newline);}\r
150 if (reg_val & 1<<8 ) {file.write(" * Bit 8 : [Boot] Reserved" + newline);}\r
151 if (reg_val & 1<<9 ) {file.write(" * Bit 9 : [Boot] Reserved" + newline);}\r
152 if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Peripheral Boot] Reserved" + newline);}\r
153 if (reg_val & 1<<11 ) {file.write(" * Bit 11 : [Peripheral Boot] Reserved" + newline);}\r
154 if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Peripheral Boot] Device initialized" + newline);}\r
155 if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Peripheral Boot] ASIC ID sent" + newline);}\r
156 if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Peripheral Boot] Image received" + newline);}\r
157 if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Peripheral Boot] Peripheral booting failed" + newline);}\r
158 if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Peripheral Boot] Booting Message not received (timeout)" + newline);}\r
159 if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Image size not received (timeout)" + newline);}\r
160 if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Image not received (timeout)" + newline);}\r
161 if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);}\r
162 if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Configuration Header] CHSETTINGS found" + newline);}\r
163 if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Configuration Header] CHSETTINGS executed" + newline);}\r
164 if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Configuration Header] CHRAM executed" + newline);}\r
165 if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Configuration Header] CHFLASH executed" + newline);}\r
166 if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Configuration Header] CHMMCSD clocks executed" + newline);}\r
167 if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Configuration Header] CHMMCSD bus width executed" + newline);}\r
168 if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);}\r
169 if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);}\r
170 if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);}\r
171 if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}\r
172 if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}\r
173 if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}\r
174 \r
175 // ROM: Tracing Vector 2\r
176 file.write(newline);\r
177 reg_val = printRegisterValue(debugSessionDAP, "ROM: Current tracing vector, word 1", 0x4030CE44);\r
178 if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Companion chip] Reserved" + newline);}\r
179 if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Companion chip] Reserved" + newline);}\r
180 if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Companion chip] Reserved" + newline);}\r
181 if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Companion chip] Reserved" + newline);}\r
182 if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [USB] USB connect" + newline);}\r
183 if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [USB] USB configured state" + newline);}\r
184 if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [USB] USB VBUS valid" + newline);}\r
185 if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [USB] USB session valid" + newline);}\r
186 if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);}\r
187 if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);}\r
188 if (reg_val & 1<<10 ) {file.write(" * Bit 10 : Reserved" + newline);}\r
189 if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);}\r
190 if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Memory Boot] Memory booting trial 0" + newline);}\r
191 if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Memory Boot] Memory booting trial 1" + newline);}\r
192 if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Memory Boot] Memory booting trial 2" + newline);}\r
193 if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Memory Boot] Memory booting trial 3" + newline);}\r
194 if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Memory Boot] Execute GP image" + newline);}\r
195 if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Start authentication of peripheral boot image" + newline);}\r
196 if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Memory & Peripheral Boot] Jumping to Initial SW" + newline);}\r
197 if (reg_val & 1<<19 ) {file.write(" * Bit 19 : [Memory & Peripheral Boot] Reserved" + newline);}\r
198 if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Memory & Peripheral Boot] Start image authentication" + newline);}\r
199 if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Memory & Peripheral Boot] Image authentication failed" + newline);}\r
200 if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Memory & Peripheral Boot] Analyzing SpeedUp" + newline);}\r
201 if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Memory & Peripheral Boot] SpeedUp failed" + newline);}\r
202 if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Memory & Peripheral Boot] Reserved" + newline);}\r
203 if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Memory & Peripheral Boot] Reserved" + newline);}\r
204 if (reg_val & 1<<26 ) {file.write(" * Bit 26 : [Memory & Peripheral Boot] Reserved" + newline);}\r
205 if (reg_val & 1<<27 ) {file.write(" * Bit 27 : [Memory & Peripheral Boot] Reserved" + newline);}\r
206 if (reg_val & 1<<28 ) {file.write(" * Bit 28 : [Memory & Peripheral Boot] Authentication procedure failed" + newline);}\r
207 if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}\r
208 if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}\r
209 if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}\r
210 \r
211 \r
212 // ROM: Tracing Vector 3\r
213 file.write(newline);\r
214 reg_val = printRegisterValue(debugSessionDAP, "ROM: Current tracing vector, word 1", 0x4030CE48);\r
215 if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Memory Boot] Memory booting device NULL" + newline);}\r
216 if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Memory Boot] Memory booting device XIP" + newline);}\r
217 if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Memory Boot] Memory booting device XIPWAIT" + newline);}\r
218 if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Memory Boot] Memory booting device NAND" + newline);}\r
219 if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Reserved" + newline);}\r
220 if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Memory Boot] Memory booting device MMCSD0" + newline);}\r
221 if (reg_val & 1<<6 ) {file.write(" * Bit 6 : Reserved" + newline);}\r
222 if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Memory Boot] Memory booting device MMCSD1" + newline);}\r
223 if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);}\r
224 if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);}\r
225 if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Memory Boot] Reserved" + newline);}\r
226 if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);}\r
227 if (reg_val & 1<<12 ) {file.write(" * Bit 12 : Memory booting device SPI" + newline);}\r
228 if (reg_val & 1<<13 ) {file.write(" * Bit 13 : Reserved" + newline);}\r
229 if (reg_val & 1<<14 ) {file.write(" * Bit 14 : Reserved" + newline);}\r
230 if (reg_val & 1<<15 ) {file.write(" * Bit 15 : Reserved" + newline);}\r
231 if (reg_val & 1<<16 ) {file.write(" * Bit 16 : Peripheral booting device UART0" + newline);}\r
232 if (reg_val & 1<<17 ) {file.write(" * Bit 17 : Reserved" + newline);}\r
233 if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Reserved" + newline);}\r
234 if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);}\r
235 if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Peripheral Boot] Peripheral booting device USB" + newline);}\r
236 if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Peripheral Boot] Reserved" + newline);}\r
237 if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Peripheral Boot] Peripheral booting device GPGMAC0" + newline);}\r
238 if (reg_val & 1<<23 ) {file.write(" * Bit 23 : Reserved" + newline);}\r
239 if (reg_val & 1<<24 ) {file.write(" * Bit 24 : Peripheral booting device NULL" + newline);}\r
240 if (reg_val & 1<<25 ) {file.write(" * Bit 25 : Reserved" + newline);}\r
241 if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);}\r
242 if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);}\r
243 if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);}\r
244 if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}\r
245 if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}\r
246 if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}\r
247 \r
248 // ROM: Copy of PRM_RSTST\r
249 file.write(newline);\r
250 reg_val = printRegisterValue(debugSessionDAP, "ROM: Current copy of PRM_RSTST", 0x4030CE4C);\r
251 if (reg_val & 1<<0 ) {file.write(" * Bit 0 : GLOBAL_COLD_RST" + newline);}\r
252 if (reg_val & 1<<1 ) {file.write(" * Bit 1 : GLOBAL_WARM_RST" + newline);}\r
253 if (reg_val & 1<<4 ) {file.write(" * Bit 4 : WDT1_RST" + newline);}\r
254 if (reg_val & 1<<5 ) {file.write(" * Bit 5 : EXTERNAL_WARM_RST" + newline);}\r
255 \r
256 // ROM: Cold Reset Tracing Vector 1\r
257 file.write(newline);\r
258 reg_val = printRegisterValue(debugSessionDAP, "ROM: Cold reset tracing vector, word 1", 0x4030CE50);\r
259 if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [General] Passed the public reset vector" + newline);}\r
260 if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [General] Entered main function" + newline);}\r
261 if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [General] Running after the cold reset" + newline);}\r
262 if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Boot] Main booting routine entered" + newline);}\r
263 if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Memory booting started" + newline);}\r
264 if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Peripheral Boot] Peripheral booting started" + newline);}\r
265 if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [Boot] Booting loop reached last device" + newline);}\r
266 if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Boot] GP header found" + newline);}\r
267 if (reg_val & 1<<8 ) {file.write(" * Bit 8 : [Boot] Reserved" + newline);}\r
268 if (reg_val & 1<<9 ) {file.write(" * Bit 9 : [Boot] Reserved" + newline);}\r
269 if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Peripheral Boot] Reserved" + newline);}\r
270 if (reg_val & 1<<11 ) {file.write(" * Bit 11 : [Peripheral Boot] Reserved" + newline);}\r
271 if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Peripheral Boot] Device initialized" + newline);}\r
272 if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Peripheral Boot] ASIC ID sent" + newline);}\r
273 if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Peripheral Boot] Image received" + newline);}\r
274 if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Peripheral Boot] Peripheral booting failed" + newline);}\r
275 if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Peripheral Boot] Booting Message not received (timeout)" + newline);}\r
276 if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Image size not received (timeout)" + newline);}\r
277 if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Image not received (timeout)" + newline);}\r
278 if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);}\r
279 if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Configuration Header] CHSETTINGS found" + newline);}\r
280 if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Configuration Header] CHSETTINGS executed" + newline);}\r
281 if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Configuration Header] CHRAM executed" + newline);}\r
282 if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Configuration Header] CHFLASH executed" + newline);}\r
283 if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Configuration Header] CHMMCSD clocks executed" + newline);}\r
284 if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Configuration Header] CHMMCSD bus width executed" + newline);}\r
285 if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);}\r
286 if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);}\r
287 if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);}\r
288 if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}\r
289 if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}\r
290 if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}\r
291 \r
292 // ROM: Cold Reset Tracing Vector 2\r
293 file.write(newline);\r
294 reg_val = printRegisterValue(debugSessionDAP, "ROM: Cold reset tracing vector, word 1", 0x4030CE54);\r
295 if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Companion chip] Reserved" + newline);}\r
296 if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Companion chip] Reserved" + newline);}\r
297 if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Companion chip] Reserved" + newline);}\r
298 if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Companion chip] Reserved" + newline);}\r
299 if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [USB] USB connect" + newline);}\r
300 if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [USB] USB configured state" + newline);}\r
301 if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [USB] USB VBUS valid" + newline);}\r
302 if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [USB] USB session valid" + newline);}\r
303 if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);}\r
304 if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);}\r
305 if (reg_val & 1<<10 ) {file.write(" * Bit 10 : Reserved" + newline);}\r
306 if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);}\r
307 if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Memory Boot] Memory booting trial 0" + newline);}\r
308 if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Memory Boot] Memory booting trial 1" + newline);}\r
309 if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Memory Boot] Memory booting trial 2" + newline);}\r
310 if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Memory Boot] Memory booting trial 3" + newline);}\r
311 if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Memory Boot] Execute GP image" + newline);}\r
312 if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Start authentication of peripheral boot image" + newline);}\r
313 if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Memory & Peripheral Boot] Jumping to Initial SW" + newline);}\r
314 if (reg_val & 1<<19 ) {file.write(" * Bit 19 : [Memory & Peripheral Boot] Reserved" + newline);}\r
315 if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Memory & Peripheral Boot] Start image authentication" + newline);}\r
316 if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Memory & Peripheral Boot] Image authentication failed" + newline);}\r
317 if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Memory & Peripheral Boot] Analyzing SpeedUp" + newline);}\r
318 if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Memory & Peripheral Boot] SpeedUp failed" + newline);}\r
319 if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Memory & Peripheral Boot] Reserved" + newline);}\r
320 if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Memory & Peripheral Boot] Reserved" + newline);}\r
321 if (reg_val & 1<<26 ) {file.write(" * Bit 26 : [Memory & Peripheral Boot] Reserved" + newline);}\r
322 if (reg_val & 1<<27 ) {file.write(" * Bit 27 : [Memory & Peripheral Boot] Reserved" + newline);}\r
323 if (reg_val & 1<<28 ) {file.write(" * Bit 28 : [Memory & Peripheral Boot] Authentication procedure failed" + newline);}\r
324 if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}\r
325 if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}\r
326 if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}\r
327 \r
328 // ROM: Cold Reset Tracing Vector 3\r
329 file.write(newline);\r
330 reg_val = printRegisterValue(debugSessionDAP, "ROM: Cold reset tracing vector, word 1", 0x4030CE58);\r
331 if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Memory Boot] Memory booting device NULL" + newline);}\r
332 if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Memory Boot] Memory booting device XIP" + newline);}\r
333 if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Memory Boot] Memory booting device XIPWAIT" + newline);}\r
334 if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Memory Boot] Memory booting device NAND" + newline);}\r
335 if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Reserved" + newline);}\r
336 if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Memory Boot] Memory booting device MMCSD0" + newline);}\r
337 if (reg_val & 1<<6 ) {file.write(" * Bit 6 : Reserved" + newline);}\r
338 if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Memory Boot] Memory booting device MMCSD1" + newline);}\r
339 if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);}\r
340 if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);}\r
341 if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Memory Boot] Reserved" + newline);}\r
342 if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);}\r
343 if (reg_val & 1<<12 ) {file.write(" * Bit 12 : Memory booting device SPI" + newline);}\r
344 if (reg_val & 1<<13 ) {file.write(" * Bit 13 : Reserved" + newline);}\r
345 if (reg_val & 1<<14 ) {file.write(" * Bit 14 : Reserved" + newline);}\r
346 if (reg_val & 1<<15 ) {file.write(" * Bit 15 : Reserved" + newline);}\r
347 if (reg_val & 1<<16 ) {file.write(" * Bit 16 : Peripheral booting device UART0" + newline);}\r
348 if (reg_val & 1<<17 ) {file.write(" * Bit 17 : Reserved" + newline);}\r
349 if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Reserved" + newline);}\r
350 if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);}\r
351 if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Peripheral Boot] Peripheral booting device USB" + newline);}\r
352 if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Peripheral Boot] Reserved" + newline);}\r
353 if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Peripheral Boot] Peripheral booting device GPGMAC0" + newline);}\r
354 if (reg_val & 1<<23 ) {file.write(" * Bit 23 : Reserved" + newline);}\r
355 if (reg_val & 1<<24 ) {file.write(" * Bit 24 : Peripheral booting device NULL" + newline);}\r
356 if (reg_val & 1<<25 ) {file.write(" * Bit 25 : Reserved" + newline);}\r
357 if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);}\r
358 if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);}\r
359 if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);}\r
360 if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}\r
361 if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}\r
362 if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}\r
363 \r
364 \r
365 debugSessionDAP.target.disconnect();\r
366 \r
367 \r
368 debugSessionA8 = ds.openSession("*","CortxA8");\r
369 debugSessionA8.target.connect();\r
370 \r
371 // Get value of ARM Program Counter\r
372 value = debugSessionA8.memory.readRegister("PC");\r
373 value_string = d2h(value);\r
374 file.write(newline + "Cortex A8 Program Counter = 0x" + value_string + newline);\r
375 \r
376 file.write(newline);\r
377 file.write("ROM Exception Vectors" + newline);\r
378 file.write(" * 0x4030CE04 Undefined" + newline);\r
379 file.write(" * 0x4030CE08 SWI" + newline);\r
380 file.write(" * 0x4030CE0C Pre-fetch abort" + newline);\r
381 file.write(" * 0x4030CE10 Data abort" + newline);\r
382 file.write(" * 0x4030CE14 Unused" + newline);\r
383 file.write(" * 0x4030CE18 IRQ" + newline);\r
384 file.write(" * 0x4030CE1C FIQ" + newline);\r
385 \r
386 file.write(newline);\r
387 file.write("ROM Dead Loops" + newline);\r
388 file.write(" * 0x00020080 Undefined exception default handler" + newline);\r
389 file.write(" * 0x00020084 SWI exception default handler" + newline);\r
390 file.write(" * 0x00020088 Pre-fetch abort exception default handler" + newline);\r
391 file.write(" * 0x0002008C Data exception default handler" + newline);\r
392 file.write(" * 0x00020090 Unused exception default handler" + newline);\r
393 file.write(" * 0x00020094 IRQ exception default handler" + newline);\r
394 file.write(" * 0x00020098 FIQ exception default handler" + newline);\r
395 file.write(" * 0x0002009C Validation test PASS" + newline);\r
396 file.write(" * 0x000200A0 Validation test FAIL" + newline);\r
397 file.write(" * 0x000200A4 Reserved" + newline);\r
398 file.write(" * 0x000200A8 Image not executed or returned" + newline);\r
399 file.write(" * 0x000200AC Reserved" + newline);\r
400 file.write(" * 0x000200B0 Reserved" + newline);\r
401 file.write(" * 0x000200B4 Reserved" + newline);\r
402 file.write(" * 0x000200B8 Reserved" + newline);\r
403 file.write(" * 0x000200BC Reserved" + newline);\r
404 \r
405 debugSessionA8.target.disconnect();\r
406 file.close();\r