1 /*
2 * Copyright (c) 2006-2014, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 function d2h(d) {return ("00000000" + (d).toString(16)).slice(-8);}
36 // helper function to create decimal numbers in ascii format
37 function d2d(d) {return ((+d).toString());}
39 function printRegisterValue(ds, name, addr)
40 {
41 value = debugSessionDAP.memory.readWord(0,addr,false);
42 value_string = d2h(value);
43 file.write(name + " = 0x" + value_string + "\n");
44 return value; // return the register value for interrogation
45 }
47 function getRegisterValue(debug, addr)
48 {
49 return debug.memory.readWord(0,addr,false);
50 }
52 function interpret_cmd_phy_macro(value, index)
53 {
54 WD1 = (value >> (21+index)) & 1;
55 WD0 = (value >> (10+index)) & 1;
56 WD = (WD1 << 1) | WD0;
57 if (WD == 0) return_string = "Pullup/Pulldown disabled\n";
58 if (WD == 1) return_string = "Weak pullup enabled\n";
59 if (WD == 2) return_string = "Weak pulldown enabled\n";
60 if (WD == 3) return_string = "Weak keeper enabled\n";
61 return return_string;
62 }
64 function interpret_data_phy_macro(value, index)
65 {
66 WD1 = (value >> (20+index)) & 1;
67 WD0 = (value >> (10+index)) & 1;
68 WD = (WD1 << 1) | WD0;
69 if (WD == 0) return_string = "Pullup/Pulldown disabled\n";
70 if (WD == 1) return_string = "Weak pullup enabled\n";
71 if (WD == 2) return_string = "Weak pulldown enabled\n";
72 if (WD == 3) return_string = "Weak keeper enabled\n";
73 return return_string;
74 }
76 // Inputs:
77 // Data - 32-bit register value
78 // Upper - Highest bit to keep
79 // Lower - Lowest bit to keep
80 // (bit 0 refers to LSB, bit 31 to MSB)
81 // Return: right aligned data
82 function bits32(data, upper, lower)
83 {
84 data = data >>> lower; // unsigned right-shift
85 upper = upper - lower;
86 bitmask = 0xFFFFFFFF >>> (31 - upper);
87 return (data & bitmask);
88 }
90 // Build a filename that includes date/time
91 var today = new Date();
92 var year4digit = today.getFullYear();
93 var month2digit = ("0" + (today.getMonth()+1)).slice(-2);
94 var day2digit = ("0" + today.getDate()).slice(-2);
95 var hour2digit = ("0" + today.getHours()).slice(-2);
96 var minutes2digit = ("0" + today.getMinutes()).slice(-2);
97 var seconds2digit = ("0" + today.getSeconds()).slice(-2);
98 var filename_date = '_' + year4digit + '-' + month2digit + '-' + day2digit + '_' + hour2digit + minutes2digit + seconds2digit;
99 var userHomeFolder = System.getProperty("user.home");
100 var filename = userHomeFolder + '/Desktop/' + 'am335x-ddr-analysis' + filename_date + '.txt';
102 debugSessionDAP = ds.openSession("*","CS_DAP_M3");
103 use_dap_m3 = 1;
105 try {
106 debugSessionDAP.target.connect();
107 } catch (ex) {
108 print("\n ERROR: Could not connect to DAP_M3.\n");
109 }
111 // Do a test read of Device_ID register at 0x44e10600
112 value = debugSessionDAP.memory.readWord(0,0x44e10600,false);
114 // If it is zero, switch to CS_DAP_DebugSS
115 if (value == 0)
116 {
117 debugSessionDAP.target.disconnect();
118 debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS");
119 debugSessionDAP.target.connect();
120 use_dap_m3 = 0;
121 }
123 var original_CM_WKUP_DEBUGSS_CLKCTRL = debugSessionDAP.memory.readWord(0,0x44e00414,false);
124 var original_CM_PER_L3_CLKSTCTRL = debugSessionDAP.memory.readWord(0,0x44E0000C,false);
125 var newline = "\n";
127 file = new java.io.FileWriter(filename);
129 // Only try to read EMIF registers if EMIF clock is enabled
130 if (original_CM_PER_L3_CLKSTCTRL & 1<<2) {
132 // CM_WKUP_DEBUGSS_CLKCTRL[MODULEMODE] = ENABLED
133 debugSessionDAP.expression.evaluate(
134 "*((unsigned int*) 0x44e00414 ) |= 0x2;");
136 debugSessionDAP.target.disconnect(); // disconnect from DAP_M3
138 // Connect to DAP_DebugSS for L3 visibility (EMIF regs)
139 debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS");
140 debugSessionDAP.target.connect();
142 var reg_val;
144 // CONTROL: device_id
145 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: device_id", 0x44E10600);
146 if ( (reg_val & 0x0FFFFFFF) == 0xb94402e ) {file.write(" * AM335x family" + newline);}
147 if ( (reg_val & 0xF0000000) == (0 << 28) ) {file.write(" * Silicon Revision 1.0" + newline);}
148 if ( (reg_val & 0xF0000000) == (1 << 28) ) {file.write(" * Silicon Revision 2.0" + newline);}
149 if ( (reg_val & 0xF0000000) == (2 << 28) ) {file.write(" * Silicon Revision 2.1" + newline);}
151 // CONTROL: control_status
152 file.write(newline);
153 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: control_status", 0x44E10040);
154 speedselect_pins = bits32(reg_val, 23, 22);
155 switch (speedselect_pins) {
156 case 0:
157 file.write(" * SYSBOOT[15:14] = 00b (19.2 MHz)" + newline);
158 input_clock = 19.2;
159 break;
160 case 1:
161 file.write(" * SYSBOOT[15:14] = 01b (24 MHz)" + newline);
162 input_clock = 24;
163 break;
164 case 2:
165 file.write(" * SYSBOOT[15:14] = 10b (25 MHz)" + newline);
166 input_clock = 25;
167 break;
168 case 3:
169 file.write(" * SYSBOOT[15:14] = 11b (26 MHz)" + newline);
170 input_clock = 26;
171 break;
172 }
174 // CM_CLKSEL_DPLL_DDR
175 reg_val = printRegisterValue(debugSessionDAP, "CM_CLKSEL_DPLL_DDR", 0x44E00440);
176 dpll_mult = bits32(reg_val, 18, 8);
177 file.write(" * DPLL_MULT = " + d2d(dpll_mult) + " (x" + d2d(dpll_mult) + ")" + newline);
178 dpll_div = bits32(reg_val, 6, 0);
179 file.write(" * DPLL_DIV = " + d2d(dpll_div) + " (/" + d2d(dpll_div+1) + ")" + newline);
180 f_dpll_ddr = input_clock*2*dpll_mult/(dpll_div+1);
182 // CM_DIV_M2_DPLL_DDR
183 reg_val = printRegisterValue(debugSessionDAP, "CM_DIV_M2_DPLL_DDR", 0x44E004A0);
184 if (reg_val & (1<<9)) // CLKST = 1
185 file.write(" * CLKST = 1: M2 output clock enabled" + newline);
186 else
187 file.write(" * CLKST = 0: M2 output clock disabled" + newline);;
188 div_m2 = reg_val & 0x1F;
189 file.write(" * DIVHS = " + d2d(div_m2) + " (/" + d2d(div_m2) + ")" + newline);
191 file.write(newline + "DPLL_DDR Summary" + newline);
192 file.write(" -> F_input = " + d2d(input_clock) + " MHz" + newline);
193 file.write(" -> CLKOUT_M2 = DDR_PLL_CLKOUT = " + f_dpll_ddr / 2 / div_m2 + " MHz" + newline);
195 // EMIF: SDRAM_CONFIG
196 file.write(newline);
197 reg_val = printRegisterValue(debugSessionDAP, "EMIF: SDRAM_CONFIG", 0x4C000008);
198 reg_sdram_type = bits32(reg_val, 31, 29);
199 reg_ibank_pos = bits32(reg_val, 28, 27);
200 reg_ddr_term = bits32(reg_val, 26, 24);
201 reg_ddr2_ddqs = bits32(reg_val, 23, 23);
202 reg_dyn_odt = bits32(reg_val, 22, 21);
203 reg_ddr_disable_dll = bits32(reg_val, 20, 20);
204 reg_sdram_drive = bits32(reg_val, 19, 18);
205 reg_cwl = bits32(reg_val, 17, 16);
206 reg_narrow_mode = bits32(reg_val, 15, 14);
207 reg_cl = bits32(reg_val, 13, 10);
208 reg_rowsize = bits32(reg_val, 9, 7);
209 reg_ibank = bits32(reg_val, 6, 4);
210 reg_ebank = bits32(reg_val, 3, 3);
211 reg_pagesize = bits32(reg_val, 2, 0);
213 var is_ddr3=0;
214 var is_ddr2=0;
215 var is_lpddr=0;
217 switch (reg_sdram_type) {
218 case 0:
219 file.write(" * ERROR! Unsupported memory type (DDR1)" + newline);
220 break;
221 case 1:
222 file.write(" * Bits 31:29 (reg_sdram_type) set for LPDDR" + newline);
223 is_lpddr=1;
224 break;
225 case 2:
226 file.write(" * Bits 31:29 (reg_sdram_type) set for DDR2" + newline);
227 is_ddr2=1;
228 break;
229 case 3:
230 file.write(" * Bits 31:29 (reg_sdram_type) set for DDR3" + newline);
231 is_ddr3=1;
232 break;
233 default:
234 file.write(" * Bits 31:29 (reg_sdram_type) set to invalid selection!" + newline);
235 }
236 file.write(" * Bits 28:27 (reg_ibank_pos) set to " + d2d(reg_ibank_pos) + newline);
237 if (is_ddr3 == 1) {
238 file.write(" * Bits 26:24 (reg_ddr_term) set for ");
239 if ( reg_ddr_term == 0 ) {file.write("termination disabled (000b)\n");}
240 if ( reg_ddr_term == 1 ) {file.write("RZQ/4 (001b)\n");}
241 if ( reg_ddr_term == 2 ) {file.write("RZQ/2 (010b)\n");}
242 if ( reg_ddr_term == 3 ) {file.write("RZQ/6 (011b)\n");}
243 if ( reg_ddr_term == 4 ) {file.write("RZQ/12 (100b)\n");}
244 if ( reg_ddr_term == 5 ) {file.write("RZQ/8 (101b)\n");}
245 if ( reg_ddr_term == 6 ) {file.write("ERROR\n");}
246 if ( reg_ddr_term == 7 ) {file.write("ERROR\n");}
247 }
248 if (is_ddr2 == 1) {
249 file.write(" * Bits 26:24 (reg_ddr_term) set for ");
250 if ( reg_ddr_term == 0 ) {file.write("termination disabled (000b)\n");}
251 if ( reg_ddr_term == 1 ) {file.write("75 Ohm (001b)\n");}
252 if ( reg_ddr_term == 2 ) {file.write("150 Ohm (010b)\n");}
253 if ( reg_ddr_term == 3 ) {file.write("50 Ohm (011b)\n");}
254 if ( reg_ddr_term == 4 ) {file.write("ERROR\n");}
255 if ( reg_ddr_term == 5 ) {file.write("ERROR\n");}
256 if ( reg_ddr_term == 6 ) {file.write("ERROR\n");}
257 if ( reg_ddr_term == 7 ) {file.write("ERROR\n");}
258 }
259 if (is_ddr2 == 1) {
260 file.write(" * Bit 23 (reg_ddr2_ddqs) set to ");
261 if ( bits32(reg_val, 23, 23) == 0 ) {
262 file.write("single ended DQS." + newline);
263 } else {
264 file.write("differential DQS." + newline);
265 }
266 }
267 if (is_ddr3 == 1) {
268 file.write(" * Bits 22:21 (reg_dyn_odt) DDR3 dynamic ODT ");
269 if (reg_dyn_odt == 0)
270 file.write("disabled" + newline);
271 else if (reg_dyn_odt == 1)
272 file.write("set to RZQ / 4" + newline);
273 else if (reg_dyn_odt == 2)
274 file.write("set to RZQ / 2" + newline);
275 else
276 file.write("ERROR (illegal value)" + newline);
277 if (reg_ddr_disable_dll == 0)
278 file.write(" * Bit 20 (reg_ddr_disable_dll) set to 0, DDR3 DLL enabled" + newline);
279 else
280 file.write(" * Bit 20 (reg_ddr_disable_dll) set to 1, DDR3 DLL disabled" + newline);
281 file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
282 if ( reg_sdram_drive == 0 ) {file.write("RZQ/6 (00b)\n");}
283 if ( reg_sdram_drive == 1 ) {file.write("RZQ/7 (01b)\n");}
284 if ( reg_sdram_drive == 2 ) {file.write("ERROR (10b)\n");}
285 if ( reg_sdram_drive == 3 ) {file.write("ERROR (11b)\n");}
286 }
287 if (is_lpddr == 1) {
288 file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
289 if ( reg_sdram_drive == 0 ) {file.write("full strength (00b)\n");}
290 if ( reg_sdram_drive == 1 ) {file.write("half strength (01b)\n");}
291 if ( reg_sdram_drive == 2 ) {file.write("quarter strength (10b)\n");}
292 if ( reg_sdram_drive == 3 ) {file.write("eighth strength (11b)\n");}
293 }
294 if (is_ddr2 == 1) {
295 file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
296 if ( reg_sdram_drive == 0 ) {file.write("normal drive (00b)\n");}
297 if ( reg_sdram_drive == 1 ) {file.write("weak drive (01b)\n");}
298 if ( reg_sdram_drive == 2 ) {file.write("ERROR (10b)\n");}
299 if ( reg_sdram_drive == 3 ) {file.write("ERROR (11b)\n");}
300 }
301 if (is_ddr3 == 1) {
302 file.write(" * Bits 17:16 (reg_cwl) set for " + d2d(reg_cwl) + ", CWL = " + d2d(reg_cwl+5) + newline);
303 }
304 if (reg_narrow_mode == 1)
305 file.write(" * Bits 15:14 (reg_narrow_mode) set to 1 -> 16-bit EMIF interface" + newline);
306 else
307 file.write(" * Bits 15:14 (reg_narrow_mode) set to ILLEGAL VALUE" + newline);
308 file.write(" * Bits 13:10 (reg_cl) set to " + d2d(reg_cl) + " -> CL = ");
309 decoded_CL = 0;
310 if (is_ddr2 == 1) {
311 switch (reg_cl) {
312 case 2:
313 case 3:
314 case 4:
315 case 5:
316 decoded_CL = reg_cl;
317 file.write(d2d(decoded_CL) + newline);
318 break;
319 default:
320 file.write("ILLEGAL VALUE" + newline);
321 break;
322 }
323 }
324 if (is_ddr3 == 1) {
325 switch (reg_cl) {
326 case 2:
327 case 4:
328 case 6:
329 case 8:
330 case 10:
331 case 12:
332 case 14:
333 decoded_CL = reg_cl/2 + 4;
334 file.write(d2d(decoded_CL) + newline);
335 break;
336 default:
337 file.write("ILLEGAL VALUE" + newline);
338 break;
339 }
340 }
341 if (is_lpddr == 1) {
342 switch (reg_cl) {
343 case 2:
344 case 3:
345 decoded_CL = reg_cl;
346 file.write(d2d(decoded_CL) + newline);
347 break;
348 default:
349 file.write("ILLEGAL VALUE" + newline);
350 break;
351 }
352 }
353 file.write(" * Bits 09:07 (reg_rowsize) set to " + d2d(reg_rowsize) + " -> " + d2d(reg_rowsize+9) + " row bits" + newline);
354 file.write(" * Bits 06:04 (reg_ibank) set to " + d2d(reg_ibank) + " -> ");
355 switch (reg_ibank) {
356 case 0:
357 case 1:
358 case 2:
359 case 3:
360 file.write(d2d(Math.pow(2,reg_ibank)) + " banks" + newline);
361 break;
362 default:
363 file.write("ILLEGAL VALUE" + newline);
364 break;
365 }
366 if (reg_ebank == 1)
367 file.write(" * Bit 03 ERROR, only 1 chip select allowed!" + newline);
368 file.write(" * Bits 02:00 (reg_pagesize) set to " + d2d(reg_pagesize) + " -> ");
369 switch (reg_pagesize) {
370 case 0:
371 case 1:
372 case 2:
373 case 3:
374 file.write(d2d(reg_pagesize+8) + " column bits" + newline);
375 break;
376 default:
377 file.write("ILLEGAL VALUE" + newline);
378 break;
379 }
381 // EMIF: PWR_MGMT_CTRL
382 file.write(newline);
383 reg_val = printRegisterValue(debugSessionDAP, "EMIF: PWR_MGMT_CTRL", 0x4C000038);
384 reg_lp_mode = bits32(reg_val, 10, 8);
385 switch (reg_lp_mode) {
386 case 1:
387 file.write(" * Bits 10:8 reg_lp_mode set to 1, clock stop mode (WARNING!)" + newline);
388 break;
389 case 2:
390 file.write(" * Bits 10:8 reg_lp_mode set to 2, self refresh (WARNING!)" + newline);
391 break;
392 case 4:
393 file.write(" * Bits 10:8 reg_lp_mode set to 4, power down (WARNING!)" + newline);
394 break;
395 default:
396 file.write(" * Bits 10:8 reg_lp_mode set to " + d2d(reg_lp_mode) + ", auto power management disabled" + newline);
397 break;
398 }
399 if ( (reg_val & 0xF0) < 0x90 ) {
400 file.write(" * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit\n");
401 file.write(" * Please see the silicon errata for more details.\n");
402 }
404 // DDR PHY: DDR_PHY_CTRL_1
405 file.write(newline);
406 reg_val = printRegisterValue(debugSessionDAP, "DDR PHY: DDR_PHY_CTRL_1", 0x4C0000E4);
407 if ( (reg_val & 1<<20) == 0 ) {file.write(" * WARNING: reg_phy_enable_dynamic_pwrdn disabled.\n");}
408 reg_phy_rd_local_odt = bits32(reg_val, 9, 8);
409 file.write(" * Bits 9:8 (reg_phy_rd_local_odt) to " + d2d(reg_phy_rd_local_odt) + " -> ");
410 switch (reg_phy_rd_local_odt) {
411 case 0:
412 case 1:
413 file.write("no termination" + newline);
414 if (is_ddr3 == 1)
415 file.write(" -> Read termination is highly recommended in general for best DDR3 signal integrity" + newline);
416 break;
417 case 2:
418 file.write("full thevenin termination\n");
419 break;
420 case 3:
421 file.write("half thevenin termination\n");
422 break;
423 default:
424 file.write("ILLEGAL VALUE" + newline);
425 break;
426 }
427 reg_read_latency = bits32(reg_val, 4, 0);
428 if( reg_read_latency < decoded_CL+1 )
429 file.write(" * Bits 4:0 (reg_read_latency) set to " + d2d(reg_read_latency) + " -> ERROR: TOO SMALL" + newline);
430 else if (reg_read_latency == decoded_CL+1) {
431 file.write(" * Bits 4:0 (reg_read_latency) set to " + d2d(reg_read_latency) + newline);
432 file.write(" -> If PHY_INVERT_CLKOUT=0, this is an appropriate value." + newline);
433 file.write(" -> If PHY_INVERT_CLKOUT=1, this is too small." + newline);
434 file.write(" -> PHY_INVERT_CLKOUT is a write-only register, so this needs to be" + newline);
435 file.write(" -> inspected closely in the code and RatioSeed spreadsheet." + newline);
436 } else
437 file.write(" * Bits 4:0 (reg_read_latency) set to " + d2d(reg_read_latency) + " -> Ok: CL+2 is typical with PHY_INVERT_CLKOUT=1." + newline);
439 file.write("\n");
440 file.write("*********************\n");
441 file.write("*** Register Dump ***\n")
442 file.write("*********************\n\n");
444 var ddr_config_regs = [
445 0x4C000000,
446 0x4C000004,
447 0x4C000008,
448 0x4C00000C,
449 0x4C000010,
450 0x4C000014,
451 0x4C000018,
452 0x4C00001C,
453 0x4C000020,
454 0x4C000024,
455 0x4C000028,
456 0x4C00002C,
457 0x4C000038,
458 0x4C00003C,
459 0x4C000054,
460 0x4C000058,
461 0x4C00005C,
462 0x4C000080,
463 0x4C000084,
464 0x4C000088,
465 0x4C00008C,
466 0x4C000090,
467 0x4C000098,
468 0x4C00009C,
469 0x4C0000A4,
470 0x4C0000AC,
471 0x4C0000B4,
472 0x4C0000BC,
473 0x4C0000C8,
474 0x4C0000D4,
475 0x4C0000D8,
476 0x4C0000DC,
477 0x4C0000E4,
478 0x4C0000E8,
479 0x4C000100,
480 0x4C000104,
481 0x4C000108,
482 0x4C000120];
484 for (i=0; i<ddr_config_regs.length; i++)
485 {
486 reg_val = getRegisterValue(debugSessionDAP, ddr_config_regs[i]);
487 file.write("*(0x" + d2h(ddr_config_regs[i]) + ")"); // Address
488 file.write(" = 0x" + d2h(reg_val) + "\n"); // Raw Reg Val
489 }
491 if ( use_dap_m3 == 1 ) {
492 // Close (Main) DAP session and use M3 DAP to view Control Registers
493 debugSessionDAP.target.disconnect();
494 debugSessionDAP = ds.openSession("*","CS_DAP_M3");
495 debugSessionDAP.target.connect();
496 }
498 // Restore CM_WKUP_DEBUGSS_CLKCTRL[MODULEMODE]
499 if ( (original_CM_WKUP_DEBUGSS_CLKCTRL & 3) == 0 ) {
500 debugSessionDAP.memory.writeWord(0,0x44e00414,original_CM_WKUP_DEBUGSS_CLKCTRL);
501 }
502 } else {
503 file.write("Skipping read of EMIF registers since EMIF clock disabled.\n");
504 file.write(" * EMIF registers are not readable when in DS0 state\n");
505 file.write(" * If you are attempting to enter DS0 this is normal.\n");
506 }
508 file.write("\n");
509 file.write("************************\n");
510 file.write("*** IOCTRL Registers ***\n")
511 file.write("************************\n\n");
513 // CONTROL: DDR_CMD0_IOCTRL
514 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD0_IOCTRL", 0x44E11404);
515 file.write(" * ddr_ba2 " + interpret_cmd_phy_macro(reg_val, 0));
516 file.write(" * ddr_wen " + interpret_cmd_phy_macro(reg_val, 1));
517 file.write(" * ddr_ba0 " + interpret_cmd_phy_macro(reg_val, 2));
518 file.write(" * ddr_a5 " + interpret_cmd_phy_macro(reg_val, 3));
519 file.write(" * ddr_ck " + interpret_cmd_phy_macro(reg_val, 4));
520 file.write(" * ddr_ckn " + interpret_cmd_phy_macro(reg_val, 5));
521 file.write(" * ddr_a3 " + interpret_cmd_phy_macro(reg_val, 6));
522 file.write(" * ddr_a4 " + interpret_cmd_phy_macro(reg_val, 7));
523 file.write(" * ddr_a8 " + interpret_cmd_phy_macro(reg_val, 8));
524 file.write(" * ddr_a9 " + interpret_cmd_phy_macro(reg_val, 9));
525 file.write(" * ddr_a6 " + interpret_cmd_phy_macro(reg_val, 10));
526 file.write(" * Bits 9:5 control ddr_ck and ddr_ckn\n");
527 file.write(" - Slew ");
528 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}
529 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("slow\n");}
530 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("fast\n");}
531 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("slowest\n");}
532 var drive_strength_mA = ((reg_val & 0xE0) >> 5) + 5;
533 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
534 file.write(" * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]\n");
535 file.write(" - Slew ");
536 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
537 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
538 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
539 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
540 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
541 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
543 // CONTROL: DDR_CMD1_IOCTRL
544 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD1_IOCTRL", 0x44E11408);
545 file.write(" * ddr_a15 " + interpret_cmd_phy_macro(reg_val, 1));
546 file.write(" * ddr_a2 " + interpret_cmd_phy_macro(reg_val, 2));
547 file.write(" * ddr_a12 " + interpret_cmd_phy_macro(reg_val, 3));
548 file.write(" * ddr_a7 " + interpret_cmd_phy_macro(reg_val, 4));
549 file.write(" * ddr_ba1 " + interpret_cmd_phy_macro(reg_val, 5));
550 file.write(" * ddr_a10 " + interpret_cmd_phy_macro(reg_val, 6));
551 file.write(" * ddr_a0 " + interpret_cmd_phy_macro(reg_val, 7));
552 file.write(" * ddr_a11 " + interpret_cmd_phy_macro(reg_val, 8));
553 file.write(" * ddr_casn " + interpret_cmd_phy_macro(reg_val, 9));
554 file.write(" * ddr_rasn " + interpret_cmd_phy_macro(reg_val, 10));
555 file.write(" * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn\n");
556 file.write(" - Slew ");
557 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
558 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
559 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
560 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
561 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
562 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
564 // CONTROL: DDR_CMD2_IOCTRL
565 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD2_IOCTRL", 0x44E1140C);
566 file.write(" * ddr_cke " + interpret_cmd_phy_macro(reg_val, 0));
567 file.write(" * ddr_resetn " + interpret_cmd_phy_macro(reg_val, 1));
568 file.write(" * ddr_odt " + interpret_cmd_phy_macro(reg_val, 2));
569 file.write(" * ddr_a14 " + interpret_cmd_phy_macro(reg_val, 4));
570 file.write(" * ddr_a13 " + interpret_cmd_phy_macro(reg_val, 5));
571 file.write(" * ddr_csn0 " + interpret_cmd_phy_macro(reg_val, 6));
572 file.write(" * ddr_a1 " + interpret_cmd_phy_macro(reg_val, 8));
573 file.write(" * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1\n");
574 file.write(" - Slew ");
575 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
576 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
577 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
578 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
579 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
580 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
582 // CONTROL: DDR_DATA0_IOCTRL
583 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_DATA0_IOCTRL", 0x44E11440);
584 file.write(" * ddr_d8 " + interpret_data_phy_macro(reg_val, 0));
585 file.write(" * ddr_d9 " + interpret_data_phy_macro(reg_val, 1));
586 file.write(" * ddr_d10 " + interpret_data_phy_macro(reg_val, 2));
587 file.write(" * ddr_d11 " + interpret_data_phy_macro(reg_val, 3));
588 file.write(" * ddr_d12 " + interpret_data_phy_macro(reg_val, 4));
589 file.write(" * ddr_d13 " + interpret_data_phy_macro(reg_val, 5));
590 file.write(" * ddr_d14 " + interpret_data_phy_macro(reg_val, 6));
591 file.write(" * ddr_d15 " + interpret_data_phy_macro(reg_val, 7));
592 file.write(" * ddr_dqm1 " + interpret_data_phy_macro(reg_val, 8));
593 file.write(" * ddr_dqs1 and ddr_dqsn1 " + interpret_data_phy_macro(reg_val, 9));
594 file.write(" * Bits 9:5 control ddr_dqs1, ddr_dqsn1\n");
595 file.write(" - Slew ");
596 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}
597 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("slow\n");}
598 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("fast\n");}
599 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("slowest\n");}
600 var drive_strength_mA = ((reg_val & 0xE0) >> 5) + 5;
601 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
602 file.write(" * Bits 4:0 control ddr_d[15:8], ddr_dqm1\n");
603 file.write(" - Slew ");
604 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
605 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
606 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
607 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
608 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
609 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
611 // CONTROL: DDR_DATA1_IOCTRL
612 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_DATA1_IOCTRL", 0x44E11444);
613 file.write(" * ddr_d0 " + interpret_data_phy_macro(reg_val, 0));
614 file.write(" * ddr_d1 " + interpret_data_phy_macro(reg_val, 1));
615 file.write(" * ddr_d2 " + interpret_data_phy_macro(reg_val, 2));
616 file.write(" * ddr_d3 " + interpret_data_phy_macro(reg_val, 3));
617 file.write(" * ddr_d4 " + interpret_data_phy_macro(reg_val, 4));
618 file.write(" * ddr_d5 " + interpret_data_phy_macro(reg_val, 5));
619 file.write(" * ddr_d6 " + interpret_data_phy_macro(reg_val, 6));
620 file.write(" * ddr_d7 " + interpret_data_phy_macro(reg_val, 7));
621 file.write(" * ddr_dqm0 " + interpret_data_phy_macro(reg_val, 8));
622 file.write(" * ddr_dqs0 and ddr_dqsn0 " + interpret_data_phy_macro(reg_val, 9));
623 file.write(" * Bits 9:5 control ddr_dqs0, ddr_dqsn0\n");
624 file.write(" - Slew ");
625 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}
626 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("slow\n");}
627 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("fast\n");}
628 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("slowest\n");}
629 var drive_strength_mA = ((reg_val & 0xE0) >> 5) + 5;
630 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
631 file.write(" * Bits 4:0 control ddr_d[7:0], dqm0\n");
632 file.write(" - Slew ");
633 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
634 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
635 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
636 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
637 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
638 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
640 // CONTROL: DDR_IO_CTRL
641 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_IO_CTRL", 0x44E10E04);
642 if ( (reg_val & (1 << 31)) == (1<<31) ) {
643 file.write(" * Bit 31: Overriding DDR_RESETn (expected for DS0).\n");
644 } else {
645 file.write(" * Bit 31: DDR_RESETn controlled by EMIF.\n");
646 }
647 if ( (reg_val & (1 << 28)) == 0) {
648 file.write(" * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.\n");
649 if (is_lpddr == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}
650 }
651 else {
652 file.write(" * Bit 28 (mddr_sel) configured for LVCMOS, i.e. LPDDR/mDDR operation.\n");
653 if (is_ddr2 == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}
654 if (is_ddr3 == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}
655 }
657 // CONTROL: VTP_CTRL
658 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: VTP_CTRL", 0x44E10E0C);
659 if ( reg_val == 0 ) {
660 file.write(" * VTP disabled (expected in DS0).\n");
661 } else {
662 file.write(" * VTP not disabled (expected in normal operation, but not DS0).\n");
663 }
665 // CONTROL: VREF_CTRL
666 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: VREF_CTRL", 0x44E10E14);
667 if ( (reg_val & 1) == 0 ) {
668 file.write(" * VREF supplied externally (typical).\n");
669 } else {
670 file.write(" * Internal VREF (unusual).\n");
671 }
673 // CONTROL: DDR_CKE_CTRL
674 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CKE_CTRL", 0x44E1131C);
675 if ( (reg_val & 1) == 0 ) {
676 file.write(" * CKE gated (forces pin low).\n");
677 } else {
678 file.write(" * CKE controlled by EMIF (normal/ungated operation).\n");
679 }
681 file.close();
682 print("Created file " + filename);
683 debugSessionDAP.target.disconnect();
687 //****************************************************************************
688 // getErrorCode
689 //****************************************************************************
690 function getErrorCode(exception)
691 {
692 var ex2 = exception.javaException;
693 if (ex2 instanceof Packages.com.ti.ccstudio.scripting.environment.ScriptingException)
694 {
695 return ex2.getErrorID();
696 }
697 return 0;
698 }