1 /*\r
2 * Copyright (c) 2006-2014, Texas Instruments Incorporated\r
3 * All rights reserved.\r
4 *\r
5 * Redistribution and use in source and binary forms, with or without\r
6 * modification, are permitted provided that the following conditions\r
7 * are met:\r
8 *\r
9 * * Redistributions of source code must retain the above copyright\r
10 * notice, this list of conditions and the following disclaimer.\r
11 *\r
12 * * Redistributions in binary form must reproduce the above copyright\r
13 * notice, this list of conditions and the following disclaimer in the\r
14 * documentation and/or other materials provided with the distribution.\r
15 *\r
16 * * Neither the name of Texas Instruments Incorporated nor the names of\r
17 * its contributors may be used to endorse or promote products derived\r
18 * from this software without specific prior written permission.\r
19 *\r
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
31 *\r
32 */\r
33 \r
34 function d2h(d) {return ("00000000" + (d).toString(16)).slice(-8);}\r
35 \r
36 function printRegisterValue(ds, name, addr)\r
37 {\r
38 value = debugSessionDAP.memory.readWord(0,addr,false);\r
39 value_string = d2h(value);\r
40 file.write(name + " = 0x" + value_string + "\n");\r
41 return value; // return the register value for interrogation\r
42 }\r
43 \r
44 function interpret_cmd_phy_macro(value, index)\r
45 {\r
46 WD1 = (value >> (21+index)) & 1;\r
47 WD0 = (value >> (10+index)) & 1;\r
48 WD = (WD1 << 1) | WD0;\r
49 if (WD == 0) return_string = "Pullup/Pulldown disabled\n";\r
50 if (WD == 1) return_string = "Weak pullup enabled\n";\r
51 if (WD == 2) return_string = "Weak pulldown enabled\n";\r
52 if (WD == 3) return_string = "Weak keeper enabled\n"; \r
53 return return_string;\r
54 }\r
55 \r
56 function interpret_data_phy_macro(value, index)\r
57 {\r
58 WD1 = (value >> (20+index)) & 1;\r
59 WD0 = (value >> (10+index)) & 1;\r
60 WD = (WD1 << 1) | WD0;\r
61 if (WD == 0) return_string = "Pullup/Pulldown disabled\n";\r
62 if (WD == 1) return_string = "Weak pullup enabled\n";\r
63 if (WD == 2) return_string = "Weak pulldown enabled\n";\r
64 if (WD == 3) return_string = "Weak keeper enabled\n"; \r
65 return return_string;\r
66 }\r
67 \r
68 // Build a filename that includes date/time\r
69 var today = new Date();\r
70 var year4digit = today.getFullYear();\r
71 var month2digit = ("0" + (today.getMonth()+1)).slice(-2);\r
72 var day2digit = ("0" + today.getDate()).slice(-2);\r
73 var hour2digit = ("0" + today.getHours()).slice(-2);\r
74 var minutes2digit = ("0" + today.getMinutes()).slice(-2);\r
75 var seconds2digit = ("0" + today.getSeconds()).slice(-2);\r
76 var filename_date = '_' + year4digit + '-' + month2digit + '-' + day2digit + '_' + hour2digit + minutes2digit + seconds2digit; \r
77 var userHomeFolder = System.getProperty("user.home");\r
78 var filename = userHomeFolder + '/Desktop/' + 'am335x-ddr-analysis' + filename_date + '.txt';\r
79 \r
80 debugSessionDAP = ds.openSession("*","CS_DAP_M3");\r
81 \r
82 try {\r
83 debugSessionDAP.target.connect();\r
84 } catch (ex) {\r
85 print("\n ERROR: Could not connect to DAP_M3.\n");\r
86 }\r
87 \r
88 var original_CM_WKUP_DEBUGSS_CLKCTRL = debugSessionDAP.memory.readWord(0,0x44e00414,false);\r
89 var original_CM_PER_L3_CLKSTCTRL = debugSessionDAP.memory.readWord(0,0x44E0000C,false);\r
90 \r
91 file = new java.io.FileWriter(filename);\r
92 \r
93 // Only try to read EMIF registers if EMIF clock is enabled\r
94 if (original_CM_PER_L3_CLKSTCTRL & 1<<2) {\r
95 \r
96 // CM_WKUP_DEBUGSS_CLKCTRL[MODULEMODE] = ENABLED\r
97 debugSessionDAP.expression.evaluate(\r
98 "*((unsigned int*) 0x44e00414 ) |= 0x2;");\r
99 \r
100 debugSessionDAP.target.disconnect(); // disconnect from DAP_M3\r
101 \r
102 // Connect to DAP_DebugSS for L3 visibility (EMIF regs)\r
103 debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS");\r
104 debugSessionDAP.target.connect();\r
105 \r
106 var reg_val;\r
107 \r
108 // EMIF: SDRAM_CONFIG\r
109 reg_val = printRegisterValue(debugSessionDAP, "EMIF: SDRAM_CONFIG", 0x4C000008);\r
110 \r
111 var is_ddr3=0;\r
112 var is_ddr2=0;\r
113 var is_lpddr=0;\r
114 if ( (reg_val & 0xE0000000) == (0 << 29) ) {file.write(" * ERROR! Unsupported memory type (DDR1)\n");}\r
115 if ( (reg_val & 0xE0000000) == (1 << 29) ) {is_lpddr=1;}\r
116 if ( (reg_val & 0xE0000000) == (2 << 29) ) {is_ddr2=1;}\r
117 if ( (reg_val & 0xE0000000) == (3 << 29) ) {is_ddr3=1;}\r
118 if (is_ddr3 == 1) {\r
119 file.write(" * Bits 26:24 (reg_ddr_term) set for ");\r
120 if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}\r
121 if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("RZQ/4 (001b)\n");}\r
122 if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("RZQ/2 (010b)\n");}\r
123 if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("RZQ/6 (011b)\n");}\r
124 if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("RZQ/12 (100b)\n");}\r
125 if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("RZQ/8 (101b)\n");}\r
126 if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}\r
127 if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}\r
128 }\r
129 if (is_ddr2 == 1) {\r
130 file.write(" * Bits 26:24 (reg_ddr_term) set for ");\r
131 if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}\r
132 if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("75 Ohm (001b)\n");}\r
133 if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("150 Ohm (010b)\n");}\r
134 if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("50 Ohm (011b)\n");}\r
135 if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("ERROR\n");}\r
136 if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("ERROR\n");}\r
137 if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}\r
138 if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}\r
139 }\r
140 if (is_ddr3 == 1) {\r
141 file.write(" * Bits 19:18 (reg_sdram_drive) set for ");\r
142 if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("RZQ/6 (00b)\n");}\r
143 if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("RZQ/7 (01b)\n");}\r
144 if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}\r
145 if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}\r
146 }\r
147 if (is_ddr2 == 1) {\r
148 file.write(" * Bits 19:18 (reg_sdram_drive) set for ");\r
149 if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("normal drive (00b)\n");}\r
150 if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("weak drive (01b)\n");}\r
151 if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}\r
152 if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}\r
153 }\r
154 if (is_lpddr == 1) {\r
155 file.write(" * Bits 19:18 (reg_sdram_drive) set for ");\r
156 if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("full strength (00b)\n");}\r
157 if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("half strength (01b)\n");}\r
158 if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("quarter strength (10b)\n");}\r
159 if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("eighth strength (11b)\n");}\r
160 }\r
161 \r
162 // EMIF: PWR_MGMT_CTRL\r
163 reg_val = printRegisterValue(debugSessionDAP, "EMIF: PWR_MGMT_CTRL", 0x4C000038);\r
164 if ( (reg_val & 0xF0) < 0x90 ) {\r
165 file.write(" * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit\n");\r
166 file.write(" * Please see the silicon errata for more details.\n");\r
167 }\r
168 \r
169 // DDR PHY: DDR_PHY_CTRL_1\r
170 reg_val = printRegisterValue(debugSessionDAP, "DDR PHY: DDR_PHY_CTRL_1", 0x4C0000E4);\r
171 if ( (reg_val & 1<<20) == 0 ) {file.write(" * WARNING: reg_phy_enable_dynamic_pwrdn disabled.\n");}\r
172 file.write(" * Bits 9:8 (reg_phy_rd_local_odt) configured as ");\r
173 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("no termination (00b)\n");}\r
174 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("no termination (01b)\n");}\r
175 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("full thevenin termination\n");}\r
176 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("half thevenin termination\n");}\r
177 \r
178 // Close (Main) DAP session and use M3 DAP to view Control Registers\r
179 debugSessionDAP.target.disconnect();\r
180 debugSessionDAP = ds.openSession("*","CS_DAP_M3");\r
181 debugSessionDAP.target.connect();\r
182 \r
183 // Restore CM_WKUP_DEBUGSS_CLKCTRL[MODULEMODE]\r
184 if ( (original_CM_WKUP_DEBUGSS_CLKCTRL & 3) == 0 ) {\r
185 debugSessionDAP.memory.writeWord(0,0x44e00414,original_CM_WKUP_DEBUGSS_CLKCTRL);\r
186 }\r
187 } else {\r
188 file.write("Skipping read of EMIF registers since EMIF clock disabled.\n");\r
189 file.write(" * EMIF registers are not readable when in DS0 state\n");\r
190 file.write(" * If you are attempting to enter DS0 this is normal.\n");\r
191 }\r
192 \r
193 // CONTROL: DDR_CMD0_IOCTRL\r
194 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD0_IOCTRL", 0x44E11404);\r
195 file.write(" * ddr_ba2 " + interpret_cmd_phy_macro(reg_val, 0));\r
196 file.write(" * ddr_wen " + interpret_cmd_phy_macro(reg_val, 1));\r
197 file.write(" * ddr_ba0 " + interpret_cmd_phy_macro(reg_val, 2));\r
198 file.write(" * ddr_a5 " + interpret_cmd_phy_macro(reg_val, 3));\r
199 file.write(" * ddr_ck " + interpret_cmd_phy_macro(reg_val, 4));\r
200 file.write(" * ddr_ckn " + interpret_cmd_phy_macro(reg_val, 5));\r
201 file.write(" * ddr_a3 " + interpret_cmd_phy_macro(reg_val, 6));\r
202 file.write(" * ddr_a4 " + interpret_cmd_phy_macro(reg_val, 7));\r
203 file.write(" * ddr_a8 " + interpret_cmd_phy_macro(reg_val, 8));\r
204 file.write(" * ddr_a9 " + interpret_cmd_phy_macro(reg_val, 9));\r
205 file.write(" * ddr_a6 " + interpret_cmd_phy_macro(reg_val, 10));\r
206 file.write(" * Bits 9:5 control ddr_ck and ddr_ckn\n");\r
207 file.write(" - Slew ");\r
208 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}\r
209 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("slow\n");}\r
210 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("fast\n");}\r
211 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("slowest\n");}\r
212 var drive_strength_mA = ((reg_val & 0xE0) >> 5) + 5;\r
213 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");\r
214 file.write(" * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]\n");\r
215 file.write(" - Slew ");\r
216 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}\r
217 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}\r
218 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}\r
219 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}\r
220 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;\r
221 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");\r
222 \r
223 // CONTROL: DDR_CMD1_IOCTRL\r
224 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD1_IOCTRL", 0x44E11408);\r
225 file.write(" * ddr_a15 " + interpret_cmd_phy_macro(reg_val, 1));\r
226 file.write(" * ddr_a2 " + interpret_cmd_phy_macro(reg_val, 2));\r
227 file.write(" * ddr_a12 " + interpret_cmd_phy_macro(reg_val, 3));\r
228 file.write(" * ddr_a7 " + interpret_cmd_phy_macro(reg_val, 4));\r
229 file.write(" * ddr_ba1 " + interpret_cmd_phy_macro(reg_val, 5));\r
230 file.write(" * ddr_a10 " + interpret_cmd_phy_macro(reg_val, 6));\r
231 file.write(" * ddr_a0 " + interpret_cmd_phy_macro(reg_val, 7));\r
232 file.write(" * ddr_a11 " + interpret_cmd_phy_macro(reg_val, 8));\r
233 file.write(" * ddr_casn " + interpret_cmd_phy_macro(reg_val, 9));\r
234 file.write(" * ddr_rasn " + interpret_cmd_phy_macro(reg_val, 10));\r
235 file.write(" * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn\n");\r
236 file.write(" - Slew ");\r
237 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}\r
238 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}\r
239 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}\r
240 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}\r
241 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;\r
242 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");\r
243 \r
244 // CONTROL: DDR_CMD2_IOCTRL\r
245 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD2_IOCTRL", 0x44E1140C);\r
246 file.write(" * ddr_cke " + interpret_cmd_phy_macro(reg_val, 0));\r
247 file.write(" * ddr_resetn " + interpret_cmd_phy_macro(reg_val, 1));\r
248 file.write(" * ddr_odt " + interpret_cmd_phy_macro(reg_val, 2));\r
249 file.write(" * ddr_a14 " + interpret_cmd_phy_macro(reg_val, 4));\r
250 file.write(" * ddr_a13 " + interpret_cmd_phy_macro(reg_val, 5));\r
251 file.write(" * ddr_csn0 " + interpret_cmd_phy_macro(reg_val, 6));\r
252 file.write(" * ddr_a1 " + interpret_cmd_phy_macro(reg_val, 8));\r
253 file.write(" * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1\n");\r
254 file.write(" - Slew ");\r
255 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}\r
256 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}\r
257 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}\r
258 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}\r
259 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;\r
260 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");\r
261 \r
262 // CONTROL: DDR_DATA0_IOCTRL\r
263 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_DATA0_IOCTRL", 0x44E11440);\r
264 file.write(" * ddr_d8 " + interpret_data_phy_macro(reg_val, 0));\r
265 file.write(" * ddr_d9 " + interpret_data_phy_macro(reg_val, 1));\r
266 file.write(" * ddr_d10 " + interpret_data_phy_macro(reg_val, 2));\r
267 file.write(" * ddr_d11 " + interpret_data_phy_macro(reg_val, 3));\r
268 file.write(" * ddr_d12 " + interpret_data_phy_macro(reg_val, 4));\r
269 file.write(" * ddr_d13 " + interpret_data_phy_macro(reg_val, 5));\r
270 file.write(" * ddr_d14 " + interpret_data_phy_macro(reg_val, 6));\r
271 file.write(" * ddr_d15 " + interpret_data_phy_macro(reg_val, 7));\r
272 file.write(" * ddr_dqm1 " + interpret_data_phy_macro(reg_val, 8));\r
273 file.write(" * ddr_dqs1 and ddr_dqsn1 " + interpret_data_phy_macro(reg_val, 9));\r
274 file.write(" * Bits 9:5 control ddr_dqs1, ddr_dqsn1\n");\r
275 file.write(" - Slew ");\r
276 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}\r
277 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("slow\n");}\r
278 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("fast\n");}\r
279 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("slowest\n");}\r
280 var drive_strength_mA = ((reg_val & 0xE0) >> 5) + 5;\r
281 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");\r
282 file.write(" * Bits 4:0 control ddr_d[15:8], ddr_dqm1\n");\r
283 file.write(" - Slew ");\r
284 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}\r
285 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}\r
286 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}\r
287 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}\r
288 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;\r
289 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");\r
290 \r
291 // CONTROL: DDR_DATA1_IOCTRL\r
292 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_DATA1_IOCTRL", 0x44E11444);\r
293 file.write(" * ddr_d0 " + interpret_data_phy_macro(reg_val, 0));\r
294 file.write(" * ddr_d1 " + interpret_data_phy_macro(reg_val, 1));\r
295 file.write(" * ddr_d2 " + interpret_data_phy_macro(reg_val, 2));\r
296 file.write(" * ddr_d3 " + interpret_data_phy_macro(reg_val, 3));\r
297 file.write(" * ddr_d4 " + interpret_data_phy_macro(reg_val, 4));\r
298 file.write(" * ddr_d5 " + interpret_data_phy_macro(reg_val, 5));\r
299 file.write(" * ddr_d6 " + interpret_data_phy_macro(reg_val, 6));\r
300 file.write(" * ddr_d7 " + interpret_data_phy_macro(reg_val, 7));\r
301 file.write(" * ddr_dqm0 " + interpret_data_phy_macro(reg_val, 8));\r
302 file.write(" * ddr_dqs0 and ddr_dqsn0 " + interpret_data_phy_macro(reg_val, 9));\r
303 file.write(" * Bits 9:5 control ddr_dqs0, ddr_dqsn0\n");\r
304 file.write(" - Slew ");\r
305 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}\r
306 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("slow\n");}\r
307 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("fast\n");}\r
308 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("slowest\n");}\r
309 var drive_strength_mA = ((reg_val & 0xE0) >> 5) + 5;\r
310 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");\r
311 file.write(" * Bits 4:0 control ddr_d[7:0], dqm0\n");\r
312 file.write(" - Slew ");\r
313 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}\r
314 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}\r
315 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}\r
316 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}\r
317 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;\r
318 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");\r
319 \r
320 // CONTROL: DDR_IO_CTRL\r
321 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_IO_CTRL", 0x44E10E04);\r
322 if ( (reg_val & (1 << 31)) == (1<<31) ) {\r
323 file.write(" * Bit 31: Overriding DDR_RESETn (expected for DS0).\n");\r
324 } else {\r
325 file.write(" * Bit 31: DDR_RESETn controlled by EMIF.\n");\r
326 }\r
327 if ( (reg_val & (1 << 28)) == 0) {\r
328 file.write(" * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.\n");\r
329 if (is_lpddr == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}\r
330 }\r
331 else {\r
332 file.write(" * Bit 28 (mddr_sel) configured for LVCMOS, i.e. LPDDR/mDDR operation.\n");\r
333 if (is_ddr2 == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}\r
334 if (is_ddr3 == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}\r
335 }\r
336 \r
337 // CONTROL: VTP_CTRL\r
338 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: VTP_CTRL", 0x44E10E0C);\r
339 if ( reg_val == 0 ) {\r
340 file.write(" * VTP disabled (expected in DS0).\n");\r
341 } else {\r
342 file.write(" * VTP not disabled (expected in normal operation, but not DS0).\n");\r
343 }\r
344 \r
345 // CONTROL: VREF_CTRL\r
346 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: VREF_CTRL", 0x44E10E14);\r
347 if ( (reg_val & 1) == 0 ) {\r
348 file.write(" * VREF supplied externally (typical).\n");\r
349 } else {\r
350 file.write(" * Internal VREF (unusual).\n");\r
351 }\r
352 \r
353 // CONTROL: DDR_CKE_CTRL\r
354 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CKE_CTRL", 0x44E1131C);\r
355 if ( (reg_val & 1) == 0 ) {\r
356 file.write(" * CKE gated (forces pin low).\n");\r
357 } else {\r
358 file.write(" * CKE controlled by EMIF (normal/ungated operation).\n");\r
359 }\r
360 \r
361 file.close();\r
362 print("Created file " + filename);\r
363 debugSessionDAP.target.disconnect();\r
364 \r
365 \r
366 \r
367 //****************************************************************************\r
368 // getErrorCode\r
369 //****************************************************************************\r
370 function getErrorCode(exception)\r
371 {\r
372 var ex2 = exception.javaException;\r
373 if (ex2 instanceof Packages.com.ti.ccstudio.scripting.environment.ScriptingException)\r
374 {\r
375 return ex2.getErrorID();\r
376 }\r
377 return 0;\r
378 }\r