1 /*
2 * Copyright (c) 2006-2014, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 function d2h(d) {return ("00000000" + (d).toString(16)).slice(-8);}
36 // helper function to create decimal numbers in ascii format
37 function d2d(d) {return ((+d).toString());}
39 function printRegisterValue(ds, name, addr)
40 {
41 value = debugSessionDAP.memory.readWord(0,addr,false);
42 value_string = d2h(value);
43 file.write(name + " = 0x" + value_string + "\n");
44 return value; // return the register value for interrogation
45 }
47 function getRegisterValue(debug, addr)
48 {
49 return debug.memory.readWord(0,addr,false);
50 }
52 function interpret_cmd_phy_macro(value, index)
53 {
54 WD1 = (value >> (21+index)) & 1;
55 WD0 = (value >> (10+index)) & 1;
56 WD = (WD1 << 1) | WD0;
57 if (WD == 0) return_string = "Pullup/Pulldown disabled\n";
58 if (WD == 1) return_string = "Weak pullup enabled\n";
59 if (WD == 2) return_string = "Weak pulldown enabled\n";
60 if (WD == 3) return_string = "Weak keeper enabled\n";
61 return return_string;
62 }
64 function interpret_data_phy_macro(value, index)
65 {
66 WD1 = (value >> (20+index)) & 1;
67 WD0 = (value >> (10+index)) & 1;
68 WD = (WD1 << 1) | WD0;
69 if (WD == 0) return_string = "Pullup/Pulldown disabled\n";
70 if (WD == 1) return_string = "Weak pullup enabled\n";
71 if (WD == 2) return_string = "Weak pulldown enabled\n";
72 if (WD == 3) return_string = "Weak keeper enabled\n";
73 return return_string;
74 }
76 // Inputs:
77 // Data - 32-bit register value
78 // Upper - Highest bit to keep
79 // Lower - Lowest bit to keep
80 // (bit 0 refers to LSB, bit 31 to MSB)
81 // Return: right aligned data
82 function bits32(data, upper, lower)
83 {
84 data = data >>> lower; // unsigned right-shift
85 upper = upper - lower;
86 bitmask = 0xFFFFFFFF >>> (31 - upper);
87 return (data & bitmask);
88 }
90 // Build a filename that includes date/time
91 var today = new Date();
92 var year4digit = today.getFullYear();
93 var month2digit = ("0" + (today.getMonth()+1)).slice(-2);
94 var day2digit = ("0" + today.getDate()).slice(-2);
95 var hour2digit = ("0" + today.getHours()).slice(-2);
96 var minutes2digit = ("0" + today.getMinutes()).slice(-2);
97 var seconds2digit = ("0" + today.getSeconds()).slice(-2);
98 var filename_date = '_' + year4digit + '-' + month2digit + '-' + day2digit + '_' + hour2digit + minutes2digit + seconds2digit;
99 var userHomeFolder = System.getProperty("user.home");
100 var filename = userHomeFolder + '/Desktop/' + 'am335x-ddr-analysis' + filename_date + '.txt';
102 debugSessionDAP = ds.openSession("*","CS_DAP_M3");
103 use_dap_m3 = 1;
105 try {
106 debugSessionDAP.target.connect();
107 } catch (ex) {
108 print("\n ERROR: Could not connect to DAP_M3.\n");
109 }
111 // Do a test read of Device_ID register at 0x44e10600
112 value = debugSessionDAP.memory.readWord(0,0x44e10600,false);
114 // If it is zero, switch to CS_DAP_DebugSS
115 if (value == 0)
116 {
117 debugSessionDAP.target.disconnect();
118 debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS");
119 debugSessionDAP.target.connect();
120 use_dap_m3 = 0;
121 }
123 var original_CM_WKUP_DEBUGSS_CLKCTRL = debugSessionDAP.memory.readWord(0,0x44e00414,false);
124 var original_CM_PER_L3_CLKSTCTRL = debugSessionDAP.memory.readWord(0,0x44E0000C,false);
125 var newline = "\n";
127 file = new java.io.FileWriter(filename);
129 // Only try to read EMIF registers if EMIF clock is enabled
130 if (original_CM_PER_L3_CLKSTCTRL & 1<<2) {
132 // CM_WKUP_DEBUGSS_CLKCTRL[MODULEMODE] = ENABLED
133 debugSessionDAP.expression.evaluate(
134 "*((unsigned int*) 0x44e00414 ) |= 0x2;");
136 debugSessionDAP.target.disconnect(); // disconnect from DAP_M3
138 // Connect to DAP_DebugSS for L3 visibility (EMIF regs)
139 debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS");
140 debugSessionDAP.target.connect();
142 var reg_val;
144 // CONTROL: device_id
145 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: device_id", 0x44E10600);
146 if ( (reg_val & 0x0FFFFFFF) == 0xb94402e ) {file.write(" * AM335x family" + newline);}
147 if ( (reg_val & 0xF0000000) == (0 << 28) ) {file.write(" * Silicon Revision 1.0" + newline);}
148 if ( (reg_val & 0xF0000000) == (1 << 28) ) {file.write(" * Silicon Revision 2.0" + newline);}
149 if ( (reg_val & 0xF0000000) == (2 << 28) ) {file.write(" * Silicon Revision 2.1" + newline);}
151 // CONTROL: control_status
152 file.write(newline);
153 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: control_status", 0x44E10040);
154 speedselect_pins = bits32(reg_val, 23, 22);
155 switch (speedselect_pins) {
156 case 0:
157 file.write(" * SYSBOOT[15:14] = 00b (19.2 MHz)" + newline);
158 input_clock = 19.2;
159 break;
160 case 1:
161 file.write(" * SYSBOOT[15:14] = 01b (24 MHz)" + newline);
162 input_clock = 24;
163 break;
164 case 2:
165 file.write(" * SYSBOOT[15:14] = 10b (25 MHz)" + newline);
166 input_clock = 25;
167 break;
168 case 3:
169 file.write(" * SYSBOOT[15:14] = 11b (26 MHz)" + newline);
170 input_clock = 26;
171 break;
172 }
174 // CM_CLKSEL_DPLL_DDR
175 reg_val = printRegisterValue(debugSessionDAP, "CM_CLKSEL_DPLL_DDR", 0x44E00440);
176 dpll_mult = bits32(reg_val, 18, 8);
177 file.write(" * DPLL_MULT = " + d2d(dpll_mult) + " (x" + d2d(dpll_mult) + ")" + newline);
178 dpll_div = bits32(reg_val, 6, 0);
179 file.write(" * DPLL_DIV = " + d2d(dpll_div) + " (/" + d2d(dpll_div+1) + ")" + newline);
180 f_dpll_ddr = input_clock*2*dpll_mult/(dpll_div+1);
182 // CM_DIV_M2_DPLL_DDR
183 reg_val = printRegisterValue(debugSessionDAP, "CM_DIV_M2_DPLL_DDR", 0x44E004A0);
184 if (reg_val & (1<<9)) // CLKST = 1
185 file.write(" * CLKST = 1: M2 output clock enabled" + newline);
186 else
187 file.write(" * CLKST = 0: M2 output clock disabled" + newline);;
188 div_m2 = reg_val & 0x1F;
189 file.write(" * DIVHS = " + d2d(div_m2) + " (/" + d2d(div_m2) + ")" + newline);
191 file.write(newline + "DPLL_DDR Summary" + newline);
192 file.write(" -> F_input = " + d2d(input_clock) + " MHz" + newline);
193 file.write(" -> CLKOUT_M2 = DDR_PLL_CLKOUT = " + f_dpll_ddr / 2 / div_m2 + " MHz" + newline);
195 // EMIF: SDRAM_CONFIG
196 file.write(newline);
197 reg_val = printRegisterValue(debugSessionDAP, "EMIF: SDRAM_CONFIG", 0x4C000008);
199 var is_ddr3=0;
200 var is_ddr2=0;
201 var is_lpddr=0;
202 if ( (reg_val & 0xE0000000) == (0 << 29) ) {file.write(" * ERROR! Unsupported memory type (DDR1)\n");}
203 if ( (reg_val & 0xE0000000) == (1 << 29) ) {is_lpddr=1;}
204 if ( (reg_val & 0xE0000000) == (2 << 29) ) {is_ddr2=1;}
205 if ( (reg_val & 0xE0000000) == (3 << 29) ) {is_ddr3=1;}
206 if (is_ddr3 == 1) {
207 file.write(" * Bits 31:29 (reg_sdram_type) set for DDR3\n");
208 file.write(" * Bits 26:24 (reg_ddr_term) set for ");
209 if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}
210 if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("RZQ/4 (001b)\n");}
211 if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("RZQ/2 (010b)\n");}
212 if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("RZQ/6 (011b)\n");}
213 if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("RZQ/12 (100b)\n");}
214 if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("RZQ/8 (101b)\n");}
215 if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}
216 if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}
217 }
218 if (is_ddr2 == 1) {
219 file.write(" * Bits 31:29 (reg_sdram_type) set for DDR2\n");
220 file.write(" * Bits 26:24 (reg_ddr_term) set for ");
221 if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}
222 if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("75 Ohm (001b)\n");}
223 if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("150 Ohm (010b)\n");}
224 if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("50 Ohm (011b)\n");}
225 if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("ERROR\n");}
226 if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("ERROR\n");}
227 if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}
228 if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}
229 }
230 if (is_ddr3 == 1) {
231 file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
232 if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("RZQ/6 (00b)\n");}
233 if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("RZQ/7 (01b)\n");}
234 if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}
235 if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}
236 }
237 if (is_ddr2 == 1) {
238 file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
239 if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("normal drive (00b)\n");}
240 if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("weak drive (01b)\n");}
241 if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}
242 if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}
243 }
244 if (is_lpddr == 1) {
245 file.write(" * Bits 31:29 (reg_sdram_type) set for LPDDR\n");
246 file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
247 if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("full strength (00b)\n");}
248 if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("half strength (01b)\n");}
249 if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("quarter strength (10b)\n");}
250 if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("eighth strength (11b)\n");}
251 }
253 // EMIF: PWR_MGMT_CTRL
254 reg_val = printRegisterValue(debugSessionDAP, "EMIF: PWR_MGMT_CTRL", 0x4C000038);
255 if ( (reg_val & 0xF0) < 0x90 ) {
256 file.write(" * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit\n");
257 file.write(" * Please see the silicon errata for more details.\n");
258 }
260 // DDR PHY: DDR_PHY_CTRL_1
261 reg_val = printRegisterValue(debugSessionDAP, "DDR PHY: DDR_PHY_CTRL_1", 0x4C0000E4);
262 if ( (reg_val & 1<<20) == 0 ) {file.write(" * WARNING: reg_phy_enable_dynamic_pwrdn disabled.\n");}
263 file.write(" * Bits 9:8 (reg_phy_rd_local_odt) configured as ");
264 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("no termination (00b)\n");}
265 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("no termination (01b)\n");}
266 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("full thevenin termination\n");}
267 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("half thevenin termination\n");}
269 file.write("\n");
270 file.write("*********************\n");
271 file.write("*** Register Dump ***\n")
272 file.write("*********************\n\n");
274 var ddr_config_regs = [
275 0x4C000000,
276 0x4C000004,
277 0x4C000008,
278 0x4C00000C,
279 0x4C000010,
280 0x4C000014,
281 0x4C000018,
282 0x4C00001C,
283 0x4C000020,
284 0x4C000024,
285 0x4C000028,
286 0x4C00002C,
287 0x4C000038,
288 0x4C00003C,
289 0x4C000054,
290 0x4C000058,
291 0x4C00005C,
292 0x4C000080,
293 0x4C000084,
294 0x4C000088,
295 0x4C00008C,
296 0x4C000090,
297 0x4C000098,
298 0x4C00009C,
299 0x4C0000A4,
300 0x4C0000AC,
301 0x4C0000B4,
302 0x4C0000BC,
303 0x4C0000C8,
304 0x4C0000D4,
305 0x4C0000D8,
306 0x4C0000DC,
307 0x4C0000E4,
308 0x4C0000E8,
309 0x4C000100,
310 0x4C000104,
311 0x4C000108,
312 0x4C000120];
314 for (i=0; i<ddr_config_regs.length; i++)
315 {
316 reg_val = getRegisterValue(debugSessionDAP, ddr_config_regs[i]);
317 file.write("*(0x" + d2h(ddr_config_regs[i]) + ")"); // Address
318 file.write(" = 0x" + d2h(reg_val) + "\n"); // Raw Reg Val
319 }
321 if ( use_dap_m3 == 1 ) {
322 // Close (Main) DAP session and use M3 DAP to view Control Registers
323 debugSessionDAP.target.disconnect();
324 debugSessionDAP = ds.openSession("*","CS_DAP_M3");
325 debugSessionDAP.target.connect();
326 }
328 // Restore CM_WKUP_DEBUGSS_CLKCTRL[MODULEMODE]
329 if ( (original_CM_WKUP_DEBUGSS_CLKCTRL & 3) == 0 ) {
330 debugSessionDAP.memory.writeWord(0,0x44e00414,original_CM_WKUP_DEBUGSS_CLKCTRL);
331 }
332 } else {
333 file.write("Skipping read of EMIF registers since EMIF clock disabled.\n");
334 file.write(" * EMIF registers are not readable when in DS0 state\n");
335 file.write(" * If you are attempting to enter DS0 this is normal.\n");
336 }
338 file.write("\n");
339 file.write("************************\n");
340 file.write("*** IOCTRL Registers ***\n")
341 file.write("************************\n\n");
343 // CONTROL: DDR_CMD0_IOCTRL
344 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD0_IOCTRL", 0x44E11404);
345 file.write(" * ddr_ba2 " + interpret_cmd_phy_macro(reg_val, 0));
346 file.write(" * ddr_wen " + interpret_cmd_phy_macro(reg_val, 1));
347 file.write(" * ddr_ba0 " + interpret_cmd_phy_macro(reg_val, 2));
348 file.write(" * ddr_a5 " + interpret_cmd_phy_macro(reg_val, 3));
349 file.write(" * ddr_ck " + interpret_cmd_phy_macro(reg_val, 4));
350 file.write(" * ddr_ckn " + interpret_cmd_phy_macro(reg_val, 5));
351 file.write(" * ddr_a3 " + interpret_cmd_phy_macro(reg_val, 6));
352 file.write(" * ddr_a4 " + interpret_cmd_phy_macro(reg_val, 7));
353 file.write(" * ddr_a8 " + interpret_cmd_phy_macro(reg_val, 8));
354 file.write(" * ddr_a9 " + interpret_cmd_phy_macro(reg_val, 9));
355 file.write(" * ddr_a6 " + interpret_cmd_phy_macro(reg_val, 10));
356 file.write(" * Bits 9:5 control ddr_ck and ddr_ckn\n");
357 file.write(" - Slew ");
358 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}
359 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("slow\n");}
360 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("fast\n");}
361 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("slowest\n");}
362 var drive_strength_mA = ((reg_val & 0xE0) >> 5) + 5;
363 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
364 file.write(" * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]\n");
365 file.write(" - Slew ");
366 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
367 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
368 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
369 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
370 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
371 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
373 // CONTROL: DDR_CMD1_IOCTRL
374 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD1_IOCTRL", 0x44E11408);
375 file.write(" * ddr_a15 " + interpret_cmd_phy_macro(reg_val, 1));
376 file.write(" * ddr_a2 " + interpret_cmd_phy_macro(reg_val, 2));
377 file.write(" * ddr_a12 " + interpret_cmd_phy_macro(reg_val, 3));
378 file.write(" * ddr_a7 " + interpret_cmd_phy_macro(reg_val, 4));
379 file.write(" * ddr_ba1 " + interpret_cmd_phy_macro(reg_val, 5));
380 file.write(" * ddr_a10 " + interpret_cmd_phy_macro(reg_val, 6));
381 file.write(" * ddr_a0 " + interpret_cmd_phy_macro(reg_val, 7));
382 file.write(" * ddr_a11 " + interpret_cmd_phy_macro(reg_val, 8));
383 file.write(" * ddr_casn " + interpret_cmd_phy_macro(reg_val, 9));
384 file.write(" * ddr_rasn " + interpret_cmd_phy_macro(reg_val, 10));
385 file.write(" * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn\n");
386 file.write(" - Slew ");
387 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
388 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
389 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
390 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
391 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
392 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
394 // CONTROL: DDR_CMD2_IOCTRL
395 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD2_IOCTRL", 0x44E1140C);
396 file.write(" * ddr_cke " + interpret_cmd_phy_macro(reg_val, 0));
397 file.write(" * ddr_resetn " + interpret_cmd_phy_macro(reg_val, 1));
398 file.write(" * ddr_odt " + interpret_cmd_phy_macro(reg_val, 2));
399 file.write(" * ddr_a14 " + interpret_cmd_phy_macro(reg_val, 4));
400 file.write(" * ddr_a13 " + interpret_cmd_phy_macro(reg_val, 5));
401 file.write(" * ddr_csn0 " + interpret_cmd_phy_macro(reg_val, 6));
402 file.write(" * ddr_a1 " + interpret_cmd_phy_macro(reg_val, 8));
403 file.write(" * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1\n");
404 file.write(" - Slew ");
405 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
406 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
407 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
408 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
409 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
410 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
412 // CONTROL: DDR_DATA0_IOCTRL
413 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_DATA0_IOCTRL", 0x44E11440);
414 file.write(" * ddr_d8 " + interpret_data_phy_macro(reg_val, 0));
415 file.write(" * ddr_d9 " + interpret_data_phy_macro(reg_val, 1));
416 file.write(" * ddr_d10 " + interpret_data_phy_macro(reg_val, 2));
417 file.write(" * ddr_d11 " + interpret_data_phy_macro(reg_val, 3));
418 file.write(" * ddr_d12 " + interpret_data_phy_macro(reg_val, 4));
419 file.write(" * ddr_d13 " + interpret_data_phy_macro(reg_val, 5));
420 file.write(" * ddr_d14 " + interpret_data_phy_macro(reg_val, 6));
421 file.write(" * ddr_d15 " + interpret_data_phy_macro(reg_val, 7));
422 file.write(" * ddr_dqm1 " + interpret_data_phy_macro(reg_val, 8));
423 file.write(" * ddr_dqs1 and ddr_dqsn1 " + interpret_data_phy_macro(reg_val, 9));
424 file.write(" * Bits 9:5 control ddr_dqs1, ddr_dqsn1\n");
425 file.write(" - Slew ");
426 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}
427 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("slow\n");}
428 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("fast\n");}
429 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("slowest\n");}
430 var drive_strength_mA = ((reg_val & 0xE0) >> 5) + 5;
431 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
432 file.write(" * Bits 4:0 control ddr_d[15:8], ddr_dqm1\n");
433 file.write(" - Slew ");
434 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
435 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
436 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
437 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
438 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
439 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
441 // CONTROL: DDR_DATA1_IOCTRL
442 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_DATA1_IOCTRL", 0x44E11444);
443 file.write(" * ddr_d0 " + interpret_data_phy_macro(reg_val, 0));
444 file.write(" * ddr_d1 " + interpret_data_phy_macro(reg_val, 1));
445 file.write(" * ddr_d2 " + interpret_data_phy_macro(reg_val, 2));
446 file.write(" * ddr_d3 " + interpret_data_phy_macro(reg_val, 3));
447 file.write(" * ddr_d4 " + interpret_data_phy_macro(reg_val, 4));
448 file.write(" * ddr_d5 " + interpret_data_phy_macro(reg_val, 5));
449 file.write(" * ddr_d6 " + interpret_data_phy_macro(reg_val, 6));
450 file.write(" * ddr_d7 " + interpret_data_phy_macro(reg_val, 7));
451 file.write(" * ddr_dqm0 " + interpret_data_phy_macro(reg_val, 8));
452 file.write(" * ddr_dqs0 and ddr_dqsn0 " + interpret_data_phy_macro(reg_val, 9));
453 file.write(" * Bits 9:5 control ddr_dqs0, ddr_dqsn0\n");
454 file.write(" - Slew ");
455 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}
456 if ( (reg_val & 0x300) == (1 << 8) ) {file.write("slow\n");}
457 if ( (reg_val & 0x300) == (2 << 8) ) {file.write("fast\n");}
458 if ( (reg_val & 0x300) == (3 << 8) ) {file.write("slowest\n");}
459 var drive_strength_mA = ((reg_val & 0xE0) >> 5) + 5;
460 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
461 file.write(" * Bits 4:0 control ddr_d[7:0], dqm0\n");
462 file.write(" - Slew ");
463 if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}
464 if ( (reg_val & 0x18) == (1 << 3) ) {file.write("slow\n");}
465 if ( (reg_val & 0x18) == (2 << 3) ) {file.write("fast\n");}
466 if ( (reg_val & 0x18) == (3 << 3) ) {file.write("slowest\n");}
467 var drive_strength_mA = ((reg_val & 0x07) >> 0) + 5;
468 file.write(" - Drive Strength " + drive_strength_mA + " mA\n");
470 // CONTROL: DDR_IO_CTRL
471 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_IO_CTRL", 0x44E10E04);
472 if ( (reg_val & (1 << 31)) == (1<<31) ) {
473 file.write(" * Bit 31: Overriding DDR_RESETn (expected for DS0).\n");
474 } else {
475 file.write(" * Bit 31: DDR_RESETn controlled by EMIF.\n");
476 }
477 if ( (reg_val & (1 << 28)) == 0) {
478 file.write(" * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.\n");
479 if (is_lpddr == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}
480 }
481 else {
482 file.write(" * Bit 28 (mddr_sel) configured for LVCMOS, i.e. LPDDR/mDDR operation.\n");
483 if (is_ddr2 == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}
484 if (is_ddr3 == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}
485 }
487 // CONTROL: VTP_CTRL
488 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: VTP_CTRL", 0x44E10E0C);
489 if ( reg_val == 0 ) {
490 file.write(" * VTP disabled (expected in DS0).\n");
491 } else {
492 file.write(" * VTP not disabled (expected in normal operation, but not DS0).\n");
493 }
495 // CONTROL: VREF_CTRL
496 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: VREF_CTRL", 0x44E10E14);
497 if ( (reg_val & 1) == 0 ) {
498 file.write(" * VREF supplied externally (typical).\n");
499 } else {
500 file.write(" * Internal VREF (unusual).\n");
501 }
503 // CONTROL: DDR_CKE_CTRL
504 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CKE_CTRL", 0x44E1131C);
505 if ( (reg_val & 1) == 0 ) {
506 file.write(" * CKE gated (forces pin low).\n");
507 } else {
508 file.write(" * CKE controlled by EMIF (normal/ungated operation).\n");
509 }
511 file.close();
512 print("Created file " + filename);
513 debugSessionDAP.target.disconnect();
517 //****************************************************************************
518 // getErrorCode
519 //****************************************************************************
520 function getErrorCode(exception)
521 {
522 var ex2 = exception.javaException;
523 if (ex2 instanceof Packages.com.ti.ccstudio.scripting.environment.ScriptingException)
524 {
525 return ex2.getErrorID();
526 }
527 return 0;
528 }