/* * Copyright (c) 2006-2014, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ function d2h(d) {return ("00000000" + (d).toString(16)).slice(-8);} var newline = "\n"; function printRegisterValue(ds, name, addr) { value = debugSessionDAP.memory.readWord(0,addr,false); value_string = d2h(value); file.write(name + " = 0x" + value_string + newline); return value; // return the register value for interrogation } // Build a filename that includes date/time var today = new Date(); var year4digit = today.getFullYear(); var month2digit = ("0" + (today.getMonth()+1)).slice(-2); var day2digit = ("0" + today.getDate()).slice(-2); var hour2digit = ("0" + today.getHours()).slice(-2); var minutes2digit = ("0" + today.getMinutes()).slice(-2); var seconds2digit = ("0" + today.getSeconds()).slice(-2); var filename_date = '_' + year4digit + '-' + month2digit + '-' + day2digit + '_' + hour2digit + minutes2digit + seconds2digit; var userHomeFolder = System.getProperty("user.home"); var filename = userHomeFolder + '/Desktop/' + 'am335x-boot-analysis' + filename_date + '.txt'; file = new java.io.FileWriter(filename); debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS"); debugSessionDAP.target.connect(); var reg_val; // CONTROL: device_id reg_val = printRegisterValue(debugSessionDAP, "CONTROL: device_id", 0x44E10600); if ( (reg_val & 0x0FFFFFFF) == 0xb94402e ) {file.write(" * AM335x family" + newline);} if ( (reg_val & 0xF0000000) == (0 << 28) ) {file.write(" * Silicon Revision 1.0" + newline);} if ( (reg_val & 0xF0000000) == (1 << 28) ) {file.write(" * Silicon Revision 2.0" + newline);} if ( (reg_val & 0xF0000000) == (2 << 28) ) {file.write(" * Silicon Revision 2.1" + newline);} // ROM: PRM_RSTST file.write(newline); reg_val = printRegisterValue(debugSessionDAP, "PRM_DEVICE: PRM_RSTST", 0x44E00F08); if (reg_val & 1<<0 ) {file.write(" * Bit 0 : GLOBAL_COLD_RST" + newline);} if (reg_val & 1<<1 ) {file.write(" * Bit 1 : GLOBAL_WARM_RST" + newline);} if (reg_val & 1<<4 ) {file.write(" * Bit 4 : WDT1_RST" + newline);} if (reg_val & 1<<5 ) {file.write(" * Bit 5 : EXTERNAL_WARM_RST" + newline);} // CONTROL: control_status file.write(newline); reg_val = printRegisterValue(debugSessionDAP, "CONTROL: control_status", 0x44E10040); boot_sequence = (reg_val & 0x1F); if ( (reg_val & 3<<22 ) == 0<<22 ) {file.write(" * SYSBOOT[15:14] = 00b (19.2 MHz)" + newline);} if ( (reg_val & 3<<22 ) == 1<<22 ) {file.write(" * SYSBOOT[15:14] = 01b (24 MHz)" + newline);} if ( (reg_val & 3<<22 ) == 2<<22 ) {file.write(" * SYSBOOT[15:14] = 10b (25 MHz)" + newline);} if ( (reg_val & 3<<22 ) == 3<<22 ) {file.write(" * SYSBOOT[15:14] = 11b (26 MHz)" + newline);} if ( (reg_val & 3<<20 ) != 0<<20 ) {file.write(" * SYSBOOT[13:12] have been set improperly!" + newline);} if ( (reg_val & 3<<18 ) == 0<<18 ) {file.write(" * SYSBOOT[11:10] = 00b No GPMC CS0 addr/data muxing" + newline);} if ( (reg_val & 3<<18 ) == 1<<18 ) {file.write(" * SYSBOOT[11:10] = 01b GPMC CS0 addr/addr/data muxing" + newline);} if ( (reg_val & 3<<18 ) == 2<<18 ) {file.write(" * SYSBOOT[11:10] = 10b GPMC CS0 addr/data muxing" + newline);} if ( (reg_val & 3<<18 ) == 3<<18 ) {file.write(" * SYSBOOT[11:10] = 11b ILLEGAL VALUE!" + newline);} if ( (reg_val & 1<<17 ) == 1<<17 ) {file.write(" * SYSBOOT[9] = 0 GPMC CS0 Ignore WAIT input" + newline);} if ( (reg_val & 1<<17 ) == 1<<17 ) {file.write(" * SYSBOOT[9] = 1 GPMC CS0 Use WAIT input" + newline);} if ( (reg_val & 1<<16 ) == 1<<16 ) {file.write(" * SYSBOOT[8] = 0 GPMC CS0 8-bit data bus" + newline);} if ( (reg_val & 1<<16 ) == 1<<16 ) {file.write(" * SYSBOOT[8] = 1 GPMC CS0 16-bit data bus" + newline);} if ( (reg_val & 7<<8 ) == 3<<8 ) {file.write(" * Device Type = General Purpose (GP)" + newline);} else {file.write(" * Device Type is NOT GP" + newline);} if ( (reg_val & 0xFF ) == 0x01 ) {file.write(" * SYSBOOT[8] = 1 GPMC CS0 16-bit data bus" + newline);} if ( (reg_val & 3<<6 ) == 0<<6 ) {file.write(" * SYSBOOT[7:6] = 00b MII (EMAC boot modes only)" + newline);} if ( (reg_val & 3<<6 ) == 1<<6 ) {file.write(" * SYSBOOT[7:6] = 01b RMII (EMAC boot modes only)" + newline);} if ( (reg_val & 3<<6 ) == 2<<6 ) {file.write(" * SYSBOOT[7:6] = 10b ILLEGAL VALUE!" + newline);} if ( (reg_val & 3<<6 ) == 3<<6 ) {file.write(" * SYSBOOT[7:6] = 11b RGMII no internal delay (EMAC boot modes only)" + newline);} if ( (reg_val & 1<<5 ) == 0<<5 ) {file.write(" * SYSBOOT[5] = 0 CLKOUT1 disabled" + newline);} if ( (reg_val & 1<<5 ) == 1<<5 ) {file.write(" * SYSBOOT[5] = 1 CLKOUT1 enabled" + newline);} if (boot_sequence == 0x00) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);} if (boot_sequence == 0x01) {file.write(" * Boot Sequence : UART0 -> XIP w/WAIT (MUX2) -> MMC0 -> SPI0" + newline);} if (boot_sequence == 0x02) {file.write(" * Boot Sequence : UART0 -> SPI0 -> NAND -> NANDI2C" + newline);} if (boot_sequence == 0x03) {file.write(" * Boot Sequence : UART0 -> SPI0 -> XIP (MUX2) -> MMC0" + newline);} if (boot_sequence == 0x04) {file.write(" * Boot Sequence : UART0 -> XIP w/WAIT (MUX1) -> MMC0 -> NAND" + newline);} if (boot_sequence == 0x05) {file.write(" * Boot Sequence : UART0 -> XIP (MUX1) -> SPI0 -> NANDI2C" + newline);} if (boot_sequence == 0x06) {file.write(" * Boot Sequence : EMAC1 -> SPI0 -> NAND -> NANDI2C" + newline);} if (boot_sequence == 0x07) {file.write(" * Boot Sequence : EMAC1 -> MMC0 -> XIP w/WAIT (MUX2) -> NAND" + newline);} if (boot_sequence == 0x08) {file.write(" * Boot Sequence : EMAC1 -> MMC0 -> XIP (MUX2) -> NANDI2C" + newline);} if (boot_sequence == 0x09) {file.write(" * Boot Sequence : EMAC1 -> XIP w/WAIT (MUX1) -> NAND -> MMC0" + newline);} if (boot_sequence == 0x0A) {file.write(" * Boot Sequence : EMAC1 -> XIP (MUX1) -> SPI0 -> NANDI2C" + newline);} if (boot_sequence == 0x0B) {file.write(" * Boot Sequence : USB0 -> NAND -> SPI0 -> MMC0" + newline);} if (boot_sequence == 0x0C) {file.write(" * Boot Sequence : USB0 -> NAND -> XIP (MUX2) -> NANDI2C" + newline);} if (boot_sequence == 0x0D) {file.write(" * Boot Sequence : USB0 -> NAND -> XIP (MUX1) -> SPI0" + newline);} if (boot_sequence == 0x0E) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);} if (boot_sequence == 0x0F) {file.write(" * Boot Sequence : UART0 -> EMAC1 -> Reserved -> Reserved" + newline);} if (boot_sequence == 0x10) {file.write(" * Boot Sequence : XIP (MUX1) -> UART0 -> EMAC1 -> MMC0 " + newline);} if (boot_sequence == 0x11) {file.write(" * Boot Sequence : XIP w/WAIT (MUX1) -> UART0 -> EMAC1 -> MMC0" + newline);} if (boot_sequence == 0x12) {file.write(" * Boot Sequence : NAND -> NANDI2C -> USB0 -> UART0" + newline);} if (boot_sequence == 0x13) {file.write(" * Boot Sequence : NAND -> NANDI2C -> MMC0 -> UART0" + newline);} if (boot_sequence == 0x14) {file.write(" * Boot Sequence : NAND -> NANDI2C -> SPI0 -> EMAC1" + newline);} if (boot_sequence == 0x15) {file.write(" * Boot Sequence : NANDI2C -> MMC0 -> EMAC1 -> UART0" + newline);} if (boot_sequence == 0x16) {file.write(" * Boot Sequence : SPI0 -> MMC0 -> UART0 -> EMAC1" + newline);} if (boot_sequence == 0x17) {file.write(" * Boot Sequence : MMC0 -> SPI0 -> UART0 -> USB0" + newline);} if (boot_sequence == 0x18) {file.write(" * Boot Sequence : SPI0 -> MMC0 -> USB0 -> UART0" + newline);} if (boot_sequence == 0x19) {file.write(" * Boot Sequence : SPI0 -> MMC0 -> EMAC1 -> UART0" + newline);} if (boot_sequence == 0x1A) {file.write(" * Boot Sequence : XIP (MUX2) -> UART0 -> SPI0 -> MMC0" + newline);} if (boot_sequence == 0x1B) {file.write(" * Boot Sequence : XIP w/WAIT (MUX2) -> UART0 -> SPI0 -> MMC0" + newline);} if (boot_sequence == 0x1C) {file.write(" * Boot Sequence : MMC1 -> MMC0 -> UART0 -> USB0" + newline);} if (boot_sequence == 0x1D) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);} if (boot_sequence == 0x1E) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);} if (boot_sequence == 0x1F) {file.write(" * Boot Sequence : Fast External Boot -> EMAC1 -> UART0 -> Reserved" + newline);} // ROM: Tracing Vector 1 file.write(newline); reg_val = printRegisterValue(debugSessionDAP, "ROM: Current tracing vector, word 1", 0x4030CE40); if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [General] Passed the public reset vector" + newline);} if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [General] Entered main function" + newline);} if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [General] Running after the cold reset" + newline);} if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Boot] Main booting routine entered" + newline);} if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Memory booting started" + newline);} if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Peripheral Boot] Peripheral booting started" + newline);} if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [Boot] Booting loop reached last device" + newline);} if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Boot] GP header found" + newline);} if (reg_val & 1<<8 ) {file.write(" * Bit 8 : [Boot] Reserved" + newline);} if (reg_val & 1<<9 ) {file.write(" * Bit 9 : [Boot] Reserved" + newline);} if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<11 ) {file.write(" * Bit 11 : [Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Peripheral Boot] Device initialized" + newline);} if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Peripheral Boot] ASIC ID sent" + newline);} if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Peripheral Boot] Image received" + newline);} if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Peripheral Boot] Peripheral booting failed" + newline);} if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Peripheral Boot] Booting Message not received (timeout)" + newline);} if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Image size not received (timeout)" + newline);} if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Image not received (timeout)" + newline);} if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);} if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Configuration Header] CHSETTINGS found" + newline);} if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Configuration Header] CHSETTINGS executed" + newline);} if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Configuration Header] CHRAM executed" + newline);} if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Configuration Header] CHFLASH executed" + newline);} if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Configuration Header] CHMMCSD clocks executed" + newline);} if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Configuration Header] CHMMCSD bus width executed" + newline);} if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);} if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);} if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);} if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);} if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);} if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);} // ROM: Tracing Vector 2 file.write(newline); reg_val = printRegisterValue(debugSessionDAP, "ROM: Current tracing vector, word 1", 0x4030CE44); if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Companion chip] Reserved" + newline);} if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Companion chip] Reserved" + newline);} if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Companion chip] Reserved" + newline);} if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Companion chip] Reserved" + newline);} if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [USB] USB connect" + newline);} if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [USB] USB configured state" + newline);} if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [USB] USB VBUS valid" + newline);} if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [USB] USB session valid" + newline);} if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);} if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);} if (reg_val & 1<<10 ) {file.write(" * Bit 10 : Reserved" + newline);} if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);} if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Memory Boot] Memory booting trial 0" + newline);} if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Memory Boot] Memory booting trial 1" + newline);} if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Memory Boot] Memory booting trial 2" + newline);} if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Memory Boot] Memory booting trial 3" + newline);} if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Memory Boot] Execute GP image" + newline);} if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Start authentication of peripheral boot image" + newline);} if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Memory & Peripheral Boot] Jumping to Initial SW" + newline);} if (reg_val & 1<<19 ) {file.write(" * Bit 19 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Memory & Peripheral Boot] Start image authentication" + newline);} if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Memory & Peripheral Boot] Image authentication failed" + newline);} if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Memory & Peripheral Boot] Analyzing SpeedUp" + newline);} if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Memory & Peripheral Boot] SpeedUp failed" + newline);} if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<26 ) {file.write(" * Bit 26 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<27 ) {file.write(" * Bit 27 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<28 ) {file.write(" * Bit 28 : [Memory & Peripheral Boot] Authentication procedure failed" + newline);} if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);} if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);} if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);} // ROM: Tracing Vector 3 file.write(newline); reg_val = printRegisterValue(debugSessionDAP, "ROM: Current tracing vector, word 1", 0x4030CE48); if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Memory Boot] Memory booting device NULL" + newline);} if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Memory Boot] Memory booting device XIP" + newline);} if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Memory Boot] Memory booting device XIPWAIT" + newline);} if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Memory Boot] Memory booting device NAND" + newline);} if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Reserved" + newline);} if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Memory Boot] Memory booting device MMCSD0" + newline);} if (reg_val & 1<<6 ) {file.write(" * Bit 6 : Reserved" + newline);} if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Memory Boot] Memory booting device MMCSD1" + newline);} if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);} if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);} if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Memory Boot] Reserved" + newline);} if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);} if (reg_val & 1<<12 ) {file.write(" * Bit 12 : Memory booting device SPI" + newline);} if (reg_val & 1<<13 ) {file.write(" * Bit 13 : Reserved" + newline);} if (reg_val & 1<<14 ) {file.write(" * Bit 14 : Reserved" + newline);} if (reg_val & 1<<15 ) {file.write(" * Bit 15 : Reserved" + newline);} if (reg_val & 1<<16 ) {file.write(" * Bit 16 : Peripheral booting device UART0" + newline);} if (reg_val & 1<<17 ) {file.write(" * Bit 17 : Reserved" + newline);} if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);} if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Peripheral Boot] Peripheral booting device USB" + newline);} if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Peripheral Boot] Peripheral booting device GPGMAC0" + newline);} if (reg_val & 1<<23 ) {file.write(" * Bit 23 : Reserved" + newline);} if (reg_val & 1<<24 ) {file.write(" * Bit 24 : Peripheral booting device NULL" + newline);} if (reg_val & 1<<25 ) {file.write(" * Bit 25 : Reserved" + newline);} if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);} if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);} if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);} if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);} if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);} if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);} // ROM: Copy of PRM_RSTST file.write(newline); reg_val = printRegisterValue(debugSessionDAP, "ROM: Current copy of PRM_RSTST", 0x4030CE4C); if (reg_val & 1<<0 ) {file.write(" * Bit 0 : GLOBAL_COLD_RST" + newline);} if (reg_val & 1<<1 ) {file.write(" * Bit 1 : GLOBAL_WARM_RST" + newline);} if (reg_val & 1<<4 ) {file.write(" * Bit 4 : WDT1_RST" + newline);} if (reg_val & 1<<5 ) {file.write(" * Bit 5 : EXTERNAL_WARM_RST" + newline);} // ROM: Cold Reset Tracing Vector 1 file.write(newline); reg_val = printRegisterValue(debugSessionDAP, "ROM: Cold reset tracing vector, word 1", 0x4030CE50); if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [General] Passed the public reset vector" + newline);} if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [General] Entered main function" + newline);} if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [General] Running after the cold reset" + newline);} if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Boot] Main booting routine entered" + newline);} if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Memory booting started" + newline);} if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Peripheral Boot] Peripheral booting started" + newline);} if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [Boot] Booting loop reached last device" + newline);} if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Boot] GP header found" + newline);} if (reg_val & 1<<8 ) {file.write(" * Bit 8 : [Boot] Reserved" + newline);} if (reg_val & 1<<9 ) {file.write(" * Bit 9 : [Boot] Reserved" + newline);} if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<11 ) {file.write(" * Bit 11 : [Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Peripheral Boot] Device initialized" + newline);} if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Peripheral Boot] ASIC ID sent" + newline);} if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Peripheral Boot] Image received" + newline);} if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Peripheral Boot] Peripheral booting failed" + newline);} if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Peripheral Boot] Booting Message not received (timeout)" + newline);} if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Image size not received (timeout)" + newline);} if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Image not received (timeout)" + newline);} if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);} if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Configuration Header] CHSETTINGS found" + newline);} if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Configuration Header] CHSETTINGS executed" + newline);} if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Configuration Header] CHRAM executed" + newline);} if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Configuration Header] CHFLASH executed" + newline);} if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Configuration Header] CHMMCSD clocks executed" + newline);} if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Configuration Header] CHMMCSD bus width executed" + newline);} if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);} if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);} if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);} if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);} if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);} if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);} // ROM: Cold Reset Tracing Vector 2 file.write(newline); reg_val = printRegisterValue(debugSessionDAP, "ROM: Cold reset tracing vector, word 1", 0x4030CE54); if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Companion chip] Reserved" + newline);} if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Companion chip] Reserved" + newline);} if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Companion chip] Reserved" + newline);} if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Companion chip] Reserved" + newline);} if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [USB] USB connect" + newline);} if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [USB] USB configured state" + newline);} if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [USB] USB VBUS valid" + newline);} if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [USB] USB session valid" + newline);} if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);} if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);} if (reg_val & 1<<10 ) {file.write(" * Bit 10 : Reserved" + newline);} if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);} if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Memory Boot] Memory booting trial 0" + newline);} if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Memory Boot] Memory booting trial 1" + newline);} if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Memory Boot] Memory booting trial 2" + newline);} if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Memory Boot] Memory booting trial 3" + newline);} if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Memory Boot] Execute GP image" + newline);} if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Start authentication of peripheral boot image" + newline);} if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Memory & Peripheral Boot] Jumping to Initial SW" + newline);} if (reg_val & 1<<19 ) {file.write(" * Bit 19 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Memory & Peripheral Boot] Start image authentication" + newline);} if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Memory & Peripheral Boot] Image authentication failed" + newline);} if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Memory & Peripheral Boot] Analyzing SpeedUp" + newline);} if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Memory & Peripheral Boot] SpeedUp failed" + newline);} if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<26 ) {file.write(" * Bit 26 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<27 ) {file.write(" * Bit 27 : [Memory & Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<28 ) {file.write(" * Bit 28 : [Memory & Peripheral Boot] Authentication procedure failed" + newline);} if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);} if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);} if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);} // ROM: Cold Reset Tracing Vector 3 file.write(newline); reg_val = printRegisterValue(debugSessionDAP, "ROM: Cold reset tracing vector, word 1", 0x4030CE58); if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Memory Boot] Memory booting device NULL" + newline);} if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Memory Boot] Memory booting device XIP" + newline);} if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Memory Boot] Memory booting device XIPWAIT" + newline);} if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Memory Boot] Memory booting device NAND" + newline);} if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Reserved" + newline);} if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Memory Boot] Memory booting device MMCSD0" + newline);} if (reg_val & 1<<6 ) {file.write(" * Bit 6 : Reserved" + newline);} if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Memory Boot] Memory booting device MMCSD1" + newline);} if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);} if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);} if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Memory Boot] Reserved" + newline);} if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);} if (reg_val & 1<<12 ) {file.write(" * Bit 12 : Memory booting device SPI" + newline);} if (reg_val & 1<<13 ) {file.write(" * Bit 13 : Reserved" + newline);} if (reg_val & 1<<14 ) {file.write(" * Bit 14 : Reserved" + newline);} if (reg_val & 1<<15 ) {file.write(" * Bit 15 : Reserved" + newline);} if (reg_val & 1<<16 ) {file.write(" * Bit 16 : Peripheral booting device UART0" + newline);} if (reg_val & 1<<17 ) {file.write(" * Bit 17 : Reserved" + newline);} if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);} if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Peripheral Boot] Peripheral booting device USB" + newline);} if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Peripheral Boot] Reserved" + newline);} if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Peripheral Boot] Peripheral booting device GPGMAC0" + newline);} if (reg_val & 1<<23 ) {file.write(" * Bit 23 : Reserved" + newline);} if (reg_val & 1<<24 ) {file.write(" * Bit 24 : Peripheral booting device NULL" + newline);} if (reg_val & 1<<25 ) {file.write(" * Bit 25 : Reserved" + newline);} if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);} if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);} if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);} if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);} if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);} if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);} debugSessionDAP.target.disconnect(); debugSessionA8 = ds.openSession("*","CortxA8"); debugSessionA8.target.connect(); // Get value of ARM Program Counter value = debugSessionA8.memory.readRegister("PC"); value_string = d2h(value); file.write(newline + "Cortex A8 Program Counter = 0x" + value_string + newline); file.write(newline); file.write("ROM Exception Vectors" + newline); file.write(" * 0x4030CE04 Undefined" + newline); file.write(" * 0x4030CE08 SWI" + newline); file.write(" * 0x4030CE0C Pre-fetch abort" + newline); file.write(" * 0x4030CE10 Data abort" + newline); file.write(" * 0x4030CE14 Unused" + newline); file.write(" * 0x4030CE18 IRQ" + newline); file.write(" * 0x4030CE1C FIQ" + newline); file.write(newline); file.write("ROM Dead Loops" + newline); file.write(" * 0x00020080 Undefined exception default handler" + newline); file.write(" * 0x00020084 SWI exception default handler" + newline); file.write(" * 0x00020088 Pre-fetch abort exception default handler" + newline); file.write(" * 0x0002008C Data exception default handler" + newline); file.write(" * 0x00020090 Unused exception default handler" + newline); file.write(" * 0x00020094 IRQ exception default handler" + newline); file.write(" * 0x00020098 FIQ exception default handler" + newline); file.write(" * 0x0002009C Validation test PASS" + newline); file.write(" * 0x000200A0 Validation test FAIL" + newline); file.write(" * 0x000200A4 Reserved" + newline); file.write(" * 0x000200A8 Image not executed or returned" + newline); file.write(" * 0x000200AC Reserved" + newline); file.write(" * 0x000200B0 Reserved" + newline); file.write(" * 0x000200B4 Reserved" + newline); file.write(" * 0x000200B8 Reserved" + newline); file.write(" * 0x000200BC Reserved" + newline); debugSessionA8.target.disconnect(); file.close();