index cbf929a00b6e86f45ea4de0ab85ccdff5905a2dd..07da1d0fa096d9e8e4b94b2cfc6c08afbb451383 100644 (file)
--- a/am335x-ddr-analysis.dss
+++ b/am335x-ddr-analysis.dss
if ( (reg_val & 0x300) == (1 << 8) ) {file.write("no termination (01b)\n");}
if ( (reg_val & 0x300) == (2 << 8) ) {file.write("full thevenin termination\n");}
if ( (reg_val & 0x300) == (3 << 8) ) {file.write("half thevenin termination\n");}
+ reg_read_latency = bits32(reg_val, 4, 0);
+ if( reg_read_latency < decoded_CL+1 )
+ file.write(" * Bits 4:0 (reg_read_latency) set to " + d2d(reg_read_latency) + " -> ERROR: TOO SMALL" + newline);
+ else if (reg_read_latency == decoded_CL+1) {
+ file.write(" * Bits 4:0 (reg_read_latency) set to " + d2d(reg_read_latency) + newline);
+ file.write(" -> If PHY_INVERT_CLKOUT=0, this is an appropriate value." + newline);
+ file.write(" -> If PHY_INVERT_CLKOUT=1, this is too small." + newline);
+ file.write(" -> PHY_INVERT_CLKOUT is a write-only register, so this needs to be" + newline);
+ file.write(" -> inspected closely in the code and RatioSeed spreadsheet." + newline);
+ } else
+ file.write(" * Bits 4:0 (reg_read_latency) set to " + d2d(reg_read_latency) + " -> Ok: CL+2 is typical with PHY_INVERT_CLKOUT=1." + newline);
file.write("\n");
file.write("*********************\n");