index 7c8871ea660ab1b49e4f430ee8d797d7c8327a1c..3aa739f7ed2a397ea5ef6ccc1f95875ad84d5c3b 100644 (file)
--- a/am335x-ddr-analysis.dss
+++ b/am335x-ddr-analysis.dss
return value; // return the register value for interrogation\r
}\r
\r
+function interpret_cmd_phy_macro(value, index)\r
+{\r
+ WD1 = (value >> (21+index)) & 1;\r
+ WD0 = (value >> (10+index)) & 1;\r
+ WD = (WD1 << 1) | WD0;\r
+ if (WD == 0) return_string = "Pullup/Pulldown disabled\n";\r
+ if (WD == 1) return_string = "Weak pullup enabled\n";\r
+ if (WD == 2) return_string = "Weak pulldown enabled\n";\r
+ if (WD == 3) return_string = "Weak keeper enabled\n"; \r
+ return return_string;\r
+}\r
+\r
+function interpret_data_phy_macro(value, index)\r
+{\r
+ WD1 = (value >> (20+index)) & 1;\r
+ WD0 = (value >> (10+index)) & 1;\r
+ WD = (WD1 << 1) | WD0;\r
+ if (WD == 0) return_string = "Pullup/Pulldown disabled\n";\r
+ if (WD == 1) return_string = "Weak pullup enabled\n";\r
+ if (WD == 2) return_string = "Weak pulldown enabled\n";\r
+ if (WD == 3) return_string = "Weak keeper enabled\n"; \r
+ return return_string;\r
+}\r
+\r
// Build a filename that includes date/time\r
var today = new Date();\r
var year4digit = today.getFullYear();\r
@@ -53,83 +77,132 @@ var filename_date = '_' + year4digit + '-' + month2digit + '-' + day2digit + '_'
var userHomeFolder = System.getProperty("user.home");\r
var filename = userHomeFolder + '/Desktop/' + 'am335x-ddr-analysis' + filename_date + '.txt';\r
\r
-file = new java.io.FileWriter(filename);\r
+debugSessionDAP = ds.openSession("*","CS_DAP_M3");\r
\r
-debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS");\r
-debugSessionDAP.target.connect();\r
-\r
-var reg_val;\r
-\r
-// EMIF: SDRAM_CONFIG\r
-reg_val = printRegisterValue(debugSessionDAP, "EMIF: SDRAM_CONFIG", 0x4C000008);\r
-var is_ddr3=0;\r
-var is_ddr2=0;\r
-var is_lpddr=0;\r
-if ( (reg_val & 0xE0000000) == (0 << 29) ) {file.write(" * ERROR! Unsupported memory type (DDR1)\n");}\r
-if ( (reg_val & 0xE0000000) == (1 << 29) ) {is_lpddr=1;}\r
-if ( (reg_val & 0xE0000000) == (2 << 29) ) {is_ddr2=1;}\r
-if ( (reg_val & 0xE0000000) == (3 << 29) ) {is_ddr3=1;}\r
-if (is_ddr3 == 1) {\r
- file.write(" * Bits 26:24 (reg_ddr_term) set for ");\r
- if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}\r
- if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("RZQ/4 (001b)\n");}\r
- if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("RZQ/2 (010b)\n");}\r
- if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("RZQ/6 (011b)\n");}\r
- if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("RZQ/12 (100b)\n");}\r
- if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("RZQ/8 (101b)\n");}\r
- if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}\r
- if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}\r
-}\r
-if (is_ddr2 == 1) {\r
- file.write(" * Bits 26:24 (reg_ddr_term) set for ");\r
- if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}\r
- if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("75 Ohm (001b)\n");}\r
- if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("150 Ohm (010b)\n");}\r
- if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("50 Ohm (011b)\n");}\r
- if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("ERROR\n");}\r
- if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("ERROR\n");}\r
- if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}\r
- if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}\r
-}\r
-if (is_ddr3 == 1) {\r
- file.write(" * Bits 19:18 (reg_sdram_drive) set for ");\r
- if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("RZQ/6 (00b)\n");}\r
- if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("RZQ/7 (01b)\n");}\r
- if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}\r
- if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}\r
-}\r
-if (is_ddr2 == 1) {\r
- file.write(" * Bits 19:18 (reg_sdram_drive) set for ");\r
- if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("normal drive (00b)\n");}\r
- if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("weak drive (01b)\n");}\r
- if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}\r
- if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}\r
-}\r
-if (is_lpddr == 1) {\r
- file.write(" * Bits 19:18 (reg_sdram_drive) set for ");\r
- if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("full strength (00b)\n");}\r
- if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("half strength (01b)\n");}\r
- if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("quarter strength (10b)\n");}\r
- if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("eighth strength (11b)\n");}\r
+try {\r
+ debugSessionDAP.target.connect();\r
+} catch (ex) {\r
+ print("\n ERROR: Could not connect to DAP_M3.\n");\r
}\r
\r
-// EMIF: PWR_MGMT_CTRL\r
-reg_val = printRegisterValue(debugSessionDAP, "EMIF: PWR_MGMT_CTRL", 0x4C000038);\r
-if ( (reg_val & 0xF0) < 0x90 ) {\r
- file.write(" * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit\n");\r
- file.write(" * Please see the silicon errata for more details.\n");\r
-}\r
+var original_CM_WKUP_DEBUGSS_CLKCTRL = debugSessionDAP.memory.readWord(0,0x44e00414,false);\r
+var original_CM_PER_L3_CLKSTCTRL = debugSessionDAP.memory.readWord(0,0x44E0000C,false);\r
+\r
+file = new java.io.FileWriter(filename);\r
+\r
+// Only try to read EMIF registers if EMIF clock is enabled\r
+if (original_CM_PER_L3_CLKSTCTRL & 1<<2) {\r
\r
-// DDR PHY: DDR_PHY_CTRL_1\r
-reg_val = printRegisterValue(debugSessionDAP, "DDR PHY: DDR_PHY_CTRL_1", 0x4C0000E4);\r
-file.write(" * Bits 9:8 (reg_phy_rd_local_odt) configured as ");\r
-if ( (reg_val & 0x300) == (0 << 8) ) {file.write("no termination (00b)\n");}\r
-if ( (reg_val & 0x300) == (1 << 8) ) {file.write("no termination (01b)\n");}\r
-if ( (reg_val & 0x300) == (2 << 8) ) {file.write("full thevenin termination\n");}\r
-if ( (reg_val & 0x300) == (3 << 8) ) {file.write("half thevenin termination\n");}\r
+ // CM_WKUP_DEBUGSS_CLKCTRL[MODULEMODE] = ENABLED\r
+ debugSessionDAP.expression.evaluate(\r
+ "*((unsigned int*) 0x44e00414 ) |= 0x2;");\r
+\r
+ debugSessionDAP.target.disconnect(); // disconnect from DAP_M3\r
+ \r
+ // Connect to DAP_DebugSS for L3 visibility (EMIF regs)\r
+ debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS");\r
+ debugSessionDAP.target.connect();\r
+ \r
+ var reg_val;\r
+ \r
+ // EMIF: SDRAM_CONFIG\r
+ reg_val = printRegisterValue(debugSessionDAP, "EMIF: SDRAM_CONFIG", 0x4C000008);\r
+\r
+ var is_ddr3=0;\r
+ var is_ddr2=0;\r
+ var is_lpddr=0;\r
+ if ( (reg_val & 0xE0000000) == (0 << 29) ) {file.write(" * ERROR! Unsupported memory type (DDR1)\n");}\r
+ if ( (reg_val & 0xE0000000) == (1 << 29) ) {is_lpddr=1;}\r
+ if ( (reg_val & 0xE0000000) == (2 << 29) ) {is_ddr2=1;}\r
+ if ( (reg_val & 0xE0000000) == (3 << 29) ) {is_ddr3=1;}\r
+ if (is_ddr3 == 1) {\r
+ file.write(" * Bits 26:24 (reg_ddr_term) set for ");\r
+ if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}\r
+ if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("RZQ/4 (001b)\n");}\r
+ if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("RZQ/2 (010b)\n");}\r
+ if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("RZQ/6 (011b)\n");}\r
+ if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("RZQ/12 (100b)\n");}\r
+ if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("RZQ/8 (101b)\n");}\r
+ if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}\r
+ if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}\r
+ }\r
+ if (is_ddr2 == 1) {\r
+ file.write(" * Bits 26:24 (reg_ddr_term) set for ");\r
+ if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}\r
+ if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("75 Ohm (001b)\n");}\r
+ if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("150 Ohm (010b)\n");}\r
+ if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("50 Ohm (011b)\n");}\r
+ if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("ERROR\n");}\r
+ if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("ERROR\n");}\r
+ if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}\r
+ if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}\r
+ }\r
+ if (is_ddr3 == 1) {\r
+ file.write(" * Bits 19:18 (reg_sdram_drive) set for ");\r
+ if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("RZQ/6 (00b)\n");}\r
+ if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("RZQ/7 (01b)\n");}\r
+ if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}\r
+ if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}\r
+ }\r
+ if (is_ddr2 == 1) {\r
+ file.write(" * Bits 19:18 (reg_sdram_drive) set for ");\r
+ if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("normal drive (00b)\n");}\r
+ if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("weak drive (01b)\n");}\r
+ if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}\r
+ if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}\r
+ }\r
+ if (is_lpddr == 1) {\r
+ file.write(" * Bits 19:18 (reg_sdram_drive) set for ");\r
+ if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("full strength (00b)\n");}\r
+ if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("half strength (01b)\n");}\r
+ if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("quarter strength (10b)\n");}\r
+ if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("eighth strength (11b)\n");}\r
+ }\r
+ \r
+ // EMIF: PWR_MGMT_CTRL\r
+ reg_val = printRegisterValue(debugSessionDAP, "EMIF: PWR_MGMT_CTRL", 0x4C000038);\r
+ if ( (reg_val & 0xF0) < 0x90 ) {\r
+ file.write(" * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit\n");\r
+ file.write(" * Please see the silicon errata for more details.\n");\r
+ }\r
+ \r
+ // DDR PHY: DDR_PHY_CTRL_1\r
+ reg_val = printRegisterValue(debugSessionDAP, "DDR PHY: DDR_PHY_CTRL_1", 0x4C0000E4);\r
+ if ( (reg_val & 1<<20) == 0 ) {file.write(" * WARNING: reg_phy_enable_dynamic_pwrdn disabled.\n");}\r
+ file.write(" * Bits 9:8 (reg_phy_rd_local_odt) configured as ");\r
+ if ( (reg_val & 0x300) == (0 << 8) ) {file.write("no termination (00b)\n");}\r
+ if ( (reg_val & 0x300) == (1 << 8) ) {file.write("no termination (01b)\n");}\r
+ if ( (reg_val & 0x300) == (2 << 8) ) {file.write("full thevenin termination\n");}\r
+ if ( (reg_val & 0x300) == (3 << 8) ) {file.write("half thevenin termination\n");}\r
+ \r
+ // Close (Main) DAP session and use M3 DAP to view Control Registers\r
+ debugSessionDAP.target.disconnect();\r
+ debugSessionDAP = ds.openSession("*","CS_DAP_M3");\r
+ debugSessionDAP.target.connect();\r
+ \r
+ // Restore CM_WKUP_DEBUGSS_CLKCTRL[MODULEMODE]\r
+ if ( (original_CM_WKUP_DEBUGSS_CLKCTRL & 3) == 0 ) {\r
+ debugSessionDAP.memory.writeWord(0,0x44e00414,original_CM_WKUP_DEBUGSS_CLKCTRL);\r
+ }\r
+} else {\r
+ file.write("Skipping read of EMIF registers since EMIF clock disabled.\n");\r
+ file.write(" * EMIF registers are not readable when in DS0 state\n");\r
+ file.write(" * If you are attempting to enter DS0 this is normal.\n");\r
+}\r
\r
// CONTROL: DDR_CMD0_IOCTRL\r
reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD0_IOCTRL", 0x44E11404);\r
+file.write(" * ddr_ba2 " + interpret_cmd_phy_macro(reg_val, 0));\r
+file.write(" * ddr_wen " + interpret_cmd_phy_macro(reg_val, 1));\r
+file.write(" * ddr_ba0 " + interpret_cmd_phy_macro(reg_val, 2));\r
+file.write(" * ddr_a5 " + interpret_cmd_phy_macro(reg_val, 3));\r
+file.write(" * ddr_ck " + interpret_cmd_phy_macro(reg_val, 4));\r
+file.write(" * ddr_ckn " + interpret_cmd_phy_macro(reg_val, 5));\r
+file.write(" * ddr_a3 " + interpret_cmd_phy_macro(reg_val, 6));\r
+file.write(" * ddr_a4 " + interpret_cmd_phy_macro(reg_val, 7));\r
+file.write(" * ddr_a8 " + interpret_cmd_phy_macro(reg_val, 8));\r
+file.write(" * ddr_a9 " + interpret_cmd_phy_macro(reg_val, 9));\r
+file.write(" * ddr_a6 " + interpret_cmd_phy_macro(reg_val, 10));\r
file.write(" * Bits 9:5 control ddr_ck and ddr_ckn\n");\r
file.write(" - Slew ");\r
if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}\r
\r
// CONTROL: DDR_CMD1_IOCTRL\r
reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD1_IOCTRL", 0x44E11408);\r
+file.write(" * ddr_a15 " + interpret_cmd_phy_macro(reg_val, 1));\r
+file.write(" * ddr_a2 " + interpret_cmd_phy_macro(reg_val, 2));\r
+file.write(" * ddr_a12 " + interpret_cmd_phy_macro(reg_val, 3));\r
+file.write(" * ddr_a7 " + interpret_cmd_phy_macro(reg_val, 4));\r
+file.write(" * ddr_ba1 " + interpret_cmd_phy_macro(reg_val, 5));\r
+file.write(" * ddr_a10 " + interpret_cmd_phy_macro(reg_val, 6));\r
+file.write(" * ddr_a0 " + interpret_cmd_phy_macro(reg_val, 7));\r
+file.write(" * ddr_a11 " + interpret_cmd_phy_macro(reg_val, 8));\r
+file.write(" * ddr_casn " + interpret_cmd_phy_macro(reg_val, 9));\r
+file.write(" * ddr_rasn " + interpret_cmd_phy_macro(reg_val, 10));\r
file.write(" * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn\n");\r
file.write(" - Slew ");\r
if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}\r
\r
// CONTROL: DDR_CMD2_IOCTRL\r
reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CMD2_IOCTRL", 0x44E1140C);\r
+file.write(" * ddr_cke " + interpret_cmd_phy_macro(reg_val, 0));\r
+file.write(" * ddr_resetn " + interpret_cmd_phy_macro(reg_val, 1));\r
+file.write(" * ddr_odt " + interpret_cmd_phy_macro(reg_val, 2));\r
+file.write(" * ddr_a14 " + interpret_cmd_phy_macro(reg_val, 4));\r
+file.write(" * ddr_a13 " + interpret_cmd_phy_macro(reg_val, 5));\r
+file.write(" * ddr_csn0 " + interpret_cmd_phy_macro(reg_val, 6));\r
+file.write(" * ddr_a1 " + interpret_cmd_phy_macro(reg_val, 8));\r
file.write(" * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1\n");\r
file.write(" - Slew ");\r
if ( (reg_val & 0x18) == (0 << 3) ) {file.write("fastest\n");}\r
\r
// CONTROL: DDR_DATA0_IOCTRL\r
reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_DATA0_IOCTRL", 0x44E11440);\r
+file.write(" * ddr_d8 " + interpret_data_phy_macro(reg_val, 0));\r
+file.write(" * ddr_d9 " + interpret_data_phy_macro(reg_val, 1));\r
+file.write(" * ddr_d10 " + interpret_data_phy_macro(reg_val, 2));\r
+file.write(" * ddr_d11 " + interpret_data_phy_macro(reg_val, 3));\r
+file.write(" * ddr_d12 " + interpret_data_phy_macro(reg_val, 4));\r
+file.write(" * ddr_d13 " + interpret_data_phy_macro(reg_val, 5));\r
+file.write(" * ddr_d14 " + interpret_data_phy_macro(reg_val, 6));\r
+file.write(" * ddr_d15 " + interpret_data_phy_macro(reg_val, 7));\r
+file.write(" * ddr_dqm1 " + interpret_data_phy_macro(reg_val, 8));\r
+file.write(" * ddr_dqs1 and ddr_dqsn1 " + interpret_data_phy_macro(reg_val, 9));\r
file.write(" * Bits 9:5 control ddr_dqs1, ddr_dqsn1\n");\r
file.write(" - Slew ");\r
if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}\r
\r
// CONTROL: DDR_DATA1_IOCTRL\r
reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_DATA1_IOCTRL", 0x44E11444);\r
+file.write(" * ddr_d0 " + interpret_data_phy_macro(reg_val, 0));\r
+file.write(" * ddr_d1 " + interpret_data_phy_macro(reg_val, 1));\r
+file.write(" * ddr_d2 " + interpret_data_phy_macro(reg_val, 2));\r
+file.write(" * ddr_d3 " + interpret_data_phy_macro(reg_val, 3));\r
+file.write(" * ddr_d4 " + interpret_data_phy_macro(reg_val, 4));\r
+file.write(" * ddr_d5 " + interpret_data_phy_macro(reg_val, 5));\r
+file.write(" * ddr_d6 " + interpret_data_phy_macro(reg_val, 6));\r
+file.write(" * ddr_d7 " + interpret_data_phy_macro(reg_val, 7));\r
+file.write(" * ddr_dqm0 " + interpret_data_phy_macro(reg_val, 8));\r
+file.write(" * ddr_dqs0 and ddr_dqsn0 " + interpret_data_phy_macro(reg_val, 9));\r
file.write(" * Bits 9:5 control ddr_dqs0, ddr_dqsn0\n");\r
file.write(" - Slew ");\r
if ( (reg_val & 0x300) == (0 << 8) ) {file.write("fastest\n");}\r
\r
// CONTROL: DDR_IO_CTRL\r
reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_IO_CTRL", 0x44E10E04);\r
+if ( (reg_val & (1 << 31)) == (1<<31) ) {\r
+ file.write(" * Bit 31: Overriding DDR_RESETn (expected for DS0).\n");\r
+} else {\r
+ file.write(" * Bit 31: DDR_RESETn controlled by EMIF.\n");\r
+}\r
if ( (reg_val & (1 << 28)) == 0) {\r
file.write(" * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.\n");\r
if (is_lpddr == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}\r
if (is_ddr3 == 1) {file.write("ERROR! Mismatch with SDRAM_CONFIG.\n");}\r
}\r
\r
-\r
+// CONTROL: VTP_CTRL\r
reg_val = printRegisterValue(debugSessionDAP, "CONTROL: VTP_CTRL", 0x44E10E0C);\r
+if ( reg_val == 0 ) {\r
+ file.write(" * VTP disabled (expected in DS0).\n");\r
+} else {\r
+ file.write(" * VTP not disabled (expected in normal operation, but not DS0).\n");\r
+}\r
+\r
+// CONTROL: VREF_CTRL\r
reg_val = printRegisterValue(debugSessionDAP, "CONTROL: VREF_CTRL", 0x44E10E14);\r
+if ( (reg_val & 1) == 0 ) {\r
+ file.write(" * VREF supplied externally (typical).\n");\r
+} else {\r
+ file.write(" * Internal VREF (unusual).\n");\r
+}\r
+\r
+// CONTROL: DDR_CKE_CTRL\r
reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_CKE_CTRL", 0x44E1131C);\r
+if ( (reg_val & 1) == 0 ) {\r
+ file.write(" * CKE gated (forces pin low).\n");\r
+} else {\r
+ file.write(" * CKE controlled by EMIF (normal/ungated operation).\n");\r
+}\r
\r
file.close();\r
+print("Created file " + filename);\r
debugSessionDAP.target.disconnect();\r
\r
+\r
+\r
+//****************************************************************************\r
+// getErrorCode\r
+//****************************************************************************\r
+function getErrorCode(exception)\r
+{\r
+ var ex2 = exception.javaException;\r
+ if (ex2 instanceof Packages.com.ti.ccstudio.scripting.environment.ScriptingException)\r
+ {\r
+ return ex2.getErrorID();\r
+ }\r
+ return 0;\r
+}\r