index 630a114457e8f8544c0246af61118f2efa09a1a6..48cf00adcc7284675547abca1424c96a67677421 100644 (file)
--- a/am335x-ddr-analysis.dss
+++ b/am335x-ddr-analysis.dss
// EMIF: SDRAM_CONFIG
file.write(newline);
reg_val = printRegisterValue(debugSessionDAP, "EMIF: SDRAM_CONFIG", 0x4C000008);
+ reg_sdram_type = bits32(reg_val, 31, 29);
+ reg_ibank_pos = bits32(reg_val, 28, 27);
+ reg_ddr_term = bits32(reg_val, 26, 24);
+ reg_ddr2_ddqs = bits32(reg_val, 23, 23);
+ reg_dyn_odt = bits32(reg_val, 22, 21);
+ reg_ddr_disable_dll = bits32(reg_val, 20, 20);
+ reg_sdram_drive = bits32(reg_val, 19, 18);
+ reg_cwl = bits32(reg_val, 17, 16);
+ reg_narrow_mode = bits32(reg_val, 15, 14);
+ reg_cl = bits32(reg_val, 13, 10);
+ reg_rowsize = bits32(reg_val, 9, 7);
+ reg_ibank = bits32(reg_val, 6, 4);
+ reg_ebank = bits32(reg_val, 3, 3);
+ reg_pagesize = bits32(reg_val, 2, 0);
var is_ddr3=0;
var is_ddr2=0;
var is_lpddr=0;
- if ( (reg_val & 0xE0000000) == (0 << 29) ) {file.write(" * ERROR! Unsupported memory type (DDR1)\n");}
- if ( (reg_val & 0xE0000000) == (1 << 29) ) {is_lpddr=1;}
- if ( (reg_val & 0xE0000000) == (2 << 29) ) {is_ddr2=1;}
- if ( (reg_val & 0xE0000000) == (3 << 29) ) {is_ddr3=1;}
+
+ switch (reg_sdram_type) {
+ case 0:
+ file.write(" * ERROR! Unsupported memory type (DDR1)" + newline);
+ break;
+ case 1:
+ file.write(" * Bits 31:29 (reg_sdram_type) set for LPDDR" + newline);
+ is_lpddr=1;
+ break;
+ case 2:
+ file.write(" * Bits 31:29 (reg_sdram_type) set for DDR2" + newline);
+ is_ddr2=1;
+ break;
+ case 3:
+ file.write(" * Bits 31:29 (reg_sdram_type) set for DDR3" + newline);
+ is_ddr3=1;
+ break;
+ default:
+ file.write(" * Bits 31:29 (reg_sdram_type) set to invalid selection!" + newline);
+ }
+ file.write(" * Bits 28:27 (reg_ibank_pos) set to " + d2d(reg_ibank_pos) + newline);
if (is_ddr3 == 1) {
- file.write(" * Bits 31:29 (reg_sdram_type) set for DDR3\n");
file.write(" * Bits 26:24 (reg_ddr_term) set for ");
- if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}
- if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("RZQ/4 (001b)\n");}
- if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("RZQ/2 (010b)\n");}
- if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("RZQ/6 (011b)\n");}
- if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("RZQ/12 (100b)\n");}
- if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("RZQ/8 (101b)\n");}
- if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}
- if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}
+ if ( reg_ddr_term == 0 ) {file.write("termination disabled (000b)\n");}
+ if ( reg_ddr_term == 1 ) {file.write("RZQ/4 (001b)\n");}
+ if ( reg_ddr_term == 2 ) {file.write("RZQ/2 (010b)\n");}
+ if ( reg_ddr_term == 3 ) {file.write("RZQ/6 (011b)\n");}
+ if ( reg_ddr_term == 4 ) {file.write("RZQ/12 (100b)\n");}
+ if ( reg_ddr_term == 5 ) {file.write("RZQ/8 (101b)\n");}
+ if ( reg_ddr_term == 6 ) {file.write("ERROR\n");}
+ if ( reg_ddr_term == 7 ) {file.write("ERROR\n");}
}
if (is_ddr2 == 1) {
- file.write(" * Bits 31:29 (reg_sdram_type) set for DDR2\n");
file.write(" * Bits 26:24 (reg_ddr_term) set for ");
- if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}
- if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("75 Ohm (001b)\n");}
- if ( (reg_val & 0x07000000) == (2 << 24) ) {file.write("150 Ohm (010b)\n");}
- if ( (reg_val & 0x07000000) == (3 << 24) ) {file.write("50 Ohm (011b)\n");}
- if ( (reg_val & 0x07000000) == (4 << 24) ) {file.write("ERROR\n");}
- if ( (reg_val & 0x07000000) == (5 << 24) ) {file.write("ERROR\n");}
- if ( (reg_val & 0x07000000) == (6 << 24) ) {file.write("ERROR\n");}
- if ( (reg_val & 0x07000000) == (7 << 24) ) {file.write("ERROR\n");}
+ if ( reg_ddr_term == 0 ) {file.write("termination disabled (000b)\n");}
+ if ( reg_ddr_term == 1 ) {file.write("75 Ohm (001b)\n");}
+ if ( reg_ddr_term == 2 ) {file.write("150 Ohm (010b)\n");}
+ if ( reg_ddr_term == 3 ) {file.write("50 Ohm (011b)\n");}
+ if ( reg_ddr_term == 4 ) {file.write("ERROR\n");}
+ if ( reg_ddr_term == 5 ) {file.write("ERROR\n");}
+ if ( reg_ddr_term == 6 ) {file.write("ERROR\n");}
+ if ( reg_ddr_term == 7 ) {file.write("ERROR\n");}
+ }
+ if (is_ddr2 == 1) {
+ file.write(" * Bit 23 (reg_ddr2_ddqs) set to ");
+ if ( bits32(reg_val, 23, 23) == 0 ) {
+ file.write("single ended DQS." + newline);
+ } else {
+ file.write("differential DQS." + newline);
+ }
}
if (is_ddr3 == 1) {
+ file.write(" * Bits 22:21 (reg_dyn_odt) DDR3 dynamic ODT ");
+ if (reg_dyn_odt == 0)
+ file.write("disabled" + newline);
+ else if (reg_dyn_odt == 1)
+ file.write("set to RZQ / 4" + newline);
+ else if (reg_dyn_odt == 2)
+ file.write("set to RZQ / 2" + newline);
+ else
+ file.write("ERROR (illegal value)" + newline);
+ if (reg_ddr_disable_dll == 0)
+ file.write(" * Bit 20 (reg_ddr_disable_dll) set to 0, DDR3 DLL enabled" + newline);
+ else
+ file.write(" * Bit 20 (reg_ddr_disable_dll) set to 1, DDR3 DLL disabled" + newline);
+ file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
+ if ( reg_sdram_drive == 0 ) {file.write("RZQ/6 (00b)\n");}
+ if ( reg_sdram_drive == 1 ) {file.write("RZQ/7 (01b)\n");}
+ if ( reg_sdram_drive == 2 ) {file.write("ERROR (10b)\n");}
+ if ( reg_sdram_drive == 3 ) {file.write("ERROR (11b)\n");}
+ }
+ if (is_lpddr == 1) {
file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
- if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("RZQ/6 (00b)\n");}
- if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("RZQ/7 (01b)\n");}
- if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}
- if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}
+ if ( reg_sdram_drive == 0 ) {file.write("full strength (00b)\n");}
+ if ( reg_sdram_drive == 1 ) {file.write("half strength (01b)\n");}
+ if ( reg_sdram_drive == 2 ) {file.write("quarter strength (10b)\n");}
+ if ( reg_sdram_drive == 3 ) {file.write("eighth strength (11b)\n");}
}
if (is_ddr2 == 1) {
file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
- if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("normal drive (00b)\n");}
- if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("weak drive (01b)\n");}
- if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("ERROR (10b)\n");}
- if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("ERROR (11b)\n");}
+ if ( reg_sdram_drive == 0 ) {file.write("normal drive (00b)\n");}
+ if ( reg_sdram_drive == 1 ) {file.write("weak drive (01b)\n");}
+ if ( reg_sdram_drive == 2 ) {file.write("ERROR (10b)\n");}
+ if ( reg_sdram_drive == 3 ) {file.write("ERROR (11b)\n");}
+ }
+ if (is_ddr3 == 1) {
+ file.write(" * Bits 17:16 (reg_cwl) set for " + d2d(reg_cwl) + ", CWL = " + d2d(reg_cwl+5) + newline);
+ }
+ if (reg_narrow_mode == 1)
+ file.write(" * Bits 15:14 (reg_narrow_mode) set to 1 -> 16-bit EMIF interface" + newline);
+ else
+ file.write(" * Bits 15:14 (reg_narrow_mode) set to ILLEGAL VALUE" + newline);
+ file.write(" * Bits 13:10 (reg_cl) set to " + d2d(reg_cl) + " -> CL = ");
+ decoded_CL = 0;
+ if (is_ddr2 == 1) {
+ switch (reg_cl) {
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ decoded_CL = reg_cl;
+ file.write(d2d(decoded_CL) + newline);
+ break;
+ default:
+ file.write("ILLEGAL VALUE" + newline);
+ break;
+ }
+ }
+ if (is_ddr3 == 1) {
+ switch (reg_cl) {
+ case 2:
+ case 4:
+ case 6:
+ case 8:
+ case 10:
+ case 12:
+ case 14:
+ decoded_CL = reg_cl/2 + 4;
+ file.write(d2d(decoded_CL) + newline);
+ break;
+ default:
+ file.write("ILLEGAL VALUE" + newline);
+ break;
+ }
}
if (is_lpddr == 1) {
- file.write(" * Bits 31:29 (reg_sdram_type) set for LPDDR\n");
- file.write(" * Bits 19:18 (reg_sdram_drive) set for ");
- if ( (reg_val & 0x000C0000) == (0 << 18) ) {file.write("full strength (00b)\n");}
- if ( (reg_val & 0x000C0000) == (1 << 18) ) {file.write("half strength (01b)\n");}
- if ( (reg_val & 0x000C0000) == (2 << 18) ) {file.write("quarter strength (10b)\n");}
- if ( (reg_val & 0x000C0000) == (3 << 18) ) {file.write("eighth strength (11b)\n");}
+ switch (reg_cl) {
+ case 2:
+ case 3:
+ decoded_CL = reg_cl;
+ file.write(d2d(decoded_CL) + newline);
+ break;
+ default:
+ file.write("ILLEGAL VALUE" + newline);
+ break;
+ }
}
-
+ file.write(" * Bits 09:07 (reg_rowsize) set to " + d2d(reg_rowsize) + " -> " + d2d(reg_rowsize+9) + " row bits" + newline);
+ file.write(" * Bits 06:04 (reg_ibank) set to " + d2d(reg_ibank) + " -> ");
+ switch (reg_ibank) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ file.write(d2d(Math.pow(2,reg_ibank)) + " banks" + newline);
+ break;
+ default:
+ file.write("ILLEGAL VALUE" + newline);
+ break;
+ }
+ if (reg_ebank == 1)
+ file.write(" * Bit 03 ERROR, only 1 chip select allowed!" + newline);
+ file.write(" * Bits 02:00 (reg_pagesize) set to " + d2d(reg_pagesize) + " -> ");
+ switch (reg_pagesize) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ file.write(d2d(reg_pagesize+8) + " column bits" + newline);
+ break;
+ default:
+ file.write("ILLEGAL VALUE" + newline);
+ break;
+ }
+
// EMIF: PWR_MGMT_CTRL
reg_val = printRegisterValue(debugSessionDAP, "EMIF: PWR_MGMT_CTRL", 0x4C000038);
if ( (reg_val & 0xF0) < 0x90 ) {