Add extra robustness with try/catch statements

[sitara-dss-files/am335x-dss-files.git] / am335x-ddr-analysis.dss

diff --git a/am335x-ddr-analysis.dss b/am335x-ddr-analysis.dss
index 3e6ef2484467da2b9c33b462958617dd191e523f..828ff3464bf9c2fd6a6874399b5c4adc4a196dd5 100644 (file)
--- a/am335x-ddr-analysis.dss
+++ b/am335x-ddr-analysis.dss
@@ -85,7 +85,12 @@ debugSessionDAP.target.connect();
 var reg_val;\r
 \r
 // EMIF: SDRAM_CONFIG\r
+try{\r
 reg_val = printRegisterValue(debugSessionDAP, "EMIF: SDRAM_CONFIG", 0x4C000008);\r
+} catch (ex) {\r
+file.write(" * EMIF registers are not readable when in DS0 state\n");\r
+file.write(" * If you are attempting to enter DS0 this is normal.\n");\r
+}\r
 var is_ddr3=0;\r
 var is_ddr2=0;\r
 var is_lpddr=0;\r
@@ -138,14 +143,24 @@ if (is_lpddr == 1) {
 }\r
 \r
 // EMIF: PWR_MGMT_CTRL\r
+try{\r
 reg_val = printRegisterValue(debugSessionDAP, "EMIF: PWR_MGMT_CTRL", 0x4C000038);\r
+} catch (ex) {\r
+file.write(" * EMIF registers are not readable when in DS0 state\n");\r
+file.write(" * If you are attempting to enter DS0 this is normal.\n");\r
+}\r
 if ( (reg_val & 0xF0) < 0x90 ) {\r
        file.write(" * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit\n");\r
        file.write(" * Please see the silicon errata for more details.\n");\r
 }\r
 \r
 // DDR PHY: DDR_PHY_CTRL_1\r
+try{\r
 reg_val = printRegisterValue(debugSessionDAP, "DDR PHY: DDR_PHY_CTRL_1", 0x4C0000E4);\r
+} catch (ex) {\r
+file.write(" * EMIF registers are not readable when in DS0 state\n");\r
+file.write(" * If you are attempting to enter DS0 this is normal.\n");\r
+}\r
 if ( (reg_val & 1<<20) == 0 ) {file.write("  * WARNING: reg_phy_enable_dynamic_pwrdn disabled.\n");}\r
 file.write("  * Bits 9:8 (reg_phy_rd_local_odt) configured as ");\r
 if ( (reg_val & 0x300) == (0 << 8) ) {file.write("no termination (00b)\n");}\r