Check PWR_MGMT_CTRL.reg_sr_tim for JEDEC compliance
authorBrad Griffis <bgriffis@ti.com>
Fri, 6 Nov 2015 17:42:49 +0000 (11:42 -0600)
committerBrad Griffis <bgriffis@ti.com>
Fri, 6 Nov 2015 17:42:49 +0000 (11:42 -0600)
commit6614f8e013cb934d1da04fa5f7fddc5413c2c314
treecf70ec437027b7d3160e670a967802a6c20cb688
parentaba9f7ad0a98f5ac854e4d8e779742bec7a2b504
Check PWR_MGMT_CTRL.reg_sr_tim for JEDEC compliance

See the section titled "DDR3: JEDEC Compliance for Maximum Self-Refresh
Command Limit" in the AM335x silicon errata for more details.
am335x-ddr-analysis.dss