Add check for ddr_io_ctrl.ddr3_rst_def_val

diff --git a/am335x-ddr-analysis.dss b/am335x-ddr-analysis.dss
index ee8893944b086282bcbd8b9cd489e26800e94294..2a5437a4a72f7ea7294bfc3a92fc782a234b62cc 100644 (file)
--- a/am335x-ddr-analysis.dss
+++ b/am335x-ddr-analysis.dss
@@ -287,6 +287,11 @@ file.write("    - Drive Strength " + drive_strength_mA + " mA\n");
 \r
 // CONTROL: DDR_IO_CTRL\r
 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_IO_CTRL", 0x44E10E04);\r
 \r
 // CONTROL: DDR_IO_CTRL\r
 reg_val = printRegisterValue(debugSessionDAP, "CONTROL: DDR_IO_CTRL", 0x44E10E04);\r

+if ( (reg_val & (1 << 31)) == (1<<31) ) {\r
+       file.write("  * Bit 31: Overriding DDR_RESETn (expected for DS0).\n");\r
+} else {\r
+       file.write("  * Bit 31: DDR_RESETn controlled by EMIF.\n");\r
+}\r

 if ( (reg_val & (1 << 28)) == 0) {\r
        file.write("  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.\n");\r
        if (is_lpddr == 1) {file.write("ERROR!  Mismatch with SDRAM_CONFIG.\n");}\r
 if ( (reg_val & (1 << 28)) == 0) {\r
        file.write("  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.\n");\r
        if (is_lpddr == 1) {file.write("ERROR!  Mismatch with SDRAM_CONFIG.\n");}\r