[DDR] formatting
authorBrad Griffis <bgriffis@ti.com>
Thu, 25 Apr 2019 21:10:24 +0000 (16:10 -0500)
committerBrad Griffis <bgriffis@ti.com>
Thu, 25 Apr 2019 21:10:24 +0000 (16:10 -0500)
am335x-ddr-analysis.dss

index 48cf00adcc7284675547abca1424c96a67677421..cbf929a00b6e86f45ea4de0ab85ccdff5905a2dd 100644 (file)
@@ -379,6 +379,7 @@ if (original_CM_PER_L3_CLKSTCTRL & 1<<2) {
        }
 
        // EMIF: PWR_MGMT_CTRL
+       file.write(newline);
        reg_val = printRegisterValue(debugSessionDAP, "EMIF: PWR_MGMT_CTRL", 0x4C000038);
        if ( (reg_val & 0xF0) < 0x90 ) {
                file.write(" * ERROR: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit\n");
@@ -386,6 +387,7 @@ if (original_CM_PER_L3_CLKSTCTRL & 1<<2) {
        }
        
        // DDR PHY: DDR_PHY_CTRL_1
+       file.write(newline);
        reg_val = printRegisterValue(debugSessionDAP, "DDR PHY: DDR_PHY_CTRL_1", 0x4C0000E4);
        if ( (reg_val & 1<<20) == 0 ) {file.write("  * WARNING: reg_phy_enable_dynamic_pwrdn disabled.\n");}
        file.write("  * Bits 9:8 (reg_phy_rd_local_odt) configured as ");