[DDR] Additional checking of DDR_PHY_CTRL_1[reg_read_latency]
[sitara-dss-files/am335x-dss-files.git] / am335x-ddr-analysis.dss
2019-04-25 Brad Griffis[DDR] Additional checking of DDR_PHY_CTRL_1[reg_read_la...
2019-04-25 Brad Griffis[DDR] formatting
2019-04-25 Brad Griffis[DDR] Full decoding of SDRAM_CONFIG register
2019-04-25 Brad Griffis[DDR] Add parsing of DPLL_DDR
2019-04-23 Brad GriffisConditionally switch back to DAP_M3
2019-04-23 Brad Griffis[DDR] check if DAP_M3 values are sane
2019-04-23 Brad Griffis[DDR] Output configured DDR type
2017-10-18 Brad GriffisAdd more complete EMIF register dump
2017-02-17 Brad GriffisFix all line endings
2015-11-14 Brad GriffisImproved robustness due to clock inspection/adjustment
2015-11-11 Brad GriffisAdd extra robustness with try/catch statements
2015-11-09 Brad Griffisanalysis of ddr_cke_ctrl
2015-11-09 Brad Griffisvref_ctrl analysis
2015-11-09 Brad Griffisminor formatting
2015-11-09 Brad GriffisAdd comments regarding vtp_ctrl register
2015-11-09 Brad GriffisAdd check for ddr_io_ctrl.ddr3_rst_def_val
2015-11-09 Brad GriffisUse DAP_M3 to read Control registers
2015-11-06 Brad GriffisDecode the values for pullup/pulldown/keeper for each...
2015-11-06 Brad GriffisAdd warning if reg_phy_enable_dynamic_pwrdn is disabled
2015-11-06 Brad GriffisAdd print that tells name of file created
2015-11-06 Brad GriffisCheck PWR_MGMT_CTRL.reg_sr_tim for JEDEC compliance
2014-05-20 Brad GriffisAdd Modified BSD License to header of files.
2014-05-15 Brad Griffisinitial commit