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raw | patch | inline | side by side (parent: 1a74b71)
raw | patch | inline | side by side (parent: 1a74b71)
author | Brad Griffis <bgriffis@ti.com> | |
Fri, 3 May 2019 16:48:46 +0000 (11:48 -0500) | ||
committer | Brad Griffis <bgriffis@ti.com> | |
Fri, 3 May 2019 16:48:46 +0000 (11:48 -0500) |
am43xx-ddr-analysis.dss | patch | blob | history |
index 5b6893f6895991ce3c5f7e705338f36c61662b1c..f24cd8db269c31c980f7fc6f1e59914756e9fd94 100755 (executable)
--- a/am43xx-ddr-analysis.dss
+++ b/am43xx-ddr-analysis.dss
return return_string;
}
+// Inputs:
+// Data - 32-bit register value
+// Upper - Highest bit to keep
+// Lower - Lowest bit to keep
+// (bit 0 refers to LSB, bit 31 to MSB)
+// Return: right aligned data
+function bits32(data, upper, lower)
+{
+ data = data >>> lower; // unsigned right-shift
+ upper = upper - lower;
+ bitmask = 0xFFFFFFFF >>> (31 - upper);
+ return (data & bitmask);
+}
+
// Build a filename that includes date/time
var today = new Date();
var year4digit = today.getFullYear();
@@ -98,11 +112,96 @@ var original_CM_PER_EMIF_CLKSTCTRL = debugSessionDAP.memory.readWord(0,0x44DF8F0
file = new java.io.FileWriter(filename);
+var reg_val;
+var newline = "\n";
+
+// CONTROL: device_id
+reg_val = printRegisterValue(debugSessionDAP, "CONTROL: device_id", 0x44E10600);
+if ( bits32(reg_val, 27, 0) == 0xb98c02f ) {file.write(" * AM43xx family" + newline);}
+if ( bits32(reg_val, 31, 28) == 1 ) {
+ file.write(" * Silicon Revision 1.1" + newline);
+ PG = 1.1;
+}
+if ( bits32(reg_val, 31, 28) == 2 ) {
+ file.write(" * Silicon Revision 1.2" + newline);
+ PG = 1.2;
+}
+
+// CONTROL: control_status
+file.write(newline);
+reg_val = printRegisterValue(debugSessionDAP, "CONTROL: control_status", 0x44E10040);
+if ( PG == 1.2) {
+ if ( bits32(reg_val, 26, 26) == 1 ) {
+ if ( bits32(reg_val, 5, 5) == 1 ) {
+ file.write(" * Bits 26 (SYSBOOT18=1) and 5 (SYSBOOT5=1): Route 50MHz EXTCLK to CLKOUT2" + newline);
+ } else {
+ file.write(" * Bits 26 (SYSBOOT18=1) and 5 (SYSBOOT5=0): Route 25MHz EXTCLK to CLKOUT2" + newline);
+ }
+ } else {
+ file.write(" * Bit 26 (SYSBOOT18=0): Do not route EXTCLK to CLKOUT2" + newline);
+ }
+}
+SYSBOOT15_14 = bits32(reg_val, 23, 22);
+file.write(" * Bits 23:22 (SYSBOOT15:14=" + d2d(SYSBOOT15_14) + "): ");
+switch (SYSBOOT15_14) {
+ case 0:
+ file.write("19.2 MHz");
+ input_clock = 19.2;
+ break;
+ case 1:
+ file.write("24 MHz");
+ input_clock = 24;
+ break;
+ case 2:
+ file.write("25 MHz");
+ input_clock = 25;
+ break;
+ case 3:
+ file.write("26 MHz");
+ input_clock = 26;
+ break;
+}
+file.write(newline);
+
+// CM_CLKSEL_DPLL_DDR
+reg_val = printRegisterValue(debugSessionDAP, "CM_CLKSEL_DPLL_DDR", 0x44DF2DAC);
+dpll_mult = bits32(reg_val, 18, 8);
+file.write(" * DPLL_MULT = " + d2d(dpll_mult) + " (x" + d2d(dpll_mult) + ")" + newline);
+dpll_div = bits32(reg_val, 6, 0);
+file.write(" * DPLL_DIV = " + d2d(dpll_div) + " (/" + d2d(dpll_div+1) + ")" + newline);
+f_dpll_ddr = input_clock*2*dpll_mult/(dpll_div+1);
+
+// CM_DIV_M2_DPLL_DDR
+reg_val = printRegisterValue(debugSessionDAP, "CM_DIV_M2_DPLL_DDR", 0x44DF2DB0);
+if (reg_val & (1<<9)) // CLKST = 1
+ file.write(" * CLKST = 1: M2 output clock enabled" + newline);
+else
+ file.write(" * CLKST = 0: M2 output clock disabled" + newline);;
+div_m2 = reg_val & 0x1F;
+file.write(" * DIVHS = " + d2d(div_m2) + " (/" + d2d(div_m2) + ")" + newline);
+
+// CM_DIV_M4_DPLL_DDR
+reg_val = printRegisterValue(debugSessionDAP, "CM_DIV_M4_DPLL_DDR", 0x44DF2DB8);
+if (reg_val & (1<<9)) // CLKST = 1
+ file.write(" * CLKST = 1: M4 output clock enabled" + newline);
+else
+ file.write(" * CLKST = 0: M4 output clock disabled" + newline);;
+div_m4 = reg_val & 0x1F;
+file.write(" * DIVHS = " + d2d(div_m4) + " (/" + d2d(div_m4) + ")" + newline);
+
+file.write(newline + "DPLL_DDR Summary" + newline);
+file.write(" -> F_input = " + d2d(input_clock) + " MHz" + newline);
+ddr_pll_clkout_freq = f_dpll_ddr / 2 / div_m2;
+dll_clkout_freq = f_dpll_ddr / div_m4;
+file.write(" -> CLKOUT_M2 = DDR_PLL_CLKOUT = " + ddr_pll_clkout_freq + " MHz" + newline);
+file.write(" -> CLKOUT_M4 = DLL_CLKOUT = " + dll_clkout_freq + " MHz" + newline);
+if (ddr_pll_clkout_freq != dll_clkout_freq)
+ file.write(" -> ERROR! DLL_CLKOUT should be same speed as DDR_PLL_CLKOUT" + newline);
+file.write(newline);
+
// Only try to read EMIF registers if EMIF clock is enabled
if (original_CM_PER_EMIF_CLKSTCTRL & 0x7<<8) {
- var reg_val;
-
// EMIF: SDRAM_CONFIG
reg_val = printRegisterValue(debugSessionDAP, "EMIF: SDRAM_CONFIG", 0x4C000008);
if ( (reg_val & 0xE0000000) == (4 << 29) ) {is_lpddr2=1; file.write(" * SDRAM_TYPE = LPDDR2\n");}
if (is_ddr3 == 1) {
+ if (ddr_pll_clkout_freq > 400)
+ file.write(" -> ERROR! DDR speed exceeds the max of 400 MHz")
file.write(" * Bits 26:24 (reg_ddr_term) set for ");
if ( (reg_val & 0x07000000) == (0 << 24) ) {file.write("termination disabled (000b)\n");}
if ( (reg_val & 0x07000000) == (1 << 24) ) {file.write("RZQ/4 (001b)\n");}
}
if (is_lpddr2 == 1) {
+ if (ddr_pll_clkout_freq > 266)
+ file.write(" -> ERROR! DDR speed exceeds the max of 266 MHz")
if ( (reg_val & 0x00800000) == 0 )
file.write(" * LPDDR2_DDQS = 0, single ended DQS\n");
else