Add xml files needed by Python script
[sitara-dss-files/am57xx-dss-files.git] / padconf / CTRL_MODULE_CORE_am571x.xml
1 <module name="CTRL_MODULE_CORE" acronym="" XML_version="1.0" HW_revision="n/a" description="">
2   <register id="CTRL_CORE_MREQDOMAIN_EXP1" acronym="CTRL_CORE_MREQDOMAIN_EXP1" offset="0x108" width="32" description="MReqDomain value configuration register.">
3     <bitfield id="MREQDOMAIN_EXP1_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
4     <bitfield id="RESERVED" width="1" begin="30" end="30" resetval="0x0" description="" range="" rwaccess="R"/>
5     <bitfield id="MREQDOMAIN_IPU2" width="3" begin="29" end="27" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that: MreqDomain[2:0]= 0b000 = DOMAIN0 MreqDomain[2:0]= 0b001 = DOMAIN1 MreqDomain[2:0]= 0b010 = DOMAIN2 MreqDomain[2:0]= 0b011 = DOMAIN3 MreqDomain[2:0]= 0b100 = DOMAIN4 MreqDomain[2:0]= 0b110 = DOMAIN6 MreqDomain[2:0]= 0b111 = DOMAIN7" range="" rwaccess="RW"/>
6     <bitfield id="RESERVED" width="3" begin="26" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
7     <bitfield id="MREQDOMAIN_GPU_P0" width="3" begin="23" end="21" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
8     <bitfield id="MREQDOMAIN_IPU1" width="3" begin="20" end="18" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
9     <bitfield id="RESERVED" width="3" begin="17" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
10     <bitfield id="MREQDOMAIN_IVAHD" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
11     <bitfield id="MREQDOMAIN_DSS" width="3" begin="11" end="9" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
12     <bitfield id="MREQDOMAIN_DSP1_CFG" width="3" begin="8" end="6" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
13     <bitfield id="RESERVED" width="6" begin="5" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
14   </register>
15   <register id="CTRL_CORE_MREQDOMAIN_EXP2" acronym="CTRL_CORE_MREQDOMAIN_EXP2" offset="0x10C" width="32" description="MReqDomain value configuration register.">
16     <bitfield id="MREQDOMAIN_EXP2_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
17     <bitfield id="RESERVED" width="4" begin="30" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
18     <bitfield id="MREQDOMAIN_SATA" width="3" begin="26" end="24" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that: MreqDomain[2:0]= 0b000 = DOMAIN0 MreqDomain[2:0]= 0b001 = DOMAIN1 MreqDomain[2:0]= 0b010 = DOMAIN2 MreqDomain[2:0]= 0b011 = DOMAIN3 MreqDomain[2:0]= 0b100 = DOMAIN4 MreqDomain[2:0]= 0b110 = DOMAIN6 MreqDomain[2:0]= 0b111 = DOMAIN7" range="" rwaccess="RW"/>
19     <bitfield id="MREQDOMAIN_USB3" width="3" begin="23" end="21" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
20     <bitfield id="MREQDOMAIN_USB2" width="3" begin="20" end="18" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
21     <bitfield id="RESERVED" width="3" begin="17" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
22     <bitfield id="MREQDOMAIN_USB1" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
23     <bitfield id="RESERVED" width="6" begin="11" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
24     <bitfield id="MREQDOMAIN_MMC2" width="3" begin="5" end="3" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
25     <bitfield id="MREQDOMAIN_MMC1" width="3" begin="2" end="0" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
26   </register>
27   <register id="CTRL_CORE_MREQDOMAIN_EXP3" acronym="CTRL_CORE_MREQDOMAIN_EXP3" offset="0x110" width="32" description="MReqDomain value configuration register.">
28     <bitfield id="MREQDOMAIN_EXP3_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
29     <bitfield id="RESERVED" width="13" begin="30" end="18" resetval="0x0" description="" range="" rwaccess="R"/>
30     <bitfield id="MREQDOMAIN_VIP1_P0" width="3" begin="17" end="15" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that:" range="" rwaccess="RW"/>
31     <bitfield id="MREQDOMAIN_PRUSS2_PRU0" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_VIP1_P0 Description" range="" rwaccess="RW"/>
32     <bitfield id="MREQDOMAIN_PRUSS1_PRU0" width="3" begin="11" end="9" resetval="0x0" description="see MREQDOMAIN_VIP1_P0 Description" range="" rwaccess="RW"/>
33     <bitfield id="MREQDOMAIN_BB2D" width="3" begin="8" end="6" resetval="0x0" description="see MREQDOMAIN_VIP1_P0 Description" range="" rwaccess="RW"/>
34     <bitfield id="RESERVED" width="6" begin="5" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
35   </register>
36   <register id="CTRL_CORE_STATUS" acronym="CTRL_CORE_STATUS" offset="0x134" width="32" description="Control Module Status Register">
37     <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
38     <bitfield id="DEVICE_TYPE" width="3" begin="8" end="6" resetval="0x3" description="Device type captured at reset time. Read 0x3 = General Purpose (GP)" range="" rwaccess="R"/>
39     <bitfield id="RESERVED" width="6" begin="5" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
40   </register>
41   <register id="CTRL_CORE_SEC_ERR_STATUS_FUNC_1" acronym="CTRL_CORE_SEC_ERR_STATUS_FUNC_1" offset="0x148" width="32" description="Firewall Error Status functional Register 1">
42     <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
43     <bitfield id="BB2D_FW_ERROR" width="1" begin="23" end="23" resetval="0x0" description="BB2D firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
44     <bitfield id="L4_WAKEUP_FW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="L4 wakeup firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
45     <bitfield id="RESERVED" width="3" begin="21" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
46     <bitfield id="DEBUGSS_FW_ERROR" width="1" begin="18" end="18" resetval="0x0" description="DebugSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
47     <bitfield id="L4_CONFIG_FW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="L4 config firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
48     <bitfield id="L4_PERIPH1_FW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="L4 periph1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
49     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
50     <bitfield id="DSS_FW_ERROR" width="1" begin="14" end="14" resetval="0x0" description="DSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
51     <bitfield id="GPU_FW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="GPU firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
52     <bitfield id="RESERVED" width="6" begin="12" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
53     <bitfield id="IVAHD_SL2_FW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IVAHD SL2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
54     <bitfield id="IPU1_FW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="IPU1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
55     <bitfield id="IVAHD_FW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="IVAHD firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
56     <bitfield id="EMIF_FW_ERROR" width="1" begin="3" end="3" resetval="0x0" description="EMIF firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
57     <bitfield id="GPMC_FW_ERROR" width="1" begin="2" end="2" resetval="0x0" description="GPMC firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
58     <bitfield id="L3RAM1_FW_ERROR" width="1" begin="1" end="1" resetval="0x0" description="L3RAM1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
59     <bitfield id="RESERVED" width="1" begin="0" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
60   </register>
61   <register id="CTRL_CORE_SEC_ERR_STATUS_DEBUG_1" acronym="CTRL_CORE_SEC_ERR_STATUS_DEBUG_1" offset="0x150" width="32" description="Firewall Error Status Debug Register 1">
62     <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
63     <bitfield id="BB2D_DBGFW_ERROR" width="1" begin="23" end="23" resetval="0x0" description="BB2D firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
64     <bitfield id="L4_WAKEUP_DBGFW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="L4 wakeup firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
65     <bitfield id="RESERVED" width="3" begin="21" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
66     <bitfield id="DEBUGSS_DBGFW_ERROR" width="1" begin="18" end="18" resetval="0x0" description="DebugSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
67     <bitfield id="L4_CONFIG_DBGFW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="L4 config firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
68     <bitfield id="L4_PERIPH1_DBGFW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="L4 periph1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
69     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
70     <bitfield id="DSS_DBGFW_ERROR" width="1" begin="14" end="14" resetval="0x0" description="DSS debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
71     <bitfield id="GPU_DBGFW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="GPU debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
72     <bitfield id="RESERVED" width="6" begin="12" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
73     <bitfield id="IVAHD_SL2_DBGFW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IVAHD SL2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
74     <bitfield id="IPU1_DBGFW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="IPU1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
75     <bitfield id="IVAHD_DBGFW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="IVAHD debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
76     <bitfield id="EMIF_DBGFW_ERROR" width="1" begin="3" end="3" resetval="0x0" description="EMIF debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
77     <bitfield id="GPMC_DBGFW_ERROR" width="1" begin="2" end="2" resetval="0x0" description="GPMC debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
78     <bitfield id="L3RAM1_DBGFW_ERROR" width="1" begin="1" end="1" resetval="0x0" description="L3RAM1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
79     <bitfield id="RESERVED" width="1" begin="0" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
80   </register>
81   <register id="CTRL_CORE_MPU_FORCEWRNP" acronym="CTRL_CORE_MPU_FORCEWRNP" offset="0x15C" width="32" description="FORCE WRITE NON POSTED">
82     <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
83     <bitfield id="MPU_FORCEWRNP" width="1" begin="0" end="0" resetval="0x0" description="Force mpu write non posted transactions 0x0 = disable force wrnp 0x1 = force wrnp" range="" rwaccess="RW"/>
84   </register>
85   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0" offset="0x194" width="32" description="Standard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
86     <bitfield id="STD_FUSE_OPP_VDD_GPU_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
87   </register>
88   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1" offset="0x198" width="32" description="Standard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
89     <bitfield id="STD_FUSE_OPP_VDD_GPU_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
90   </register>
91   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2" offset="0x19C" width="32" description="Standard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
92     <bitfield id="STD_FUSE_OPP_VDD_GPU_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
93   </register>
94   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3" offset="0x1A0" width="32" description="Standard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
95     <bitfield id="STD_FUSE_OPP_VDD_GPU_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
96   </register>
97   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4" offset="0x1A4" width="32" description="Standard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
98     <bitfield id="STD_FUSE_OPP_VDD_GPU_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
99   </register>
100   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5" offset="0x1A8" width="32" description="Standard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
101     <bitfield id="STD_FUSE_OPP_VDD_GPU_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
102   </register>
103   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0" offset="0x1AC" width="32" description="Standard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
104     <bitfield id="STD_FUSE_OPP_VDD_MPU_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
105   </register>
106   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1" offset="0x1B0" width="32" description="Standard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
107     <bitfield id="STD_FUSE_OPP_VDD_MPU_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
108   </register>
109   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2" offset="0x1B4" width="32" description="Standard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
110     <bitfield id="STD_FUSE_OPP_VDD_MPU_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
111   </register>
112   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3" offset="0x1B8" width="32" description="Standard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
113     <bitfield id="STD_FUSE_OPP_VDD_MPU_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
114   </register>
115   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4" offset="0x1BC" width="32" description="Standard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
116     <bitfield id="STD_FUSE_OPP_VDD_MPU_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
117   </register>
118   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5" offset="0x1C0" width="32" description="Standard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
119     <bitfield id="STD_FUSE_OPP_VDD_MPU_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
120   </register>
121   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6" offset="0x1C4" width="32" description="Standard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
122     <bitfield id="STD_FUSE_OPP_VDD_MPU_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
123   </register>
124   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7" offset="0x1C8" width="32" description="Standard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
125     <bitfield id="STD_FUSE_OPP_VDD_MPU_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
126   </register>
127   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0" offset="0x1CC" width="32" description="Standard Fuse OPP VDD_CORE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
128     <bitfield id="STD_FUSE_OPP_VDD_CORE_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
129   </register>
130   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1" offset="0x1D0" width="32" description="Standard Fuse OPP VDD_CORE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
131     <bitfield id="STD_FUSE_OPP_VDD_CORE_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
132   </register>
133   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2" offset="0x1D4" width="32" description="Standard Fuse OPP VDD_CORE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
134     <bitfield id="STD_FUSE_OPP_VDD_CORE_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
135   </register>
136   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3" offset="0x1D8" width="32" description="Standard Fuse OPP VDD_CORE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
137     <bitfield id="STD_FUSE_OPP_VDD_CORE_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
138   </register>
139   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4" offset="0x1DC" width="32" description="Standard Fuse OPP VDD_CORE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
140     <bitfield id="STD_FUSE_OPP_VDD_CORE_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
141   </register>
142   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_GPU" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_GPU" offset="0x1E0" width="32" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">
143     <bitfield id="STD_FUSE_OPP_BGAP_GPU_0" width="8" begin="31" end="24" resetval="0x-" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
144     <bitfield id="STD_FUSE_OPP_BGAP_GPU_1" width="8" begin="23" end="16" resetval="0x-" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
145     <bitfield id="STD_FUSE_OPP_BGAP_GPU_2" width="8" begin="15" end="8" resetval="0x-" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
146     <bitfield id="STD_FUSE_OPP_BGAP_GPU_3" width="8" begin="7" end="0" resetval="0x-" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
147   </register>
148   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU" offset="0x1E4" width="32" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">
149     <bitfield id="STD_FUSE_OPP_BGAP_MPU_0" width="8" begin="31" end="24" resetval="0x-" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
150     <bitfield id="STD_FUSE_OPP_BGAP_MPU_1" width="8" begin="23" end="16" resetval="0x-" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
151     <bitfield id="STD_FUSE_OPP_BGAP_MPU_2" width="8" begin="15" end="8" resetval="0x-" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
152     <bitfield id="STD_FUSE_OPP_BGAP_MPU_3" width="8" begin="7" end="0" resetval="0x-" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
153   </register>
154   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_CORE" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_CORE" offset="0x1E8" width="32" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">
155     <bitfield id="STD_FUSE_OPP_BGAP_CORE_0" width="8" begin="31" end="24" resetval="0x-" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
156     <bitfield id="STD_FUSE_OPP_BGAP_CORE_1" width="8" begin="23" end="16" resetval="0x-" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
157     <bitfield id="STD_FUSE_OPP_BGAP_CORE_2" width="8" begin="15" end="8" resetval="0x-" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
158     <bitfield id="STD_FUSE_OPP_BGAP_CORE_3" width="8" begin="7" end="0" resetval="0x-" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
159   </register>
160   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23" offset="0x1EC" width="32" description="Standard Fuse OPP BGAP. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
161     <bitfield id="STD_FUSE_OPP_BGAP_MPU3" width="16" begin="31" end="16" resetval="0x0" description="" range="" rwaccess="R"/>
162     <bitfield id="STD_FUSE_OPP_BGAP_MPU2" width="16" begin="15" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
163   </register>
164   <register id="CTRL_CORE_STD_FUSE_MPK_0" acronym="CTRL_CORE_STD_FUSE_MPK_0" offset="0x220" width="32" description="Standard Fuse keys. Root_public_key_hash [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
165     <bitfield id="STD_FUSE_MPK_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
166   </register>
167   <register id="CTRL_CORE_STD_FUSE_MPK_1" acronym="CTRL_CORE_STD_FUSE_MPK_1" offset="0x224" width="32" description="Standard Fuse keys. Root_public_key_hash [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
168     <bitfield id="STD_FUSE_MPK_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
169   </register>
170   <register id="CTRL_CORE_STD_FUSE_MPK_2" acronym="CTRL_CORE_STD_FUSE_MPK_2" offset="0x228" width="32" description="Standard Fuse keys. Root_public_key_hash [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
171     <bitfield id="STD_FUSE_MPK_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
172   </register>
173   <register id="CTRL_CORE_STD_FUSE_MPK_3" acronym="CTRL_CORE_STD_FUSE_MPK_3" offset="0x22C" width="32" description="Standard Fuse keys. Root_public_key_hash [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
174     <bitfield id="STD_FUSE_MPK_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
175   </register>
176   <register id="CTRL_CORE_STD_FUSE_MPK_4" acronym="CTRL_CORE_STD_FUSE_MPK_4" offset="0x230" width="32" description="Standard Fuse keys. Root_public_key_hash [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
177     <bitfield id="STD_FUSE_MPK_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
178   </register>
179   <register id="CTRL_CORE_STD_FUSE_MPK_5" acronym="CTRL_CORE_STD_FUSE_MPK_5" offset="0x234" width="32" description="Standard Fuse keys. Root_public_key_hash [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
180     <bitfield id="STD_FUSE_MPK_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
181   </register>
182   <register id="CTRL_CORE_STD_FUSE_MPK_6" acronym="CTRL_CORE_STD_FUSE_MPK_6" offset="0x238" width="32" description="Standard Fuse keys. Root_public_key_hash [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
183     <bitfield id="STD_FUSE_MPK_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
184   </register>
185   <register id="CTRL_CORE_STD_FUSE_MPK_7" acronym="CTRL_CORE_STD_FUSE_MPK_7" offset="0x23C" width="32" description="Standard Fuse keys. Root_public_key_hash [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
186     <bitfield id="STD_FUSE_MPK_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
187   </register>
188   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0" offset="0x240" width="32" description="Standard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
189     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
190   </register>
191   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1" offset="0x244" width="32" description="Standard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
192     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
193   </register>
194   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2" offset="0x248" width="32" description="Standard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
195     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
196   </register>
197   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3" offset="0x24C" width="32" description="Standard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
198     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
199   </register>
200   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4" offset="0x250" width="32" description="Standard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
201     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
202   </register>
203   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5" offset="0x254" width="32" description="Standard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
204     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
205   </register>
206   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0" offset="0x258" width="32" description="Standard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
207     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
208   </register>
209   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1" offset="0x25C" width="32" description="Standard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
210     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
211   </register>
212   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2" offset="0x260" width="32" description="Standard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
213     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
214   </register>
215   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3" offset="0x264" width="32" description="Standard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
216     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
217   </register>
218   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4" offset="0x268" width="32" description="Standard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
219     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
220   </register>
221   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5" offset="0x26C" width="32" description="Standard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
222     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
223   </register>
224   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6" offset="0x270" width="32" description="Standard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
225     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
226   </register>
227   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7" offset="0x274" width="32" description="Standard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
228     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
229   </register>
230   <register id="CTRL_CORE_CUST_FUSE_SWRV_0" acronym="CTRL_CORE_CUST_FUSE_SWRV_0" offset="0x2BC" width="32" description="Customer Fuse keys. Software Version Control [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
231     <bitfield id="CUST_FUSE_SWRV_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
232   </register>
233   <register id="CTRL_CORE_CUST_FUSE_SWRV_1" acronym="CTRL_CORE_CUST_FUSE_SWRV_1" offset="0x2C0" width="32" description="Customer Fuse keys. Software Version Control [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
234     <bitfield id="CUST_FUSE_SWRV_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
235   </register>
236   <register id="CTRL_CORE_CUST_FUSE_SWRV_2" acronym="CTRL_CORE_CUST_FUSE_SWRV_2" offset="0x2C4" width="32" description="Customer Fuse keys. Software Version Control [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
237     <bitfield id="CUST_FUSE_SWRV_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
238   </register>
239   <register id="CTRL_CORE_CUST_FUSE_SWRV_3" acronym="CTRL_CORE_CUST_FUSE_SWRV_3" offset="0x2C8" width="32" description="Customer Fuse keys. Software Version Control [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
240     <bitfield id="CUST_FUSE_SWRV_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
241   </register>
242   <register id="CTRL_CORE_CUST_FUSE_SWRV_4" acronym="CTRL_CORE_CUST_FUSE_SWRV_4" offset="0x2CC" width="32" description="Customer Fuse keys. Software Version Control [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
243     <bitfield id="CUST_FUSE_SWRV_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
244   </register>
245   <register id="CTRL_CORE_CUST_FUSE_SWRV_5" acronym="CTRL_CORE_CUST_FUSE_SWRV_5" offset="0x2D0" width="32" description="Customer Fuse keys. Software Version Control [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
246     <bitfield id="CUST_FUSE_SWRV_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
247   </register>
248   <register id="CTRL_CORE_CUST_FUSE_SWRV_6" acronym="CTRL_CORE_CUST_FUSE_SWRV_6" offset="0x2D4" width="32" description="Customer Fuse keys. Software Version Control [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
249     <bitfield id="CUST_FUSE_SWRV_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
250   </register>
251   <register id="CTRL_CORE_DEV_CONF" acronym="CTRL_CORE_DEV_CONF" offset="0x300" width="32" description="This register is used to power down the USB2_PHY1">
252     <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
253     <bitfield id="USBPHY_PD" width="1" begin="0" end="0" resetval="0x0" description="Power down the entire USB2_PHY1 (data, common module and UTMI). 0x0: Normal operation 0x1: Power down the USB2_PHY1" range="" rwaccess="RW"/>
254   </register>
255   <register id="CTRL_CORE_TEMP_SENSOR_MPU" acronym="CTRL_CORE_TEMP_SENSOR_MPU" offset="0x32C" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
256     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
257     <bitfield id="BGAP_TMPSOFF_MPU" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
258     <bitfield id="BGAP_EOCZ_MPU" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_MPU is valid." range="" rwaccess="R"/>
259     <bitfield id="BGAP_DTEMP_MPU" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
260   </register>
261   <register id="CTRL_CORE_TEMP_SENSOR_GPU" acronym="CTRL_CORE_TEMP_SENSOR_GPU" offset="0x330" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
262     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
263     <bitfield id="BGAP_TMPSOFF_GPU" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
264     <bitfield id="BGAP_EOCZ_GPU" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_GPU is valid." range="" rwaccess="R"/>
265     <bitfield id="BGAP_DTEMP_GPU" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
266   </register>
267   <register id="CTRL_CORE_TEMP_SENSOR_CORE" acronym="CTRL_CORE_TEMP_SENSOR_CORE" offset="0x334" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
268     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
269     <bitfield id="BGAP_TMPSOFF_CORE" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
270     <bitfield id="BGAP_EOCZ_CORE" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_CORE is valid." range="" rwaccess="R"/>
271     <bitfield id="BGAP_DTEMP_CORE" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
272   </register>
273   <register id="CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR" acronym="CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR" offset="0x358" width="32" description="Cortex M4 register">
274     <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
275     <bitfield id="CORTEX_M4_MMUADDRTRANSLTR" width="20" begin="19" end="0" resetval="0x0" description="Used to save the IPU AMMU translated/boot address" range="" rwaccess="RW"/>
276   </register>
277   <register id="CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR" acronym="CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR" offset="0x35C" width="32" description="">
278     <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
279     <bitfield id="CORTEX_M4_MMUADDRLOGICTR" width="20" begin="19" end="0" resetval="0x0" description="Used to save the IPU AMMU logical source address" range="" rwaccess="RW"/>
280   </register>
281   <register id="CTRL_CORE_HWOBS_CONTROL" acronym="CTRL_CORE_HWOBS_CONTROL" offset="0x360" width="32" description="HW observability control. This register enables or disables HW observability outputs (to save power primarily)">
282     <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
283     <bitfield id="HWOBS_CLKDIV_SEL_2" width="5" begin="18" end="14" resetval="0x0" description="Clock divider selection on po_hwobs(2). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" range="" rwaccess="RW"/>
284     <bitfield id="HWOBS_CLKDIV_SEL_1" width="5" begin="13" end="9" resetval="0x0" description="Clock divider selection on po_hwobs(1). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" range="" rwaccess="RW"/>
285     <bitfield id="RESERVED" width="1" begin="8" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
286     <bitfield id="HWOBS_CLKDIV_SEL" width="5" begin="7" end="3" resetval="0x0" description="Clock divider selection on po_hwobs(0). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" range="" rwaccess="RW"/>
287     <bitfield id="HWOBS_ALL_ZERO_MODE" width="1" begin="2" end="2" resetval="0x0" description="Used to gate observable signals. When set all outputs are set to zero (can be used to check the path from HW observability to external pads). 0x0 = hw observability ports are not gated 0x1 = hw observability ports are all set to 0" range="" rwaccess="RW"/>
288     <bitfield id="HWOBS_ALL_ONE_MODE" width="1" begin="1" end="1" resetval="0x0" description="Used to gate observable signals. When set all outputs are set to one (can be used to check the path from HW observability to external pads). 0x0 = hw observability ports are not gated 0x1 = hw observability ports are all set to 1" range="" rwaccess="RW"/>
289     <bitfield id="HWOBS_MACRO_ENABLE" width="1" begin="0" end="0" resetval="0x0" description="Used to gate observable signals coming from macros using the 32:bit HWOBS bus definition. When deasserted all outputs of the HWOBS busdef are set to zero. 0x0 = hw observability ports from macros are gated and set to zero 0x1 = hw observability ports from macros are not gated" range="" rwaccess="RW"/>
290   </register>
291   <register id="CTRL_CORE_PHY_POWER_USB" acronym="CTRL_CORE_PHY_POWER_USB" offset="0x370" width="32" description="phy_power_usb">
292     <bitfield id="USB_PWRCTL_CLK_FREQ" width="10" begin="31" end="22" resetval="0x0" description="Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." range="" rwaccess="RW"/>
293     <bitfield id="USB_PWRCTL_CLK_CMD" width="8" begin="21" end="14" resetval="0x0" description="Powers up/down the USB3_PHY_TX and USB3_PHY_RX modules. This bit field is also used for partially power down these TX and RX modules. Each bit has the following meaning: Bit[14] - 0x1: Powers-up the USB3_PHY_RX Bit[15] - 0x1: Powers-up the USB3_PHY_TX Bit[16] - A don&#8217;t care bit. Not used. Bit[17] - A don&#8217;t care bit. Not used. Bit[18] - 0x1: Disables the synchronized power-up of USB3_PHY_TX with USB3_PHY_RX. The TX power-up is independent of the RX power-up. Bit[19] - 0x1: Disables the automatic power-cycling of USB3_PHY_RX in P3 power state when PLL_CLK stops and starts. Bit[20] - 0x1: Partially powers-down the USB3_PHY_RX when it is in P3 power state. DCC, Phase interpolator, Equalizer are disabled. Bit[21] - A don&#8217;t care bit. Not used." range="" rwaccess="RW"/>
294     <bitfield id="RESERVED" width="14" begin="13" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
295   </register>
296   <register id="CTRL_CORE_PHY_POWER_SATA" acronym="CTRL_CORE_PHY_POWER_SATA" offset="0x374" width="32" description="phy_power_sata">
297     <bitfield id="SATA_PWRCTL_CLK_FREQ" width="10" begin="31" end="22" resetval="0x0" description="Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." range="" rwaccess="RW"/>
298     <bitfield id="SATA_PWRCTL_CLK_CMD" width="8" begin="21" end="14" resetval="0x0" description="Powers up/down the SATA_PHY_TX and SATA_PHY_RX modules. 0x0: Powers down SATA_PHY_TX and SATA_PHY_RX 0x1: Powers up SATA_PHY_RX 0x2: Powers up SATA_PHY_TX 0x3: Powers up SATA_PHY_TX and SATA_PHY_RX 0x4-0xFF: Reserved" range="" rwaccess="RW"/>
299     <bitfield id="RESERVED" width="14" begin="13" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
300   </register>
301   <register id="CTRL_CORE_BANDGAP_MASK_1" acronym="CTRL_CORE_BANDGAP_MASK_1" offset="0x380" width="32" description="bgap_mask">
302     <bitfield id="SIDLEMODE" width="2" begin="31" end="30" resetval="0x0" description="sidlemode for bandgap 0x0 = No Idle 0x1 = Force Idle 0x2 = Smart Idle 0x3 = Reserved" range="" rwaccess="RW"/>
303     <bitfield id="COUNTER_DELAY" width="3" begin="29" end="27" resetval="0x0" description="Counter delay 0x0 = Imediat 0x1 = Delay of 1ms 0x2 = Delay of 10ms 0x3 = Delay of 100ms 0x4 = Delay of 250ms 0x5 = Delay of 500ms" range="" rwaccess="RW"/>
304     <bitfield id="RESERVED" width="3" begin="26" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
305     <bitfield id="FREEZE_CORE" width="1" begin="23" end="23" resetval="0x0" description="Freeze the FIFO CORE 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
306     <bitfield id="FREEZE_GPU" width="1" begin="22" end="22" resetval="0x0" description="Freeze the FIFO GPU 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
307     <bitfield id="FREEZE_MPU" width="1" begin="21" end="21" resetval="0x0" description="Freeze the FIFO MPU 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
308     <bitfield id="CLEAR_CORE" width="1" begin="20" end="20" resetval="0x0" description="Reset the FIFO CORE 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
309     <bitfield id="CLEAR_GPU" width="1" begin="19" end="19" resetval="0x0" description="Reset the FIFO GPU 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
310     <bitfield id="CLEAR_MPU" width="1" begin="18" end="18" resetval="0x0" description="Reset the FIFO MPU 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
311     <bitfield id="RESERVED" width="12" begin="17" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
312     <bitfield id="MASK_HOT_CORE" width="1" begin="5" end="5" resetval="0x0" description="Mask for hot event CORE 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
313     <bitfield id="MASK_COLD_CORE" width="1" begin="4" end="4" resetval="0x0" description="Mask for cold event CORE 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
314     <bitfield id="MASK_HOT_GPU" width="1" begin="3" end="3" resetval="0x0" description="Mask for hot event GPU 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
315     <bitfield id="MASK_COLD_GPU" width="1" begin="2" end="2" resetval="0x0" description="Mask for cold event GPU 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
316     <bitfield id="MASK_HOT_MPU" width="1" begin="1" end="1" resetval="0x0" description="Mask for hot event MPU 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
317     <bitfield id="MASK_COLD_MPU" width="1" begin="0" end="0" resetval="0x0" description="Mask for cold event MPU 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
318   </register>
319   <register id="CTRL_CORE_BANDGAP_THRESHOLD_MPU" acronym="CTRL_CORE_BANDGAP_THRESHOLD_MPU" offset="0x384" width="32" description="BGAP THRESHOLD MPU">
320     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
321     <bitfield id="THOLD_HOT_MPU" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
322     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
323     <bitfield id="THOLD_COLD_MPU" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
324   </register>
325   <register id="CTRL_CORE_BANDGAP_THRESHOLD_GPU" acronym="CTRL_CORE_BANDGAP_THRESHOLD_GPU" offset="0x388" width="32" description="BGAP THRESHOLD MM">
326     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
327     <bitfield id="THOLD_HOT_GPU" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
328     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
329     <bitfield id="THOLD_COLD_GPU" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
330   </register>
331   <register id="CTRL_CORE_BANDGAP_THRESHOLD_CORE" acronym="CTRL_CORE_BANDGAP_THRESHOLD_CORE" offset="0x38C" width="32" description="BGAP THRESHOLD CORE">
332     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
333     <bitfield id="THOLD_HOT_CORE" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
334     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
335     <bitfield id="THOLD_COLD_CORE" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
336   </register>
337   <register id="CTRL_CORE_BANDGAP_TSHUT_MPU" acronym="CTRL_CORE_BANDGAP_TSHUT_MPU" offset="0x390" width="32" description="BGAP TSHUT THRESHOLD MPU">
338     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
339     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
340     <bitfield id="TSHUT_HOT_MPU" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
341     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
342     <bitfield id="TSHUT_COLD_MPU" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
343   </register>
344   <register id="CTRL_CORE_BANDGAP_TSHUT_GPU" acronym="CTRL_CORE_BANDGAP_TSHUT_GPU" offset="0x394" width="32" description="BGAP TSHUT THRESHOLD GPU">
345     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
346     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
347     <bitfield id="TSHUT_HOT_GPU" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
348     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
349     <bitfield id="TSHUT_COLD_GPU" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
350   </register>
351   <register id="CTRL_CORE_BANDGAP_TSHUT_CORE" acronym="CTRL_CORE_BANDGAP_TSHUT_CORE" offset="0x398" width="32" description="BGAP TSHUT THRESHOLD CORE">
352     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
353     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
354     <bitfield id="TSHUT_HOT_CORE" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
355     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
356     <bitfield id="TSHUT_COLD_CORE" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
357   </register>
358   <register id="CTRL_CORE_BANDGAP_STATUS_1" acronym="CTRL_CORE_BANDGAP_STATUS_1" offset="0x3A8" width="32" description="BGAP STATUS">
359     <bitfield id="ALERT" width="1" begin="31" end="31" resetval="0x0" description="Alert temperature when '1'" range="" rwaccess="R"/>
360     <bitfield id="RESERVED" width="25" begin="30" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
361     <bitfield id="HOT_CORE" width="1" begin="5" end="5" resetval="0x0" description="Event for hot temperature mpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
362     <bitfield id="COLD_CORE" width="1" begin="4" end="4" resetval="0x0" description="Event for cold temperature mpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
363     <bitfield id="HOT_GPU" width="1" begin="3" end="3" resetval="0x0" description="Event for hot temperature gpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
364     <bitfield id="COLD_GPU" width="1" begin="2" end="2" resetval="0x0" description="Event for cold temperature gpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
365     <bitfield id="HOT_MPU" width="1" begin="1" end="1" resetval="0x0" description="Event for hot temperature core bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
366     <bitfield id="COLD_MPU" width="1" begin="0" end="0" resetval="0x0" description="Event for cold temperature core bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
367   </register>
368   <register id="CTRL_CORE_SATA_EXT_MODE" acronym="CTRL_CORE_SATA_EXT_MODE" offset="0x3AC" width="32" description="SATA EXTENDED MODE">
369     <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
370     <bitfield id="SATA_EXTENDED_MODE" width="1" begin="0" end="0" resetval="0x0" description="sata extended mode 0x0 = no extended mode 0x1 = extended mode" range="" rwaccess="RW"/>
371   </register>
372   <register id="CTRL_CORE_DTEMP_MPU_0" acronym="CTRL_CORE_DTEMP_MPU_0" offset="0x3C0" width="32" description="TAGGED TEMPERATURE MPU DOMAIN. Most recent sample">
373     <bitfield id="DTEMP_TAG_MPU_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
374     <bitfield id="DTEMP_TEMPERATURE_MPU_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
375   </register>
376   <register id="CTRL_CORE_DTEMP_MPU_1" acronym="CTRL_CORE_DTEMP_MPU_1" offset="0x3C4" width="32" description="TAGGED TEMPERATURE MPU DOMAIN">
377     <bitfield id="DTEMP_TAG_MPU_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
378     <bitfield id="DTEMP_TEMPERATURE_MPU_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
379   </register>
380   <register id="CTRL_CORE_DTEMP_MPU_2" acronym="CTRL_CORE_DTEMP_MPU_2" offset="0x3C8" width="32" description="TAGGED TEMPERATURE MPU DOMAIN">
381     <bitfield id="DTEMP_TAG_MPU_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
382     <bitfield id="DTEMP_TEMPERATURE_MPU_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
383   </register>
384   <register id="CTRL_CORE_DTEMP_MPU_3" acronym="CTRL_CORE_DTEMP_MPU_3" offset="0x3CC" width="32" description="TAGGED TEMPERATURE MPU DOMAIN">
385     <bitfield id="DTEMP_TAG_MPU_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
386     <bitfield id="DTEMP_TEMPERATURE_MPU_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
387   </register>
388   <register id="CTRL_CORE_DTEMP_MPU_4" acronym="CTRL_CORE_DTEMP_MPU_4" offset="0x3D0" width="32" description="TAGGED TEMPERATURE MPU DOMAIN. Oldest sample">
389     <bitfield id="DTEMP_TAG_MPU_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
390     <bitfield id="DTEMP_TEMPERATURE_MPU_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
391   </register>
392   <register id="CTRL_CORE_DTEMP_GPU_0" acronym="CTRL_CORE_DTEMP_GPU_0" offset="0x3D4" width="32" description="TAGGED TEMPERATURE GPU DOMAIN. Most recent sample.">
393     <bitfield id="DTEMP_TAG_GPU_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
394     <bitfield id="DTEMP_TEMPERATURE_GPU_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
395   </register>
396   <register id="CTRL_CORE_DTEMP_GPU_1" acronym="CTRL_CORE_DTEMP_GPU_1" offset="0x3D8" width="32" description="TAGGED TEMPERATURE GPU DOMAIN.">
397     <bitfield id="DTEMP_TAG_GPU_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
398     <bitfield id="DTEMP_TEMPERATURE_GPU_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
399   </register>
400   <register id="CTRL_CORE_DTEMP_GPU_2" acronym="CTRL_CORE_DTEMP_GPU_2" offset="0x3DC" width="32" description="TAGGED TEMPERATURE GPU DOMAIN.">
401     <bitfield id="DTEMP_TAG_GPU_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
402     <bitfield id="DTEMP_TEMPERATURE_GPU_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
403   </register>
404   <register id="CTRL_CORE_DTEMP_GPU_3" acronym="CTRL_CORE_DTEMP_GPU_3" offset="0x3E0" width="32" description="TAGGED TEMPERATURE GPU DOMAIN.">
405     <bitfield id="DTEMP_TAG_GPU_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
406     <bitfield id="DTEMP_TEMPERATURE_GPU_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
407   </register>
408   <register id="CTRL_CORE_DTEMP_GPU_4" acronym="CTRL_CORE_DTEMP_GPU_4" offset="0x3E4" width="32" description="TAGGED TEMPERATURE GPU DOMAIN. Oldest sample.">
409     <bitfield id="DTEMP_TAG_GPU_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
410     <bitfield id="DTEMP_TEMPERATURE_GPU_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
411   </register>
412   <register id="CTRL_CORE_DTEMP_CORE_0" acronym="CTRL_CORE_DTEMP_CORE_0" offset="0x3E8" width="32" description="TAGGED TEMPERATURE CORE DOMAIN. Most recent sample.">
413     <bitfield id="DTEMP_TAG_CORE_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
414     <bitfield id="DTEMP_TEMPERATURE_CORE_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
415   </register>
416   <register id="CTRL_CORE_DTEMP_CORE_1" acronym="CTRL_CORE_DTEMP_CORE_1" offset="0x3EC" width="32" description="TAGGED TEMPERATURE CORE DOMAIN">
417     <bitfield id="DTEMP_TAG_CORE_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
418     <bitfield id="DTEMP_TEMPERATURE_CORE_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
419   </register>
420   <register id="CTRL_CORE_DTEMP_CORE_2" acronym="CTRL_CORE_DTEMP_CORE_2" offset="0x3F0" width="32" description="TAGGED TEMPERATURE CORE DOMAIN">
421     <bitfield id="DTEMP_TAG_CORE_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
422     <bitfield id="DTEMP_TEMPERATURE_CORE_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
423   </register>
424   <register id="CTRL_CORE_DTEMP_CORE_3" acronym="CTRL_CORE_DTEMP_CORE_3" offset="0x3F4" width="32" description="TAGGED TEMPERATURE CORE DOMAIN">
425     <bitfield id="DTEMP_TAG_CORE_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
426     <bitfield id="DTEMP_TEMPERATURE_CORE_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
427   </register>
428   <register id="CTRL_CORE_DTEMP_CORE_4" acronym="CTRL_CORE_DTEMP_CORE_4" offset="0x3F8" width="32" description="TAGGED TEMPERATURE CORE DOMAIN. Oldest sample.">
429     <bitfield id="DTEMP_TAG_CORE_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
430     <bitfield id="DTEMP_TEMPERATURE_CORE_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
431   </register>
432   <register id="CTRL_CORE_SMA_SW_0" acronym="CTRL_CORE_SMA_SW_0" offset="0x3FC" width="32" description="OCP Spare Register">
433     <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
434     <bitfield id="SATA_PLL_SOFT_RESET" width="1" begin="18" end="18" resetval="0x0" description="Software reset control for SATA PLL. When this bit is set the SATA PLL goes into reset." range="" rwaccess="RW">
435       <bitenum value="0" id="RST_NOT_ACTIVE" token="SATA_PLL_SOFT_RESET_0" description="Reset is not active for SATA controller"/>
436       <bitenum value="1" id="RST_ACTIVE" token="SATA_PLL_SOFT_RESET_1" description="Reset is active for SATA controller"/>
437     </bitfield>
438     <bitfield id="RESERVED" width="13" begin="17" end="5" resetval="0x0" description="" range="" rwaccess="R"/>
439     <bitfield id="HWOBS_DCC_SDL2_SIG_OUT" width="1" begin="4" end="4" resetval="0x0" description="HWOBS select for DCC SDL2 output. 0x0: SDL2 clock output would not be sent to HWOBS pin. 0x1: SDL2 clock output would be sent to the DMM reset HWOBS pin." range="" rwaccess="RW"/>
440     <bitfield id="I2C1_CLK_EN" width="1" begin="3" end="3" resetval="0x0" description="Enable I2C1 clock. 0x0: I2C1 clock depends on PRCM operation. 0x1: Enable I2C1 clock irrespective of I2C1 operation state." range="" rwaccess="RW"/>
441     <bitfield id="ISO_CTRL_IO" width="1" begin="2" end="2" resetval="0x0" description="ISO control for the IO pads." range="" rwaccess="RW">
442       <bitenum value="0" id="ISO_ENBL_NOT_SET" token="ISO_CTRL_IO_0" description="ISO enable for pads is not set"/>
443       <bitenum value="1" id="ISO_ENBL_SET" token="ISO_CTRL_IO_1" description="ISO enable for pads is set"/>
444     </bitfield>
445     <bitfield id="RESERVED" width="1" begin="1" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
446     <bitfield id="CKE_GATING_CTRL" width="1" begin="0" end="0" resetval="0x0" description="Forces the EMIF1 CKE pad to tri-state." range="" rwaccess="RW">
447       <bitenum value="0" id="CKE_NOT_IN_TRI_STATE" token="CKE_GATING_CTRL_0" description="The CKE pad is not in tri-state and can be controlled by EMIF1"/>
448       <bitenum value="1" id="CKE_IN_TRI_STATE" token="CKE_GATING_CTRL_1" description="The CKE pad is in tri-state"/>
449     </bitfield>
450   </register>
451   <register id="CTRL_CORE_MREQDOMAIN_EXP4" acronym="CTRL_CORE_MREQDOMAIN_EXP4" offset="0x400" width="32" description="MReqDomain value configuration register.">
452     <bitfield id="MREQDOMAIN_EXP4_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
453     <bitfield id="RESERVED" width="4" begin="30" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
454     <bitfield id="MREQDOMAIN_DSP1_MDMA" width="3" begin="26" end="24" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that:" range="" rwaccess="RW"/>
455     <bitfield id="MREQDOMAIN_VPE_P0" width="3" begin="23" end="21" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
456     <bitfield id="MREQDOMAIN_GMACSW" width="3" begin="20" end="18" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
457     <bitfield id="MREQDOMAIN_MMU2" width="3" begin="17" end="15" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
458     <bitfield id="MREQDOMAIN_MMU1" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
459     <bitfield id="MREQDOMAIN_PCIESS2" width="3" begin="11" end="9" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
460     <bitfield id="MREQDOMAIN_PCIESS1" width="3" begin="8" end="6" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
461     <bitfield id="RESERVED" width="3" begin="5" end="3" resetval="0x0" description="" range="" rwaccess="R"/>
462     <bitfield id="MREQDOMAIN_MLB" width="3" begin="2" end="0" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
463   </register>
464   <register id="CTRL_CORE_MREQDOMAIN_EXP5" acronym="CTRL_CORE_MREQDOMAIN_EXP5" offset="0x404" width="32" description="MReqDomain value configuration register.">
465     <bitfield id="MREQDOMAIN_EXP5_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
466     <bitfield id="RESERVED" width="10" begin="30" end="21" resetval="0x0" description="" range="" rwaccess="R"/>
467     <bitfield id="MREQDOMAIN_PRUSS2_PRU1" width="3" begin="20" end="18" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that: MreqDomain[2:0]= 0b000 = DOMAIN0 MreqDomain[2:0]= 0b001 = DOMAIN1 MreqDomain[2:0]= 0b010 = DOMAIN2 MreqDomain[2:0]= 0b011 = DOMAIN3 MreqDomain[2:0]= 0b100 = DOMAIN4 MreqDomain[2:0]= 0b101 = DOMAIN5 MreqDomain[2:0]= 0b110 = DOMAIN6 MreqDomain[2:0]= 0b111 = DOMAIN7" range="" rwaccess="RW"/>
468     <bitfield id="MREQDOMAIN_PRUSS1_PRU1" width="3" begin="17" end="15" resetval="0x0" description="see MREQDOMAIN_PRUSS2_PRU1 Description" range="" rwaccess="RW"/>
469     <bitfield id="MREQDOMAIN_GPU_P1" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_PRUSS2_PRU1 Description" range="" rwaccess="RW"/>
470     <bitfield id="MREQDOMAIN_VPE_P1" width="3" begin="11" end="9" resetval="0x0" description="see MREQDOMAIN_PRUSS2_PRU1 Description" range="" rwaccess="RW"/>
471     <bitfield id="RESERVED" width="6" begin="8" end="3" resetval="0x0" description="" range="" rwaccess="R"/>
472     <bitfield id="MREQDOMAIN_VIP1_P1" width="3" begin="2" end="0" resetval="0x0" description="see MREQDOMAIN_PRUSS2_PRU1 Description" range="" rwaccess="RW"/>
473   </register>
474   <register id="CTRL_CORE_SEC_ERR_STATUS_FUNC_2" acronym="CTRL_CORE_SEC_ERR_STATUS_FUNC_2" offset="0x414" width="32" description="Firewall Error Status functional Register 2">
475     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
476     <bitfield id="TC1_EDMA_FW_ERROR" width="1" begin="26" end="26" resetval="0x0" description="EDMA TC1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
477     <bitfield id="RESERVED" width="3" begin="25" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
478     <bitfield id="QSPI_FW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="QSPI firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
479     <bitfield id="PRUSS2_FW_ERROR" width="1" begin="21" end="21" resetval="0x0" description="PRU-ICSS2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
480     <bitfield id="PRUSS1_FW_ERROR" width="1" begin="20" end="20" resetval="0x0" description="PRU-ICSS1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
481     <bitfield id="RESERVED" width="2" begin="19" end="18" resetval="0x0" description="" range="" rwaccess="R"/>
482     <bitfield id="TPCC_EDMA_FW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="EDMA TPCC firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
483     <bitfield id="TC0_EDMA_FW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="EDMA TC0 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
484     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
485     <bitfield id="MCASP3_FW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="McASP3 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
486     <bitfield id="MCASP2_FW_ERROR" width="1" begin="12" end="12" resetval="0x0" description="McASP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
487     <bitfield id="MCASP1_FW_ERROR" width="1" begin="11" end="11" resetval="0x0" description="McASP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
488     <bitfield id="VCP2_FW_ERROR" width="1" begin="10" end="10" resetval="0x0" description="VCP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
489     <bitfield id="VCP1_FW_ERROR" width="1" begin="9" end="9" resetval="0x0" description="VCP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
490     <bitfield id="PCIESS2_FW_ERROR" width="1" begin="8" end="8" resetval="0x0" description="PCIeSS2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
491     <bitfield id="PCIESS1_FW_ERROR" width="1" begin="7" end="7" resetval="0x0" description="PCIeSS1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
492     <bitfield id="IPU2_FW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IPU2 firewall. 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
493     <bitfield id="L4_PERIPH3_FW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="L4 periph3 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
494     <bitfield id="L4_PERIPH2_FW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="L4 periph2 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
495     <bitfield id="RESERVED" width="3" begin="3" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
496     <bitfield id="DSP1_FW_ERROR" width="1" begin="0" end="0" resetval="0x0" description="DSP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
497   </register>
498   <register id="CTRL_CORE_SEC_ERR_STATUS_DEBUG_2" acronym="CTRL_CORE_SEC_ERR_STATUS_DEBUG_2" offset="0x41C" width="32" description="Firewall Error Status debug Register 2">
499     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
500     <bitfield id="TC1_EDMA_DBGFW_ERROR" width="1" begin="26" end="26" resetval="0x0" description="EDMA TC1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
501     <bitfield id="RESERVED" width="3" begin="25" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
502     <bitfield id="QSPI_DBGFW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="QSPI debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
503     <bitfield id="PRUSS2_DBGFW_ERROR" width="1" begin="21" end="21" resetval="0x0" description="PRU-ICSS2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
504     <bitfield id="PRUSS1_DBGFW_ERROR" width="1" begin="20" end="20" resetval="0x0" description="PRU-ICSS1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
505     <bitfield id="RESERVED" width="2" begin="19" end="18" resetval="0x0" description="" range="" rwaccess="R"/>
506     <bitfield id="TPCC_EDMA_DBGFW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="EDMA TPCC debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
507     <bitfield id="TC0_EDMA_DBGFW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="EDMA TC0 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
508     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
509     <bitfield id="MCASP3_DBGFW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="McASP3 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
510     <bitfield id="MCASP2_DBGFW_ERROR" width="1" begin="12" end="12" resetval="0x0" description="McASP2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
511     <bitfield id="MCASP1_DBGFW_ERROR" width="1" begin="11" end="11" resetval="0x0" description="McASP1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
512     <bitfield id="VCP2_DBGFW_ERROR" width="1" begin="10" end="10" resetval="0x0" description="VCP2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
513     <bitfield id="VCP1_DBGFW_ERROR" width="1" begin="9" end="9" resetval="0x0" description="VCP1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
514     <bitfield id="PCIESS2_DBGFW_ERROR" width="1" begin="8" end="8" resetval="0x0" description="PCIeSS2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
515     <bitfield id="PCIESS1_DBGFW_ERROR" width="1" begin="7" end="7" resetval="0x0" description="PCIeSS1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
516     <bitfield id="IPU2_DBGFW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IPU2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
517     <bitfield id="L4_PERIPH3_DBGFW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="L4 periph3 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
518     <bitfield id="L4_PERIPH2_DBGFW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="L4 periph2 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
519     <bitfield id="RESERVED" width="3" begin="3" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
520     <bitfield id="DSP1_DBGFW_ERROR" width="1" begin="0" end="0" resetval="0x0" description="DSP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
521   </register>
522   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_1" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_1" offset="0x420" width="32" description="Register for priority settings for EMIF arbitration">
523     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
524     <bitfield id="MPU_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="MPU priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
525     <bitfield id="RESERVED" width="9" begin="27" end="19" resetval="0x88" description="" range="" rwaccess="R"/>
526     <bitfield id="DSP1_MDMA_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="DSP1 MDMA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
527     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
528     <bitfield id="DSP1_CFG_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="DSP1 CFG priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
529     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
530     <bitfield id="DSP1_EDMA_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="DSP1 EDMA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
531     <bitfield id="RESERVED" width="8" begin="7" end="0" resetval="0x44" description="" range="" rwaccess="R"/>
532   </register>
533   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_2" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_2" offset="0x424" width="32" description="Register for priority settings for EMIF arbitration">
534     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x4" description="" range="" rwaccess="R"/>
535     <bitfield id="IVA_ICONT1_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="IVA ICONT1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
536     <bitfield id="RESERVED" width="21" begin="23" end="3" resetval="0x8888" description="" range="" rwaccess="R"/>
537     <bitfield id="PRUSS1_PRU0_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="PRU-ICSS1 PRU0 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
538   </register>
539   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_3" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_3" offset="0x428" width="32" description="Register for priority settings for EMIF arbitration">
540     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
541     <bitfield id="PRUSS1_PRU1_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="PRU-ICSS1 PRU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>
542     <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
543     <bitfield id="PRUSS2_PRU0_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="PRU-ICSS2 PRU0 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>
544     <bitfield id="RESERVED" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
545     <bitfield id="PRUSS2_PRU1_EMIF_PRIORITY" width="3" begin="22" end="20" resetval="0x4" description="PRU-ICSS2 PRU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>
546     <bitfield id="RESERVED" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
547     <bitfield id="IPU1_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="IPU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>
548     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
549     <bitfield id="IPU2_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="IPU2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
550     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
551     <bitfield id="DMA_SYSTEM_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="DMA SYSTEM priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
552     <bitfield id="RESERVED" width="5" begin="7" end="3" resetval="0x8" description="" range="" rwaccess="R"/>
553     <bitfield id="EDMA_TC0_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="EDMA TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
554   </register>
555   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_4" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_4" offset="0x42C" width="32" description="Register for priority settings for EMIF arbitration">
556     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
557     <bitfield id="EDMA_TC1_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="EDMA TC1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
558     <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
559     <bitfield id="DSS_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="DSS priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
560     <bitfield id="RESERVED" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
561     <bitfield id="MLB_MMU1_EMIF_PRIORITY" width="3" begin="22" end="20" resetval="0x4" description="MLB, MMU1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
562     <bitfield id="RESERVED" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
563     <bitfield id="PCIESS1_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="PCIeSS1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
564     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
565     <bitfield id="PCIESS2_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="PCIeSS2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
566     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
567     <bitfield id="VIP1_P1_P2_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="VIP1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
568     <bitfield id="RESERVED" width="8" begin="7" end="0" resetval="0x44" description="" range="" rwaccess="R"/>
569   </register>
570   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_5" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_5" offset="0x430" width="32" description="Register for priority settings for EMIF arbitration">
571     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
572     <bitfield id="VPE_P1_P2_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="VPE priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
573     <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
574     <bitfield id="MMC1_GPU_P1_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="MMC1, GPU P1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
575     <bitfield id="RESERVED" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
576     <bitfield id="MMC2_GPU_P2_EMIF_PRIORITY" width="3" begin="22" end="20" resetval="0x4" description="MMC2, GPU P2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
577     <bitfield id="RESERVED" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
578     <bitfield id="BB2D_P1_P2_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="BB2D priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
579     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
580     <bitfield id="GMAC_SW_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="GMAC_SW priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
581     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
582     <bitfield id="USB1_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="USB1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
583     <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
584     <bitfield id="USB2_EMIF_PRIORITY" width="3" begin="6" end="4" resetval="0x4" description="USB2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
585     <bitfield id="RESERVED" width="1" begin="3" end="3" resetval="0x0" description="" range="" rwaccess="R"/>
586     <bitfield id="USB3_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="USB3 priority setting 0x0 = highest priority 0x7 = lowest priorty" range="" rwaccess="RW"/>
587   </register>
588   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_6" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_6" offset="0x434" width="32" description="Register for priority settings for EMIF arbitration">
589     <bitfield id="RESERVED" width="17" begin="31" end="15" resetval="0x8888" description="" range="" rwaccess="R"/>
590     <bitfield id="SATA_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="SATA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
591     <bitfield id="RESERVED" width="12" begin="11" end="0" resetval="0x444" description="" range="" rwaccess="R"/>
592   </register>
593   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_1" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_1" offset="0x43C" width="32" description="Register for pressure settings for L3 arbitration">
594     <bitfield id="RESERVED" width="4" begin="31" end="28" resetval="0x0" description="" range="" rwaccess="R"/>
595     <bitfield id="MPU_L3_PRESSURE" width="2" begin="27" end="26" resetval="0x0" description="MPU pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
596     <bitfield id="RESERVED" width="7" begin="25" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
597     <bitfield id="DSP1_CFG_L3_PRESSURE" width="2" begin="18" end="17" resetval="0x0" description="DSP1 CFG pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
598     <bitfield id="RESERVED" width="17" begin="16" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
599   </register>
600   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_2" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_2" offset="0x440" width="32" description="Register for pressure settings for L3 arbitration">
601     <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
602     <bitfield id="CSI2_1_L3_PRESSURE" width="2" begin="19" end="18" resetval="0x0" description="CSI2_1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
603     <bitfield id="RESERVED" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="R"/>
604     <bitfield id="CSI2_2_L3_PRESSURE" width="2" begin="16" end="15" resetval="0x0" description="CSI2_2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
605     <bitfield id="RESERVED" width="1" begin="14" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
606     <bitfield id="IPU1_L3_PRESSURE" width="2" begin="13" end="12" resetval="0x0" description="IPU1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
607     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
608     <bitfield id="IPU2_L3_PRESSURE" width="2" begin="10" end="9" resetval="0x0" description="IPU2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
609     <bitfield id="RESERVED" width="1" begin="8" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
610     <bitfield id="PRUSS1_PRU0_L3_PRESSURE" width="2" begin="7" end="6" resetval="0x0" description="PRU-ICSS1 PRU0 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
611     <bitfield id="RESERVED" width="1" begin="5" end="5" resetval="0x0" description="" range="" rwaccess="R"/>
612     <bitfield id="PRUSS1_PRU1_L3_PRESSURE" width="2" begin="4" end="3" resetval="0x0" description="PRU-ICSS1 PRU1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
613     <bitfield id="RESERVED" width="1" begin="2" end="2" resetval="0x0" description="" range="" rwaccess="R"/>
614     <bitfield id="PRUSS2_PRU0_L3_PRESSURE" width="2" begin="1" end="0" resetval="0x0" description="PRU-ICSS2 PRU0 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
615   </register>
616   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_3" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_3" offset="0x444" width="32" description="Register for pressure settings for L3 arbitration">
617     <bitfield id="RESERVED" width="4" begin="31" end="28" resetval="0x0" description="" range="" rwaccess="R"/>
618     <bitfield id="PRUSS2_PRU1_L3_PRESSURE" width="2" begin="27" end="26" resetval="0x0" description="PRU-ICSS2 PRU1 pressure setting0x0 = lowest enum=LOWEST . 0x3 = highest enum=HIGHEST ." range="" rwaccess="RW"/>
619     <bitfield id="RESERVED" width="26" begin="25" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
620   </register>
621   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_4" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_4" offset="0x448" width="32" description="Register for pressure settings for L3 arbitration">
622     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
623     <bitfield id="GPU_P1_L3_PRESSURE" width="2" begin="24" end="23" resetval="0x0" description="GPU P1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
624     <bitfield id="RESERVED" width="1" begin="22" end="22" resetval="0x0" description="" range="" rwaccess="R"/>
625     <bitfield id="GPU_P2_L3_PRESSURE" width="2" begin="21" end="20" resetval="0x0" description="GPU P2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
626     <bitfield id="RESERVED" width="20" begin="19" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
627   </register>
628   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_5" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_5" offset="0x44C" width="32" description="Register for pressure settings for L3 arbitration">
629     <bitfield id="RESERVED" width="27" begin="31" end="5" resetval="0x0" description="" range="" rwaccess="R"/>
630     <bitfield id="SATA_L3_PRESSURE" width="2" begin="4" end="3" resetval="0x0" description="SATA pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
631     <bitfield id="RESERVED" width="1" begin="2" end="2" resetval="0x0" description="" range="" rwaccess="R"/>
632     <bitfield id="MMC1_L3_PRESSURE" width="2" begin="1" end="0" resetval="0x0" description="MMC1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
633   </register>
634   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_6" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_6" offset="0x450" width="32" description="Register for pressure settings for L3 arbitration">
635     <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
636     <bitfield id="MMC2_L3_PRESSURE" width="2" begin="18" end="17" resetval="0x0" description="MMC2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
637     <bitfield id="USB1_L3_PRESSURE" width="2" begin="16" end="15" resetval="0x0" description="USB1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
638     <bitfield id="RESERVED" width="1" begin="14" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
639     <bitfield id="USB2_L3_PRESSURE" width="2" begin="13" end="12" resetval="0x0" description="USB2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
640     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
641     <bitfield id="USB3_L3_PRESSURE" width="2" begin="10" end="9" resetval="0x0" description="USB3 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
642     <bitfield id="RESERVED" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
643   </register>
644   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0" offset="0x458" width="32" description="Standard Fuse OPP VDD_iva [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
645     <bitfield id="STD_FUSE_OPP_VDD_IVA_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
646   </register>
647   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1" offset="0x45C" width="32" description="Standard Fuse OPP VDD_iva [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
648     <bitfield id="STD_FUSE_OPP_VDD_IVA_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
649   </register>
650   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2" offset="0x460" width="32" description="Standard Fuse OPP VDD_iva [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
651     <bitfield id="STD_FUSE_OPP_VDD_IVA_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
652   </register>
653   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3" offset="0x464" width="32" description="Standard Fuse OPP VDD_iva [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
654     <bitfield id="STD_FUSE_OPP_VDD_IVA_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
655   </register>
656   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4" offset="0x468" width="32" description="Standard Fuse OPP VDD_iva [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
657     <bitfield id="STD_FUSE_OPP_VDD_IVA_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
658   </register>
659   <register id="CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL" offset="0x46C" width="32" description="DSPEVE Voltage Body Bias LDO Control register">
660     <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
661     <bitfield id="LDOVBBDSPEVE_FBB_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" range="" rwaccess="RW"/>
662     <bitfield id="LDOVBBDSPEVE_FBB_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Forward Body Bias voltage value" range="" rwaccess="R"/>
663     <bitfield id="LDOVBBDSPEVE_FBB_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_x[24:20] VSETABB bit fields. This value applies if LDOVBBDSPEVE_FBB_MUX_CTRL is set to 0x1." range="" rwaccess="RW"/>
664   </register>
665   <register id="CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL" offset="0x470" width="32" description="IVA Voltage Body Bias LDO Control register">
666     <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
667     <bitfield id="LDOVBBIVA_FBB_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" range="" rwaccess="RW"/>
668     <bitfield id="LDOVBBIVA_FBB_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Forward Body Bias voltage value" range="" rwaccess="R"/>
669     <bitfield id="LDOVBBIVA_FBB_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_x[24:20] VSETABB bit fields. This value applies if LDOVBBIVA_FBB_MUX_CTRL is set to 0x1." range="" rwaccess="RW"/>
670   </register>
671   <register id="CTRL_CORE_CUST_FUSE_UID_0" acronym="CTRL_CORE_CUST_FUSE_UID_0" offset="0x4E8" width="32" description="Customer Fuse keys. UID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
672     <bitfield id="CUST_FUSE_UID_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
673   </register>
674   <register id="CTRL_CORE_CUST_FUSE_UID_1" acronym="CTRL_CORE_CUST_FUSE_UID_1" offset="0x4EC" width="32" description="Customer Fuse keys. UID [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
675     <bitfield id="CUST_FUSE_UID_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
676   </register>
677   <register id="CTRL_CORE_CUST_FUSE_UID_2" acronym="CTRL_CORE_CUST_FUSE_UID_2" offset="0x4F0" width="32" description="Customer Fuse keys. UID [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
678     <bitfield id="CUST_FUSE_UID_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
679   </register>
680   <register id="CTRL_CORE_CUST_FUSE_UID_3" acronym="CTRL_CORE_CUST_FUSE_UID_3" offset="0x4F4" width="32" description="Customer Fuse keys. UID [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
681     <bitfield id="CUST_FUSE_UID_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
682   </register>
683   <register id="CTRL_CORE_CUST_FUSE_UID_4" acronym="CTRL_CORE_CUST_FUSE_UID_4" offset="0x4F8" width="32" description="Customer Fuse keys. UID [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
684     <bitfield id="CUST_FUSE_UID_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
685   </register>
686   <register id="CTRL_CORE_CUST_FUSE_UID_5" acronym="CTRL_CORE_CUST_FUSE_UID_5" offset="0x4FC" width="32" description="Customer Fuse keys. UID [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
687     <bitfield id="CUST_FUSE_UID_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
688   </register>
689   <register id="CTRL_CORE_CUST_FUSE_UID_6" acronym="CTRL_CORE_CUST_FUSE_UID_6" offset="0x500" width="32" description="Customer Fuse keys. UID [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
690     <bitfield id="CUST_FUSE_UID_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
691   </register>
692   <register id="CTRL_CORE_CUST_FUSE_PCIE_ID_0" acronym="CTRL_CORE_CUST_FUSE_PCIE_ID_0" offset="0x508" width="32" description="Customer Fuse keys. PCIe ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
693     <bitfield id="CUST_FUSE_PCIE_ID_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
694   </register>
695   <register id="CTRL_CORE_CUST_FUSE_USB_ID_0" acronym="CTRL_CORE_CUST_FUSE_USB_ID_0" offset="0x510" width="32" description="Customer Fuse keys. USB ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
696     <bitfield id="CUST_FUSE_USB_ID_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
697   </register>
698   <register id="CTRL_CORE_MAC_ID_SW_0" acronym="CTRL_CORE_MAC_ID_SW_0" offset="0x514" width="32" description="Standard Fuse keys, MAC ID_1 [63:32].">
699     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
700     <bitfield id="STD_FUSE_MAC_ID_SW_0" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 0. Bits [23:16] contain the 4th octet of the MAC address. Bits [15:8] contain the 5th octet of the MAC address. Bits [7:0] contain the last (6th) octet of the MAC address." range="" rwaccess="R"/>
701   </register>
702   <register id="CTRL_CORE_MAC_ID_SW_1" acronym="CTRL_CORE_MAC_ID_SW_1" offset="0x518" width="32" description="Standard Fuse keys, MAC ID_1 [31:0].">
703     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
704     <bitfield id="STD_FUSE_MAC_ID_SW_1" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 0. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." range="" rwaccess="R"/>
705   </register>
706   <register id="CTRL_CORE_MAC_ID_SW_2" acronym="CTRL_CORE_MAC_ID_SW_2" offset="0x51C" width="32" description="Standard Fuse keys, MAC ID_2 [63:32].">
707     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
708     <bitfield id="STD_FUSE_MAC_ID_SW_2" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the 4th octet of the MAC address. Bits [15:8] contain the 5th octet of the MAC address. Bits [7:0] contain the last (6th) octet of the MAC address." range="" rwaccess="R"/>
709   </register>
710   <register id="CTRL_CORE_MAC_ID_SW_3" acronym="CTRL_CORE_MAC_ID_SW_3" offset="0x520" width="32" description="Standard Fuse keys, MAC ID_2 [31:0].">
711     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
712     <bitfield id="STD_FUSE_MAC_ID_SW_3" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." range="" rwaccess="R"/>
713   </register>
714   <register id="CTRL_CORE_SMA_SW_1" acronym="CTRL_CORE_SMA_SW_1" offset="0x534" width="32" description="OCP Spare Register">
715     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
716     <bitfield id="RGMII2_ID_MODE_N" width="1" begin="26" end="26" resetval="0x0" description="Ethernet RGMII port 2 internal delay on transmit (SR2.x) 0x0: Internal delay enabled 0x1: Internal delay disabled" range="" rwaccess="RW"/>
717     <bitfield id="RGMII1_ID_MODE_N" width="1" begin="25" end="25" resetval="0x0" description="Ethernet RGMII port 1 internal delay on transmit (SR2.x) 0x0: Internal delay enabled 0x1: Internal delay disabled" range="" rwaccess="RW"/>
718     <bitfield id="DSS_CH2_ON_OFF" width="1" begin="24" end="24" resetval="0x0" description="DSS Channel 2 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH2_RF" range="" rwaccess="RW"/>
719     <bitfield id="DSS_CH1_ON_OFF" width="1" begin="23" end="23" resetval="0x0" description="DSS Channel 1 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH1_RF" range="" rwaccess="RW"/>
720     <bitfield id="DSS_CH0_ON_OFF" width="1" begin="22" end="22" resetval="0x0" description="DSS Channel 0 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH0_RF" range="" rwaccess="RW"/>
721     <bitfield id="DSS_CH2_IPC" width="1" begin="21" end="21" resetval="0x0" description="DSS Channel 2 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" range="" rwaccess="RW"/>
722     <bitfield id="DSS_CH1_IPC" width="1" begin="20" end="20" resetval="0x0" description="DSS Channel 1 IPC controlDSS Channel 2 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" range="" rwaccess="RW"/>
723     <bitfield id="DSS_CH0_IPC" width="1" begin="19" end="19" resetval="0x0" description="DSS Channel 0 IPC controlDSS Channel 2 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" range="" rwaccess="RW"/>
724     <bitfield id="DSS_CH2_RF" width="1" begin="18" end="18" resetval="0x0" description="DSS Channel 2 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1)" range="" rwaccess="RW"/>
725     <bitfield id="DSS_CH1_RF" width="1" begin="17" end="17" resetval="0x0" description="DSS Channel 1 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1)" range="" rwaccess="RW"/>
726     <bitfield id="DSS_CH0_RF" width="1" begin="16" end="16" resetval="0x0" description="DSS Channel 0 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1)" range="" rwaccess="RW"/>
727     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
728     <bitfield id="VIP3_CLK_INV_PORT_1A" width="1" begin="10" end="10" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP5A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
729     <bitfield id="VIP3_CLK_INV_PORT_2A" width="1" begin="9" end="9" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP6A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
730     <bitfield id="VPE_CLK_DIV_BY_2_EN" width="1" begin="8" end="8" resetval="0x0" description="Selects alternative clock source for VPE. 0x0: Default clock source from DPLL_CORE is selected 0x1: Alternative clock source from DPLL_VIDEO1 is selected" range="" rwaccess="RW"/>
731     <bitfield id="VIP2_CLK_INV_PORT_2B" width="1" begin="7" end="7" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP4B. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
732     <bitfield id="VIP2_CLK_INV_PORT_1B" width="1" begin="6" end="6" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP3B. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
733     <bitfield id="VIP2_CLK_INV_PORT_2A" width="1" begin="5" end="5" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP4A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
734     <bitfield id="VIP2_CLK_INV_PORT_1A" width="1" begin="4" end="4" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP3A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
735     <bitfield id="VIP1_CLK_INV_PORT_2B" width="1" begin="3" end="3" resetval="0x0" description="VIP1 Slice 1 Clock inversion for Port B enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
736     <bitfield id="VIP1_CLK_INV_PORT_1B" width="1" begin="2" end="2" resetval="0x0" description="VIP1 Slice 0 Clock inversion for Port B enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
737     <bitfield id="VIP1_CLK_INV_PORT_2A" width="1" begin="1" end="1" resetval="0x0" description="VIP1 Slice 1 Clock inversion for Port A enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
738     <bitfield id="VIP1_CLK_INV_PORT_1A" width="1" begin="0" end="0" resetval="0x0" description="VIP1 Slice 0 Clock inversion for Port A enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
739   </register>
740   <register id="CTRL_CORE_DSS_PLL_CONTROL" acronym="CTRL_CORE_DSS_PLL_CONTROL" offset="0x538" width="32" description="DSS PLLs Mux control register">
741     <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>
742     <bitfield id="SDVENC_CLK_SELECTION" width="2" begin="10" end="9" resetval="0x1" description="SDVENC_CLK mux configuration 0x0 = HDMI_CLK 0x1 = DPLL_VIDEO1_HSDIVIDER_clkout3" range="" rwaccess="RW"/>
743     <bitfield id="DSI1_C_CLK1_SELECTION" width="2" begin="8" end="7" resetval="0x1" description="DSI1_C_CLK1 mux configuration 0x0 = Reserved 0x1 = DPLL_VIDEO1 0x2 = DPLL_HDMI" range="" rwaccess="RW"/>
744     <bitfield id="DSI1_B_CLK1_SELECTION" width="2" begin="6" end="5" resetval="0x1" description="DSI1_B_CLK1 mux configuration 0x0 = DPLL_VIDEO1 0x1 = Reserved 0x2 = DPLL_HDMI 0x3 = DPLL_ABE" range="" rwaccess="RW"/>
745     <bitfield id="DSI1_A_CLK1_SELECTION" width="2" begin="4" end="3" resetval="0x1" description="DSI1_A_CLK1 mux configuration 0x0 = DPLL_VIDEO1 0x1 = DPLL_HDMI" range="" rwaccess="RW"/>
746     <bitfield id="PLL_HDMI_DSS_CONTROL_DISABLE" width="1" begin="2" end="2" resetval="0x1" description="HDMI PLL disable 0x0 = PLL enabled 0x1 = PLL disabled" range="" rwaccess="RW"/>
747     <bitfield id="RESERVED" width="1" begin="1" end="1" resetval="0x1" description="" range="" rwaccess="R"/>
748     <bitfield id="PLL_VIDEO1_DSS_CONTROL_DISABLE" width="1" begin="0" end="0" resetval="0x1" description="VIDEO1 PLL disable 0x0 = PLL enabled 0x1 = PLL disabled" range="" rwaccess="RW"/>
749   </register>
750   <register id="CTRL_CORE_MMR_LOCK_1" acronym="CTRL_CORE_MMR_LOCK_1" offset="0x540" width="32" description="Register to lock memory region starting at address offset 0x0000 0100 and ending at address offset 0x0000 079F">
751     <bitfield id="MMR_LOCK_1" width="32" begin="31" end="0" resetval="0x1A1C8144" description="Lock value for region 0x0000 0100 to 0x0000 079F 0x1A1C8144 = lock value 0x2FF1AC2B = unlock value" range="" rwaccess="RW"/>
752   </register>
753   <register id="CTRL_CORE_MMR_LOCK_2" acronym="CTRL_CORE_MMR_LOCK_2" offset="0x544" width="32" description="Register to lock memory region starting at address offset 0x0000 07A0 and ending at address offset 0x0000 0D9F">
754     <bitfield id="MMR_LOCK_2" width="32" begin="31" end="0" resetval="0xFDF45530" description="Lock value for region 0x0000 07A0 to 0x0000 0D9F 0xFDF45530 = lock value 0xF757FDC0 = unlock value" range="" rwaccess="RW"/>
755   </register>
756   <register id="CTRL_CORE_MMR_LOCK_3" acronym="CTRL_CORE_MMR_LOCK_3" offset="0x548" width="32" description="Register to lock memory region starting at address offset 0x0000 0DA0 and ending at address offset 0x0000 0FFF">
757     <bitfield id="MMR_LOCK_3" width="32" begin="31" end="0" resetval="0x1AE6E320" description="Lock value for region 0x0000 0DA0 to 0x0000 0FFF 0x1AE6E320 = lock value 0xE2BC3A6D = unlock value" range="" rwaccess="RW"/>
758   </register>
759   <register id="CTRL_CORE_MMR_LOCK_4" acronym="CTRL_CORE_MMR_LOCK_4" offset="0x54C" width="32" description="Register to lock memory region starting at address offset 0x0000 1000 and ending at address offset 0x0000 13FF">
760     <bitfield id="MMR_LOCK_4" width="32" begin="31" end="0" resetval="0x2FFA927C" description="Lock value for region 0x0000 1000 to 0x0000 13FF 0x2FFA927C = lock value 0x1EBF131D = unlock value" range="" rwaccess="RW"/>
761   </register>
762   <register id="CTRL_CORE_MMR_LOCK_5" acronym="CTRL_CORE_MMR_LOCK_5" offset="0x550" width="32" description="Register to lock memory region starting at address offset 0x0000 1400 and ending at address offset 0x0000 1FFF">
763     <bitfield id="MMR_LOCK_5" width="32" begin="31" end="0" resetval="0x143F832C" description="Lock value for region 0x0000 1400 to 0x0000 1FFF 0x143F832C = lock value 0x6F361E05 = unlock value" range="" rwaccess="RW"/>
764   </register>
765   <register id="CTRL_CORE_CONTROL_IO_1" acronym="CTRL_CORE_CONTROL_IO_1" offset="0x554" width="32" description="Register to configure some IP level signals">
766     <bitfield id="RESERVED" width="11" begin="31" end="21" resetval="0x0" description="" range="" rwaccess="R"/>
767     <bitfield id="MMU2_DISABLE" width="1" begin="20" end="20" resetval="0x0" description="MMU2 DISABLE setting" range="" rwaccess="RW"/>
768     <bitfield id="RESERVED" width="3" begin="19" end="17" resetval="0x0" description="" range="" rwaccess="R"/>
769     <bitfield id="MMU1_DISABLE" width="1" begin="16" end="16" resetval="0x0" description="MMU1 DISABLE setting" range="" rwaccess="RW"/>
770     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
771     <bitfield id="TC1_DEFAULT_BURST_SIZE" width="2" begin="13" end="12" resetval="0x3" description="EDMA TC1 Default Burst Size (DBS) setting 0x0: 16 byte burst 0x1: 32 byte burst 0x2: 64 byte burst 0x3: 128 byte burst" range="" rwaccess="RW"/>
772     <bitfield id="RESERVED" width="2" begin="11" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
773     <bitfield id="TC0_DEFAULT_BURST_SIZE" width="2" begin="9" end="8" resetval="0x3" description="EDMA TC0 Default Burst Size (DBS) setting 0x0: 16 byte burst 0x1: 32 byte burst 0x2: 64 byte burst 0x3: 128 byte burst" range="" rwaccess="RW"/>
774     <bitfield id="RESERVED" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
775     <bitfield id="GMII2_SEL" width="2" begin="5" end="4" resetval="0x0" description="GMII2 selection setting 0x0: GMII/MII 0x1: RMII 0x2: RGMII 0x3: Reserved" range="" rwaccess="RW"/>
776     <bitfield id="RESERVED" width="2" begin="3" end="2" resetval="0x0" description="" range="" rwaccess="R"/>
777     <bitfield id="GMII1_SEL" width="2" begin="1" end="0" resetval="0x0" description="GMII1 selection setting 0x0: GMII/MII 0x1: RMII 0x2: RGMII 0x3: Reserved" range="" rwaccess="RW"/>
778   </register>
779   <register id="CTRL_CORE_CONTROL_IO_2" acronym="CTRL_CORE_CONTROL_IO_2" offset="0x558" width="32" description="Register to configure some IP level signals">
780     <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
781     <bitfield id="GMAC_RESET_ISOLATION_ENABLE" width="1" begin="23" end="23" resetval="0x0" description="Reset isolation enable setting 0x0 = Reset is not isolated 0x1 = Reset is isolated" range="" rwaccess="RW"/>
782     <bitfield id="PWMSS3_TBCLKEN" width="1" begin="22" end="22" resetval="0x0" description="PWMSS3 CLOCK ENABLE setting" range="" rwaccess="RW"/>
783     <bitfield id="PWMSS2_TBCLKEN" width="1" begin="21" end="21" resetval="0x0" description="PWMSS2 CLOCK ENABLE setting" range="" rwaccess="RW"/>
784     <bitfield id="PWMSS1_TBCLKEN" width="1" begin="20" end="20" resetval="0x0" description="PWMSS1 CLOCK ENABLE setting" range="" rwaccess="RW"/>
785     <bitfield id="RESERVED" width="6" begin="19" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
786     <bitfield id="PCIE_1LANE_2LANE_SELECTION" width="1" begin="13" end="13" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>
787     <bitfield id="RESERVED" width="2" begin="12" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
788     <bitfield id="QSPI_MEMMAPPED_CS" width="3" begin="10" end="8" resetval="0x0" description="QSPI CS MAPPING setting. 0x0: The QSPI configuration registers are accessed 0x1: An external device connected to CS0 is accessed 0x2: An external device connected to CS1 is accessed 0x3: An external device connected to CS2 is accessed 0x4-0x7: An external device connected to CS3 is accessed" range="" rwaccess="RW"/>
789     <bitfield id="RESERVED" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
790     <bitfield id="DCAN2_RAMINIT_START" width="1" begin="5" end="5" resetval="0x0" description="DCAN2 RAM INIT START setting To initialize DCAN2 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>
791     <bitfield id="DSS_DESHDCP_DISABLE" width="1" begin="4" end="4" resetval="0x0" description="DSS DESHDCP DISABLE setting" range="" rwaccess="RW"/>
792     <bitfield id="DCAN1_RAMINIT_START" width="1" begin="3" end="3" resetval="0x0" description="DCAN1 RAM INIT START setting To initialize DCAN1 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>
793     <bitfield id="DCAN2_RAMINIT_DONE" width="1" begin="2" end="2" resetval="0x0" description="DCAN2 RAM INIT DONE status" range="" rwaccess="RW"/>
794     <bitfield id="DCAN1_RAMINIT_DONE" width="1" begin="1" end="1" resetval="0x0" description="DCAN1 RAM INIT DONE status" range="" rwaccess="RW"/>
795     <bitfield id="DSS_DESHDCP_CLKEN" width="1" begin="0" end="0" resetval="0x0" description="DSS DESHDCP CLOCK ENABLE setting" range="" rwaccess="RW"/>
796   </register>
797   <register id="CTRL_CORE_CONTROL_DSP1_RST_VECT" acronym="CTRL_CORE_CONTROL_DSP1_RST_VECT" offset="0x55C" width="32" description="Register for storing DSP1 reset vector">
798     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>
799     <bitfield id="DSP1_NUM_MM" width="3" begin="26" end="24" resetval="0x0" description="Number of DSP instances in the SoC 0x1 = 1 0x2 = 2" range="" rwaccess="RW"/>
800     <bitfield id="RESERVED" width="2" begin="23" end="22" resetval="0x0" description="" range="" rwaccess="R"/>
801     <bitfield id="DSP1_RST_VECT" width="22" begin="21" end="0" resetval="0x0" description="DSP1 reset vector address" range="" rwaccess="RW"/>
802   </register>
803   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE" offset="0x564" width="32" description="Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use.">
804     <bitfield id="RESERVED" width="16" begin="31" end="16" resetval="0x-" description="" range="" rwaccess="R"/>
805     <bitfield id="STD_FUSE_OPP_BGAP_DSPEVE_0" width="8" begin="15" end="8" resetval="0x-" description="Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
806     <bitfield id="STD_FUSE_OPP_BGAP_DSPEVE_1" width="8" begin="7" end="0" resetval="0x-" description="Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
807   </register>
808   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_IVA" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_IVA" offset="0x568" width="32" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">
809     <bitfield id="STD_FUSE_OPP_BGAP_IVA_0" width="8" begin="31" end="24" resetval="0x-" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
810     <bitfield id="STD_FUSE_OPP_BGAP_IVA_1" width="8" begin="23" end="16" resetval="0x-" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
811     <bitfield id="STD_FUSE_OPP_BGAP_IVA_2" width="8" begin="15" end="8" resetval="0x-" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
812     <bitfield id="STD_FUSE_OPP_BGAP_IVA_3" width="8" begin="7" end="0" resetval="0x-" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
813   </register>
814   <register id="CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL" offset="0x56C" width="32" description="DSPEVE SRAM LDO Control register">
815     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
816     <bitfield id="LDOSRAMDSPEVE_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">
817       <bitenum value="0" id="EFUSE" token="LDOSRAMDSPEVE_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>
818       <bitenum value="1" id="OCP" token="LDOSRAMDSPEVE_RETMODE_MUX_CTRL_1" description="Override value is used"/>
819     </bitfield>
820     <bitfield id="LDOSRAMDSPEVE_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>
821     <bitfield id="LDOSRAMDSPEVE_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>
822     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
823     <bitfield id="LDOSRAMDSPEVE_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">
824       <bitenum value="0" id="EFUSE" token="LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>
825       <bitenum value="1" id="OCP" token="LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_1" description="Override value is used"/>
826     </bitfield>
827     <bitfield id="LDOSRAMDSPEVE_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>
828     <bitfield id="LDOSRAMDSPEVE_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>
829   </register>
830   <register id="CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL" offset="0x570" width="32" description="IVA SRAM LDO Control register">
831     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
832     <bitfield id="LDOSRAMIVA_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">
833       <bitenum value="0" id="EFUSE" token="LDOSRAMIVA_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>
834       <bitenum value="1" id="OCP" token="LDOSRAMIVA_RETMODE_MUX_CTRL_1" description="Override value is used"/>
835     </bitfield>
836     <bitfield id="LDOSRAMIVA_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>
837     <bitfield id="LDOSRAMIVA_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>
838     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
839     <bitfield id="LDOSRAMIVA_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">
840       <bitenum value="0" id="EFUSE" token="LDOSRAMIVA_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>
841       <bitenum value="1" id="OCP" token="LDOSRAMIVA_ACTMODE_MUX_CTRL_1" description="Override value is used"/>
842     </bitfield>
843     <bitfield id="LDOSRAMIVA_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>
844     <bitfield id="LDOSRAMIVA_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>
845   </register>
846   <register id="CTRL_CORE_TEMP_SENSOR_DSPEVE" acronym="CTRL_CORE_TEMP_SENSOR_DSPEVE" offset="0x574" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
847     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
848     <bitfield id="BGAP_TMPSOFF_DSPEVE" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
849     <bitfield id="BGAP_EOCZ_DSPEVE" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_DSPEVE is valid." range="" rwaccess="R"/>
850     <bitfield id="BGAP_DTEMP_DSPEVE" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
851   </register>
852   <register id="CTRL_CORE_TEMP_SENSOR_IVA" acronym="CTRL_CORE_TEMP_SENSOR_IVA" offset="0x578" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
853     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
854     <bitfield id="BGAP_TMPSOFF_IVA" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
855     <bitfield id="BGAP_EOCZ_IVA" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_IVA is valid." range="" rwaccess="R"/>
856     <bitfield id="BGAP_DTEMP_IVA" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
857   </register>
858   <register id="CTRL_CORE_BANDGAP_MASK_2" acronym="CTRL_CORE_BANDGAP_MASK_2" offset="0x57C" width="32" description="bgap_mask">
859     <bitfield id="RESERVED" width="9" begin="31" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
860     <bitfield id="FREEZE_IVA" width="1" begin="22" end="22" resetval="0x0" description="Freeze the FIFO IVA 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
861     <bitfield id="FREEZE_DSPEVE" width="1" begin="21" end="21" resetval="0x0" description="Freeze the FIFO DSPEVE 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
862     <bitfield id="RESERVED" width="1" begin="20" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
863     <bitfield id="CLEAR_IVA" width="1" begin="19" end="19" resetval="0x0" description="Reset the FIFO IVA 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
864     <bitfield id="CLEAR_DSPEVE" width="1" begin="18" end="18" resetval="0x0" description="Reset the FIFO DSPEVE 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
865     <bitfield id="RESERVED" width="14" begin="17" end="4" resetval="0x0" description="" range="" rwaccess="R"/>
866     <bitfield id="MASK_HOT_IVA" width="1" begin="3" end="3" resetval="0x0" description="Mask for hot event IVA 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
867     <bitfield id="MASK_COLD_IVA" width="1" begin="2" end="2" resetval="0x0" description="Mask for cold event IVA 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
868     <bitfield id="MASK_HOT_DSPEVE" width="1" begin="1" end="1" resetval="0x0" description="Mask for hot event DSPEVE 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
869     <bitfield id="MASK_COLD_DSPEVE" width="1" begin="0" end="0" resetval="0x0" description="Mask for cold event DSPEVE 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
870   </register>
871   <register id="CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE" acronym="CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE" offset="0x580" width="32" description="BGAP THRESHOLD DSPEVE">
872     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
873     <bitfield id="THOLD_HOT_DSPEVE" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
874     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
875     <bitfield id="THOLD_COLD_DSPEVE" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
876   </register>
877   <register id="CTRL_CORE_BANDGAP_THRESHOLD_IVA" acronym="CTRL_CORE_BANDGAP_THRESHOLD_IVA" offset="0x584" width="32" description="BGAP THRESHOLD IVA">
878     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
879     <bitfield id="THOLD_HOT_IVA" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
880     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
881     <bitfield id="THOLD_COLD_IVA" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
882   </register>
883   <register id="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" acronym="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" offset="0x588" width="32" description="BGAP TSHUT THRESHOLD IVA">
884     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
885     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
886     <bitfield id="TSHUT_HOT_DSPEVE" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
887     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
888     <bitfield id="TSHUT_COLD_DSPEVE" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
889   </register>
890   <register id="CTRL_CORE_BANDGAP_TSHUT_IVA" acronym="CTRL_CORE_BANDGAP_TSHUT_IVA" offset="0x58C" width="32" description="BGAP TSHUT THRESHOLD IVA">
891     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
892     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
893     <bitfield id="TSHUT_HOT_IVA" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
894     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
895     <bitfield id="TSHUT_COLD_IVA" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
896   </register>
897   <register id="CTRL_CORE_BANDGAP_STATUS_2" acronym="CTRL_CORE_BANDGAP_STATUS_2" offset="0x598" width="32" description="BGAP STATUS">
898     <bitfield id="RESERVED" width="28" begin="31" end="4" resetval="0x0" description="" range="" rwaccess="R"/>
899     <bitfield id="HOT_IVA" width="1" begin="3" end="3" resetval="0x0" description="Event for hot temperature iva bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
900     <bitfield id="COLD_IVA" width="1" begin="2" end="2" resetval="0x0" description="Event for cold temperature iva bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
901     <bitfield id="HOT_DSPEVE" width="1" begin="1" end="1" resetval="0x0" description="Event for hot temperature dspeve bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
902     <bitfield id="COLD_DSPEVE" width="1" begin="0" end="0" resetval="0x0" description="Event for cold temperature dspeve bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
903   </register>
904   <register id="CTRL_CORE_DTEMP_DSPEVE_0" acronym="CTRL_CORE_DTEMP_DSPEVE_0" offset="0x59C" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN. Most recent sample">
905     <bitfield id="DTEMP_TAG_DSPEVE_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
906     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
907   </register>
908   <register id="CTRL_CORE_DTEMP_DSPEVE_1" acronym="CTRL_CORE_DTEMP_DSPEVE_1" offset="0x5A0" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN">
909     <bitfield id="DTEMP_TAG_DSPEVE_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
910     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
911   </register>
912   <register id="CTRL_CORE_DTEMP_DSPEVE_2" acronym="CTRL_CORE_DTEMP_DSPEVE_2" offset="0x5A4" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN">
913     <bitfield id="DTEMP_TAG_DSPEVE_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
914     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
915   </register>
916   <register id="CTRL_CORE_DTEMP_DSPEVE_3" acronym="CTRL_CORE_DTEMP_DSPEVE_3" offset="0x5A8" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN">
917     <bitfield id="DTEMP_TAG_DSPEVE_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
918     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
919   </register>
920   <register id="CTRL_CORE_DTEMP_DSPEVE_4" acronym="CTRL_CORE_DTEMP_DSPEVE_4" offset="0x5AC" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN. Oldest sample">
921     <bitfield id="DTEMP_TAG_DSPEVE_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
922     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
923   </register>
924   <register id="CTRL_CORE_DTEMP_IVA_0" acronym="CTRL_CORE_DTEMP_IVA_0" offset="0x5B0" width="32" description="TAGGED TEMPERATURE IVA DOMAIN. Most recent sample">
925     <bitfield id="DTEMP_TAG_IVA_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
926     <bitfield id="DTEMP_TEMPERATURE_IVA_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
927   </register>
928   <register id="CTRL_CORE_DTEMP_IVA_1" acronym="CTRL_CORE_DTEMP_IVA_1" offset="0x5B4" width="32" description="TAGGED TEMPERATURE IVA DOMAIN">
929     <bitfield id="DTEMP_TAG_IVA_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
930     <bitfield id="DTEMP_TEMPERATURE_IVA_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
931   </register>
932   <register id="CTRL_CORE_DTEMP_IVA_2" acronym="CTRL_CORE_DTEMP_IVA_2" offset="0x5B8" width="32" description="TAGGED TEMPERATURE IVA DOMAIN">
933     <bitfield id="DTEMP_TAG_IVA_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
934     <bitfield id="DTEMP_TEMPERATURE_IVA_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
935   </register>
936   <register id="CTRL_CORE_DTEMP_IVA_3" acronym="CTRL_CORE_DTEMP_IVA_3" offset="0x5BC" width="32" description="TAGGED TEMPERATURE IVA DOMAIN">
937     <bitfield id="DTEMP_TAG_IVA_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
938     <bitfield id="DTEMP_TEMPERATURE_IVA_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
939   </register>
940   <register id="CTRL_CORE_DTEMP_IVA_4" acronym="CTRL_CORE_DTEMP_IVA_4" offset="0x5C0" width="32" description="TAGGED TEMPERATURE IVA DOMAIN. Oldest sample">
941     <bitfield id="DTEMP_TAG_IVA_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
942     <bitfield id="DTEMP_TEMPERATURE_IVA_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
943   </register>
944   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2" offset="0x5CC" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP.">
945     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
946     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
947       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
948       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
949     </bitfield>
950     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
951     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
952     <bitfield id="STD_FUSE_OPP_VMIN_IVA_2" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
953   </register>
954   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3" offset="0x5D0" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP.">
955     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
956     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
957       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
958       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
959     </bitfield>
960     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
961     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
962     <bitfield id="STD_FUSE_OPP_VMIN_IVA_3" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
963   </register>
964   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4" offset="0x5D4" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP.">
965     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
966     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
967       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
968       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
969     </bitfield>
970     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
971     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
972     <bitfield id="STD_FUSE_OPP_VMIN_IVA_4" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
973   </register>
974   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2" offset="0x5E0" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP.">
975     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
976     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
977       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
978       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
979     </bitfield>
980     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
981     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
982     <bitfield id="STD_FUSE_OPP_VMIN_DSPEVE_2" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
983   </register>
984   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3" offset="0x5E4" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP.">
985     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
986     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
987       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
988       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
989     </bitfield>
990     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
991     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
992     <bitfield id="STD_FUSE_OPP_VMIN_DSPEVE_3" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
993   </register>
994   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4" offset="0x5E8" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP.">
995     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
996     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
997       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
998       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
999     </bitfield>
1000     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL[4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
1001     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
1002     <bitfield id="STD_FUSE_OPP_VMIN_DSPEVE_4" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
1003   </register>
1004   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2" offset="0x5F4" width="32" description="This register contains the AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM.">
1005     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
1006     <bitfield id="STD_FUSE_OPP_VMIN_CORE_2" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
1007   </register>
1008   <register id="CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL" offset="0x680" width="32" description="CORE 2nd SRAM LDO Control register">
1009     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
1010     <bitfield id="LDOSRAMCORE_2_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">
1011       <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_2_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>
1012       <bitenum value="1" id="OCP" token="LDOSRAMCORE_2_RETMODE_MUX_CTRL_1" description="Override value is used"/>
1013     </bitfield>
1014     <bitfield id="LDOSRAMCORE_2_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>
1015     <bitfield id="LDOSRAMCORE_2_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>
1016     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
1017     <bitfield id="LDOSRAMCORE_2_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">
1018       <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_2_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>
1019       <bitenum value="1" id="OCP" token="LDOSRAMCORE_2_ACTMODE_MUX_CTRL_1" description="Override value is used"/>
1020     </bitfield>
1021     <bitfield id="LDOSRAMCORE_2_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>
1022     <bitfield id="LDOSRAMCORE_2_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>
1023   </register>
1024   <register id="CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL" offset="0x684" width="32" description="CORE 3rd SRAM LDO Control register">
1025     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
1026     <bitfield id="LDOSRAMCORE_3_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">
1027       <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_3_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>
1028       <bitenum value="1" id="OCP" token="LDOSRAMCORE_3_RETMODE_MUX_CTRL_1" description="Override value is used"/>
1029     </bitfield>
1030     <bitfield id="LDOSRAMCORE_3_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>
1031     <bitfield id="LDOSRAMCORE_3_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>
1032     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
1033     <bitfield id="LDOSRAMCORE_3_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">
1034       <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_3_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>
1035       <bitenum value="1" id="OCP" token="LDOSRAMCORE_3_ACTMODE_MUX_CTRL_1" description="Override value is used"/>
1036     </bitfield>
1037     <bitfield id="LDOSRAMCORE_3_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>
1038     <bitfield id="LDOSRAMCORE_3_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>
1039   </register>
1040   <register id="CTRL_CORE_NMI_DESTINATION_1" acronym="CTRL_CORE_NMI_DESTINATION_1" offset="0x68C" width="32" description="Register for routing NMI interrupt to respective cores">
1041     <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>
1042     <bitfield id="IPU2_C1" width="8" begin="23" end="16" resetval="0x0" description="Enable IPU2 CORE1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
1043     <bitfield id="IPU2_C0" width="8" begin="15" end="8" resetval="0x0" description="Enable IPU2 CORE0 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
1044     <bitfield id="IPU1_C1" width="8" begin="7" end="0" resetval="0x0" description="Enable IPU1 CORE1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
1045   </register>
1046   <register id="CTRL_CORE_NMI_DESTINATION_2" acronym="CTRL_CORE_NMI_DESTINATION_2" offset="0x690" width="32" description="Register for routing NMI interrupt to respective cores">
1047     <bitfield id="IPU1_C0" width="8" begin="31" end="24" resetval="0x0" description="Enable IPU1 CORE0 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
1048     <bitfield id="RESERVED" width="8" begin="23" end="16" resetval="0x0" description="" range="" rwaccess="R"/>
1049     <bitfield id="DSP1" width="8" begin="15" end="8" resetval="0x0" description="Enable DSP1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
1050     <bitfield id="MPU" width="8" begin="7" end="0" resetval="0x0" description="Comes from Efuse (MPU_EN) 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
1051   </register>
1052   <register id="CTRL_CORE_IP_PRESSURE" acronym="CTRL_CORE_IP_PRESSURE" offset="0x698" width="32" description="Register to override the L3 pressure setting for the MLB module">
1053     <bitfield id="RESERVED" width="29" begin="31" end="3" resetval="0x0" description="" range="" rwaccess="R"/>
1054     <bitfield id="MLB_L3_PRESSURE_ENABLE" width="1" begin="2" end="2" resetval="0x0" description="Override enable for the MLB L3 pressure setting 0x0 = Overriding of the L3 pressure setting for the MLB module is disabled 0x1 = Overriding of the L3 pressure setting for the MLB module is enabled" range="" rwaccess="RW"/>
1055     <bitfield id="MLB_L3_PRESSURE" width="2" begin="1" end="0" resetval="0x0" description="MLB L3 pressure setting 0x0 = Lowest 0x3 = Highest" range="" rwaccess="RW"/>
1056   </register>
1057   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0" offset="0x6A0" width="32" description="Standard Fuse OPP VDD_DSPEVE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
1058     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1059   </register>
1060   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1" offset="0x6A4" width="32" description="Standard Fuse OPP VDD_DSPEVE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
1061     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1062   </register>
1063   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2" offset="0x6A8" width="32" description="Standard Fuse OPP VDD_DSPEVE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
1064     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1065   </register>
1066   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3" offset="0x6AC" width="32" description="Standard Fuse OPP VDD_DSPEVE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
1067     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1068   </register>
1069   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4" offset="0x6B0" width="32" description="Standard Fuse OPP VDD_DSPEVE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
1070     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1071   </register>
1072   <register id="CTRL_CORE_CUST_FUSE_SWRV_7" acronym="CTRL_CORE_CUST_FUSE_SWRV_7" offset="0x6B4" width="32" description="Customer Fuse keys. SWRV [31:0] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
1073     <bitfield id="CUST_FUSE_SWRV_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1074   </register>
1075   <register id="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0" acronym="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0" offset="0x6B8" width="32" description="Standard Fuse Calibration override value [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
1076     <bitfield id="STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1077   </register>
1078   <register id="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1" acronym="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1" offset="0x6BC" width="32" description="Standard Fuse Calibration override value [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
1079     <bitfield id="STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1080   </register>
1081   <register id="CTRL_CORE_PCIE_POWER_STATE" acronym="CTRL_CORE_PCIE_POWER_STATE" offset="0x6C0" width="32" description="Register to PCIe related controls">
1082     <bitfield id="BYPASS_EN_APLL_PCIE" width="1" begin="31" end="31" resetval="0x0" description="Bypass enable bit setting for APLL_PCIe" range="" rwaccess="RW"/>
1083     <bitfield id="CLKOOUTEN_APLL_PCIE" width="1" begin="30" end="30" resetval="0x0" description="Clock output enable bit setting for APLL_PCIe" range="" rwaccess="RW"/>
1084     <bitfield id="RESERVED" width="4" begin="29" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
1085     <bitfield id="EFUSE_TRIM_ACS_PCIE" width="10" begin="25" end="16" resetval="0x0" description="MMR override capability for ACS_PCIe efuse trim bits" range="" rwaccess="RW"/>
1086     <bitfield id="EFUSE_TRIM_PCIE_PLL" width="16" begin="15" end="0" resetval="0x0" description="MMR override capability for PCIe PLL efuse trim bits" range="" rwaccess="RW"/>
1087   </register>
1088   <register id="CTRL_CORE_BOOTSTRAP" acronym="CTRL_CORE_BOOTSTRAP" offset="0x6C4" width="32" description="Register to view all the sysboot settings">
1089     <bitfield id="RESERVED" width="16" begin="31" end="16" resetval="0x0" description="" range="" rwaccess="R"/>
1090     <bitfield id="DSP_CLOCK_DIVIDER" width="1" begin="15" end="15" resetval="0x0" description="SR1.x Only: Divide factor for DSP clock SR2.x Only: Permanently disables the internal PU/PD resistors on pads gpmc_a[27:24, 22:19]. 0x0: Internal pull-down resistors are enabled 0x1: Internal pull-down resistors are permanently disabled" range="" rwaccess="R"/>
1091     <bitfield id="RESERVED" width="1" begin="14" end="14" resetval="0x0" description="For proper device operation, a value of 0 is required on sysboot14" range="" rwaccess="R"/>
1092     <bitfield id="BOOTDEVICESIZE" width="1" begin="13" end="13" resetval="0x0" description="Select the size of the flash device on CS0. 0x0: 8-bit 0x1: 16-bit" range="" rwaccess="R"/>
1093     <bitfield id="MUXCS0DEVICE" width="2" begin="12" end="11" resetval="0x0" description="Select IC boot sequence to be executed from a multiplexed address and data device attached to CS0. 0x0: Non-muxed device attached 0x1: Addr-Data Mux device attached 0x2: Reserved 0x3: Reserved" range="" rwaccess="R"/>
1094     <bitfield id="BOOTWAITEN" width="1" begin="10" end="10" resetval="0x0" description="Enable the monitoring on CS0 of the wait pin at IC reset release time for read accesses. 0x0: Wait pin is not monitored for read accesses 0x1: Wait pin is monitored for read accesses" range="" rwaccess="R"/>
1095     <bitfield id="SPEEDSELECT" width="2" begin="9" end="8" resetval="0x0" description="Indicates the SYS_CLK1 frequency (from osc0). Note that the internal FUNC_32K_CLK is equal to SYS_CLK1/610, which is nominally 32.7869 kHz with 20 MHz clock. 0x0: Reserved 0x1: 20 MHz 0x2: 27 MHz 0x3: 19.2 MHz" range="" rwaccess="R"/>
1096     <bitfield id="SYSBOOT_76" width="2" begin="7" end="6" resetval="0x0" description="Sector offset for the location of the redundant SBL images in QSPI. 0x0: 64 KB offset 0x1: 128 KB offset 0x2: 256 KB offset 0x3: 512 KB offset" range="" rwaccess="R"/>
1097     <bitfield id="BOOTMODE" width="6" begin="5" end="0" resetval="0x0" description="SYSBOOT mode" range="" rwaccess="R"/>
1098   </register>
1099   <register id="CTRL_CORE_MLB_SIG_IO_CTRL" acronym="CTRL_CORE_MLB_SIG_IO_CTRL" offset="0x6C8" width="32" description="Register to set the MLB's SIG IO characteristics">
1100     <bitfield id="RESERVED" width="9" begin="31" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
1101     <bitfield id="SIG_RX_TRIM_EN" width="1" begin="22" end="22" resetval="0x0" description="0x0: Trimming is disabled 0x1: Trimming is enabled" range="" rwaccess="RW"/>
1102     <bitfield id="SIG_NC_IN" width="6" begin="21" end="16" resetval="0x0" description="efuse trim for Nmos impedance" range="" rwaccess="RW"/>
1103     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
1104     <bitfield id="SIG_PC_IN" width="6" begin="13" end="8" resetval="0x0" description="efuse trim for Pmos impedance" range="" rwaccess="RW"/>
1105     <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
1106     <bitfield id="SIG_REMOVE_SKEW" width="1" begin="6" end="6" resetval="0x0" description="Adjust for skew generated by the receiver due to asymmetric inputs. 0x0: skew compensation is disabled 0x1: skew compensation is enabled" range="" rwaccess="RW"/>
1107     <bitfield id="SIG_PWRDNRX" width="1" begin="5" end="5" resetval="0x1" description="powerdown receiver, active high 0x0 = Powered ON 0x1 = Powered OFF" range="" rwaccess="RW"/>
1108     <bitfield id="SIG_PWRDNTX" width="1" begin="4" end="4" resetval="0x1" description="powerdown transmitter, active high 0x0 = Powered ON 0x1 = Powered OFF" range="" rwaccess="RW"/>
1109     <bitfield id="SIG_EN_EXT_RES" width="1" begin="3" end="3" resetval="0x0" description="disables internal resistors 0x0 = Disabled 0x1 = Enabled" range="" rwaccess="RW"/>
1110     <bitfield id="RESERVED" width="3" begin="2" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1111   </register>
1112   <register id="CTRL_CORE_MLB_DAT_IO_CTRL" acronym="CTRL_CORE_MLB_DAT_IO_CTRL" offset="0x6CC" width="32" description="Register to set the MLB's DAT IO characteristics">
1113     <bitfield id="RESERVED" width="9" begin="31" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
1114     <bitfield id="DAT_RX_TRIM_EN" width="1" begin="22" end="22" resetval="0x0" description="0x0: Trimming is disabled 0x1: Trimming is enabled" range="" rwaccess="RW"/>
1115     <bitfield id="DAT_NC_IN" width="6" begin="21" end="16" resetval="0x0" description="efuse trim for Nmos impedance" range="" rwaccess="RW"/>
1116     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
1117     <bitfield id="DAT_PC_IN" width="6" begin="13" end="8" resetval="0x0" description="efuse trim for Pmos impedance" range="" rwaccess="RW"/>
1118     <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
1119     <bitfield id="DAT_REMOVE_SKEW" width="1" begin="6" end="6" resetval="0x0" description="Adjust for skew generated by the receiver due to asymmetric inputs. 0x0: skew compensation is disabled 0x1: skew compensation is enabled" range="" rwaccess="RW"/>
1120     <bitfield id="DAT_PWRDNRX" width="1" begin="5" end="5" resetval="0x1" description="powerdown receiver, active high 0x0: Powered ON 0x1: Powered OFF" range="" rwaccess="RW"/>
1121     <bitfield id="DAT_PWRDNTX" width="1" begin="4" end="4" resetval="0x1" description="powerdown transmitter, active high 0x0: Powered ON 0x1: Powered OFF" range="" rwaccess="RW"/>
1122     <bitfield id="DAT_EN_EXT_RES" width="1" begin="3" end="3" resetval="0x0" description="Enable/disable internal resistors 0x0: Disabled 0x1: Enabled" range="" rwaccess="RW"/>
1123     <bitfield id="RESERVED" width="3" begin="2" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
1124   </register>
1125   <register id="CTRL_CORE_MLB_CLK_BG_CTRL" acronym="CTRL_CORE_MLB_CLK_BG_CTRL" offset="0x6D0" width="32" description="Register to set the MLB's clock receiver IO and bandgap characteristics">
1126     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1127     <bitfield id="RX_TRIM_EN" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW"/>
1128     <bitfield id="CLK_REMOVE_SKEW" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="RW"/>
1129     <bitfield id="CLK_PWRDNRX" width="1" begin="22" end="22" resetval="0x1" description="" range="" rwaccess="RW"/>
1130     <bitfield id="RESERVED" width="5" begin="21" end="17" resetval="0x0" description="" range="" rwaccess="R"/>
1131     <bitfield id="T_HYSTERISIS_EN" width="1" begin="16" end="16" resetval="0x0" description="Hysterisis enable 0x0 = Disabled 0x1 = Enabled" range="" rwaccess="RW"/>
1132     <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
1133     <bitfield id="BG_TRIM" width="6" begin="7" end="2" resetval="0x0" description="Trim values for MLB bandgap" range="" rwaccess="RW"/>
1134     <bitfield id="BG_PWRDN" width="1" begin="1" end="1" resetval="0x0" description="MLB bandgap cell enable. 0x0 = The MLB bandgap cell is powered (enabled) 0x1 = The MLB bandgap cell is disabled" range="" rwaccess="RW"/>
1135     <bitfield id="CLK_PWRDN" width="1" begin="0" end="0" resetval="0x1" description="Enable the MLB differential clock receiver. 0x0 = MLB differential clock receiver is enabled 0x1 = MLB differential clock receiver is disabled" range="" rwaccess="RW"/>
1136   </register>
1137   <register id="CTRL_CORE_CAL_REG" acronym="CTRL_CORE_CAL_REG" offset="0x794" width="32" description="">
1138     <bitfield id="RESERVED" width="28" begin="31" end="4" resetval="0x0" description="" range="" rwaccess="R"/>
1139     <bitfield id="CAL_PRIORITY" width="3" begin="3" end="1" resetval="0x0" description="CAL priority setting when accessing the EMIF. 0x0: Highest priority 0x7: Lowest priority" range="" rwaccess="RW"/>
1140     <bitfield id="CAL_TILED_MEMORY_SPACE" width="1" begin="0" end="0" resetval="0x0" description="This is the 33rd address bit on the L3_MAIN associated with CAL. This bit controls whether CAL performs an access to Q0-Q3 address range or to TILER_VIEW address range. 0x0: The lower 4GiB address space (Q0-Q3) is accessed. 0x1: The address space associated with the 8 TILER views is accessed." range="" rwaccess="RW"/>
1141   </register>
1142   <register id="CTRL_CORE_MLB_DLL" acronym="CTRL_CORE_MLB_DLL" offset="0x798" width="32" description="">
1143     <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
1144     <bitfield id="DLL_CLOCK_DISABLE" width="1" begin="10" end="10" resetval="0x0" description="0x0: MDLL reference clock is enabled 0x1: MDLL reference clock is disabled" range="" rwaccess="RW"/>
1145     <bitfield id="DLL_LOCK" width="1" begin="9" end="9" resetval="0x0" description="Value of 0x1 indicates that the MDLL has locked to its reference clock. This bit remains high till MDLL reset occurs." range="" rwaccess="RW"/>
1146     <bitfield id="SDL_LOCK" width="1" begin="8" end="8" resetval="0x0" description="Value of 0x1 indicates that the SDL has been updated with a code. This bit remains high till the SDL reset occurs." range="" rwaccess="RW"/>
1147     <bitfield id="DLL_RATIO" width="8" begin="7" end="0" resetval="0x0" description="The value which has to be loaded in this bit field is calculated based on the equation DLL_RATIO = (2,5/MP)*256, where MP is the MDLL clock period measured in ns." range="" rwaccess="RW"/>
1148   </register>
1149   <register id="CTRL_CORE_MLB_CLK" acronym="CTRL_CORE_MLB_CLK" offset="0x79C" width="32" description="">
1150     <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
1151     <bitfield id="CLK_SEL_MLB" width="1" begin="0" end="0" resetval="0x0" description="0x0: The frequency of the MLB clock line is not doubled (100MHz clock is used) 0x1: The frequency of the MLB clock line is doubled (200MHz clock is used)" range="" rwaccess="RW"/>
1152   </register>
1153   <register id="CTRL_CORE_IPU1_IRQ_23_24" acronym="CTRL_CORE_IPU1_IRQ_23_24" offset="0x7E0" width="32" description="">
1154     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1155     <bitfield id="IPU1_IRQ_24" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>
1156     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1157     <bitfield id="IPU1_IRQ_23" width="9" begin="8" end="0" resetval="0x14" description="" range="" rwaccess="RW"/>
1158   </register>
1159   <register id="CTRL_CORE_IPU1_IRQ_25_26" acronym="CTRL_CORE_IPU1_IRQ_25_26" offset="0x7E4" width="32" description="">
1160     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1161     <bitfield id="IPU1_IRQ_26" width="9" begin="24" end="16" resetval="0x60" description="" range="" rwaccess="RW"/>
1162     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1163     <bitfield id="IPU1_IRQ_25" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
1164   </register>
1165   <register id="CTRL_CORE_IPU1_IRQ_27_28" acronym="CTRL_CORE_IPU1_IRQ_27_28" offset="0x7E8" width="32" description="">
1166     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1167     <bitfield id="IPU1_IRQ_28" width="9" begin="24" end="16" resetval="0x7F" description="" range="" rwaccess="RW"/>
1168     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1169     <bitfield id="IPU1_IRQ_27" width="9" begin="8" end="0" resetval="0x7E" description="" range="" rwaccess="RW"/>
1170   </register>
1171   <register id="CTRL_CORE_IPU1_IRQ_29_30" acronym="CTRL_CORE_IPU1_IRQ_29_30" offset="0x7EC" width="32" description="">
1172     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1173     <bitfield id="IPU1_IRQ_30" width="9" begin="24" end="16" resetval="0x81" description="" range="" rwaccess="RW"/>
1174     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1175     <bitfield id="IPU1_IRQ_29" width="9" begin="8" end="0" resetval="0x80" description="" range="" rwaccess="RW"/>
1176   </register>
1177   <register id="CTRL_CORE_IPU1_IRQ_31_32" acronym="CTRL_CORE_IPU1_IRQ_31_32" offset="0x7F0" width="32" description="">
1178     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1179     <bitfield id="IPU1_IRQ_32" width="9" begin="24" end="16" resetval="0x13" description="" range="" rwaccess="RW"/>
1180     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1181     <bitfield id="IPU1_IRQ_31" width="9" begin="8" end="0" resetval="0x82" description="" range="" rwaccess="RW"/>
1182   </register>
1183   <register id="CTRL_CORE_IPU1_IRQ_33_34" acronym="CTRL_CORE_IPU1_IRQ_33_34" offset="0x7F4" width="32" description="">
1184     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1185     <bitfield id="IPU1_IRQ_34" width="9" begin="24" end="16" resetval="0x7" description="" range="" rwaccess="RW"/>
1186     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1187     <bitfield id="IPU1_IRQ_33" width="9" begin="8" end="0" resetval="0x83" description="" range="" rwaccess="RW"/>
1188   </register>
1189   <register id="CTRL_CORE_IPU1_IRQ_35_36" acronym="CTRL_CORE_IPU1_IRQ_35_36" offset="0x7F8" width="32" description="">
1190     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1191     <bitfield id="IPU1_IRQ_36" width="9" begin="24" end="16" resetval="0x9" description="" range="" rwaccess="RW"/>
1192     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1193     <bitfield id="IPU1_IRQ_35" width="9" begin="8" end="0" resetval="0x8" description="" range="" rwaccess="RW"/>
1194   </register>
1195   <register id="CTRL_CORE_IPU1_IRQ_37_38" acronym="CTRL_CORE_IPU1_IRQ_37_38" offset="0x7FC" width="32" description="">
1196     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1197     <bitfield id="IPU1_IRQ_38" width="9" begin="24" end="16" resetval="0x84" description="" range="" rwaccess="RW"/>
1198     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1199     <bitfield id="IPU1_IRQ_37" width="9" begin="8" end="0" resetval="0xA" description="" range="" rwaccess="RW"/>
1200   </register>
1201   <register id="CTRL_CORE_IPU1_IRQ_39_40" acronym="CTRL_CORE_IPU1_IRQ_39_40" offset="0x800" width="32" description="">
1202     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1203     <bitfield id="IPU1_IRQ_40" width="9" begin="24" end="16" resetval="0x63" description="" range="" rwaccess="RW"/>
1204     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1205     <bitfield id="IPU1_IRQ_39" width="9" begin="8" end="0" resetval="0x62" description="" range="" rwaccess="RW"/>
1206   </register>
1207   <register id="CTRL_CORE_IPU1_IRQ_41_42" acronym="CTRL_CORE_IPU1_IRQ_41_42" offset="0x804" width="32" description="">
1208     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1209     <bitfield id="IPU1_IRQ_42" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>
1210     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1211     <bitfield id="IPU1_IRQ_41" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>
1212   </register>
1213   <register id="CTRL_CORE_IPU1_IRQ_43_44" acronym="CTRL_CORE_IPU1_IRQ_43_44" offset="0x808" width="32" description="">
1214     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1215     <bitfield id="IPU1_IRQ_44" width="9" begin="24" end="16" resetval="0x39" description="" range="" rwaccess="RW"/>
1216     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1217     <bitfield id="IPU1_IRQ_43" width="9" begin="8" end="0" resetval="0x38" description="" range="" rwaccess="RW"/>
1218   </register>
1219   <register id="CTRL_CORE_IPU1_IRQ_45_46" acronym="CTRL_CORE_IPU1_IRQ_45_46" offset="0x80C" width="32" description="">
1220     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1221     <bitfield id="IPU1_IRQ_46" width="9" begin="24" end="16" resetval="0x5" description="" range="" rwaccess="RW"/>
1222     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1223     <bitfield id="IPU1_IRQ_45" width="9" begin="8" end="0" resetval="0x45" description="" range="" rwaccess="RW"/>
1224   </register>
1225   <register id="CTRL_CORE_IPU1_IRQ_47_48" acronym="CTRL_CORE_IPU1_IRQ_47_48" offset="0x810" width="32" description="">
1226     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1227     <bitfield id="IPU1_IRQ_48" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
1228     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1229     <bitfield id="IPU1_IRQ_47" width="9" begin="8" end="0" resetval="0x85" description="" range="" rwaccess="RW"/>
1230   </register>
1231   <register id="CTRL_CORE_IPU1_IRQ_49_50" acronym="CTRL_CORE_IPU1_IRQ_49_50" offset="0x814" width="32" description="">
1232     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1233     <bitfield id="IPU1_IRQ_50" width="9" begin="24" end="16" resetval="0x86" description="" range="" rwaccess="RW"/>
1234     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1235     <bitfield id="IPU1_IRQ_49" width="9" begin="8" end="0" resetval="0x42" description="" range="" rwaccess="RW"/>
1236   </register>
1237   <register id="CTRL_CORE_IPU1_IRQ_51_52" acronym="CTRL_CORE_IPU1_IRQ_51_52" offset="0x818" width="32" description="">
1238     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1239     <bitfield id="IPU1_IRQ_52" width="9" begin="24" end="16" resetval="0x19" description="" range="" rwaccess="RW"/>
1240     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1241     <bitfield id="IPU1_IRQ_51" width="9" begin="8" end="0" resetval="0x18" description="" range="" rwaccess="RW"/>
1242   </register>
1243   <register id="CTRL_CORE_IPU1_IRQ_53_54" acronym="CTRL_CORE_IPU1_IRQ_53_54" offset="0x81C" width="32" description="">
1244     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1245     <bitfield id="IPU1_IRQ_54" width="9" begin="24" end="16" resetval="0x23" description="" range="" rwaccess="RW"/>
1246     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1247     <bitfield id="IPU1_IRQ_53" width="9" begin="8" end="0" resetval="0x22" description="" range="" rwaccess="RW"/>
1248   </register>
1249   <register id="CTRL_CORE_IPU1_IRQ_55_56" acronym="CTRL_CORE_IPU1_IRQ_55_56" offset="0x820" width="32" description="">
1250     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1251     <bitfield id="IPU1_IRQ_56" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>
1252     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1253     <bitfield id="IPU1_IRQ_55" width="9" begin="8" end="0" resetval="0x28" description="" range="" rwaccess="RW"/>
1254   </register>
1255   <register id="CTRL_CORE_IPU1_IRQ_57_58" acronym="CTRL_CORE_IPU1_IRQ_57_58" offset="0x824" width="32" description="">
1256     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1257     <bitfield id="IPU1_IRQ_58" width="9" begin="24" end="16" resetval="0x3D" description="" range="" rwaccess="RW"/>
1258     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1259     <bitfield id="IPU1_IRQ_57" width="9" begin="8" end="0" resetval="0x3C" description="" range="" rwaccess="RW"/>
1260   </register>
1261   <register id="CTRL_CORE_IPU1_IRQ_59_60" acronym="CTRL_CORE_IPU1_IRQ_59_60" offset="0x828" width="32" description="">
1262     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1263     <bitfield id="IPU1_IRQ_60" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
1264     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1265     <bitfield id="IPU1_IRQ_59" width="9" begin="8" end="0" resetval="0x32" description="" range="" rwaccess="RW"/>
1266   </register>
1267   <register id="CTRL_CORE_IPU1_IRQ_61_62" acronym="CTRL_CORE_IPU1_IRQ_61_62" offset="0x82C" width="32" description="">
1268     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1269     <bitfield id="IPU1_IRQ_62" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
1270     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1271     <bitfield id="IPU1_IRQ_61" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
1272   </register>
1273   <register id="CTRL_CORE_IPU1_IRQ_63_64" acronym="CTRL_CORE_IPU1_IRQ_63_64" offset="0x830" width="32" description="">
1274     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1275     <bitfield id="IPU1_IRQ_64" width="9" begin="24" end="16" resetval="0x6C" description="" range="" rwaccess="RW"/>
1276     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1277     <bitfield id="IPU1_IRQ_63" width="9" begin="8" end="0" resetval="0x53" description="" range="" rwaccess="RW"/>
1278   </register>
1279   <register id="CTRL_CORE_IPU1_IRQ_65_66" acronym="CTRL_CORE_IPU1_IRQ_65_66" offset="0x834" width="32" description="">
1280     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1281     <bitfield id="IPU1_IRQ_66" width="9" begin="24" end="16" resetval="0x4E" description="" range="" rwaccess="RW"/>
1282     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1283     <bitfield id="IPU1_IRQ_65" width="9" begin="8" end="0" resetval="0x78" description="" range="" rwaccess="RW"/>
1284   </register>
1285   <register id="CTRL_CORE_IPU1_IRQ_67_68" acronym="CTRL_CORE_IPU1_IRQ_67_68" offset="0x838" width="32" description="">
1286     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1287     <bitfield id="IPU1_IRQ_68" width="9" begin="24" end="16" resetval="0x59" description="" range="" rwaccess="RW"/>
1288     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1289     <bitfield id="IPU1_IRQ_67" width="9" begin="8" end="0" resetval="0x51" description="" range="" rwaccess="RW"/>
1290   </register>
1291   <register id="CTRL_CORE_IPU1_IRQ_69_70" acronym="CTRL_CORE_IPU1_IRQ_69_70" offset="0x83C" width="32" description="">
1292     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1293     <bitfield id="IPU1_IRQ_70" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
1294     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1295     <bitfield id="IPU1_IRQ_69" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
1296   </register>
1297   <register id="CTRL_CORE_IPU1_IRQ_71_72" acronym="CTRL_CORE_IPU1_IRQ_71_72" offset="0x840" width="32" description="">
1298     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1299     <bitfield id="IPU1_IRQ_72" width="9" begin="24" end="16" resetval="0x76" description="" range="" rwaccess="RW"/>
1300     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1301     <bitfield id="IPU1_IRQ_71" width="9" begin="8" end="0" resetval="0x77" description="" range="" rwaccess="RW"/>
1302   </register>
1303   <register id="CTRL_CORE_IPU1_IRQ_73_74" acronym="CTRL_CORE_IPU1_IRQ_73_74" offset="0x844" width="32" description="">
1304     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1305     <bitfield id="IPU1_IRQ_74" width="9" begin="24" end="16" resetval="0x49" description="" range="" rwaccess="RW"/>
1306     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1307     <bitfield id="IPU1_IRQ_73" width="9" begin="8" end="0" resetval="0x48" description="" range="" rwaccess="RW"/>
1308   </register>
1309   <register id="CTRL_CORE_IPU1_IRQ_75_76" acronym="CTRL_CORE_IPU1_IRQ_75_76" offset="0x848" width="32" description="">
1310     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1311     <bitfield id="IPU1_IRQ_76" width="9" begin="24" end="16" resetval="0x57" description="" range="" rwaccess="RW"/>
1312     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1313     <bitfield id="IPU1_IRQ_75" width="9" begin="8" end="0" resetval="0x75" description="" range="" rwaccess="RW"/>
1314   </register>
1315   <register id="CTRL_CORE_IPU1_IRQ_77_78" acronym="CTRL_CORE_IPU1_IRQ_77_78" offset="0x84C" width="32" description="">
1316     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1317     <bitfield id="IPU1_IRQ_78" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>
1318     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1319     <bitfield id="IPU1_IRQ_77" width="9" begin="8" end="0" resetval="0x58" description="" range="" rwaccess="RW"/>
1320   </register>
1321   <register id="CTRL_CORE_IPU1_IRQ_79_80" acronym="CTRL_CORE_IPU1_IRQ_79_80" offset="0x850" width="32" description="">
1322     <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1323     <bitfield id="IPU1_IRQ_79" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>
1324   </register>
1325   <register id="CTRL_CORE_IPU2_IRQ_23_24" acronym="CTRL_CORE_IPU2_IRQ_23_24" offset="0x854" width="32" description="">
1326     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1327     <bitfield id="IPU2_IRQ_24" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>
1328     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1329     <bitfield id="IPU2_IRQ_23" width="9" begin="8" end="0" resetval="0x14" description="" range="" rwaccess="RW"/>
1330   </register>
1331   <register id="CTRL_CORE_IPU2_IRQ_25_26" acronym="CTRL_CORE_IPU2_IRQ_25_26" offset="0x858" width="32" description="">
1332     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1333     <bitfield id="IPU2_IRQ_26" width="9" begin="24" end="16" resetval="0x60" description="" range="" rwaccess="RW"/>
1334     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1335     <bitfield id="IPU2_IRQ_25" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
1336   </register>
1337   <register id="CTRL_CORE_IPU2_IRQ_27_28" acronym="CTRL_CORE_IPU2_IRQ_27_28" offset="0x85C" width="32" description="">
1338     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1339     <bitfield id="IPU2_IRQ_28" width="9" begin="24" end="16" resetval="0x7F" description="" range="" rwaccess="RW"/>
1340     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1341     <bitfield id="IPU2_IRQ_27" width="9" begin="8" end="0" resetval="0x7E" description="" range="" rwaccess="RW"/>
1342   </register>
1343   <register id="CTRL_CORE_IPU2_IRQ_29_30" acronym="CTRL_CORE_IPU2_IRQ_29_30" offset="0x860" width="32" description="">
1344     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1345     <bitfield id="IPU2_IRQ_30" width="9" begin="24" end="16" resetval="0x81" description="" range="" rwaccess="RW"/>
1346     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1347     <bitfield id="IPU2_IRQ_29" width="9" begin="8" end="0" resetval="0x80" description="" range="" rwaccess="RW"/>
1348   </register>
1349   <register id="CTRL_CORE_IPU2_IRQ_31_32" acronym="CTRL_CORE_IPU2_IRQ_31_32" offset="0x864" width="32" description="">
1350     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1351     <bitfield id="IPU2_IRQ_32" width="9" begin="24" end="16" resetval="0x13" description="" range="" rwaccess="RW"/>
1352     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1353     <bitfield id="IPU2_IRQ_31" width="9" begin="8" end="0" resetval="0x82" description="" range="" rwaccess="RW"/>
1354   </register>
1355   <register id="CTRL_CORE_IPU2_IRQ_33_34" acronym="CTRL_CORE_IPU2_IRQ_33_34" offset="0x868" width="32" description="">
1356     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1357     <bitfield id="IPU2_IRQ_34" width="9" begin="24" end="16" resetval="0x7" description="" range="" rwaccess="RW"/>
1358     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1359     <bitfield id="IPU2_IRQ_33" width="9" begin="8" end="0" resetval="0x83" description="" range="" rwaccess="RW"/>
1360   </register>
1361   <register id="CTRL_CORE_IPU2_IRQ_35_36" acronym="CTRL_CORE_IPU2_IRQ_35_36" offset="0x86C" width="32" description="">
1362     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1363     <bitfield id="IPU2_IRQ_36" width="9" begin="24" end="16" resetval="0x9" description="" range="" rwaccess="RW"/>
1364     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1365     <bitfield id="IPU2_IRQ_35" width="9" begin="8" end="0" resetval="0x8" description="" range="" rwaccess="RW"/>
1366   </register>
1367   <register id="CTRL_CORE_IPU2_IRQ_37_38" acronym="CTRL_CORE_IPU2_IRQ_37_38" offset="0x870" width="32" description="">
1368     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1369     <bitfield id="IPU2_IRQ_38" width="9" begin="24" end="16" resetval="0x84" description="" range="" rwaccess="RW"/>
1370     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1371     <bitfield id="IPU2_IRQ_37" width="9" begin="8" end="0" resetval="0xA" description="" range="" rwaccess="RW"/>
1372   </register>
1373   <register id="CTRL_CORE_IPU2_IRQ_39_40" acronym="CTRL_CORE_IPU2_IRQ_39_40" offset="0x874" width="32" description="">
1374     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1375     <bitfield id="IPU2_IRQ_40" width="9" begin="24" end="16" resetval="0x63" description="" range="" rwaccess="RW"/>
1376     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1377     <bitfield id="IPU2_IRQ_39" width="9" begin="8" end="0" resetval="0x62" description="" range="" rwaccess="RW"/>
1378   </register>
1379   <register id="CTRL_CORE_IPU2_IRQ_41_42" acronym="CTRL_CORE_IPU2_IRQ_41_42" offset="0x878" width="32" description="">
1380     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1381     <bitfield id="IPU2_IRQ_42" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>
1382     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1383     <bitfield id="IPU2_IRQ_41" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>
1384   </register>
1385   <register id="CTRL_CORE_IPU2_IRQ_43_44" acronym="CTRL_CORE_IPU2_IRQ_43_44" offset="0x87C" width="32" description="">
1386     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1387     <bitfield id="IPU2_IRQ_44" width="9" begin="24" end="16" resetval="0x39" description="" range="" rwaccess="RW"/>
1388     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1389     <bitfield id="IPU2_IRQ_43" width="9" begin="8" end="0" resetval="0x38" description="" range="" rwaccess="RW"/>
1390   </register>
1391   <register id="CTRL_CORE_IPU2_IRQ_45_46" acronym="CTRL_CORE_IPU2_IRQ_45_46" offset="0x880" width="32" description="">
1392     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1393     <bitfield id="IPU2_IRQ_46" width="9" begin="24" end="16" resetval="0x5" description="" range="" rwaccess="RW"/>
1394     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1395     <bitfield id="IPU2_IRQ_45" width="9" begin="8" end="0" resetval="0x45" description="" range="" rwaccess="RW"/>
1396   </register>
1397   <register id="CTRL_CORE_IPU2_IRQ_47_48" acronym="CTRL_CORE_IPU2_IRQ_47_48" offset="0x884" width="32" description="">
1398     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1399     <bitfield id="IPU2_IRQ_48" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
1400     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1401     <bitfield id="IPU2_IRQ_47" width="9" begin="8" end="0" resetval="0x85" description="" range="" rwaccess="RW"/>
1402   </register>
1403   <register id="CTRL_CORE_IPU2_IRQ_49_50" acronym="CTRL_CORE_IPU2_IRQ_49_50" offset="0x888" width="32" description="">
1404     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1405     <bitfield id="IPU2_IRQ_50" width="9" begin="24" end="16" resetval="0x86" description="" range="" rwaccess="RW"/>
1406     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1407     <bitfield id="IPU2_IRQ_49" width="9" begin="8" end="0" resetval="0x42" description="" range="" rwaccess="RW"/>
1408   </register>
1409   <register id="CTRL_CORE_IPU2_IRQ_51_52" acronym="CTRL_CORE_IPU2_IRQ_51_52" offset="0x88C" width="32" description="">
1410     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1411     <bitfield id="IPU2_IRQ_52" width="9" begin="24" end="16" resetval="0x19" description="" range="" rwaccess="RW"/>
1412     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1413     <bitfield id="IPU2_IRQ_51" width="9" begin="8" end="0" resetval="0x18" description="" range="" rwaccess="RW"/>
1414   </register>
1415   <register id="CTRL_CORE_IPU2_IRQ_53_54" acronym="CTRL_CORE_IPU2_IRQ_53_54" offset="0x890" width="32" description="">
1416     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1417     <bitfield id="IPU2_IRQ_54" width="9" begin="24" end="16" resetval="0x23" description="" range="" rwaccess="RW"/>
1418     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1419     <bitfield id="IPU2_IRQ_53" width="9" begin="8" end="0" resetval="0x22" description="" range="" rwaccess="RW"/>
1420   </register>
1421   <register id="CTRL_CORE_IPU2_IRQ_55_56" acronym="CTRL_CORE_IPU2_IRQ_55_56" offset="0x894" width="32" description="">
1422     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1423     <bitfield id="IPU2_IRQ_56" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>
1424     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1425     <bitfield id="IPU2_IRQ_55" width="9" begin="8" end="0" resetval="0x28" description="" range="" rwaccess="RW"/>
1426   </register>
1427   <register id="CTRL_CORE_IPU2_IRQ_57_58" acronym="CTRL_CORE_IPU2_IRQ_57_58" offset="0x898" width="32" description="">
1428     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1429     <bitfield id="IPU2_IRQ_58" width="9" begin="24" end="16" resetval="0x3D" description="" range="" rwaccess="RW"/>
1430     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1431     <bitfield id="IPU2_IRQ_57" width="9" begin="8" end="0" resetval="0x3C" description="" range="" rwaccess="RW"/>
1432   </register>
1433   <register id="CTRL_CORE_IPU2_IRQ_59_60" acronym="CTRL_CORE_IPU2_IRQ_59_60" offset="0x89C" width="32" description="">
1434     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1435     <bitfield id="IPU2_IRQ_60" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
1436     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1437     <bitfield id="IPU2_IRQ_59" width="9" begin="8" end="0" resetval="0x32" description="" range="" rwaccess="RW"/>
1438   </register>
1439   <register id="CTRL_CORE_IPU2_IRQ_61_62" acronym="CTRL_CORE_IPU2_IRQ_61_62" offset="0x8A0" width="32" description="">
1440     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1441     <bitfield id="IPU2_IRQ_62" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
1442     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1443     <bitfield id="IPU2_IRQ_61" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
1444   </register>
1445   <register id="CTRL_CORE_IPU2_IRQ_63_64" acronym="CTRL_CORE_IPU2_IRQ_63_64" offset="0x8A4" width="32" description="">
1446     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1447     <bitfield id="IPU2_IRQ_64" width="9" begin="24" end="16" resetval="0x6C" description="" range="" rwaccess="RW"/>
1448     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1449     <bitfield id="IPU2_IRQ_63" width="9" begin="8" end="0" resetval="0x53" description="" range="" rwaccess="RW"/>
1450   </register>
1451   <register id="CTRL_CORE_IPU2_IRQ_65_66" acronym="CTRL_CORE_IPU2_IRQ_65_66" offset="0x8A8" width="32" description="">
1452     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1453     <bitfield id="IPU2_IRQ_66" width="9" begin="24" end="16" resetval="0x4E" description="" range="" rwaccess="RW"/>
1454     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1455     <bitfield id="IPU2_IRQ_65" width="9" begin="8" end="0" resetval="0x78" description="" range="" rwaccess="RW"/>
1456   </register>
1457   <register id="CTRL_CORE_IPU2_IRQ_67_68" acronym="CTRL_CORE_IPU2_IRQ_67_68" offset="0x8AC" width="32" description="">
1458     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1459     <bitfield id="IPU2_IRQ_68" width="9" begin="24" end="16" resetval="0x59" description="" range="" rwaccess="RW"/>
1460     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1461     <bitfield id="IPU2_IRQ_67" width="9" begin="8" end="0" resetval="0x51" description="" range="" rwaccess="RW"/>
1462   </register>
1463   <register id="CTRL_CORE_IPU2_IRQ_69_70" acronym="CTRL_CORE_IPU2_IRQ_69_70" offset="0x8B0" width="32" description="">
1464     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1465     <bitfield id="IPU2_IRQ_70" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
1466     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1467     <bitfield id="IPU2_IRQ_69" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
1468   </register>
1469   <register id="CTRL_CORE_IPU2_IRQ_71_72" acronym="CTRL_CORE_IPU2_IRQ_71_72" offset="0x8B4" width="32" description="">
1470     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1471     <bitfield id="IPU2_IRQ_72" width="9" begin="24" end="16" resetval="0x76" description="" range="" rwaccess="RW"/>
1472     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1473     <bitfield id="IPU2_IRQ_71" width="9" begin="8" end="0" resetval="0x77" description="" range="" rwaccess="RW"/>
1474   </register>
1475   <register id="CTRL_CORE_IPU2_IRQ_73_74" acronym="CTRL_CORE_IPU2_IRQ_73_74" offset="0x8B8" width="32" description="">
1476     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1477     <bitfield id="IPU2_IRQ_74" width="9" begin="24" end="16" resetval="0x49" description="" range="" rwaccess="RW"/>
1478     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1479     <bitfield id="IPU2_IRQ_73" width="9" begin="8" end="0" resetval="0x48" description="" range="" rwaccess="RW"/>
1480   </register>
1481   <register id="CTRL_CORE_IPU2_IRQ_75_76" acronym="CTRL_CORE_IPU2_IRQ_75_76" offset="0x8BC" width="32" description="">
1482     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1483     <bitfield id="IPU2_IRQ_76" width="9" begin="24" end="16" resetval="0x57" description="" range="" rwaccess="RW"/>
1484     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1485     <bitfield id="IPU2_IRQ_75" width="9" begin="8" end="0" resetval="0x75" description="" range="" rwaccess="RW"/>
1486   </register>
1487   <register id="CTRL_CORE_IPU2_IRQ_77_78" acronym="CTRL_CORE_IPU2_IRQ_77_78" offset="0x8C0" width="32" description="">
1488     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1489     <bitfield id="IPU2_IRQ_78" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>
1490     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1491     <bitfield id="IPU2_IRQ_77" width="9" begin="8" end="0" resetval="0x58" description="" range="" rwaccess="RW"/>
1492   </register>
1493   <register id="CTRL_CORE_IPU2_IRQ_79_80" acronym="CTRL_CORE_IPU2_IRQ_79_80" offset="0x8C4" width="32" description="">
1494     <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1495     <bitfield id="IPU2_IRQ_79" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>
1496   </register>
1497   <register id="CTRL_CORE_PRUSS1_IRQ_32_33" acronym="CTRL_CORE_PRUSS1_IRQ_32_33" offset="0x8C8" width="32" description="">
1498     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1499     <bitfield id="PRUSS1_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
1500     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1501     <bitfield id="PRUSS1_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
1502   </register>
1503   <register id="CTRL_CORE_PRUSS1_IRQ_34_35" acronym="CTRL_CORE_PRUSS1_IRQ_34_35" offset="0x8CC" width="32" description="">
1504     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1505     <bitfield id="PRUSS1_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
1506     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1507     <bitfield id="PRUSS1_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
1508   </register>
1509   <register id="CTRL_CORE_PRUSS1_IRQ_36_37" acronym="CTRL_CORE_PRUSS1_IRQ_36_37" offset="0x8D0" width="32" description="">
1510     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1511     <bitfield id="PRUSS1_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
1512     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1513     <bitfield id="PRUSS1_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>
1514   </register>
1515   <register id="CTRL_CORE_PRUSS1_IRQ_38_39" acronym="CTRL_CORE_PRUSS1_IRQ_38_39" offset="0x8D4" width="32" description="">
1516     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1517     <bitfield id="PRUSS1_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
1518     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1519     <bitfield id="PRUSS1_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
1520   </register>
1521   <register id="CTRL_CORE_PRUSS1_IRQ_40_41" acronym="CTRL_CORE_PRUSS1_IRQ_40_41" offset="0x8D8" width="32" description="">
1522     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1523     <bitfield id="PRUSS1_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
1524     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1525     <bitfield id="PRUSS1_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
1526   </register>
1527   <register id="CTRL_CORE_PRUSS1_IRQ_42_43" acronym="CTRL_CORE_PRUSS1_IRQ_42_43" offset="0x8DC" width="32" description="">
1528     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1529     <bitfield id="PRUSS1_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
1530     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1531     <bitfield id="PRUSS1_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
1532   </register>
1533   <register id="CTRL_CORE_PRUSS1_IRQ_44_45" acronym="CTRL_CORE_PRUSS1_IRQ_44_45" offset="0x8E0" width="32" description="">
1534     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1535     <bitfield id="PRUSS1_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
1536     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1537     <bitfield id="PRUSS1_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
1538   </register>
1539   <register id="CTRL_CORE_PRUSS1_IRQ_46_47" acronym="CTRL_CORE_PRUSS1_IRQ_46_47" offset="0x8E4" width="32" description="">
1540     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1541     <bitfield id="PRUSS1_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
1542     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1543     <bitfield id="PRUSS1_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
1544   </register>
1545   <register id="CTRL_CORE_PRUSS1_IRQ_48_49" acronym="CTRL_CORE_PRUSS1_IRQ_48_49" offset="0x8E8" width="32" description="">
1546     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1547     <bitfield id="PRUSS1_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
1548     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1549     <bitfield id="PRUSS1_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
1550   </register>
1551   <register id="CTRL_CORE_PRUSS1_IRQ_50_51" acronym="CTRL_CORE_PRUSS1_IRQ_50_51" offset="0x8EC" width="32" description="">
1552     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1553     <bitfield id="PRUSS1_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
1554     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1555     <bitfield id="PRUSS1_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
1556   </register>
1557   <register id="CTRL_CORE_PRUSS1_IRQ_52_53" acronym="CTRL_CORE_PRUSS1_IRQ_52_53" offset="0x8F0" width="32" description="">
1558     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1559     <bitfield id="PRUSS1_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
1560     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1561     <bitfield id="PRUSS1_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
1562   </register>
1563   <register id="CTRL_CORE_PRUSS1_IRQ_54_55" acronym="CTRL_CORE_PRUSS1_IRQ_54_55" offset="0x8F4" width="32" description="">
1564     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1565     <bitfield id="PRUSS1_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
1566     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1567     <bitfield id="PRUSS1_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
1568   </register>
1569   <register id="CTRL_CORE_PRUSS1_IRQ_56_57" acronym="CTRL_CORE_PRUSS1_IRQ_56_57" offset="0x8F8" width="32" description="">
1570     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1571     <bitfield id="PRUSS1_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
1572     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1573     <bitfield id="PRUSS1_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
1574   </register>
1575   <register id="CTRL_CORE_PRUSS1_IRQ_58_59" acronym="CTRL_CORE_PRUSS1_IRQ_58_59" offset="0x8FC" width="32" description="">
1576     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1577     <bitfield id="PRUSS1_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
1578     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1579     <bitfield id="PRUSS1_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
1580   </register>
1581   <register id="CTRL_CORE_PRUSS1_IRQ_60_61" acronym="CTRL_CORE_PRUSS1_IRQ_60_61" offset="0x900" width="32" description="">
1582     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1583     <bitfield id="PRUSS1_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
1584     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1585     <bitfield id="PRUSS1_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
1586   </register>
1587   <register id="CTRL_CORE_PRUSS1_IRQ_62_63" acronym="CTRL_CORE_PRUSS1_IRQ_62_63" offset="0x904" width="32" description="">
1588     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1589     <bitfield id="PRUSS1_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
1590     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1591     <bitfield id="PRUSS1_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
1592   </register>
1593   <register id="CTRL_CORE_PRUSS2_IRQ_32_33" acronym="CTRL_CORE_PRUSS2_IRQ_32_33" offset="0x908" width="32" description="">
1594     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1595     <bitfield id="PRUSS2_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
1596     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1597     <bitfield id="PRUSS2_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
1598   </register>
1599   <register id="CTRL_CORE_PRUSS2_IRQ_34_35" acronym="CTRL_CORE_PRUSS2_IRQ_34_35" offset="0x90C" width="32" description="">
1600     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1601     <bitfield id="PRUSS2_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
1602     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1603     <bitfield id="PRUSS2_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
1604   </register>
1605   <register id="CTRL_CORE_PRUSS2_IRQ_36_37" acronym="CTRL_CORE_PRUSS2_IRQ_36_37" offset="0x910" width="32" description="">
1606     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1607     <bitfield id="PRUSS2_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
1608     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1609     <bitfield id="PRUSS2_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>
1610   </register>
1611   <register id="CTRL_CORE_PRUSS2_IRQ_38_39" acronym="CTRL_CORE_PRUSS2_IRQ_38_39" offset="0x914" width="32" description="">
1612     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1613     <bitfield id="PRUSS2_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
1614     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1615     <bitfield id="PRUSS2_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
1616   </register>
1617   <register id="CTRL_CORE_PRUSS2_IRQ_40_41" acronym="CTRL_CORE_PRUSS2_IRQ_40_41" offset="0x918" width="32" description="">
1618     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1619     <bitfield id="PRUSS2_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
1620     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1621     <bitfield id="PRUSS2_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
1622   </register>
1623   <register id="CTRL_CORE_PRUSS2_IRQ_42_43" acronym="CTRL_CORE_PRUSS2_IRQ_42_43" offset="0x91C" width="32" description="">
1624     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1625     <bitfield id="PRUSS2_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
1626     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1627     <bitfield id="PRUSS2_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
1628   </register>
1629   <register id="CTRL_CORE_PRUSS2_IRQ_44_45" acronym="CTRL_CORE_PRUSS2_IRQ_44_45" offset="0x920" width="32" description="">
1630     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1631     <bitfield id="PRUSS2_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
1632     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1633     <bitfield id="PRUSS2_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
1634   </register>
1635   <register id="CTRL_CORE_PRUSS2_IRQ_46_47" acronym="CTRL_CORE_PRUSS2_IRQ_46_47" offset="0x924" width="32" description="">
1636     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1637     <bitfield id="PRUSS2_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
1638     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1639     <bitfield id="PRUSS2_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
1640   </register>
1641   <register id="CTRL_CORE_PRUSS2_IRQ_48_49" acronym="CTRL_CORE_PRUSS2_IRQ_48_49" offset="0x928" width="32" description="">
1642     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1643     <bitfield id="PRUSS2_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
1644     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1645     <bitfield id="PRUSS2_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
1646   </register>
1647   <register id="CTRL_CORE_PRUSS2_IRQ_50_51" acronym="CTRL_CORE_PRUSS2_IRQ_50_51" offset="0x92C" width="32" description="">
1648     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1649     <bitfield id="PRUSS2_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
1650     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1651     <bitfield id="PRUSS2_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
1652   </register>
1653   <register id="CTRL_CORE_PRUSS2_IRQ_52_53" acronym="CTRL_CORE_PRUSS2_IRQ_52_53" offset="0x930" width="32" description="">
1654     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1655     <bitfield id="PRUSS2_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
1656     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1657     <bitfield id="PRUSS2_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
1658   </register>
1659   <register id="CTRL_CORE_PRUSS2_IRQ_54_55" acronym="CTRL_CORE_PRUSS2_IRQ_54_55" offset="0x934" width="32" description="">
1660     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1661     <bitfield id="PRUSS2_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
1662     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1663     <bitfield id="PRUSS2_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
1664   </register>
1665   <register id="CTRL_CORE_PRUSS2_IRQ_56_57" acronym="CTRL_CORE_PRUSS2_IRQ_56_57" offset="0x938" width="32" description="">
1666     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1667     <bitfield id="PRUSS2_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
1668     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1669     <bitfield id="PRUSS2_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
1670   </register>
1671   <register id="CTRL_CORE_PRUSS2_IRQ_58_59" acronym="CTRL_CORE_PRUSS2_IRQ_58_59" offset="0x93C" width="32" description="">
1672     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1673     <bitfield id="PRUSS2_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
1674     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1675     <bitfield id="PRUSS2_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
1676   </register>
1677   <register id="CTRL_CORE_PRUSS2_IRQ_60_61" acronym="CTRL_CORE_PRUSS2_IRQ_60_61" offset="0x940" width="32" description="">
1678     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1679     <bitfield id="PRUSS2_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
1680     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1681     <bitfield id="PRUSS2_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
1682   </register>
1683   <register id="CTRL_CORE_PRUSS2_IRQ_62_63" acronym="CTRL_CORE_PRUSS2_IRQ_62_63" offset="0x944" width="32" description="">
1684     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1685     <bitfield id="PRUSS2_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
1686     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1687     <bitfield id="PRUSS2_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
1688   </register>
1689   <register id="CTRL_CORE_DSP1_IRQ_32_33" acronym="CTRL_CORE_DSP1_IRQ_32_33" offset="0x948" width="32" description="">
1690     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1691     <bitfield id="DSP1_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
1692     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1693     <bitfield id="DSP1_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
1694   </register>
1695   <register id="CTRL_CORE_DSP1_IRQ_34_35" acronym="CTRL_CORE_DSP1_IRQ_34_35" offset="0x94C" width="32" description="">
1696     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1697     <bitfield id="DSP1_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
1698     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1699     <bitfield id="DSP1_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
1700   </register>
1701   <register id="CTRL_CORE_DSP1_IRQ_36_37" acronym="CTRL_CORE_DSP1_IRQ_36_37" offset="0x950" width="32" description="">
1702     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1703     <bitfield id="DSP1_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
1704     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1705     <bitfield id="DSP1_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>
1706   </register>
1707   <register id="CTRL_CORE_DSP1_IRQ_38_39" acronym="CTRL_CORE_DSP1_IRQ_38_39" offset="0x954" width="32" description="">
1708     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1709     <bitfield id="DSP1_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
1710     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1711     <bitfield id="DSP1_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
1712   </register>
1713   <register id="CTRL_CORE_DSP1_IRQ_40_41" acronym="CTRL_CORE_DSP1_IRQ_40_41" offset="0x958" width="32" description="">
1714     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1715     <bitfield id="DSP1_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
1716     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1717     <bitfield id="DSP1_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
1718   </register>
1719   <register id="CTRL_CORE_DSP1_IRQ_42_43" acronym="CTRL_CORE_DSP1_IRQ_42_43" offset="0x95C" width="32" description="">
1720     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1721     <bitfield id="DSP1_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
1722     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1723     <bitfield id="DSP1_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
1724   </register>
1725   <register id="CTRL_CORE_DSP1_IRQ_44_45" acronym="CTRL_CORE_DSP1_IRQ_44_45" offset="0x960" width="32" description="">
1726     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1727     <bitfield id="DSP1_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
1728     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1729     <bitfield id="DSP1_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
1730   </register>
1731   <register id="CTRL_CORE_DSP1_IRQ_46_47" acronym="CTRL_CORE_DSP1_IRQ_46_47" offset="0x964" width="32" description="">
1732     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1733     <bitfield id="DSP1_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
1734     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1735     <bitfield id="DSP1_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
1736   </register>
1737   <register id="CTRL_CORE_DSP1_IRQ_48_49" acronym="CTRL_CORE_DSP1_IRQ_48_49" offset="0x968" width="32" description="">
1738     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1739     <bitfield id="DSP1_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
1740     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1741     <bitfield id="DSP1_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
1742   </register>
1743   <register id="CTRL_CORE_DSP1_IRQ_50_51" acronym="CTRL_CORE_DSP1_IRQ_50_51" offset="0x96C" width="32" description="">
1744     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1745     <bitfield id="DSP1_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
1746     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1747     <bitfield id="DSP1_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
1748   </register>
1749   <register id="CTRL_CORE_DSP1_IRQ_52_53" acronym="CTRL_CORE_DSP1_IRQ_52_53" offset="0x970" width="32" description="">
1750     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1751     <bitfield id="DSP1_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
1752     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1753     <bitfield id="DSP1_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
1754   </register>
1755   <register id="CTRL_CORE_DSP1_IRQ_54_55" acronym="CTRL_CORE_DSP1_IRQ_54_55" offset="0x974" width="32" description="">
1756     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1757     <bitfield id="DSP1_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
1758     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1759     <bitfield id="DSP1_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
1760   </register>
1761   <register id="CTRL_CORE_DSP1_IRQ_56_57" acronym="CTRL_CORE_DSP1_IRQ_56_57" offset="0x978" width="32" description="">
1762     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1763     <bitfield id="DSP1_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
1764     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1765     <bitfield id="DSP1_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
1766   </register>
1767   <register id="CTRL_CORE_DSP1_IRQ_58_59" acronym="CTRL_CORE_DSP1_IRQ_58_59" offset="0x97C" width="32" description="">
1768     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1769     <bitfield id="DSP1_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
1770     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1771     <bitfield id="DSP1_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
1772   </register>
1773   <register id="CTRL_CORE_DSP1_IRQ_60_61" acronym="CTRL_CORE_DSP1_IRQ_60_61" offset="0x980" width="32" description="">
1774     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1775     <bitfield id="DSP1_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
1776     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1777     <bitfield id="DSP1_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
1778   </register>
1779   <register id="CTRL_CORE_DSP1_IRQ_62_63" acronym="CTRL_CORE_DSP1_IRQ_62_63" offset="0x984" width="32" description="">
1780     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1781     <bitfield id="DSP1_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
1782     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1783     <bitfield id="DSP1_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
1784   </register>
1785   <register id="CTRL_CORE_DSP1_IRQ_64_65" acronym="CTRL_CORE_DSP1_IRQ_64_65" offset="0x988" width="32" description="">
1786     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1787     <bitfield id="DSP1_IRQ_65" width="9" begin="24" end="16" resetval="0x22" description="" range="" rwaccess="RW"/>
1788     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1789     <bitfield id="DSP1_IRQ_64" width="9" begin="8" end="0" resetval="0x21" description="" range="" rwaccess="RW"/>
1790   </register>
1791   <register id="CTRL_CORE_DSP1_IRQ_66_67" acronym="CTRL_CORE_DSP1_IRQ_66_67" offset="0x98C" width="32" description="">
1792     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1793     <bitfield id="DSP1_IRQ_67" width="9" begin="24" end="16" resetval="0x24" description="" range="" rwaccess="RW"/>
1794     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1795     <bitfield id="DSP1_IRQ_66" width="9" begin="8" end="0" resetval="0x23" description="" range="" rwaccess="RW"/>
1796   </register>
1797   <register id="CTRL_CORE_DSP1_IRQ_68_69" acronym="CTRL_CORE_DSP1_IRQ_68_69" offset="0x990" width="32" description="">
1798     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1799     <bitfield id="DSP1_IRQ_69" width="9" begin="24" end="16" resetval="0x26" description="" range="" rwaccess="RW"/>
1800     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1801     <bitfield id="DSP1_IRQ_68" width="9" begin="8" end="0" resetval="0x25" description="" range="" rwaccess="RW"/>
1802   </register>
1803   <register id="CTRL_CORE_DSP1_IRQ_70_71" acronym="CTRL_CORE_DSP1_IRQ_70_71" offset="0x994" width="32" description="">
1804     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1805     <bitfield id="DSP1_IRQ_71" width="9" begin="24" end="16" resetval="0x28" description="" range="" rwaccess="RW"/>
1806     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1807     <bitfield id="DSP1_IRQ_70" width="9" begin="8" end="0" resetval="0x27" description="" range="" rwaccess="RW"/>
1808   </register>
1809   <register id="CTRL_CORE_DSP1_IRQ_72_73" acronym="CTRL_CORE_DSP1_IRQ_72_73" offset="0x998" width="32" description="">
1810     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1811     <bitfield id="DSP1_IRQ_73" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>
1812     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1813     <bitfield id="DSP1_IRQ_72" width="9" begin="8" end="0" resetval="0x29" description="" range="" rwaccess="RW"/>
1814   </register>
1815   <register id="CTRL_CORE_DSP1_IRQ_74_75" acronym="CTRL_CORE_DSP1_IRQ_74_75" offset="0x99C" width="32" description="">
1816     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1817     <bitfield id="DSP1_IRQ_75" width="9" begin="24" end="16" resetval="0x2C" description="" range="" rwaccess="RW"/>
1818     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1819     <bitfield id="DSP1_IRQ_74" width="9" begin="8" end="0" resetval="0x2B" description="" range="" rwaccess="RW"/>
1820   </register>
1821   <register id="CTRL_CORE_DSP1_IRQ_76_77" acronym="CTRL_CORE_DSP1_IRQ_76_77" offset="0x9A0" width="32" description="">
1822     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1823     <bitfield id="DSP1_IRQ_77" width="9" begin="24" end="16" resetval="0x2E" description="" range="" rwaccess="RW"/>
1824     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1825     <bitfield id="DSP1_IRQ_76" width="9" begin="8" end="0" resetval="0x2D" description="" range="" rwaccess="RW"/>
1826   </register>
1827   <register id="CTRL_CORE_DSP1_IRQ_78_79" acronym="CTRL_CORE_DSP1_IRQ_78_79" offset="0x9A4" width="32" description="">
1828     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1829     <bitfield id="DSP1_IRQ_79" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>
1830     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1831     <bitfield id="DSP1_IRQ_78" width="9" begin="8" end="0" resetval="0x2F" description="" range="" rwaccess="RW"/>
1832   </register>
1833   <register id="CTRL_CORE_DSP1_IRQ_80_81" acronym="CTRL_CORE_DSP1_IRQ_80_81" offset="0x9A8" width="32" description="">
1834     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1835     <bitfield id="DSP1_IRQ_81" width="9" begin="24" end="16" resetval="0x32" description="" range="" rwaccess="RW"/>
1836     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1837     <bitfield id="DSP1_IRQ_80" width="9" begin="8" end="0" resetval="0x31" description="" range="" rwaccess="RW"/>
1838   </register>
1839   <register id="CTRL_CORE_DSP1_IRQ_82_83" acronym="CTRL_CORE_DSP1_IRQ_82_83" offset="0x9AC" width="32" description="">
1840     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1841     <bitfield id="DSP1_IRQ_83" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>
1842     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1843     <bitfield id="DSP1_IRQ_82" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>
1844   </register>
1845   <register id="CTRL_CORE_DSP1_IRQ_84_85" acronym="CTRL_CORE_DSP1_IRQ_84_85" offset="0x9B0" width="32" description="">
1846     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1847     <bitfield id="DSP1_IRQ_85" width="9" begin="24" end="16" resetval="0x36" description="" range="" rwaccess="RW"/>
1848     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1849     <bitfield id="DSP1_IRQ_84" width="9" begin="8" end="0" resetval="0x35" description="" range="" rwaccess="RW"/>
1850   </register>
1851   <register id="CTRL_CORE_DSP1_IRQ_86_87" acronym="CTRL_CORE_DSP1_IRQ_86_87" offset="0x9B4" width="32" description="">
1852     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1853     <bitfield id="DSP1_IRQ_87" width="9" begin="24" end="16" resetval="0x38" description="" range="" rwaccess="RW"/>
1854     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1855     <bitfield id="DSP1_IRQ_86" width="9" begin="8" end="0" resetval="0x37" description="" range="" rwaccess="RW"/>
1856   </register>
1857   <register id="CTRL_CORE_DSP1_IRQ_88_89" acronym="CTRL_CORE_DSP1_IRQ_88_89" offset="0x9B8" width="32" description="">
1858     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1859     <bitfield id="DSP1_IRQ_89" width="9" begin="24" end="16" resetval="0x3A" description="" range="" rwaccess="RW"/>
1860     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1861     <bitfield id="DSP1_IRQ_88" width="9" begin="8" end="0" resetval="0x39" description="" range="" rwaccess="RW"/>
1862   </register>
1863   <register id="CTRL_CORE_DSP1_IRQ_90_91" acronym="CTRL_CORE_DSP1_IRQ_90_91" offset="0x9BC" width="32" description="">
1864     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1865     <bitfield id="DSP1_IRQ_91" width="9" begin="24" end="16" resetval="0x3C" description="" range="" rwaccess="RW"/>
1866     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1867     <bitfield id="DSP1_IRQ_90" width="9" begin="8" end="0" resetval="0x3B" description="" range="" rwaccess="RW"/>
1868   </register>
1869   <register id="CTRL_CORE_DSP1_IRQ_92_93" acronym="CTRL_CORE_DSP1_IRQ_92_93" offset="0x9C0" width="32" description="">
1870     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1871     <bitfield id="DSP1_IRQ_93" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>
1872     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1873     <bitfield id="DSP1_IRQ_92" width="9" begin="8" end="0" resetval="0x3D" description="" range="" rwaccess="RW"/>
1874   </register>
1875   <register id="CTRL_CORE_DSP1_IRQ_94_95" acronym="CTRL_CORE_DSP1_IRQ_94_95" offset="0x9C4" width="32" description="">
1876     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1877     <bitfield id="DSP1_IRQ_95" width="9" begin="24" end="16" resetval="0x40" description="" range="" rwaccess="RW"/>
1878     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1879     <bitfield id="DSP1_IRQ_94" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>
1880   </register>
1881   <register id="CTRL_CORE_MPU_IRQ_4_7" acronym="CTRL_CORE_MPU_IRQ_4_7" offset="0xA48" width="32" description="">
1882     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1883     <bitfield id="MPU_IRQ_7" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
1884     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1885     <bitfield id="MPU_IRQ_4" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
1886   </register>
1887   <register id="CTRL_CORE_MPU_IRQ_8_9" acronym="CTRL_CORE_MPU_IRQ_8_9" offset="0xA4C" width="32" description="">
1888     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1889     <bitfield id="MPU_IRQ_9" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
1890     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1891     <bitfield id="MPU_IRQ_8" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
1892   </register>
1893   <register id="CTRL_CORE_MPU_IRQ_10_11" acronym="CTRL_CORE_MPU_IRQ_10_11" offset="0xA50" width="32" description="">
1894     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1895     <bitfield id="MPU_IRQ_11" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
1896     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1897     <bitfield id="MPU_IRQ_10" width="9" begin="8" end="0" resetval="0x5" description="NOTE: This bit field is not functional" range="" rwaccess="RW"/>
1898   </register>
1899   <register id="CTRL_CORE_MPU_IRQ_12_13" acronym="CTRL_CORE_MPU_IRQ_12_13" offset="0xA54" width="32" description="">
1900     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1901     <bitfield id="MPU_IRQ_13" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
1902     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1903     <bitfield id="MPU_IRQ_12" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
1904   </register>
1905   <register id="CTRL_CORE_MPU_IRQ_14_15" acronym="CTRL_CORE_MPU_IRQ_14_15" offset="0xA58" width="32" description="">
1906     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1907     <bitfield id="MPU_IRQ_15" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
1908     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1909     <bitfield id="MPU_IRQ_14" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
1910   </register>
1911   <register id="CTRL_CORE_MPU_IRQ_16_17" acronym="CTRL_CORE_MPU_IRQ_16_17" offset="0xA5C" width="32" description="">
1912     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1913     <bitfield id="MPU_IRQ_17" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
1914     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1915     <bitfield id="MPU_IRQ_16" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
1916   </register>
1917   <register id="CTRL_CORE_MPU_IRQ_18_19" acronym="CTRL_CORE_MPU_IRQ_18_19" offset="0xA60" width="32" description="">
1918     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1919     <bitfield id="MPU_IRQ_19" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
1920     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1921     <bitfield id="MPU_IRQ_18" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
1922   </register>
1923   <register id="CTRL_CORE_MPU_IRQ_20_21" acronym="CTRL_CORE_MPU_IRQ_20_21" offset="0xA64" width="32" description="">
1924     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1925     <bitfield id="MPU_IRQ_21" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
1926     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1927     <bitfield id="MPU_IRQ_20" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
1928   </register>
1929   <register id="CTRL_CORE_MPU_IRQ_22_23" acronym="CTRL_CORE_MPU_IRQ_22_23" offset="0xA68" width="32" description="">
1930     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1931     <bitfield id="MPU_IRQ_23" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
1932     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1933     <bitfield id="MPU_IRQ_22" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
1934   </register>
1935   <register id="CTRL_CORE_MPU_IRQ_24_25" acronym="CTRL_CORE_MPU_IRQ_24_25" offset="0xA6C" width="32" description="">
1936     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1937     <bitfield id="MPU_IRQ_25" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
1938     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1939     <bitfield id="MPU_IRQ_24" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
1940   </register>
1941   <register id="CTRL_CORE_MPU_IRQ_26_27" acronym="CTRL_CORE_MPU_IRQ_26_27" offset="0xA70" width="32" description="">
1942     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1943     <bitfield id="MPU_IRQ_27" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
1944     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1945     <bitfield id="MPU_IRQ_26" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
1946   </register>
1947   <register id="CTRL_CORE_MPU_IRQ_28_29" acronym="CTRL_CORE_MPU_IRQ_28_29" offset="0xA74" width="32" description="">
1948     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1949     <bitfield id="MPU_IRQ_29" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
1950     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1951     <bitfield id="MPU_IRQ_28" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
1952   </register>
1953   <register id="CTRL_CORE_MPU_IRQ_30_31" acronym="CTRL_CORE_MPU_IRQ_30_31" offset="0xA78" width="32" description="">
1954     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1955     <bitfield id="MPU_IRQ_31" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
1956     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1957     <bitfield id="MPU_IRQ_30" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
1958   </register>
1959   <register id="CTRL_CORE_MPU_IRQ_32_33" acronym="CTRL_CORE_MPU_IRQ_32_33" offset="0xA7C" width="32" description="">
1960     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1961     <bitfield id="MPU_IRQ_33" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
1962     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1963     <bitfield id="MPU_IRQ_32" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
1964   </register>
1965   <register id="CTRL_CORE_MPU_IRQ_34_35" acronym="CTRL_CORE_MPU_IRQ_34_35" offset="0xA80" width="32" description="">
1966     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1967     <bitfield id="MPU_IRQ_35" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
1968     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1969     <bitfield id="MPU_IRQ_34" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
1970   </register>
1971   <register id="CTRL_CORE_MPU_IRQ_36_37" acronym="CTRL_CORE_MPU_IRQ_36_37" offset="0xA84" width="32" description="">
1972     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1973     <bitfield id="MPU_IRQ_37" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
1974     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1975     <bitfield id="MPU_IRQ_36" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
1976   </register>
1977   <register id="CTRL_CORE_MPU_IRQ_38_39" acronym="CTRL_CORE_MPU_IRQ_38_39" offset="0xA88" width="32" description="">
1978     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1979     <bitfield id="MPU_IRQ_39" width="9" begin="24" end="16" resetval="0x22" description="" range="" rwaccess="RW"/>
1980     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1981     <bitfield id="MPU_IRQ_38" width="9" begin="8" end="0" resetval="0x21" description="" range="" rwaccess="RW"/>
1982   </register>
1983   <register id="CTRL_CORE_MPU_IRQ_40_41" acronym="CTRL_CORE_MPU_IRQ_40_41" offset="0xA8C" width="32" description="">
1984     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1985     <bitfield id="MPU_IRQ_41" width="9" begin="24" end="16" resetval="0x24" description="" range="" rwaccess="RW"/>
1986     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1987     <bitfield id="MPU_IRQ_40" width="9" begin="8" end="0" resetval="0x23" description="" range="" rwaccess="RW"/>
1988   </register>
1989   <register id="CTRL_CORE_MPU_IRQ_42_43" acronym="CTRL_CORE_MPU_IRQ_42_43" offset="0xA90" width="32" description="">
1990     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1991     <bitfield id="MPU_IRQ_43" width="9" begin="24" end="16" resetval="0x26" description="" range="" rwaccess="RW"/>
1992     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1993     <bitfield id="MPU_IRQ_42" width="9" begin="8" end="0" resetval="0x25" description="" range="" rwaccess="RW"/>
1994   </register>
1995   <register id="CTRL_CORE_MPU_IRQ_44_45" acronym="CTRL_CORE_MPU_IRQ_44_45" offset="0xA94" width="32" description="">
1996     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
1997     <bitfield id="MPU_IRQ_45" width="9" begin="24" end="16" resetval="0x28" description="" range="" rwaccess="RW"/>
1998     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
1999     <bitfield id="MPU_IRQ_44" width="9" begin="8" end="0" resetval="0x27" description="" range="" rwaccess="RW"/>
2000   </register>