Add xml files needed by Python script
authorBrad Griffis <bgriffis@ti.com>
Wed, 9 Jan 2019 17:38:20 +0000 (11:38 -0600)
committerBrad Griffis <bgriffis@ti.com>
Wed, 9 Jan 2019 17:38:20 +0000 (11:38 -0600)
padconf/CTRL_MODULE_CORE_am571x.xml [new file with mode: 0755]
padconf/CTRL_MODULE_CORE_am572x.xml [new file with mode: 0755]
padconf/CTRL_MODULE_CORE_am574x.xml [new file with mode: 0755]

diff --git a/padconf/CTRL_MODULE_CORE_am571x.xml b/padconf/CTRL_MODULE_CORE_am571x.xml
new file mode 100755 (executable)
index 0000000..2f40447
--- /dev/null
@@ -0,0 +1,14144 @@
+<module name="CTRL_MODULE_CORE" acronym="" XML_version="1.0" HW_revision="n/a" description="">
+  <register id="CTRL_CORE_MREQDOMAIN_EXP1" acronym="CTRL_CORE_MREQDOMAIN_EXP1" offset="0x108" width="32" description="MReqDomain value configuration register.">
+    <bitfield id="MREQDOMAIN_EXP1_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
+    <bitfield id="RESERVED" width="1" begin="30" end="30" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_IPU2" width="3" begin="29" end="27" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that: MreqDomain[2:0]= 0b000 = DOMAIN0 MreqDomain[2:0]= 0b001 = DOMAIN1 MreqDomain[2:0]= 0b010 = DOMAIN2 MreqDomain[2:0]= 0b011 = DOMAIN3 MreqDomain[2:0]= 0b100 = DOMAIN4 MreqDomain[2:0]= 0b110 = DOMAIN6 MreqDomain[2:0]= 0b111 = DOMAIN7" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="3" begin="26" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_GPU_P0" width="3" begin="23" end="21" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_IPU1" width="3" begin="20" end="18" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="3" begin="17" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_IVAHD" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_DSS" width="3" begin="11" end="9" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_DSP1_CFG" width="3" begin="8" end="6" resetval="0x0" description="see MREQDOMAIN_IPU2 Description" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="5" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_MREQDOMAIN_EXP2" acronym="CTRL_CORE_MREQDOMAIN_EXP2" offset="0x10C" width="32" description="MReqDomain value configuration register.">
+    <bitfield id="MREQDOMAIN_EXP2_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
+    <bitfield id="RESERVED" width="4" begin="30" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_SATA" width="3" begin="26" end="24" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that: MreqDomain[2:0]= 0b000 = DOMAIN0 MreqDomain[2:0]= 0b001 = DOMAIN1 MreqDomain[2:0]= 0b010 = DOMAIN2 MreqDomain[2:0]= 0b011 = DOMAIN3 MreqDomain[2:0]= 0b100 = DOMAIN4 MreqDomain[2:0]= 0b110 = DOMAIN6 MreqDomain[2:0]= 0b111 = DOMAIN7" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_USB3" width="3" begin="23" end="21" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_USB2" width="3" begin="20" end="18" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="3" begin="17" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_USB1" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="11" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_MMC2" width="3" begin="5" end="3" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_MMC1" width="3" begin="2" end="0" resetval="0x0" description="see MREQDOMAIN_SATA Description" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MREQDOMAIN_EXP3" acronym="CTRL_CORE_MREQDOMAIN_EXP3" offset="0x110" width="32" description="MReqDomain value configuration register.">
+    <bitfield id="MREQDOMAIN_EXP3_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
+    <bitfield id="RESERVED" width="13" begin="30" end="18" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_VIP1_P0" width="3" begin="17" end="15" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that:" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_PRUSS2_PRU0" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_VIP1_P0 Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_PRUSS1_PRU0" width="3" begin="11" end="9" resetval="0x0" description="see MREQDOMAIN_VIP1_P0 Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_BB2D" width="3" begin="8" end="6" resetval="0x0" description="see MREQDOMAIN_VIP1_P0 Description" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="5" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STATUS" acronym="CTRL_CORE_STATUS" offset="0x134" width="32" description="Control Module Status Register">
+    <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DEVICE_TYPE" width="3" begin="8" end="6" resetval="0x3" description="Device type captured at reset time. Read 0x3 = General Purpose (GP)" range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="6" begin="5" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_SEC_ERR_STATUS_FUNC_1" acronym="CTRL_CORE_SEC_ERR_STATUS_FUNC_1" offset="0x148" width="32" description="Firewall Error Status functional Register 1">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="BB2D_FW_ERROR" width="1" begin="23" end="23" resetval="0x0" description="BB2D firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_WAKEUP_FW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="L4 wakeup firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="3" begin="21" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DEBUGSS_FW_ERROR" width="1" begin="18" end="18" resetval="0x0" description="DebugSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_CONFIG_FW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="L4 config firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_PERIPH1_FW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="L4 periph1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSS_FW_ERROR" width="1" begin="14" end="14" resetval="0x0" description="DSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="GPU_FW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="GPU firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="6" begin="12" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IVAHD_SL2_FW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IVAHD SL2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="IPU1_FW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="IPU1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="IVAHD_FW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="IVAHD firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="EMIF_FW_ERROR" width="1" begin="3" end="3" resetval="0x0" description="EMIF firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="GPMC_FW_ERROR" width="1" begin="2" end="2" resetval="0x0" description="GPMC firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L3RAM1_FW_ERROR" width="1" begin="1" end="1" resetval="0x0" description="L3RAM1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="1" begin="0" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_SEC_ERR_STATUS_DEBUG_1" acronym="CTRL_CORE_SEC_ERR_STATUS_DEBUG_1" offset="0x150" width="32" description="Firewall Error Status Debug Register 1">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="BB2D_DBGFW_ERROR" width="1" begin="23" end="23" resetval="0x0" description="BB2D firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_WAKEUP_DBGFW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="L4 wakeup firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="3" begin="21" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DEBUGSS_DBGFW_ERROR" width="1" begin="18" end="18" resetval="0x0" description="DebugSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_CONFIG_DBGFW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="L4 config firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_PERIPH1_DBGFW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="L4 periph1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSS_DBGFW_ERROR" width="1" begin="14" end="14" resetval="0x0" description="DSS debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="GPU_DBGFW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="GPU debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="6" begin="12" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IVAHD_SL2_DBGFW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IVAHD SL2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="IPU1_DBGFW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="IPU1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="IVAHD_DBGFW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="IVAHD debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="EMIF_DBGFW_ERROR" width="1" begin="3" end="3" resetval="0x0" description="EMIF debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="GPMC_DBGFW_ERROR" width="1" begin="2" end="2" resetval="0x0" description="GPMC debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L3RAM1_DBGFW_ERROR" width="1" begin="1" end="1" resetval="0x0" description="L3RAM1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="1" begin="0" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_MPU_FORCEWRNP" acronym="CTRL_CORE_MPU_FORCEWRNP" offset="0x15C" width="32" description="FORCE WRITE NON POSTED">
+    <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_FORCEWRNP" width="1" begin="0" end="0" resetval="0x0" description="Force mpu write non posted transactions 0x0 = disable force wrnp 0x1 = force wrnp" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0" offset="0x194" width="32" description="Standard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1" offset="0x198" width="32" description="Standard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2" offset="0x19C" width="32" description="Standard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3" offset="0x1A0" width="32" description="Standard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4" offset="0x1A4" width="32" description="Standard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5" offset="0x1A8" width="32" description="Standard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0" offset="0x1AC" width="32" description="Standard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1" offset="0x1B0" width="32" description="Standard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2" offset="0x1B4" width="32" description="Standard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3" offset="0x1B8" width="32" description="Standard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4" offset="0x1BC" width="32" description="Standard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5" offset="0x1C0" width="32" description="Standard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6" offset="0x1C4" width="32" description="Standard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7" offset="0x1C8" width="32" description="Standard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0" offset="0x1CC" width="32" description="Standard Fuse OPP VDD_CORE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_CORE_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1" offset="0x1D0" width="32" description="Standard Fuse OPP VDD_CORE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_CORE_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2" offset="0x1D4" width="32" description="Standard Fuse OPP VDD_CORE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_CORE_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3" offset="0x1D8" width="32" description="Standard Fuse OPP VDD_CORE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_CORE_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4" offset="0x1DC" width="32" description="Standard Fuse OPP VDD_CORE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_CORE_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_GPU" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_GPU" offset="0x1E0" width="32" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">
+    <bitfield id="STD_FUSE_OPP_BGAP_GPU_0" width="8" begin="31" end="24" resetval="0x-" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_GPU_1" width="8" begin="23" end="16" resetval="0x-" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_GPU_2" width="8" begin="15" end="8" resetval="0x-" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_GPU_3" width="8" begin="7" end="0" resetval="0x-" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU" offset="0x1E4" width="32" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">
+    <bitfield id="STD_FUSE_OPP_BGAP_MPU_0" width="8" begin="31" end="24" resetval="0x-" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_MPU_1" width="8" begin="23" end="16" resetval="0x-" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_MPU_2" width="8" begin="15" end="8" resetval="0x-" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_MPU_3" width="8" begin="7" end="0" resetval="0x-" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_CORE" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_CORE" offset="0x1E8" width="32" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">
+    <bitfield id="STD_FUSE_OPP_BGAP_CORE_0" width="8" begin="31" end="24" resetval="0x-" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_CORE_1" width="8" begin="23" end="16" resetval="0x-" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_CORE_2" width="8" begin="15" end="8" resetval="0x-" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_CORE_3" width="8" begin="7" end="0" resetval="0x-" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23" offset="0x1EC" width="32" description="Standard Fuse OPP BGAP. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_BGAP_MPU3" width="16" begin="31" end="16" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_MPU2" width="16" begin="15" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_MPK_0" acronym="CTRL_CORE_STD_FUSE_MPK_0" offset="0x220" width="32" description="Standard Fuse keys. Root_public_key_hash [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_MPK_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_MPK_1" acronym="CTRL_CORE_STD_FUSE_MPK_1" offset="0x224" width="32" description="Standard Fuse keys. Root_public_key_hash [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_MPK_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_MPK_2" acronym="CTRL_CORE_STD_FUSE_MPK_2" offset="0x228" width="32" description="Standard Fuse keys. Root_public_key_hash [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_MPK_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_MPK_3" acronym="CTRL_CORE_STD_FUSE_MPK_3" offset="0x22C" width="32" description="Standard Fuse keys. Root_public_key_hash [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_MPK_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_MPK_4" acronym="CTRL_CORE_STD_FUSE_MPK_4" offset="0x230" width="32" description="Standard Fuse keys. Root_public_key_hash [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_MPK_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_MPK_5" acronym="CTRL_CORE_STD_FUSE_MPK_5" offset="0x234" width="32" description="Standard Fuse keys. Root_public_key_hash [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_MPK_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_MPK_6" acronym="CTRL_CORE_STD_FUSE_MPK_6" offset="0x238" width="32" description="Standard Fuse keys. Root_public_key_hash [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_MPK_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_MPK_7" acronym="CTRL_CORE_STD_FUSE_MPK_7" offset="0x23C" width="32" description="Standard Fuse keys. Root_public_key_hash [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_MPK_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0" offset="0x240" width="32" description="Standard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1" offset="0x244" width="32" description="Standard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2" offset="0x248" width="32" description="Standard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3" offset="0x24C" width="32" description="Standard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4" offset="0x250" width="32" description="Standard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5" offset="0x254" width="32" description="Standard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0" offset="0x258" width="32" description="Standard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1" offset="0x25C" width="32" description="Standard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2" offset="0x260" width="32" description="Standard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3" offset="0x264" width="32" description="Standard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4" offset="0x268" width="32" description="Standard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5" offset="0x26C" width="32" description="Standard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6" offset="0x270" width="32" description="Standard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7" offset="0x274" width="32" description="Standard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_SWRV_0" acronym="CTRL_CORE_CUST_FUSE_SWRV_0" offset="0x2BC" width="32" description="Customer Fuse keys. Software Version Control [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_SWRV_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_SWRV_1" acronym="CTRL_CORE_CUST_FUSE_SWRV_1" offset="0x2C0" width="32" description="Customer Fuse keys. Software Version Control [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_SWRV_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_SWRV_2" acronym="CTRL_CORE_CUST_FUSE_SWRV_2" offset="0x2C4" width="32" description="Customer Fuse keys. Software Version Control [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_SWRV_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_SWRV_3" acronym="CTRL_CORE_CUST_FUSE_SWRV_3" offset="0x2C8" width="32" description="Customer Fuse keys. Software Version Control [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_SWRV_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_SWRV_4" acronym="CTRL_CORE_CUST_FUSE_SWRV_4" offset="0x2CC" width="32" description="Customer Fuse keys. Software Version Control [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_SWRV_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_SWRV_5" acronym="CTRL_CORE_CUST_FUSE_SWRV_5" offset="0x2D0" width="32" description="Customer Fuse keys. Software Version Control [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_SWRV_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_SWRV_6" acronym="CTRL_CORE_CUST_FUSE_SWRV_6" offset="0x2D4" width="32" description="Customer Fuse keys. Software Version Control [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_SWRV_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DEV_CONF" acronym="CTRL_CORE_DEV_CONF" offset="0x300" width="32" description="This register is used to power down the USB2_PHY1">
+    <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="USBPHY_PD" width="1" begin="0" end="0" resetval="0x0" description="Power down the entire USB2_PHY1 (data, common module and UTMI). 0x0: Normal operation 0x1: Power down the USB2_PHY1" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_TEMP_SENSOR_MPU" acronym="CTRL_CORE_TEMP_SENSOR_MPU" offset="0x32C" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
+    <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="BGAP_TMPSOFF_MPU" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
+    <bitfield id="BGAP_EOCZ_MPU" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_MPU is valid." range="" rwaccess="R"/>
+    <bitfield id="BGAP_DTEMP_MPU" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_TEMP_SENSOR_GPU" acronym="CTRL_CORE_TEMP_SENSOR_GPU" offset="0x330" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
+    <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="BGAP_TMPSOFF_GPU" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
+    <bitfield id="BGAP_EOCZ_GPU" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_GPU is valid." range="" rwaccess="R"/>
+    <bitfield id="BGAP_DTEMP_GPU" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_TEMP_SENSOR_CORE" acronym="CTRL_CORE_TEMP_SENSOR_CORE" offset="0x334" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
+    <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="BGAP_TMPSOFF_CORE" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
+    <bitfield id="BGAP_EOCZ_CORE" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_CORE is valid." range="" rwaccess="R"/>
+    <bitfield id="BGAP_DTEMP_CORE" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR" acronym="CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR" offset="0x358" width="32" description="Cortex M4 register">
+    <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CORTEX_M4_MMUADDRTRANSLTR" width="20" begin="19" end="0" resetval="0x0" description="Used to save the IPU AMMU translated/boot address" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR" acronym="CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR" offset="0x35C" width="32" description="">
+    <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CORTEX_M4_MMUADDRLOGICTR" width="20" begin="19" end="0" resetval="0x0" description="Used to save the IPU AMMU logical source address" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_HWOBS_CONTROL" acronym="CTRL_CORE_HWOBS_CONTROL" offset="0x360" width="32" description="HW observability control. This register enables or disables HW observability outputs (to save power primarily)">
+    <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="HWOBS_CLKDIV_SEL_2" width="5" begin="18" end="14" resetval="0x0" description="Clock divider selection on po_hwobs(2). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" range="" rwaccess="RW"/>
+    <bitfield id="HWOBS_CLKDIV_SEL_1" width="5" begin="13" end="9" resetval="0x0" description="Clock divider selection on po_hwobs(1). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="8" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="HWOBS_CLKDIV_SEL" width="5" begin="7" end="3" resetval="0x0" description="Clock divider selection on po_hwobs(0). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" range="" rwaccess="RW"/>
+    <bitfield id="HWOBS_ALL_ZERO_MODE" width="1" begin="2" end="2" resetval="0x0" description="Used to gate observable signals. When set all outputs are set to zero (can be used to check the path from HW observability to external pads). 0x0 = hw observability ports are not gated 0x1 = hw observability ports are all set to 0" range="" rwaccess="RW"/>
+    <bitfield id="HWOBS_ALL_ONE_MODE" width="1" begin="1" end="1" resetval="0x0" description="Used to gate observable signals. When set all outputs are set to one (can be used to check the path from HW observability to external pads). 0x0 = hw observability ports are not gated 0x1 = hw observability ports are all set to 1" range="" rwaccess="RW"/>
+    <bitfield id="HWOBS_MACRO_ENABLE" width="1" begin="0" end="0" resetval="0x0" description="Used to gate observable signals coming from macros using the 32:bit HWOBS bus definition. When deasserted all outputs of the HWOBS busdef are set to zero. 0x0 = hw observability ports from macros are gated and set to zero 0x1 = hw observability ports from macros are not gated" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PHY_POWER_USB" acronym="CTRL_CORE_PHY_POWER_USB" offset="0x370" width="32" description="phy_power_usb">
+    <bitfield id="USB_PWRCTL_CLK_FREQ" width="10" begin="31" end="22" resetval="0x0" description="Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." range="" rwaccess="RW"/>
+    <bitfield id="USB_PWRCTL_CLK_CMD" width="8" begin="21" end="14" resetval="0x0" description="Powers up/down the USB3_PHY_TX and USB3_PHY_RX modules. This bit field is also used for partially power down these TX and RX modules. Each bit has the following meaning: Bit[14] - 0x1: Powers-up the USB3_PHY_RX Bit[15] - 0x1: Powers-up the USB3_PHY_TX Bit[16] - A don&#8217;t care bit. Not used. Bit[17] - A don&#8217;t care bit. Not used. Bit[18] - 0x1: Disables the synchronized power-up of USB3_PHY_TX with USB3_PHY_RX. The TX power-up is independent of the RX power-up. Bit[19] - 0x1: Disables the automatic power-cycling of USB3_PHY_RX in P3 power state when PLL_CLK stops and starts. Bit[20] - 0x1: Partially powers-down the USB3_PHY_RX when it is in P3 power state. DCC, Phase interpolator, Equalizer are disabled. Bit[21] - A don&#8217;t care bit. Not used." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="14" begin="13" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_PHY_POWER_SATA" acronym="CTRL_CORE_PHY_POWER_SATA" offset="0x374" width="32" description="phy_power_sata">
+    <bitfield id="SATA_PWRCTL_CLK_FREQ" width="10" begin="31" end="22" resetval="0x0" description="Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." range="" rwaccess="RW"/>
+    <bitfield id="SATA_PWRCTL_CLK_CMD" width="8" begin="21" end="14" resetval="0x0" description="Powers up/down the SATA_PHY_TX and SATA_PHY_RX modules. 0x0: Powers down SATA_PHY_TX and SATA_PHY_RX 0x1: Powers up SATA_PHY_RX 0x2: Powers up SATA_PHY_TX 0x3: Powers up SATA_PHY_TX and SATA_PHY_RX 0x4-0xFF: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="14" begin="13" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_MASK_1" acronym="CTRL_CORE_BANDGAP_MASK_1" offset="0x380" width="32" description="bgap_mask">
+    <bitfield id="SIDLEMODE" width="2" begin="31" end="30" resetval="0x0" description="sidlemode for bandgap 0x0 = No Idle 0x1 = Force Idle 0x2 = Smart Idle 0x3 = Reserved" range="" rwaccess="RW"/>
+    <bitfield id="COUNTER_DELAY" width="3" begin="29" end="27" resetval="0x0" description="Counter delay 0x0 = Imediat 0x1 = Delay of 1ms 0x2 = Delay of 10ms 0x3 = Delay of 100ms 0x4 = Delay of 250ms 0x5 = Delay of 500ms" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="3" begin="26" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="FREEZE_CORE" width="1" begin="23" end="23" resetval="0x0" description="Freeze the FIFO CORE 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="FREEZE_GPU" width="1" begin="22" end="22" resetval="0x0" description="Freeze the FIFO GPU 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="FREEZE_MPU" width="1" begin="21" end="21" resetval="0x0" description="Freeze the FIFO MPU 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="CLEAR_CORE" width="1" begin="20" end="20" resetval="0x0" description="Reset the FIFO CORE 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="CLEAR_GPU" width="1" begin="19" end="19" resetval="0x0" description="Reset the FIFO GPU 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="CLEAR_MPU" width="1" begin="18" end="18" resetval="0x0" description="Reset the FIFO MPU 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="12" begin="17" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MASK_HOT_CORE" width="1" begin="5" end="5" resetval="0x0" description="Mask for hot event CORE 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
+    <bitfield id="MASK_COLD_CORE" width="1" begin="4" end="4" resetval="0x0" description="Mask for cold event CORE 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
+    <bitfield id="MASK_HOT_GPU" width="1" begin="3" end="3" resetval="0x0" description="Mask for hot event GPU 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
+    <bitfield id="MASK_COLD_GPU" width="1" begin="2" end="2" resetval="0x0" description="Mask for cold event GPU 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
+    <bitfield id="MASK_HOT_MPU" width="1" begin="1" end="1" resetval="0x0" description="Mask for hot event MPU 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
+    <bitfield id="MASK_COLD_MPU" width="1" begin="0" end="0" resetval="0x0" description="Mask for cold event MPU 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_THRESHOLD_MPU" acronym="CTRL_CORE_BANDGAP_THRESHOLD_MPU" offset="0x384" width="32" description="BGAP THRESHOLD MPU">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_HOT_MPU" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_COLD_MPU" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_THRESHOLD_GPU" acronym="CTRL_CORE_BANDGAP_THRESHOLD_GPU" offset="0x388" width="32" description="BGAP THRESHOLD MM">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_HOT_GPU" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_COLD_GPU" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_THRESHOLD_CORE" acronym="CTRL_CORE_BANDGAP_THRESHOLD_CORE" offset="0x38C" width="32" description="BGAP THRESHOLD CORE">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_HOT_CORE" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_COLD_CORE" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_TSHUT_MPU" acronym="CTRL_CORE_BANDGAP_TSHUT_MPU" offset="0x390" width="32" description="BGAP TSHUT THRESHOLD MPU">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_HOT_MPU" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_COLD_MPU" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_TSHUT_GPU" acronym="CTRL_CORE_BANDGAP_TSHUT_GPU" offset="0x394" width="32" description="BGAP TSHUT THRESHOLD GPU">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_HOT_GPU" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_COLD_GPU" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_TSHUT_CORE" acronym="CTRL_CORE_BANDGAP_TSHUT_CORE" offset="0x398" width="32" description="BGAP TSHUT THRESHOLD CORE">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_HOT_CORE" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_COLD_CORE" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_STATUS_1" acronym="CTRL_CORE_BANDGAP_STATUS_1" offset="0x3A8" width="32" description="BGAP STATUS">
+    <bitfield id="ALERT" width="1" begin="31" end="31" resetval="0x0" description="Alert temperature when '1'" range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="25" begin="30" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="HOT_CORE" width="1" begin="5" end="5" resetval="0x0" description="Event for hot temperature mpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+    <bitfield id="COLD_CORE" width="1" begin="4" end="4" resetval="0x0" description="Event for cold temperature mpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+    <bitfield id="HOT_GPU" width="1" begin="3" end="3" resetval="0x0" description="Event for hot temperature gpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+    <bitfield id="COLD_GPU" width="1" begin="2" end="2" resetval="0x0" description="Event for cold temperature gpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+    <bitfield id="HOT_MPU" width="1" begin="1" end="1" resetval="0x0" description="Event for hot temperature core bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+    <bitfield id="COLD_MPU" width="1" begin="0" end="0" resetval="0x0" description="Event for cold temperature core bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_SATA_EXT_MODE" acronym="CTRL_CORE_SATA_EXT_MODE" offset="0x3AC" width="32" description="SATA EXTENDED MODE">
+    <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="SATA_EXTENDED_MODE" width="1" begin="0" end="0" resetval="0x0" description="sata extended mode 0x0 = no extended mode 0x1 = extended mode" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_MPU_0" acronym="CTRL_CORE_DTEMP_MPU_0" offset="0x3C0" width="32" description="TAGGED TEMPERATURE MPU DOMAIN. Most recent sample">
+    <bitfield id="DTEMP_TAG_MPU_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_MPU_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_MPU_1" acronym="CTRL_CORE_DTEMP_MPU_1" offset="0x3C4" width="32" description="TAGGED TEMPERATURE MPU DOMAIN">
+    <bitfield id="DTEMP_TAG_MPU_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_MPU_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_MPU_2" acronym="CTRL_CORE_DTEMP_MPU_2" offset="0x3C8" width="32" description="TAGGED TEMPERATURE MPU DOMAIN">
+    <bitfield id="DTEMP_TAG_MPU_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_MPU_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_MPU_3" acronym="CTRL_CORE_DTEMP_MPU_3" offset="0x3CC" width="32" description="TAGGED TEMPERATURE MPU DOMAIN">
+    <bitfield id="DTEMP_TAG_MPU_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_MPU_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_MPU_4" acronym="CTRL_CORE_DTEMP_MPU_4" offset="0x3D0" width="32" description="TAGGED TEMPERATURE MPU DOMAIN. Oldest sample">
+    <bitfield id="DTEMP_TAG_MPU_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_MPU_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_GPU_0" acronym="CTRL_CORE_DTEMP_GPU_0" offset="0x3D4" width="32" description="TAGGED TEMPERATURE GPU DOMAIN. Most recent sample.">
+    <bitfield id="DTEMP_TAG_GPU_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_GPU_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_GPU_1" acronym="CTRL_CORE_DTEMP_GPU_1" offset="0x3D8" width="32" description="TAGGED TEMPERATURE GPU DOMAIN.">
+    <bitfield id="DTEMP_TAG_GPU_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_GPU_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_GPU_2" acronym="CTRL_CORE_DTEMP_GPU_2" offset="0x3DC" width="32" description="TAGGED TEMPERATURE GPU DOMAIN.">
+    <bitfield id="DTEMP_TAG_GPU_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_GPU_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_GPU_3" acronym="CTRL_CORE_DTEMP_GPU_3" offset="0x3E0" width="32" description="TAGGED TEMPERATURE GPU DOMAIN.">
+    <bitfield id="DTEMP_TAG_GPU_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_GPU_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_GPU_4" acronym="CTRL_CORE_DTEMP_GPU_4" offset="0x3E4" width="32" description="TAGGED TEMPERATURE GPU DOMAIN. Oldest sample.">
+    <bitfield id="DTEMP_TAG_GPU_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_GPU_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_CORE_0" acronym="CTRL_CORE_DTEMP_CORE_0" offset="0x3E8" width="32" description="TAGGED TEMPERATURE CORE DOMAIN. Most recent sample.">
+    <bitfield id="DTEMP_TAG_CORE_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_CORE_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_CORE_1" acronym="CTRL_CORE_DTEMP_CORE_1" offset="0x3EC" width="32" description="TAGGED TEMPERATURE CORE DOMAIN">
+    <bitfield id="DTEMP_TAG_CORE_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_CORE_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_CORE_2" acronym="CTRL_CORE_DTEMP_CORE_2" offset="0x3F0" width="32" description="TAGGED TEMPERATURE CORE DOMAIN">
+    <bitfield id="DTEMP_TAG_CORE_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_CORE_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_CORE_3" acronym="CTRL_CORE_DTEMP_CORE_3" offset="0x3F4" width="32" description="TAGGED TEMPERATURE CORE DOMAIN">
+    <bitfield id="DTEMP_TAG_CORE_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_CORE_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_CORE_4" acronym="CTRL_CORE_DTEMP_CORE_4" offset="0x3F8" width="32" description="TAGGED TEMPERATURE CORE DOMAIN. Oldest sample.">
+    <bitfield id="DTEMP_TAG_CORE_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_CORE_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_SMA_SW_0" acronym="CTRL_CORE_SMA_SW_0" offset="0x3FC" width="32" description="OCP Spare Register">
+    <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="SATA_PLL_SOFT_RESET" width="1" begin="18" end="18" resetval="0x0" description="Software reset control for SATA PLL. When this bit is set the SATA PLL goes into reset." range="" rwaccess="RW">
+      <bitenum value="0" id="RST_NOT_ACTIVE" token="SATA_PLL_SOFT_RESET_0" description="Reset is not active for SATA controller"/>
+      <bitenum value="1" id="RST_ACTIVE" token="SATA_PLL_SOFT_RESET_1" description="Reset is active for SATA controller"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="13" begin="17" end="5" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="HWOBS_DCC_SDL2_SIG_OUT" width="1" begin="4" end="4" resetval="0x0" description="HWOBS select for DCC SDL2 output. 0x0: SDL2 clock output would not be sent to HWOBS pin. 0x1: SDL2 clock output would be sent to the DMM reset HWOBS pin." range="" rwaccess="RW"/>
+    <bitfield id="I2C1_CLK_EN" width="1" begin="3" end="3" resetval="0x0" description="Enable I2C1 clock. 0x0: I2C1 clock depends on PRCM operation. 0x1: Enable I2C1 clock irrespective of I2C1 operation state." range="" rwaccess="RW"/>
+    <bitfield id="ISO_CTRL_IO" width="1" begin="2" end="2" resetval="0x0" description="ISO control for the IO pads." range="" rwaccess="RW">
+      <bitenum value="0" id="ISO_ENBL_NOT_SET" token="ISO_CTRL_IO_0" description="ISO enable for pads is not set"/>
+      <bitenum value="1" id="ISO_ENBL_SET" token="ISO_CTRL_IO_1" description="ISO enable for pads is set"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="1" begin="1" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CKE_GATING_CTRL" width="1" begin="0" end="0" resetval="0x0" description="Forces the EMIF1 CKE pad to tri-state." range="" rwaccess="RW">
+      <bitenum value="0" id="CKE_NOT_IN_TRI_STATE" token="CKE_GATING_CTRL_0" description="The CKE pad is not in tri-state and can be controlled by EMIF1"/>
+      <bitenum value="1" id="CKE_IN_TRI_STATE" token="CKE_GATING_CTRL_1" description="The CKE pad is in tri-state"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_MREQDOMAIN_EXP4" acronym="CTRL_CORE_MREQDOMAIN_EXP4" offset="0x400" width="32" description="MReqDomain value configuration register.">
+    <bitfield id="MREQDOMAIN_EXP4_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
+    <bitfield id="RESERVED" width="4" begin="30" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_DSP1_MDMA" width="3" begin="26" end="24" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that:" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_VPE_P0" width="3" begin="23" end="21" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_GMACSW" width="3" begin="20" end="18" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_MMU2" width="3" begin="17" end="15" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_MMU1" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_PCIESS2" width="3" begin="11" end="9" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_PCIESS1" width="3" begin="8" end="6" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="3" begin="5" end="3" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_MLB" width="3" begin="2" end="0" resetval="0x0" description="see MREQDOMAIN_DSP1_MDMA Description" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MREQDOMAIN_EXP5" acronym="CTRL_CORE_MREQDOMAIN_EXP5" offset="0x404" width="32" description="MReqDomain value configuration register.">
+    <bitfield id="MREQDOMAIN_EXP5_LOCK" width="1" begin="31" end="31" resetval="0x0" description="Lock bit. When high register cannot be written again" range="" rwaccess="RW Woco"/>
+    <bitfield id="RESERVED" width="10" begin="30" end="21" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_PRUSS2_PRU1" width="3" begin="20" end="18" resetval="0x0" description="This field allows to specify to which DOMAIN the initiator belongs to by configuring at initiator port level a fixed MReqDomain value such that: MreqDomain[2:0]= 0b000 = DOMAIN0 MreqDomain[2:0]= 0b001 = DOMAIN1 MreqDomain[2:0]= 0b010 = DOMAIN2 MreqDomain[2:0]= 0b011 = DOMAIN3 MreqDomain[2:0]= 0b100 = DOMAIN4 MreqDomain[2:0]= 0b101 = DOMAIN5 MreqDomain[2:0]= 0b110 = DOMAIN6 MreqDomain[2:0]= 0b111 = DOMAIN7" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_PRUSS1_PRU1" width="3" begin="17" end="15" resetval="0x0" description="see MREQDOMAIN_PRUSS2_PRU1 Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_GPU_P1" width="3" begin="14" end="12" resetval="0x0" description="see MREQDOMAIN_PRUSS2_PRU1 Description" range="" rwaccess="RW"/>
+    <bitfield id="MREQDOMAIN_VPE_P1" width="3" begin="11" end="9" resetval="0x0" description="see MREQDOMAIN_PRUSS2_PRU1 Description" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="8" end="3" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MREQDOMAIN_VIP1_P1" width="3" begin="2" end="0" resetval="0x0" description="see MREQDOMAIN_PRUSS2_PRU1 Description" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_SEC_ERR_STATUS_FUNC_2" acronym="CTRL_CORE_SEC_ERR_STATUS_FUNC_2" offset="0x414" width="32" description="Firewall Error Status functional Register 2">
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TC1_EDMA_FW_ERROR" width="1" begin="26" end="26" resetval="0x0" description="EDMA TC1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="3" begin="25" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="QSPI_FW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="QSPI firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="PRUSS2_FW_ERROR" width="1" begin="21" end="21" resetval="0x0" description="PRU-ICSS2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="PRUSS1_FW_ERROR" width="1" begin="20" end="20" resetval="0x0" description="PRU-ICSS1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="2" begin="19" end="18" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TPCC_EDMA_FW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="EDMA TPCC firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="TC0_EDMA_FW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="EDMA TC0 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MCASP3_FW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="McASP3 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="MCASP2_FW_ERROR" width="1" begin="12" end="12" resetval="0x0" description="McASP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="MCASP1_FW_ERROR" width="1" begin="11" end="11" resetval="0x0" description="McASP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="VCP2_FW_ERROR" width="1" begin="10" end="10" resetval="0x0" description="VCP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="VCP1_FW_ERROR" width="1" begin="9" end="9" resetval="0x0" description="VCP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="PCIESS2_FW_ERROR" width="1" begin="8" end="8" resetval="0x0" description="PCIeSS2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="PCIESS1_FW_ERROR" width="1" begin="7" end="7" resetval="0x0" description="PCIeSS1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="IPU2_FW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IPU2 firewall. 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_PERIPH3_FW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="L4 periph3 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_PERIPH2_FW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="L4 periph2 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="3" begin="3" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_FW_ERROR" width="1" begin="0" end="0" resetval="0x0" description="DSP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+  </register>
+  <register id="CTRL_CORE_SEC_ERR_STATUS_DEBUG_2" acronym="CTRL_CORE_SEC_ERR_STATUS_DEBUG_2" offset="0x41C" width="32" description="Firewall Error Status debug Register 2">
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TC1_EDMA_DBGFW_ERROR" width="1" begin="26" end="26" resetval="0x0" description="EDMA TC1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="3" begin="25" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="QSPI_DBGFW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="QSPI debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="PRUSS2_DBGFW_ERROR" width="1" begin="21" end="21" resetval="0x0" description="PRU-ICSS2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="PRUSS1_DBGFW_ERROR" width="1" begin="20" end="20" resetval="0x0" description="PRU-ICSS1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="2" begin="19" end="18" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TPCC_EDMA_DBGFW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="EDMA TPCC debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="TC0_EDMA_DBGFW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="EDMA TC0 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MCASP3_DBGFW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="McASP3 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="MCASP2_DBGFW_ERROR" width="1" begin="12" end="12" resetval="0x0" description="McASP2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="MCASP1_DBGFW_ERROR" width="1" begin="11" end="11" resetval="0x0" description="McASP1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="VCP2_DBGFW_ERROR" width="1" begin="10" end="10" resetval="0x0" description="VCP2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="VCP1_DBGFW_ERROR" width="1" begin="9" end="9" resetval="0x0" description="VCP1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="PCIESS2_DBGFW_ERROR" width="1" begin="8" end="8" resetval="0x0" description="PCIeSS2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="PCIESS1_DBGFW_ERROR" width="1" begin="7" end="7" resetval="0x0" description="PCIeSS1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="IPU2_DBGFW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IPU2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_PERIPH3_DBGFW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="L4 periph3 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="L4_PERIPH2_DBGFW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="L4 periph2 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+    <bitfield id="RESERVED" width="3" begin="3" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_DBGFW_ERROR" width="1" begin="0" end="0" resetval="0x0" description="DSP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>
+  </register>
+  <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_1" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_1" offset="0x420" width="32" description="Register for priority settings for EMIF arbitration">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="MPU priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="9" begin="27" end="19" resetval="0x88" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_MDMA_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="DSP1 MDMA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_CFG_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="DSP1 CFG priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_EDMA_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="DSP1 EDMA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="7" end="0" resetval="0x44" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_2" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_2" offset="0x424" width="32" description="Register for priority settings for EMIF arbitration">
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x4" description="" range="" rwaccess="R"/>
+    <bitfield id="IVA_ICONT1_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="IVA ICONT1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="21" begin="23" end="3" resetval="0x8888" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_PRU0_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="PRU-ICSS1 PRU0 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_3" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_3" offset="0x428" width="32" description="Register for priority settings for EMIF arbitration">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_PRU1_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="PRU-ICSS1 PRU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_PRU0_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="PRU-ICSS2 PRU0 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_PRU1_EMIF_PRIORITY" width="3" begin="22" end="20" resetval="0x4" description="PRU-ICSS2 PRU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="IPU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="IPU2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="DMA SYSTEM priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="7" end="3" resetval="0x8" description="" range="" rwaccess="R"/>
+    <bitfield id="EDMA_TC0_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="EDMA TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_4" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_4" offset="0x42C" width="32" description="Register for priority settings for EMIF arbitration">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="EDMA_TC1_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="EDMA TC1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSS_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="DSS priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MLB_MMU1_EMIF_PRIORITY" width="3" begin="22" end="20" resetval="0x4" description="MLB, MMU1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PCIESS1_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="PCIeSS1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PCIESS2_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="PCIeSS2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="VIP1_P1_P2_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="VIP1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="7" end="0" resetval="0x44" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_5" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_5" offset="0x430" width="32" description="Register for priority settings for EMIF arbitration">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="VPE_P1_P2_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="VPE priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MMC1_GPU_P1_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="MMC1, GPU P1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MMC2_GPU_P2_EMIF_PRIORITY" width="3" begin="22" end="20" resetval="0x4" description="MMC2, GPU P2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="BB2D_P1_P2_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="BB2D priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GMAC_SW_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="GMAC_SW priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="USB1_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="USB1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="USB2_EMIF_PRIORITY" width="3" begin="6" end="4" resetval="0x4" description="USB2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="3" end="3" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="USB3_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="USB3 priority setting 0x0 = highest priority 0x7 = lowest priorty" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_6" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_6" offset="0x434" width="32" description="Register for priority settings for EMIF arbitration">
+    <bitfield id="RESERVED" width="17" begin="31" end="15" resetval="0x8888" description="" range="" rwaccess="R"/>
+    <bitfield id="SATA_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="SATA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="12" begin="11" end="0" resetval="0x444" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_1" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_1" offset="0x43C" width="32" description="Register for pressure settings for L3 arbitration">
+    <bitfield id="RESERVED" width="4" begin="31" end="28" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_L3_PRESSURE" width="2" begin="27" end="26" resetval="0x0" description="MPU pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="25" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_CFG_L3_PRESSURE" width="2" begin="18" end="17" resetval="0x0" description="DSP1 CFG pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="17" begin="16" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_2" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_2" offset="0x440" width="32" description="Register for pressure settings for L3 arbitration">
+    <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CSI2_1_L3_PRESSURE" width="2" begin="19" end="18" resetval="0x0" description="CSI2_1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CSI2_2_L3_PRESSURE" width="2" begin="16" end="15" resetval="0x0" description="CSI2_2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="14" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_L3_PRESSURE" width="2" begin="13" end="12" resetval="0x0" description="IPU1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_L3_PRESSURE" width="2" begin="10" end="9" resetval="0x0" description="IPU2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="8" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_PRU0_L3_PRESSURE" width="2" begin="7" end="6" resetval="0x0" description="PRU-ICSS1 PRU0 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="5" end="5" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_PRU1_L3_PRESSURE" width="2" begin="4" end="3" resetval="0x0" description="PRU-ICSS1 PRU1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="2" end="2" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_PRU0_L3_PRESSURE" width="2" begin="1" end="0" resetval="0x0" description="PRU-ICSS2 PRU0 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_3" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_3" offset="0x444" width="32" description="Register for pressure settings for L3 arbitration">
+    <bitfield id="RESERVED" width="4" begin="31" end="28" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_PRU1_L3_PRESSURE" width="2" begin="27" end="26" resetval="0x0" description="PRU-ICSS2 PRU1 pressure setting0x0 = lowest enum=LOWEST . 0x3 = highest enum=HIGHEST ." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="26" begin="25" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_4" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_4" offset="0x448" width="32" description="Register for pressure settings for L3 arbitration">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="GPU_P1_L3_PRESSURE" width="2" begin="24" end="23" resetval="0x0" description="GPU P1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="22" end="22" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPU_P2_L3_PRESSURE" width="2" begin="21" end="20" resetval="0x0" description="GPU P2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="20" begin="19" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_5" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_5" offset="0x44C" width="32" description="Register for pressure settings for L3 arbitration">
+    <bitfield id="RESERVED" width="27" begin="31" end="5" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="SATA_L3_PRESSURE" width="2" begin="4" end="3" resetval="0x0" description="SATA pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="2" end="2" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MMC1_L3_PRESSURE" width="2" begin="1" end="0" resetval="0x0" description="MMC1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_6" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_6" offset="0x450" width="32" description="Register for pressure settings for L3 arbitration">
+    <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MMC2_L3_PRESSURE" width="2" begin="18" end="17" resetval="0x0" description="MMC2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="USB1_L3_PRESSURE" width="2" begin="16" end="15" resetval="0x0" description="USB1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="14" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="USB2_L3_PRESSURE" width="2" begin="13" end="12" resetval="0x0" description="USB2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="USB3_L3_PRESSURE" width="2" begin="10" end="9" resetval="0x0" description="USB3 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0" offset="0x458" width="32" description="Standard Fuse OPP VDD_iva [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_IVA_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1" offset="0x45C" width="32" description="Standard Fuse OPP VDD_iva [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_IVA_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2" offset="0x460" width="32" description="Standard Fuse OPP VDD_iva [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_IVA_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3" offset="0x464" width="32" description="Standard Fuse OPP VDD_iva [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_IVA_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4" offset="0x468" width="32" description="Standard Fuse OPP VDD_iva [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_IVA_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL" offset="0x46C" width="32" description="DSPEVE Voltage Body Bias LDO Control register">
+    <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOVBBDSPEVE_FBB_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" range="" rwaccess="RW"/>
+    <bitfield id="LDOVBBDSPEVE_FBB_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Forward Body Bias voltage value" range="" rwaccess="R"/>
+    <bitfield id="LDOVBBDSPEVE_FBB_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_x[24:20] VSETABB bit fields. This value applies if LDOVBBDSPEVE_FBB_MUX_CTRL is set to 0x1." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL" offset="0x470" width="32" description="IVA Voltage Body Bias LDO Control register">
+    <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOVBBIVA_FBB_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" range="" rwaccess="RW"/>
+    <bitfield id="LDOVBBIVA_FBB_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Forward Body Bias voltage value" range="" rwaccess="R"/>
+    <bitfield id="LDOVBBIVA_FBB_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_x[24:20] VSETABB bit fields. This value applies if LDOVBBIVA_FBB_MUX_CTRL is set to 0x1." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_UID_0" acronym="CTRL_CORE_CUST_FUSE_UID_0" offset="0x4E8" width="32" description="Customer Fuse keys. UID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_UID_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_UID_1" acronym="CTRL_CORE_CUST_FUSE_UID_1" offset="0x4EC" width="32" description="Customer Fuse keys. UID [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_UID_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_UID_2" acronym="CTRL_CORE_CUST_FUSE_UID_2" offset="0x4F0" width="32" description="Customer Fuse keys. UID [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_UID_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_UID_3" acronym="CTRL_CORE_CUST_FUSE_UID_3" offset="0x4F4" width="32" description="Customer Fuse keys. UID [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_UID_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_UID_4" acronym="CTRL_CORE_CUST_FUSE_UID_4" offset="0x4F8" width="32" description="Customer Fuse keys. UID [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_UID_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_UID_5" acronym="CTRL_CORE_CUST_FUSE_UID_5" offset="0x4FC" width="32" description="Customer Fuse keys. UID [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_UID_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_UID_6" acronym="CTRL_CORE_CUST_FUSE_UID_6" offset="0x500" width="32" description="Customer Fuse keys. UID [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_UID_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_PCIE_ID_0" acronym="CTRL_CORE_CUST_FUSE_PCIE_ID_0" offset="0x508" width="32" description="Customer Fuse keys. PCIe ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_PCIE_ID_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_USB_ID_0" acronym="CTRL_CORE_CUST_FUSE_USB_ID_0" offset="0x510" width="32" description="Customer Fuse keys. USB ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_USB_ID_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_MAC_ID_SW_0" acronym="CTRL_CORE_MAC_ID_SW_0" offset="0x514" width="32" description="Standard Fuse keys, MAC ID_1 [63:32].">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_MAC_ID_SW_0" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 0. Bits [23:16] contain the 4th octet of the MAC address. Bits [15:8] contain the 5th octet of the MAC address. Bits [7:0] contain the last (6th) octet of the MAC address." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_MAC_ID_SW_1" acronym="CTRL_CORE_MAC_ID_SW_1" offset="0x518" width="32" description="Standard Fuse keys, MAC ID_1 [31:0].">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_MAC_ID_SW_1" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 0. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_MAC_ID_SW_2" acronym="CTRL_CORE_MAC_ID_SW_2" offset="0x51C" width="32" description="Standard Fuse keys, MAC ID_2 [63:32].">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_MAC_ID_SW_2" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the 4th octet of the MAC address. Bits [15:8] contain the 5th octet of the MAC address. Bits [7:0] contain the last (6th) octet of the MAC address." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_MAC_ID_SW_3" acronym="CTRL_CORE_MAC_ID_SW_3" offset="0x520" width="32" description="Standard Fuse keys, MAC ID_2 [31:0].">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_MAC_ID_SW_3" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_SMA_SW_1" acronym="CTRL_CORE_SMA_SW_1" offset="0x534" width="32" description="OCP Spare Register">
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="RGMII2_ID_MODE_N" width="1" begin="26" end="26" resetval="0x0" description="Ethernet RGMII port 2 internal delay on transmit (SR2.x) 0x0: Internal delay enabled 0x1: Internal delay disabled" range="" rwaccess="RW"/>
+    <bitfield id="RGMII1_ID_MODE_N" width="1" begin="25" end="25" resetval="0x0" description="Ethernet RGMII port 1 internal delay on transmit (SR2.x) 0x0: Internal delay enabled 0x1: Internal delay disabled" range="" rwaccess="RW"/>
+    <bitfield id="DSS_CH2_ON_OFF" width="1" begin="24" end="24" resetval="0x0" description="DSS Channel 2 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH2_RF" range="" rwaccess="RW"/>
+    <bitfield id="DSS_CH1_ON_OFF" width="1" begin="23" end="23" resetval="0x0" description="DSS Channel 1 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH1_RF" range="" rwaccess="RW"/>
+    <bitfield id="DSS_CH0_ON_OFF" width="1" begin="22" end="22" resetval="0x0" description="DSS Channel 0 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH0_RF" range="" rwaccess="RW"/>
+    <bitfield id="DSS_CH2_IPC" width="1" begin="21" end="21" resetval="0x0" description="DSS Channel 2 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" range="" rwaccess="RW"/>
+    <bitfield id="DSS_CH1_IPC" width="1" begin="20" end="20" resetval="0x0" description="DSS Channel 1 IPC controlDSS Channel 2 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" range="" rwaccess="RW"/>
+    <bitfield id="DSS_CH0_IPC" width="1" begin="19" end="19" resetval="0x0" description="DSS Channel 0 IPC controlDSS Channel 2 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" range="" rwaccess="RW"/>
+    <bitfield id="DSS_CH2_RF" width="1" begin="18" end="18" resetval="0x0" description="DSS Channel 2 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1)" range="" rwaccess="RW"/>
+    <bitfield id="DSS_CH1_RF" width="1" begin="17" end="17" resetval="0x0" description="DSS Channel 1 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1)" range="" rwaccess="RW"/>
+    <bitfield id="DSS_CH0_RF" width="1" begin="16" end="16" resetval="0x0" description="DSS Channel 0 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1)" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="VIP3_CLK_INV_PORT_1A" width="1" begin="10" end="10" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP5A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+    <bitfield id="VIP3_CLK_INV_PORT_2A" width="1" begin="9" end="9" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP6A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+    <bitfield id="VPE_CLK_DIV_BY_2_EN" width="1" begin="8" end="8" resetval="0x0" description="Selects alternative clock source for VPE. 0x0: Default clock source from DPLL_CORE is selected 0x1: Alternative clock source from DPLL_VIDEO1 is selected" range="" rwaccess="RW"/>
+    <bitfield id="VIP2_CLK_INV_PORT_2B" width="1" begin="7" end="7" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP4B. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+    <bitfield id="VIP2_CLK_INV_PORT_1B" width="1" begin="6" end="6" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP3B. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+    <bitfield id="VIP2_CLK_INV_PORT_2A" width="1" begin="5" end="5" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP4A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+    <bitfield id="VIP2_CLK_INV_PORT_1A" width="1" begin="4" end="4" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP3A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+    <bitfield id="VIP1_CLK_INV_PORT_2B" width="1" begin="3" end="3" resetval="0x0" description="VIP1 Slice 1 Clock inversion for Port B enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+    <bitfield id="VIP1_CLK_INV_PORT_1B" width="1" begin="2" end="2" resetval="0x0" description="VIP1 Slice 0 Clock inversion for Port B enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+    <bitfield id="VIP1_CLK_INV_PORT_2A" width="1" begin="1" end="1" resetval="0x0" description="VIP1 Slice 1 Clock inversion for Port A enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+    <bitfield id="VIP1_CLK_INV_PORT_1A" width="1" begin="0" end="0" resetval="0x0" description="VIP1 Slice 0 Clock inversion for Port A enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSS_PLL_CONTROL" acronym="CTRL_CORE_DSS_PLL_CONTROL" offset="0x538" width="32" description="DSS PLLs Mux control register">
+    <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>
+    <bitfield id="SDVENC_CLK_SELECTION" width="2" begin="10" end="9" resetval="0x1" description="SDVENC_CLK mux configuration 0x0 = HDMI_CLK 0x1 = DPLL_VIDEO1_HSDIVIDER_clkout3" range="" rwaccess="RW"/>
+    <bitfield id="DSI1_C_CLK1_SELECTION" width="2" begin="8" end="7" resetval="0x1" description="DSI1_C_CLK1 mux configuration 0x0 = Reserved 0x1 = DPLL_VIDEO1 0x2 = DPLL_HDMI" range="" rwaccess="RW"/>
+    <bitfield id="DSI1_B_CLK1_SELECTION" width="2" begin="6" end="5" resetval="0x1" description="DSI1_B_CLK1 mux configuration 0x0 = DPLL_VIDEO1 0x1 = Reserved 0x2 = DPLL_HDMI 0x3 = DPLL_ABE" range="" rwaccess="RW"/>
+    <bitfield id="DSI1_A_CLK1_SELECTION" width="2" begin="4" end="3" resetval="0x1" description="DSI1_A_CLK1 mux configuration 0x0 = DPLL_VIDEO1 0x1 = DPLL_HDMI" range="" rwaccess="RW"/>
+    <bitfield id="PLL_HDMI_DSS_CONTROL_DISABLE" width="1" begin="2" end="2" resetval="0x1" description="HDMI PLL disable 0x0 = PLL enabled 0x1 = PLL disabled" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="1" end="1" resetval="0x1" description="" range="" rwaccess="R"/>
+    <bitfield id="PLL_VIDEO1_DSS_CONTROL_DISABLE" width="1" begin="0" end="0" resetval="0x1" description="VIDEO1 PLL disable 0x0 = PLL enabled 0x1 = PLL disabled" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MMR_LOCK_1" acronym="CTRL_CORE_MMR_LOCK_1" offset="0x540" width="32" description="Register to lock memory region starting at address offset 0x0000 0100 and ending at address offset 0x0000 079F">
+    <bitfield id="MMR_LOCK_1" width="32" begin="31" end="0" resetval="0x1A1C8144" description="Lock value for region 0x0000 0100 to 0x0000 079F 0x1A1C8144 = lock value 0x2FF1AC2B = unlock value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MMR_LOCK_2" acronym="CTRL_CORE_MMR_LOCK_2" offset="0x544" width="32" description="Register to lock memory region starting at address offset 0x0000 07A0 and ending at address offset 0x0000 0D9F">
+    <bitfield id="MMR_LOCK_2" width="32" begin="31" end="0" resetval="0xFDF45530" description="Lock value for region 0x0000 07A0 to 0x0000 0D9F 0xFDF45530 = lock value 0xF757FDC0 = unlock value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MMR_LOCK_3" acronym="CTRL_CORE_MMR_LOCK_3" offset="0x548" width="32" description="Register to lock memory region starting at address offset 0x0000 0DA0 and ending at address offset 0x0000 0FFF">
+    <bitfield id="MMR_LOCK_3" width="32" begin="31" end="0" resetval="0x1AE6E320" description="Lock value for region 0x0000 0DA0 to 0x0000 0FFF 0x1AE6E320 = lock value 0xE2BC3A6D = unlock value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MMR_LOCK_4" acronym="CTRL_CORE_MMR_LOCK_4" offset="0x54C" width="32" description="Register to lock memory region starting at address offset 0x0000 1000 and ending at address offset 0x0000 13FF">
+    <bitfield id="MMR_LOCK_4" width="32" begin="31" end="0" resetval="0x2FFA927C" description="Lock value for region 0x0000 1000 to 0x0000 13FF 0x2FFA927C = lock value 0x1EBF131D = unlock value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MMR_LOCK_5" acronym="CTRL_CORE_MMR_LOCK_5" offset="0x550" width="32" description="Register to lock memory region starting at address offset 0x0000 1400 and ending at address offset 0x0000 1FFF">
+    <bitfield id="MMR_LOCK_5" width="32" begin="31" end="0" resetval="0x143F832C" description="Lock value for region 0x0000 1400 to 0x0000 1FFF 0x143F832C = lock value 0x6F361E05 = unlock value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_IO_1" acronym="CTRL_CORE_CONTROL_IO_1" offset="0x554" width="32" description="Register to configure some IP level signals">
+    <bitfield id="RESERVED" width="11" begin="31" end="21" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MMU2_DISABLE" width="1" begin="20" end="20" resetval="0x0" description="MMU2 DISABLE setting" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="3" begin="19" end="17" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MMU1_DISABLE" width="1" begin="16" end="16" resetval="0x0" description="MMU1 DISABLE setting" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TC1_DEFAULT_BURST_SIZE" width="2" begin="13" end="12" resetval="0x3" description="EDMA TC1 Default Burst Size (DBS) setting 0x0: 16 byte burst 0x1: 32 byte burst 0x2: 64 byte burst 0x3: 128 byte burst" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="2" begin="11" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TC0_DEFAULT_BURST_SIZE" width="2" begin="9" end="8" resetval="0x3" description="EDMA TC0 Default Burst Size (DBS) setting 0x0: 16 byte burst 0x1: 32 byte burst 0x2: 64 byte burst 0x3: 128 byte burst" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GMII2_SEL" width="2" begin="5" end="4" resetval="0x0" description="GMII2 selection setting 0x0: GMII/MII 0x1: RMII 0x2: RGMII 0x3: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="2" begin="3" end="2" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GMII1_SEL" width="2" begin="1" end="0" resetval="0x0" description="GMII1 selection setting 0x0: GMII/MII 0x1: RMII 0x2: RGMII 0x3: Reserved" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_IO_2" acronym="CTRL_CORE_CONTROL_IO_2" offset="0x558" width="32" description="Register to configure some IP level signals">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GMAC_RESET_ISOLATION_ENABLE" width="1" begin="23" end="23" resetval="0x0" description="Reset isolation enable setting 0x0 = Reset is not isolated 0x1 = Reset is isolated" range="" rwaccess="RW"/>
+    <bitfield id="PWMSS3_TBCLKEN" width="1" begin="22" end="22" resetval="0x0" description="PWMSS3 CLOCK ENABLE setting" range="" rwaccess="RW"/>
+    <bitfield id="PWMSS2_TBCLKEN" width="1" begin="21" end="21" resetval="0x0" description="PWMSS2 CLOCK ENABLE setting" range="" rwaccess="RW"/>
+    <bitfield id="PWMSS1_TBCLKEN" width="1" begin="20" end="20" resetval="0x0" description="PWMSS1 CLOCK ENABLE setting" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="19" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PCIE_1LANE_2LANE_SELECTION" width="1" begin="13" end="13" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="2" begin="12" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="QSPI_MEMMAPPED_CS" width="3" begin="10" end="8" resetval="0x0" description="QSPI CS MAPPING setting. 0x0: The QSPI configuration registers are accessed 0x1: An external device connected to CS0 is accessed 0x2: An external device connected to CS1 is accessed 0x3: An external device connected to CS2 is accessed 0x4-0x7: An external device connected to CS3 is accessed" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DCAN2_RAMINIT_START" width="1" begin="5" end="5" resetval="0x0" description="DCAN2 RAM INIT START setting To initialize DCAN2 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>
+    <bitfield id="DSS_DESHDCP_DISABLE" width="1" begin="4" end="4" resetval="0x0" description="DSS DESHDCP DISABLE setting" range="" rwaccess="RW"/>
+    <bitfield id="DCAN1_RAMINIT_START" width="1" begin="3" end="3" resetval="0x0" description="DCAN1 RAM INIT START setting To initialize DCAN1 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>
+    <bitfield id="DCAN2_RAMINIT_DONE" width="1" begin="2" end="2" resetval="0x0" description="DCAN2 RAM INIT DONE status" range="" rwaccess="RW"/>
+    <bitfield id="DCAN1_RAMINIT_DONE" width="1" begin="1" end="1" resetval="0x0" description="DCAN1 RAM INIT DONE status" range="" rwaccess="RW"/>
+    <bitfield id="DSS_DESHDCP_CLKEN" width="1" begin="0" end="0" resetval="0x0" description="DSS DESHDCP CLOCK ENABLE setting" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_DSP1_RST_VECT" acronym="CTRL_CORE_CONTROL_DSP1_RST_VECT" offset="0x55C" width="32" description="Register for storing DSP1 reset vector">
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DSP1_NUM_MM" width="3" begin="26" end="24" resetval="0x0" description="Number of DSP instances in the SoC 0x1 = 1 0x2 = 2" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="2" begin="23" end="22" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_RST_VECT" width="22" begin="21" end="0" resetval="0x0" description="DSP1 reset vector address" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE" offset="0x564" width="32" description="Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use.">
+    <bitfield id="RESERVED" width="16" begin="31" end="16" resetval="0x-" description="" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_DSPEVE_0" width="8" begin="15" end="8" resetval="0x-" description="Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_DSPEVE_1" width="8" begin="7" end="0" resetval="0x-" description="Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_IVA" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_IVA" offset="0x568" width="32" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">
+    <bitfield id="STD_FUSE_OPP_BGAP_IVA_0" width="8" begin="31" end="24" resetval="0x-" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_IVA_1" width="8" begin="23" end="16" resetval="0x-" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_IVA_2" width="8" begin="15" end="8" resetval="0x-" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_BGAP_IVA_3" width="8" begin="7" end="0" resetval="0x-" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL" offset="0x56C" width="32" description="DSPEVE SRAM LDO Control register">
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMDSPEVE_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">
+      <bitenum value="0" id="EFUSE" token="LDOSRAMDSPEVE_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>
+      <bitenum value="1" id="OCP" token="LDOSRAMDSPEVE_RETMODE_MUX_CTRL_1" description="Override value is used"/>
+    </bitfield>
+    <bitfield id="LDOSRAMDSPEVE_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMDSPEVE_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMDSPEVE_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">
+      <bitenum value="0" id="EFUSE" token="LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>
+      <bitenum value="1" id="OCP" token="LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_1" description="Override value is used"/>
+    </bitfield>
+    <bitfield id="LDOSRAMDSPEVE_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMDSPEVE_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL" offset="0x570" width="32" description="IVA SRAM LDO Control register">
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMIVA_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">
+      <bitenum value="0" id="EFUSE" token="LDOSRAMIVA_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>
+      <bitenum value="1" id="OCP" token="LDOSRAMIVA_RETMODE_MUX_CTRL_1" description="Override value is used"/>
+    </bitfield>
+    <bitfield id="LDOSRAMIVA_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMIVA_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMIVA_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">
+      <bitenum value="0" id="EFUSE" token="LDOSRAMIVA_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>
+      <bitenum value="1" id="OCP" token="LDOSRAMIVA_ACTMODE_MUX_CTRL_1" description="Override value is used"/>
+    </bitfield>
+    <bitfield id="LDOSRAMIVA_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMIVA_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_TEMP_SENSOR_DSPEVE" acronym="CTRL_CORE_TEMP_SENSOR_DSPEVE" offset="0x574" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
+    <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="BGAP_TMPSOFF_DSPEVE" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
+    <bitfield id="BGAP_EOCZ_DSPEVE" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_DSPEVE is valid." range="" rwaccess="R"/>
+    <bitfield id="BGAP_DTEMP_DSPEVE" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_TEMP_SENSOR_IVA" acronym="CTRL_CORE_TEMP_SENSOR_IVA" offset="0x578" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">
+    <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="BGAP_TMPSOFF_IVA" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>
+    <bitfield id="BGAP_EOCZ_IVA" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_IVA is valid." range="" rwaccess="R"/>
+    <bitfield id="BGAP_DTEMP_IVA" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_MASK_2" acronym="CTRL_CORE_BANDGAP_MASK_2" offset="0x57C" width="32" description="bgap_mask">
+    <bitfield id="RESERVED" width="9" begin="31" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="FREEZE_IVA" width="1" begin="22" end="22" resetval="0x0" description="Freeze the FIFO IVA 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="FREEZE_DSPEVE" width="1" begin="21" end="21" resetval="0x0" description="Freeze the FIFO DSPEVE 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="20" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CLEAR_IVA" width="1" begin="19" end="19" resetval="0x0" description="Reset the FIFO IVA 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="CLEAR_DSPEVE" width="1" begin="18" end="18" resetval="0x0" description="Reset the FIFO DSPEVE 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="14" begin="17" end="4" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MASK_HOT_IVA" width="1" begin="3" end="3" resetval="0x0" description="Mask for hot event IVA 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
+    <bitfield id="MASK_COLD_IVA" width="1" begin="2" end="2" resetval="0x0" description="Mask for cold event IVA 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
+    <bitfield id="MASK_HOT_DSPEVE" width="1" begin="1" end="1" resetval="0x0" description="Mask for hot event DSPEVE 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>
+    <bitfield id="MASK_COLD_DSPEVE" width="1" begin="0" end="0" resetval="0x0" description="Mask for cold event DSPEVE 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE" acronym="CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE" offset="0x580" width="32" description="BGAP THRESHOLD DSPEVE">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_HOT_DSPEVE" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_COLD_DSPEVE" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_THRESHOLD_IVA" acronym="CTRL_CORE_BANDGAP_THRESHOLD_IVA" offset="0x584" width="32" description="BGAP THRESHOLD IVA">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_HOT_IVA" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="THOLD_COLD_IVA" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" acronym="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" offset="0x588" width="32" description="BGAP TSHUT THRESHOLD IVA">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_HOT_DSPEVE" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_COLD_DSPEVE" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_TSHUT_IVA" acronym="CTRL_CORE_BANDGAP_TSHUT_IVA" offset="0x58C" width="32" description="BGAP TSHUT THRESHOLD IVA">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_HOT_IVA" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="TSHUT_COLD_IVA" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BANDGAP_STATUS_2" acronym="CTRL_CORE_BANDGAP_STATUS_2" offset="0x598" width="32" description="BGAP STATUS">
+    <bitfield id="RESERVED" width="28" begin="31" end="4" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="HOT_IVA" width="1" begin="3" end="3" resetval="0x0" description="Event for hot temperature iva bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+    <bitfield id="COLD_IVA" width="1" begin="2" end="2" resetval="0x0" description="Event for cold temperature iva bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+    <bitfield id="HOT_DSPEVE" width="1" begin="1" end="1" resetval="0x0" description="Event for hot temperature dspeve bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+    <bitfield id="COLD_DSPEVE" width="1" begin="0" end="0" resetval="0x0" description="Event for cold temperature dspeve bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_DSPEVE_0" acronym="CTRL_CORE_DTEMP_DSPEVE_0" offset="0x59C" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN. Most recent sample">
+    <bitfield id="DTEMP_TAG_DSPEVE_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_DSPEVE_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_DSPEVE_1" acronym="CTRL_CORE_DTEMP_DSPEVE_1" offset="0x5A0" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN">
+    <bitfield id="DTEMP_TAG_DSPEVE_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_DSPEVE_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_DSPEVE_2" acronym="CTRL_CORE_DTEMP_DSPEVE_2" offset="0x5A4" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN">
+    <bitfield id="DTEMP_TAG_DSPEVE_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_DSPEVE_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_DSPEVE_3" acronym="CTRL_CORE_DTEMP_DSPEVE_3" offset="0x5A8" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN">
+    <bitfield id="DTEMP_TAG_DSPEVE_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_DSPEVE_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_DSPEVE_4" acronym="CTRL_CORE_DTEMP_DSPEVE_4" offset="0x5AC" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN. Oldest sample">
+    <bitfield id="DTEMP_TAG_DSPEVE_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_DSPEVE_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_IVA_0" acronym="CTRL_CORE_DTEMP_IVA_0" offset="0x5B0" width="32" description="TAGGED TEMPERATURE IVA DOMAIN. Most recent sample">
+    <bitfield id="DTEMP_TAG_IVA_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_IVA_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_IVA_1" acronym="CTRL_CORE_DTEMP_IVA_1" offset="0x5B4" width="32" description="TAGGED TEMPERATURE IVA DOMAIN">
+    <bitfield id="DTEMP_TAG_IVA_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_IVA_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_IVA_2" acronym="CTRL_CORE_DTEMP_IVA_2" offset="0x5B8" width="32" description="TAGGED TEMPERATURE IVA DOMAIN">
+    <bitfield id="DTEMP_TAG_IVA_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_IVA_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_IVA_3" acronym="CTRL_CORE_DTEMP_IVA_3" offset="0x5BC" width="32" description="TAGGED TEMPERATURE IVA DOMAIN">
+    <bitfield id="DTEMP_TAG_IVA_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_IVA_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_DTEMP_IVA_4" acronym="CTRL_CORE_DTEMP_IVA_4" offset="0x5C0" width="32" description="TAGGED TEMPERATURE IVA DOMAIN. Oldest sample">
+    <bitfield id="DTEMP_TAG_IVA_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>
+    <bitfield id="DTEMP_TEMPERATURE_IVA_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2" offset="0x5CC" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP.">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
+      <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
+      <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
+    </bitfield>
+    <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_VMIN_IVA_2" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3" offset="0x5D0" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP.">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
+      <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
+      <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
+    </bitfield>
+    <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_VMIN_IVA_3" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4" offset="0x5D4" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP.">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
+      <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
+      <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
+    </bitfield>
+    <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_VMIN_IVA_4" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2" offset="0x5E0" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP.">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
+      <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
+      <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
+    </bitfield>
+    <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_VMIN_DSPEVE_2" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3" offset="0x5E4" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP.">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
+      <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
+      <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
+    </bitfield>
+    <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_VMIN_DSPEVE_3" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4" offset="0x5E8" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP.">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x-" description="" range="" rwaccess="R">
+      <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>
+      <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>
+    </bitfield>
+    <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x-" description="This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL[4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_VMIN_DSPEVE_4" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd_dsp voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2" offset="0x5F4" width="32" description="This register contains the AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM.">
+    <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x-" description="Reserved" range="" rwaccess="R"/>
+    <bitfield id="STD_FUSE_OPP_VMIN_CORE_2" width="12" begin="11" end="0" resetval="0x-" description="AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL" offset="0x680" width="32" description="CORE 2nd SRAM LDO Control register">
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMCORE_2_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">
+      <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_2_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>
+      <bitenum value="1" id="OCP" token="LDOSRAMCORE_2_RETMODE_MUX_CTRL_1" description="Override value is used"/>
+    </bitfield>
+    <bitfield id="LDOSRAMCORE_2_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMCORE_2_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMCORE_2_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">
+      <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_2_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>
+      <bitenum value="1" id="OCP" token="LDOSRAMCORE_2_ACTMODE_MUX_CTRL_1" description="Override value is used"/>
+    </bitfield>
+    <bitfield id="LDOSRAMCORE_2_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMCORE_2_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL" offset="0x684" width="32" description="CORE 3rd SRAM LDO Control register">
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMCORE_3_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">
+      <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_3_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>
+      <bitenum value="1" id="OCP" token="LDOSRAMCORE_3_RETMODE_MUX_CTRL_1" description="Override value is used"/>
+    </bitfield>
+    <bitfield id="LDOSRAMCORE_3_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMCORE_3_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMCORE_3_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">
+      <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_3_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>
+      <bitenum value="1" id="OCP" token="LDOSRAMCORE_3_ACTMODE_MUX_CTRL_1" description="Override value is used"/>
+    </bitfield>
+    <bitfield id="LDOSRAMCORE_3_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>
+    <bitfield id="LDOSRAMCORE_3_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_NMI_DESTINATION_1" acronym="CTRL_CORE_NMI_DESTINATION_1" offset="0x68C" width="32" description="Register for routing NMI interrupt to respective cores">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>
+    <bitfield id="IPU2_C1" width="8" begin="23" end="16" resetval="0x0" description="Enable IPU2 CORE1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
+    <bitfield id="IPU2_C0" width="8" begin="15" end="8" resetval="0x0" description="Enable IPU2 CORE0 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
+    <bitfield id="IPU1_C1" width="8" begin="7" end="0" resetval="0x0" description="Enable IPU1 CORE1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_NMI_DESTINATION_2" acronym="CTRL_CORE_NMI_DESTINATION_2" offset="0x690" width="32" description="Register for routing NMI interrupt to respective cores">
+    <bitfield id="IPU1_C0" width="8" begin="31" end="24" resetval="0x0" description="Enable IPU1 CORE0 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="23" end="16" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1" width="8" begin="15" end="8" resetval="0x0" description="Enable DSP1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
+    <bitfield id="MPU" width="8" begin="7" end="0" resetval="0x0" description="Comes from Efuse (MPU_EN) 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IP_PRESSURE" acronym="CTRL_CORE_IP_PRESSURE" offset="0x698" width="32" description="Register to override the L3 pressure setting for the MLB module">
+    <bitfield id="RESERVED" width="29" begin="31" end="3" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MLB_L3_PRESSURE_ENABLE" width="1" begin="2" end="2" resetval="0x0" description="Override enable for the MLB L3 pressure setting 0x0 = Overriding of the L3 pressure setting for the MLB module is disabled 0x1 = Overriding of the L3 pressure setting for the MLB module is enabled" range="" rwaccess="RW"/>
+    <bitfield id="MLB_L3_PRESSURE" width="2" begin="1" end="0" resetval="0x0" description="MLB L3 pressure setting 0x0 = Lowest 0x3 = Highest" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0" offset="0x6A0" width="32" description="Standard Fuse OPP VDD_DSPEVE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1" offset="0x6A4" width="32" description="Standard Fuse OPP VDD_DSPEVE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2" offset="0x6A8" width="32" description="Standard Fuse OPP VDD_DSPEVE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3" offset="0x6AC" width="32" description="Standard Fuse OPP VDD_DSPEVE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4" offset="0x6B0" width="32" description="Standard Fuse OPP VDD_DSPEVE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CUST_FUSE_SWRV_7" acronym="CTRL_CORE_CUST_FUSE_SWRV_7" offset="0x6B4" width="32" description="Customer Fuse keys. SWRV [31:0] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="CUST_FUSE_SWRV_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0" acronym="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0" offset="0x6B8" width="32" description="Standard Fuse Calibration override value [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1" acronym="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1" offset="0x6BC" width="32" description="Standard Fuse Calibration override value [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">
+    <bitfield id="STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_PCIE_POWER_STATE" acronym="CTRL_CORE_PCIE_POWER_STATE" offset="0x6C0" width="32" description="Register to PCIe related controls">
+    <bitfield id="BYPASS_EN_APLL_PCIE" width="1" begin="31" end="31" resetval="0x0" description="Bypass enable bit setting for APLL_PCIe" range="" rwaccess="RW"/>
+    <bitfield id="CLKOOUTEN_APLL_PCIE" width="1" begin="30" end="30" resetval="0x0" description="Clock output enable bit setting for APLL_PCIe" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="4" begin="29" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="EFUSE_TRIM_ACS_PCIE" width="10" begin="25" end="16" resetval="0x0" description="MMR override capability for ACS_PCIe efuse trim bits" range="" rwaccess="RW"/>
+    <bitfield id="EFUSE_TRIM_PCIE_PLL" width="16" begin="15" end="0" resetval="0x0" description="MMR override capability for PCIe PLL efuse trim bits" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_BOOTSTRAP" acronym="CTRL_CORE_BOOTSTRAP" offset="0x6C4" width="32" description="Register to view all the sysboot settings">
+    <bitfield id="RESERVED" width="16" begin="31" end="16" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP_CLOCK_DIVIDER" width="1" begin="15" end="15" resetval="0x0" description="SR1.x Only: Divide factor for DSP clock SR2.x Only: Permanently disables the internal PU/PD resistors on pads gpmc_a[27:24, 22:19]. 0x0: Internal pull-down resistors are enabled 0x1: Internal pull-down resistors are permanently disabled" range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="1" begin="14" end="14" resetval="0x0" description="For proper device operation, a value of 0 is required on sysboot14" range="" rwaccess="R"/>
+    <bitfield id="BOOTDEVICESIZE" width="1" begin="13" end="13" resetval="0x0" description="Select the size of the flash device on CS0. 0x0: 8-bit 0x1: 16-bit" range="" rwaccess="R"/>
+    <bitfield id="MUXCS0DEVICE" width="2" begin="12" end="11" resetval="0x0" description="Select IC boot sequence to be executed from a multiplexed address and data device attached to CS0. 0x0: Non-muxed device attached 0x1: Addr-Data Mux device attached 0x2: Reserved 0x3: Reserved" range="" rwaccess="R"/>
+    <bitfield id="BOOTWAITEN" width="1" begin="10" end="10" resetval="0x0" description="Enable the monitoring on CS0 of the wait pin at IC reset release time for read accesses. 0x0: Wait pin is not monitored for read accesses 0x1: Wait pin is monitored for read accesses" range="" rwaccess="R"/>
+    <bitfield id="SPEEDSELECT" width="2" begin="9" end="8" resetval="0x0" description="Indicates the SYS_CLK1 frequency (from osc0). Note that the internal FUNC_32K_CLK is equal to SYS_CLK1/610, which is nominally 32.7869 kHz with 20 MHz clock. 0x0: Reserved 0x1: 20 MHz 0x2: 27 MHz 0x3: 19.2 MHz" range="" rwaccess="R"/>
+    <bitfield id="SYSBOOT_76" width="2" begin="7" end="6" resetval="0x0" description="Sector offset for the location of the redundant SBL images in QSPI. 0x0: 64 KB offset 0x1: 128 KB offset 0x2: 256 KB offset 0x3: 512 KB offset" range="" rwaccess="R"/>
+    <bitfield id="BOOTMODE" width="6" begin="5" end="0" resetval="0x0" description="SYSBOOT mode" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_MLB_SIG_IO_CTRL" acronym="CTRL_CORE_MLB_SIG_IO_CTRL" offset="0x6C8" width="32" description="Register to set the MLB's SIG IO characteristics">
+    <bitfield id="RESERVED" width="9" begin="31" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="SIG_RX_TRIM_EN" width="1" begin="22" end="22" resetval="0x0" description="0x0: Trimming is disabled 0x1: Trimming is enabled" range="" rwaccess="RW"/>
+    <bitfield id="SIG_NC_IN" width="6" begin="21" end="16" resetval="0x0" description="efuse trim for Nmos impedance" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="SIG_PC_IN" width="6" begin="13" end="8" resetval="0x0" description="efuse trim for Pmos impedance" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="SIG_REMOVE_SKEW" width="1" begin="6" end="6" resetval="0x0" description="Adjust for skew generated by the receiver due to asymmetric inputs. 0x0: skew compensation is disabled 0x1: skew compensation is enabled" range="" rwaccess="RW"/>
+    <bitfield id="SIG_PWRDNRX" width="1" begin="5" end="5" resetval="0x1" description="powerdown receiver, active high 0x0 = Powered ON 0x1 = Powered OFF" range="" rwaccess="RW"/>
+    <bitfield id="SIG_PWRDNTX" width="1" begin="4" end="4" resetval="0x1" description="powerdown transmitter, active high 0x0 = Powered ON 0x1 = Powered OFF" range="" rwaccess="RW"/>
+    <bitfield id="SIG_EN_EXT_RES" width="1" begin="3" end="3" resetval="0x0" description="disables internal resistors 0x0 = Disabled 0x1 = Enabled" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="3" begin="2" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_MLB_DAT_IO_CTRL" acronym="CTRL_CORE_MLB_DAT_IO_CTRL" offset="0x6CC" width="32" description="Register to set the MLB's DAT IO characteristics">
+    <bitfield id="RESERVED" width="9" begin="31" end="23" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DAT_RX_TRIM_EN" width="1" begin="22" end="22" resetval="0x0" description="0x0: Trimming is disabled 0x1: Trimming is enabled" range="" rwaccess="RW"/>
+    <bitfield id="DAT_NC_IN" width="6" begin="21" end="16" resetval="0x0" description="efuse trim for Nmos impedance" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DAT_PC_IN" width="6" begin="13" end="8" resetval="0x0" description="efuse trim for Pmos impedance" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DAT_REMOVE_SKEW" width="1" begin="6" end="6" resetval="0x0" description="Adjust for skew generated by the receiver due to asymmetric inputs. 0x0: skew compensation is disabled 0x1: skew compensation is enabled" range="" rwaccess="RW"/>
+    <bitfield id="DAT_PWRDNRX" width="1" begin="5" end="5" resetval="0x1" description="powerdown receiver, active high 0x0: Powered ON 0x1: Powered OFF" range="" rwaccess="RW"/>
+    <bitfield id="DAT_PWRDNTX" width="1" begin="4" end="4" resetval="0x1" description="powerdown transmitter, active high 0x0: Powered ON 0x1: Powered OFF" range="" rwaccess="RW"/>
+    <bitfield id="DAT_EN_EXT_RES" width="1" begin="3" end="3" resetval="0x0" description="Enable/disable internal resistors 0x0: Disabled 0x1: Enabled" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="3" begin="2" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_MLB_CLK_BG_CTRL" acronym="CTRL_CORE_MLB_CLK_BG_CTRL" offset="0x6D0" width="32" description="Register to set the MLB's clock receiver IO and bandgap characteristics">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="RX_TRIM_EN" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="CLK_REMOVE_SKEW" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="CLK_PWRDNRX" width="1" begin="22" end="22" resetval="0x1" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="5" begin="21" end="17" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="T_HYSTERISIS_EN" width="1" begin="16" end="16" resetval="0x0" description="Hysterisis enable 0x0 = Disabled 0x1 = Enabled" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="BG_TRIM" width="6" begin="7" end="2" resetval="0x0" description="Trim values for MLB bandgap" range="" rwaccess="RW"/>
+    <bitfield id="BG_PWRDN" width="1" begin="1" end="1" resetval="0x0" description="MLB bandgap cell enable. 0x0 = The MLB bandgap cell is powered (enabled) 0x1 = The MLB bandgap cell is disabled" range="" rwaccess="RW"/>
+    <bitfield id="CLK_PWRDN" width="1" begin="0" end="0" resetval="0x1" description="Enable the MLB differential clock receiver. 0x0 = MLB differential clock receiver is enabled 0x1 = MLB differential clock receiver is disabled" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CAL_REG" acronym="CTRL_CORE_CAL_REG" offset="0x794" width="32" description="">
+    <bitfield id="RESERVED" width="28" begin="31" end="4" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CAL_PRIORITY" width="3" begin="3" end="1" resetval="0x0" description="CAL priority setting when accessing the EMIF. 0x0: Highest priority 0x7: Lowest priority" range="" rwaccess="RW"/>
+    <bitfield id="CAL_TILED_MEMORY_SPACE" width="1" begin="0" end="0" resetval="0x0" description="This is the 33rd address bit on the L3_MAIN associated with CAL. This bit controls whether CAL performs an access to Q0-Q3 address range or to TILER_VIEW address range. 0x0: The lower 4GiB address space (Q0-Q3) is accessed. 0x1: The address space associated with the 8 TILER views is accessed." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MLB_DLL" acronym="CTRL_CORE_MLB_DLL" offset="0x798" width="32" description="">
+    <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DLL_CLOCK_DISABLE" width="1" begin="10" end="10" resetval="0x0" description="0x0: MDLL reference clock is enabled 0x1: MDLL reference clock is disabled" range="" rwaccess="RW"/>
+    <bitfield id="DLL_LOCK" width="1" begin="9" end="9" resetval="0x0" description="Value of 0x1 indicates that the MDLL has locked to its reference clock. This bit remains high till MDLL reset occurs." range="" rwaccess="RW"/>
+    <bitfield id="SDL_LOCK" width="1" begin="8" end="8" resetval="0x0" description="Value of 0x1 indicates that the SDL has been updated with a code. This bit remains high till the SDL reset occurs." range="" rwaccess="RW"/>
+    <bitfield id="DLL_RATIO" width="8" begin="7" end="0" resetval="0x0" description="The value which has to be loaded in this bit field is calculated based on the equation DLL_RATIO = (2,5/MP)*256, where MP is the MDLL clock period measured in ns." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MLB_CLK" acronym="CTRL_CORE_MLB_CLK" offset="0x79C" width="32" description="">
+    <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CLK_SEL_MLB" width="1" begin="0" end="0" resetval="0x0" description="0x0: The frequency of the MLB clock line is not doubled (100MHz clock is used) 0x1: The frequency of the MLB clock line is doubled (200MHz clock is used)" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_23_24" acronym="CTRL_CORE_IPU1_IRQ_23_24" offset="0x7E0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_24" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_23" width="9" begin="8" end="0" resetval="0x14" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_25_26" acronym="CTRL_CORE_IPU1_IRQ_25_26" offset="0x7E4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_26" width="9" begin="24" end="16" resetval="0x60" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_25" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_27_28" acronym="CTRL_CORE_IPU1_IRQ_27_28" offset="0x7E8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_28" width="9" begin="24" end="16" resetval="0x7F" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_27" width="9" begin="8" end="0" resetval="0x7E" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_29_30" acronym="CTRL_CORE_IPU1_IRQ_29_30" offset="0x7EC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_30" width="9" begin="24" end="16" resetval="0x81" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_29" width="9" begin="8" end="0" resetval="0x80" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_31_32" acronym="CTRL_CORE_IPU1_IRQ_31_32" offset="0x7F0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_32" width="9" begin="24" end="16" resetval="0x13" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_31" width="9" begin="8" end="0" resetval="0x82" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_33_34" acronym="CTRL_CORE_IPU1_IRQ_33_34" offset="0x7F4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_34" width="9" begin="24" end="16" resetval="0x7" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_33" width="9" begin="8" end="0" resetval="0x83" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_35_36" acronym="CTRL_CORE_IPU1_IRQ_35_36" offset="0x7F8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_36" width="9" begin="24" end="16" resetval="0x9" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_35" width="9" begin="8" end="0" resetval="0x8" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_37_38" acronym="CTRL_CORE_IPU1_IRQ_37_38" offset="0x7FC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_38" width="9" begin="24" end="16" resetval="0x84" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_37" width="9" begin="8" end="0" resetval="0xA" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_39_40" acronym="CTRL_CORE_IPU1_IRQ_39_40" offset="0x800" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_40" width="9" begin="24" end="16" resetval="0x63" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_39" width="9" begin="8" end="0" resetval="0x62" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_41_42" acronym="CTRL_CORE_IPU1_IRQ_41_42" offset="0x804" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_42" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_41" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_43_44" acronym="CTRL_CORE_IPU1_IRQ_43_44" offset="0x808" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_44" width="9" begin="24" end="16" resetval="0x39" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_43" width="9" begin="8" end="0" resetval="0x38" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_45_46" acronym="CTRL_CORE_IPU1_IRQ_45_46" offset="0x80C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_46" width="9" begin="24" end="16" resetval="0x5" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_45" width="9" begin="8" end="0" resetval="0x45" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_47_48" acronym="CTRL_CORE_IPU1_IRQ_47_48" offset="0x810" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_48" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_47" width="9" begin="8" end="0" resetval="0x85" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_49_50" acronym="CTRL_CORE_IPU1_IRQ_49_50" offset="0x814" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_50" width="9" begin="24" end="16" resetval="0x86" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_49" width="9" begin="8" end="0" resetval="0x42" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_51_52" acronym="CTRL_CORE_IPU1_IRQ_51_52" offset="0x818" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_52" width="9" begin="24" end="16" resetval="0x19" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_51" width="9" begin="8" end="0" resetval="0x18" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_53_54" acronym="CTRL_CORE_IPU1_IRQ_53_54" offset="0x81C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_54" width="9" begin="24" end="16" resetval="0x23" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_53" width="9" begin="8" end="0" resetval="0x22" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_55_56" acronym="CTRL_CORE_IPU1_IRQ_55_56" offset="0x820" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_56" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_55" width="9" begin="8" end="0" resetval="0x28" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_57_58" acronym="CTRL_CORE_IPU1_IRQ_57_58" offset="0x824" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_58" width="9" begin="24" end="16" resetval="0x3D" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_57" width="9" begin="8" end="0" resetval="0x3C" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_59_60" acronym="CTRL_CORE_IPU1_IRQ_59_60" offset="0x828" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_60" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_59" width="9" begin="8" end="0" resetval="0x32" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_61_62" acronym="CTRL_CORE_IPU1_IRQ_61_62" offset="0x82C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_62" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_61" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_63_64" acronym="CTRL_CORE_IPU1_IRQ_63_64" offset="0x830" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_64" width="9" begin="24" end="16" resetval="0x6C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_63" width="9" begin="8" end="0" resetval="0x53" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_65_66" acronym="CTRL_CORE_IPU1_IRQ_65_66" offset="0x834" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_66" width="9" begin="24" end="16" resetval="0x4E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_65" width="9" begin="8" end="0" resetval="0x78" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_67_68" acronym="CTRL_CORE_IPU1_IRQ_67_68" offset="0x838" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_68" width="9" begin="24" end="16" resetval="0x59" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_67" width="9" begin="8" end="0" resetval="0x51" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_69_70" acronym="CTRL_CORE_IPU1_IRQ_69_70" offset="0x83C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_70" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_69" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_71_72" acronym="CTRL_CORE_IPU1_IRQ_71_72" offset="0x840" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_72" width="9" begin="24" end="16" resetval="0x76" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_71" width="9" begin="8" end="0" resetval="0x77" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_73_74" acronym="CTRL_CORE_IPU1_IRQ_73_74" offset="0x844" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_74" width="9" begin="24" end="16" resetval="0x49" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_73" width="9" begin="8" end="0" resetval="0x48" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_75_76" acronym="CTRL_CORE_IPU1_IRQ_75_76" offset="0x848" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_76" width="9" begin="24" end="16" resetval="0x57" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_75" width="9" begin="8" end="0" resetval="0x75" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_77_78" acronym="CTRL_CORE_IPU1_IRQ_77_78" offset="0x84C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_78" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_77" width="9" begin="8" end="0" resetval="0x58" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU1_IRQ_79_80" acronym="CTRL_CORE_IPU1_IRQ_79_80" offset="0x850" width="32" description="">
+    <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU1_IRQ_79" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_23_24" acronym="CTRL_CORE_IPU2_IRQ_23_24" offset="0x854" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_24" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_23" width="9" begin="8" end="0" resetval="0x14" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_25_26" acronym="CTRL_CORE_IPU2_IRQ_25_26" offset="0x858" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_26" width="9" begin="24" end="16" resetval="0x60" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_25" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_27_28" acronym="CTRL_CORE_IPU2_IRQ_27_28" offset="0x85C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_28" width="9" begin="24" end="16" resetval="0x7F" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_27" width="9" begin="8" end="0" resetval="0x7E" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_29_30" acronym="CTRL_CORE_IPU2_IRQ_29_30" offset="0x860" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_30" width="9" begin="24" end="16" resetval="0x81" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_29" width="9" begin="8" end="0" resetval="0x80" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_31_32" acronym="CTRL_CORE_IPU2_IRQ_31_32" offset="0x864" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_32" width="9" begin="24" end="16" resetval="0x13" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_31" width="9" begin="8" end="0" resetval="0x82" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_33_34" acronym="CTRL_CORE_IPU2_IRQ_33_34" offset="0x868" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_34" width="9" begin="24" end="16" resetval="0x7" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_33" width="9" begin="8" end="0" resetval="0x83" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_35_36" acronym="CTRL_CORE_IPU2_IRQ_35_36" offset="0x86C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_36" width="9" begin="24" end="16" resetval="0x9" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_35" width="9" begin="8" end="0" resetval="0x8" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_37_38" acronym="CTRL_CORE_IPU2_IRQ_37_38" offset="0x870" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_38" width="9" begin="24" end="16" resetval="0x84" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_37" width="9" begin="8" end="0" resetval="0xA" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_39_40" acronym="CTRL_CORE_IPU2_IRQ_39_40" offset="0x874" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_40" width="9" begin="24" end="16" resetval="0x63" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_39" width="9" begin="8" end="0" resetval="0x62" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_41_42" acronym="CTRL_CORE_IPU2_IRQ_41_42" offset="0x878" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_42" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_41" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_43_44" acronym="CTRL_CORE_IPU2_IRQ_43_44" offset="0x87C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_44" width="9" begin="24" end="16" resetval="0x39" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_43" width="9" begin="8" end="0" resetval="0x38" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_45_46" acronym="CTRL_CORE_IPU2_IRQ_45_46" offset="0x880" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_46" width="9" begin="24" end="16" resetval="0x5" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_45" width="9" begin="8" end="0" resetval="0x45" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_47_48" acronym="CTRL_CORE_IPU2_IRQ_47_48" offset="0x884" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_48" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_47" width="9" begin="8" end="0" resetval="0x85" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_49_50" acronym="CTRL_CORE_IPU2_IRQ_49_50" offset="0x888" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_50" width="9" begin="24" end="16" resetval="0x86" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_49" width="9" begin="8" end="0" resetval="0x42" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_51_52" acronym="CTRL_CORE_IPU2_IRQ_51_52" offset="0x88C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_52" width="9" begin="24" end="16" resetval="0x19" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_51" width="9" begin="8" end="0" resetval="0x18" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_53_54" acronym="CTRL_CORE_IPU2_IRQ_53_54" offset="0x890" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_54" width="9" begin="24" end="16" resetval="0x23" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_53" width="9" begin="8" end="0" resetval="0x22" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_55_56" acronym="CTRL_CORE_IPU2_IRQ_55_56" offset="0x894" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_56" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_55" width="9" begin="8" end="0" resetval="0x28" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_57_58" acronym="CTRL_CORE_IPU2_IRQ_57_58" offset="0x898" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_58" width="9" begin="24" end="16" resetval="0x3D" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_57" width="9" begin="8" end="0" resetval="0x3C" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_59_60" acronym="CTRL_CORE_IPU2_IRQ_59_60" offset="0x89C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_60" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_59" width="9" begin="8" end="0" resetval="0x32" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_61_62" acronym="CTRL_CORE_IPU2_IRQ_61_62" offset="0x8A0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_62" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_61" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_63_64" acronym="CTRL_CORE_IPU2_IRQ_63_64" offset="0x8A4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_64" width="9" begin="24" end="16" resetval="0x6C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_63" width="9" begin="8" end="0" resetval="0x53" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_65_66" acronym="CTRL_CORE_IPU2_IRQ_65_66" offset="0x8A8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_66" width="9" begin="24" end="16" resetval="0x4E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_65" width="9" begin="8" end="0" resetval="0x78" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_67_68" acronym="CTRL_CORE_IPU2_IRQ_67_68" offset="0x8AC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_68" width="9" begin="24" end="16" resetval="0x59" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_67" width="9" begin="8" end="0" resetval="0x51" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_69_70" acronym="CTRL_CORE_IPU2_IRQ_69_70" offset="0x8B0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_70" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_69" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_71_72" acronym="CTRL_CORE_IPU2_IRQ_71_72" offset="0x8B4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_72" width="9" begin="24" end="16" resetval="0x76" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_71" width="9" begin="8" end="0" resetval="0x77" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_73_74" acronym="CTRL_CORE_IPU2_IRQ_73_74" offset="0x8B8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_74" width="9" begin="24" end="16" resetval="0x49" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_73" width="9" begin="8" end="0" resetval="0x48" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_75_76" acronym="CTRL_CORE_IPU2_IRQ_75_76" offset="0x8BC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_76" width="9" begin="24" end="16" resetval="0x57" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_75" width="9" begin="8" end="0" resetval="0x75" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_77_78" acronym="CTRL_CORE_IPU2_IRQ_77_78" offset="0x8C0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_78" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_77" width="9" begin="8" end="0" resetval="0x58" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_IPU2_IRQ_79_80" acronym="CTRL_CORE_IPU2_IRQ_79_80" offset="0x8C4" width="32" description="">
+    <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="IPU2_IRQ_79" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_32_33" acronym="CTRL_CORE_PRUSS1_IRQ_32_33" offset="0x8C8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_34_35" acronym="CTRL_CORE_PRUSS1_IRQ_34_35" offset="0x8CC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_36_37" acronym="CTRL_CORE_PRUSS1_IRQ_36_37" offset="0x8D0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_38_39" acronym="CTRL_CORE_PRUSS1_IRQ_38_39" offset="0x8D4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_40_41" acronym="CTRL_CORE_PRUSS1_IRQ_40_41" offset="0x8D8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_42_43" acronym="CTRL_CORE_PRUSS1_IRQ_42_43" offset="0x8DC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_44_45" acronym="CTRL_CORE_PRUSS1_IRQ_44_45" offset="0x8E0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_46_47" acronym="CTRL_CORE_PRUSS1_IRQ_46_47" offset="0x8E4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_48_49" acronym="CTRL_CORE_PRUSS1_IRQ_48_49" offset="0x8E8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_50_51" acronym="CTRL_CORE_PRUSS1_IRQ_50_51" offset="0x8EC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_52_53" acronym="CTRL_CORE_PRUSS1_IRQ_52_53" offset="0x8F0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_54_55" acronym="CTRL_CORE_PRUSS1_IRQ_54_55" offset="0x8F4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_56_57" acronym="CTRL_CORE_PRUSS1_IRQ_56_57" offset="0x8F8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_58_59" acronym="CTRL_CORE_PRUSS1_IRQ_58_59" offset="0x8FC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_60_61" acronym="CTRL_CORE_PRUSS1_IRQ_60_61" offset="0x900" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS1_IRQ_62_63" acronym="CTRL_CORE_PRUSS1_IRQ_62_63" offset="0x904" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS1_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_32_33" acronym="CTRL_CORE_PRUSS2_IRQ_32_33" offset="0x908" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_34_35" acronym="CTRL_CORE_PRUSS2_IRQ_34_35" offset="0x90C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_36_37" acronym="CTRL_CORE_PRUSS2_IRQ_36_37" offset="0x910" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_38_39" acronym="CTRL_CORE_PRUSS2_IRQ_38_39" offset="0x914" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_40_41" acronym="CTRL_CORE_PRUSS2_IRQ_40_41" offset="0x918" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_42_43" acronym="CTRL_CORE_PRUSS2_IRQ_42_43" offset="0x91C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_44_45" acronym="CTRL_CORE_PRUSS2_IRQ_44_45" offset="0x920" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_46_47" acronym="CTRL_CORE_PRUSS2_IRQ_46_47" offset="0x924" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_48_49" acronym="CTRL_CORE_PRUSS2_IRQ_48_49" offset="0x928" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_50_51" acronym="CTRL_CORE_PRUSS2_IRQ_50_51" offset="0x92C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_52_53" acronym="CTRL_CORE_PRUSS2_IRQ_52_53" offset="0x930" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_54_55" acronym="CTRL_CORE_PRUSS2_IRQ_54_55" offset="0x934" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_56_57" acronym="CTRL_CORE_PRUSS2_IRQ_56_57" offset="0x938" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_58_59" acronym="CTRL_CORE_PRUSS2_IRQ_58_59" offset="0x93C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_60_61" acronym="CTRL_CORE_PRUSS2_IRQ_60_61" offset="0x940" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PRUSS2_IRQ_62_63" acronym="CTRL_CORE_PRUSS2_IRQ_62_63" offset="0x944" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="PRUSS2_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_32_33" acronym="CTRL_CORE_DSP1_IRQ_32_33" offset="0x948" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_34_35" acronym="CTRL_CORE_DSP1_IRQ_34_35" offset="0x94C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_36_37" acronym="CTRL_CORE_DSP1_IRQ_36_37" offset="0x950" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_38_39" acronym="CTRL_CORE_DSP1_IRQ_38_39" offset="0x954" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_40_41" acronym="CTRL_CORE_DSP1_IRQ_40_41" offset="0x958" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_42_43" acronym="CTRL_CORE_DSP1_IRQ_42_43" offset="0x95C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_44_45" acronym="CTRL_CORE_DSP1_IRQ_44_45" offset="0x960" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_46_47" acronym="CTRL_CORE_DSP1_IRQ_46_47" offset="0x964" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_48_49" acronym="CTRL_CORE_DSP1_IRQ_48_49" offset="0x968" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_50_51" acronym="CTRL_CORE_DSP1_IRQ_50_51" offset="0x96C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_52_53" acronym="CTRL_CORE_DSP1_IRQ_52_53" offset="0x970" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_54_55" acronym="CTRL_CORE_DSP1_IRQ_54_55" offset="0x974" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_56_57" acronym="CTRL_CORE_DSP1_IRQ_56_57" offset="0x978" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_58_59" acronym="CTRL_CORE_DSP1_IRQ_58_59" offset="0x97C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_60_61" acronym="CTRL_CORE_DSP1_IRQ_60_61" offset="0x980" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_62_63" acronym="CTRL_CORE_DSP1_IRQ_62_63" offset="0x984" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_64_65" acronym="CTRL_CORE_DSP1_IRQ_64_65" offset="0x988" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_65" width="9" begin="24" end="16" resetval="0x22" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_64" width="9" begin="8" end="0" resetval="0x21" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_66_67" acronym="CTRL_CORE_DSP1_IRQ_66_67" offset="0x98C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_67" width="9" begin="24" end="16" resetval="0x24" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_66" width="9" begin="8" end="0" resetval="0x23" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_68_69" acronym="CTRL_CORE_DSP1_IRQ_68_69" offset="0x990" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_69" width="9" begin="24" end="16" resetval="0x26" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_68" width="9" begin="8" end="0" resetval="0x25" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_70_71" acronym="CTRL_CORE_DSP1_IRQ_70_71" offset="0x994" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_71" width="9" begin="24" end="16" resetval="0x28" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_70" width="9" begin="8" end="0" resetval="0x27" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_72_73" acronym="CTRL_CORE_DSP1_IRQ_72_73" offset="0x998" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_73" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_72" width="9" begin="8" end="0" resetval="0x29" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_74_75" acronym="CTRL_CORE_DSP1_IRQ_74_75" offset="0x99C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_75" width="9" begin="24" end="16" resetval="0x2C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_74" width="9" begin="8" end="0" resetval="0x2B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_76_77" acronym="CTRL_CORE_DSP1_IRQ_76_77" offset="0x9A0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_77" width="9" begin="24" end="16" resetval="0x2E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_76" width="9" begin="8" end="0" resetval="0x2D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_78_79" acronym="CTRL_CORE_DSP1_IRQ_78_79" offset="0x9A4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_79" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_78" width="9" begin="8" end="0" resetval="0x2F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_80_81" acronym="CTRL_CORE_DSP1_IRQ_80_81" offset="0x9A8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_81" width="9" begin="24" end="16" resetval="0x32" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_80" width="9" begin="8" end="0" resetval="0x31" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_82_83" acronym="CTRL_CORE_DSP1_IRQ_82_83" offset="0x9AC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_83" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_82" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_84_85" acronym="CTRL_CORE_DSP1_IRQ_84_85" offset="0x9B0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_85" width="9" begin="24" end="16" resetval="0x36" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_84" width="9" begin="8" end="0" resetval="0x35" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_86_87" acronym="CTRL_CORE_DSP1_IRQ_86_87" offset="0x9B4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_87" width="9" begin="24" end="16" resetval="0x38" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_86" width="9" begin="8" end="0" resetval="0x37" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_88_89" acronym="CTRL_CORE_DSP1_IRQ_88_89" offset="0x9B8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_89" width="9" begin="24" end="16" resetval="0x3A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_88" width="9" begin="8" end="0" resetval="0x39" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_90_91" acronym="CTRL_CORE_DSP1_IRQ_90_91" offset="0x9BC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_91" width="9" begin="24" end="16" resetval="0x3C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_90" width="9" begin="8" end="0" resetval="0x3B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_92_93" acronym="CTRL_CORE_DSP1_IRQ_92_93" offset="0x9C0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_93" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_92" width="9" begin="8" end="0" resetval="0x3D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DSP1_IRQ_94_95" acronym="CTRL_CORE_DSP1_IRQ_94_95" offset="0x9C4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_95" width="9" begin="24" end="16" resetval="0x40" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DSP1_IRQ_94" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_4_7" acronym="CTRL_CORE_MPU_IRQ_4_7" offset="0xA48" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_7" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_4" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_8_9" acronym="CTRL_CORE_MPU_IRQ_8_9" offset="0xA4C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_9" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_8" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_10_11" acronym="CTRL_CORE_MPU_IRQ_10_11" offset="0xA50" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_11" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_10" width="9" begin="8" end="0" resetval="0x5" description="NOTE: This bit field is not functional" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_12_13" acronym="CTRL_CORE_MPU_IRQ_12_13" offset="0xA54" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_13" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_12" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_14_15" acronym="CTRL_CORE_MPU_IRQ_14_15" offset="0xA58" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_15" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_14" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_16_17" acronym="CTRL_CORE_MPU_IRQ_16_17" offset="0xA5C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_17" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_16" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_18_19" acronym="CTRL_CORE_MPU_IRQ_18_19" offset="0xA60" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_19" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_18" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_20_21" acronym="CTRL_CORE_MPU_IRQ_20_21" offset="0xA64" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_21" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_20" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_22_23" acronym="CTRL_CORE_MPU_IRQ_22_23" offset="0xA68" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_23" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_22" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_24_25" acronym="CTRL_CORE_MPU_IRQ_24_25" offset="0xA6C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_25" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_24" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_26_27" acronym="CTRL_CORE_MPU_IRQ_26_27" offset="0xA70" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_27" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_26" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_28_29" acronym="CTRL_CORE_MPU_IRQ_28_29" offset="0xA74" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_29" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_28" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_30_31" acronym="CTRL_CORE_MPU_IRQ_30_31" offset="0xA78" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_31" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_30" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_32_33" acronym="CTRL_CORE_MPU_IRQ_32_33" offset="0xA7C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_33" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_32" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_34_35" acronym="CTRL_CORE_MPU_IRQ_34_35" offset="0xA80" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_35" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_34" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_36_37" acronym="CTRL_CORE_MPU_IRQ_36_37" offset="0xA84" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_37" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_36" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_38_39" acronym="CTRL_CORE_MPU_IRQ_38_39" offset="0xA88" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_39" width="9" begin="24" end="16" resetval="0x22" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_38" width="9" begin="8" end="0" resetval="0x21" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_40_41" acronym="CTRL_CORE_MPU_IRQ_40_41" offset="0xA8C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_41" width="9" begin="24" end="16" resetval="0x24" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_40" width="9" begin="8" end="0" resetval="0x23" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_42_43" acronym="CTRL_CORE_MPU_IRQ_42_43" offset="0xA90" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_43" width="9" begin="24" end="16" resetval="0x26" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_42" width="9" begin="8" end="0" resetval="0x25" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_44_45" acronym="CTRL_CORE_MPU_IRQ_44_45" offset="0xA94" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_45" width="9" begin="24" end="16" resetval="0x28" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_44" width="9" begin="8" end="0" resetval="0x27" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_46_47" acronym="CTRL_CORE_MPU_IRQ_46_47" offset="0xA98" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_47" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_46" width="9" begin="8" end="0" resetval="0x29" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_48_49" acronym="CTRL_CORE_MPU_IRQ_48_49" offset="0xA9C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_49" width="9" begin="24" end="16" resetval="0x2C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_48" width="9" begin="8" end="0" resetval="0x2B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_50_51" acronym="CTRL_CORE_MPU_IRQ_50_51" offset="0xAA0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_51" width="9" begin="24" end="16" resetval="0x2E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_50" width="9" begin="8" end="0" resetval="0x2D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_52_53" acronym="CTRL_CORE_MPU_IRQ_52_53" offset="0xAA4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_53" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_52" width="9" begin="8" end="0" resetval="0x2F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_54_55" acronym="CTRL_CORE_MPU_IRQ_54_55" offset="0xAA8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_55" width="9" begin="24" end="16" resetval="0x32" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_54" width="9" begin="8" end="0" resetval="0x31" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_56_57" acronym="CTRL_CORE_MPU_IRQ_56_57" offset="0xAAC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_57" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_56" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_58_59" acronym="CTRL_CORE_MPU_IRQ_58_59" offset="0xAB0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_59" width="9" begin="24" end="16" resetval="0x36" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_58" width="9" begin="8" end="0" resetval="0x35" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_60_61" acronym="CTRL_CORE_MPU_IRQ_60_61" offset="0xAB4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_61" width="9" begin="24" end="16" resetval="0x38" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_60" width="9" begin="8" end="0" resetval="0x37" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_62_63" acronym="CTRL_CORE_MPU_IRQ_62_63" offset="0xAB8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_63" width="9" begin="24" end="16" resetval="0x3A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_62" width="9" begin="8" end="0" resetval="0x39" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_64_65" acronym="CTRL_CORE_MPU_IRQ_64_65" offset="0xABC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_65" width="9" begin="24" end="16" resetval="0x3C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_64" width="9" begin="8" end="0" resetval="0x3B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_66_67" acronym="CTRL_CORE_MPU_IRQ_66_67" offset="0xAC0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_67" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_66" width="9" begin="8" end="0" resetval="0x3D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_68_69" acronym="CTRL_CORE_MPU_IRQ_68_69" offset="0xAC4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_69" width="9" begin="24" end="16" resetval="0x40" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_68" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_70_71" acronym="CTRL_CORE_MPU_IRQ_70_71" offset="0xAC8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_71" width="9" begin="24" end="16" resetval="0x42" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_70" width="9" begin="8" end="0" resetval="0x41" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_72_73" acronym="CTRL_CORE_MPU_IRQ_72_73" offset="0xACC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_73" width="9" begin="24" end="16" resetval="0x44" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_72" width="9" begin="8" end="0" resetval="0x43" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_74_75" acronym="CTRL_CORE_MPU_IRQ_74_75" offset="0xAD0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_75" width="9" begin="24" end="16" resetval="0x46" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_74" width="9" begin="8" end="0" resetval="0x45" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_76_77" acronym="CTRL_CORE_MPU_IRQ_76_77" offset="0xAD4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_77" width="9" begin="24" end="16" resetval="0x48" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_76" width="9" begin="8" end="0" resetval="0x47" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_78_79" acronym="CTRL_CORE_MPU_IRQ_78_79" offset="0xAD8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_79" width="9" begin="24" end="16" resetval="0x4A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_78" width="9" begin="8" end="0" resetval="0x49" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_80_81" acronym="CTRL_CORE_MPU_IRQ_80_81" offset="0xADC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_81" width="9" begin="24" end="16" resetval="0x4C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_80" width="9" begin="8" end="0" resetval="0x4B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_82_83" acronym="CTRL_CORE_MPU_IRQ_82_83" offset="0xAE0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_83" width="9" begin="24" end="16" resetval="0x4E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_82" width="9" begin="8" end="0" resetval="0x4D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_84_85" acronym="CTRL_CORE_MPU_IRQ_84_85" offset="0xAE4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_85" width="9" begin="24" end="16" resetval="0x50" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_84" width="9" begin="8" end="0" resetval="0x4F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_86_87" acronym="CTRL_CORE_MPU_IRQ_86_87" offset="0xAE8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_87" width="9" begin="24" end="16" resetval="0x52" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_86" width="9" begin="8" end="0" resetval="0x51" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_88_89" acronym="CTRL_CORE_MPU_IRQ_88_89" offset="0xAEC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_89" width="9" begin="24" end="16" resetval="0x54" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_88" width="9" begin="8" end="0" resetval="0x53" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_90_91" acronym="CTRL_CORE_MPU_IRQ_90_91" offset="0xAF0" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_91" width="9" begin="24" end="16" resetval="0x56" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_90" width="9" begin="8" end="0" resetval="0x55" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_92_93" acronym="CTRL_CORE_MPU_IRQ_92_93" offset="0xAF4" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_93" width="9" begin="24" end="16" resetval="0x58" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_92" width="9" begin="8" end="0" resetval="0x57" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_94_95" acronym="CTRL_CORE_MPU_IRQ_94_95" offset="0xAF8" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_95" width="9" begin="24" end="16" resetval="0x5A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_94" width="9" begin="8" end="0" resetval="0x59" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_96_97" acronym="CTRL_CORE_MPU_IRQ_96_97" offset="0xAFC" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_97" width="9" begin="24" end="16" resetval="0x5C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_96" width="9" begin="8" end="0" resetval="0x5B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_98_99" acronym="CTRL_CORE_MPU_IRQ_98_99" offset="0xB00" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_99" width="9" begin="24" end="16" resetval="0x5E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_98" width="9" begin="8" end="0" resetval="0x5D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_100_101" acronym="CTRL_CORE_MPU_IRQ_100_101" offset="0xB04" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_101" width="9" begin="24" end="16" resetval="0x60" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_100" width="9" begin="8" end="0" resetval="0x18B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_102_103" acronym="CTRL_CORE_MPU_IRQ_102_103" offset="0xB08" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_103" width="9" begin="24" end="16" resetval="0x62" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_102" width="9" begin="8" end="0" resetval="0x61" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_104_105" acronym="CTRL_CORE_MPU_IRQ_104_105" offset="0xB0C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_105" width="9" begin="24" end="16" resetval="0x64" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_104" width="9" begin="8" end="0" resetval="0x63" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_106_107" acronym="CTRL_CORE_MPU_IRQ_106_107" offset="0xB10" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_107" width="9" begin="24" end="16" resetval="0x66" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_106" width="9" begin="8" end="0" resetval="0x65" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_108_109" acronym="CTRL_CORE_MPU_IRQ_108_109" offset="0xB14" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_109" width="9" begin="24" end="16" resetval="0x68" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_108" width="9" begin="8" end="0" resetval="0x67" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_110_111" acronym="CTRL_CORE_MPU_IRQ_110_111" offset="0xB18" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_111" width="9" begin="24" end="16" resetval="0x6A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_110" width="9" begin="8" end="0" resetval="0x69" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_112_113" acronym="CTRL_CORE_MPU_IRQ_112_113" offset="0xB1C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_113" width="9" begin="24" end="16" resetval="0x6C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_112" width="9" begin="8" end="0" resetval="0x6B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_114_115" acronym="CTRL_CORE_MPU_IRQ_114_115" offset="0xB20" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_115" width="9" begin="24" end="16" resetval="0x6E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_114" width="9" begin="8" end="0" resetval="0x6D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_116_117" acronym="CTRL_CORE_MPU_IRQ_116_117" offset="0xB24" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_117" width="9" begin="24" end="16" resetval="0x70" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_116" width="9" begin="8" end="0" resetval="0x6F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_118_119" acronym="CTRL_CORE_MPU_IRQ_118_119" offset="0xB28" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_119" width="9" begin="24" end="16" resetval="0x72" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_118" width="9" begin="8" end="0" resetval="0x71" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_120_121" acronym="CTRL_CORE_MPU_IRQ_120_121" offset="0xB2C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_121" width="9" begin="24" end="16" resetval="0x74" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_120" width="9" begin="8" end="0" resetval="0x73" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_122_123" acronym="CTRL_CORE_MPU_IRQ_122_123" offset="0xB30" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_123" width="9" begin="24" end="16" resetval="0x76" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_122" width="9" begin="8" end="0" resetval="0x75" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_124_125" acronym="CTRL_CORE_MPU_IRQ_124_125" offset="0xB34" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_125" width="9" begin="24" end="16" resetval="0x78" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_124" width="9" begin="8" end="0" resetval="0x77" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_126_127" acronym="CTRL_CORE_MPU_IRQ_126_127" offset="0xB38" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_127" width="9" begin="24" end="16" resetval="0x7A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_126" width="9" begin="8" end="0" resetval="0x79" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_128_129" acronym="CTRL_CORE_MPU_IRQ_128_129" offset="0xB3C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_129" width="9" begin="24" end="16" resetval="0x7C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_128" width="9" begin="8" end="0" resetval="0x7B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_130_133" acronym="CTRL_CORE_MPU_IRQ_130_133" offset="0xB40" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_133" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_130" width="9" begin="8" end="0" resetval="0x7D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_134_135" acronym="CTRL_CORE_MPU_IRQ_134_135" offset="0xB44" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_135" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_134" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_136_137" acronym="CTRL_CORE_MPU_IRQ_136_137" offset="0xB48" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_137" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_136" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_138_139" acronym="CTRL_CORE_MPU_IRQ_138_139" offset="0xB4C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_139" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_138" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_140_141" acronym="CTRL_CORE_MPU_IRQ_140_141" offset="0xB50" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_141" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_140" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_142_143" acronym="CTRL_CORE_MPU_IRQ_142_143" offset="0xB54" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_143" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_142" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_144_145" acronym="CTRL_CORE_MPU_IRQ_144_145" offset="0xB58" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_145" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_144" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_146_147" acronym="CTRL_CORE_MPU_IRQ_146_147" offset="0xB5C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_147" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_146" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_148_149" acronym="CTRL_CORE_MPU_IRQ_148_149" offset="0xB60" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_149" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_148" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_150_151" acronym="CTRL_CORE_MPU_IRQ_150_151" offset="0xB64" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_151" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_150" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_152_153" acronym="CTRL_CORE_MPU_IRQ_152_153" offset="0xB68" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_153" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_152" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_154_155" acronym="CTRL_CORE_MPU_IRQ_154_155" offset="0xB6C" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_155" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_154" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_156_157" acronym="CTRL_CORE_MPU_IRQ_156_157" offset="0xB70" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_157" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_156" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_MPU_IRQ_158_159" acronym="CTRL_CORE_MPU_IRQ_158_159" offset="0xB74" width="32" description="">
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_159" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="MPU_IRQ_158" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_0_1" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_0_1" offset="0xB78" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_1_IRQ_1" width="8" begin="23" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_0_IRQ_0" width="8" begin="7" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_2_3" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_2_3" offset="0xB7C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_3_IRQ_3" width="8" begin="23" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_2_IRQ_2" width="8" begin="7" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_4_5" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_4_5" offset="0xB80" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_5_IRQ_5" width="8" begin="23" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_4_IRQ_4" width="8" begin="7" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_6_7" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_6_7" offset="0xB84" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_7_IRQ_7" width="8" begin="23" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_6_IRQ_6" width="8" begin="7" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_8_9" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_8_9" offset="0xB88" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_9_IRQ_9" width="8" begin="23" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_8_IRQ_8" width="8" begin="7" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_10_11" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_10_11" offset="0xB8C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_11_IRQ_11" width="8" begin="23" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_10_IRQ_10" width="8" begin="7" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_12_13" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_12_13" offset="0xB90" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_13_IRQ_13" width="8" begin="23" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_12_IRQ_12" width="8" begin="7" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_14_15" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_14_15" offset="0xB94" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_15_IRQ_15" width="8" begin="23" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_14_IRQ_14" width="8" begin="7" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_16_17" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_16_17" offset="0xB98" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_17_IRQ_17" width="8" begin="23" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_16_IRQ_16" width="8" begin="7" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_18_19" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_18_19" offset="0xB9C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_19_IRQ_19" width="8" begin="23" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_18_IRQ_18" width="8" begin="7" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_20_21" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_20_21" offset="0xBA0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_21_IRQ_21" width="8" begin="23" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_20_IRQ_20" width="8" begin="7" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_22_23" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_22_23" offset="0xBA4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_23_IRQ_23" width="8" begin="23" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_22_IRQ_22" width="8" begin="7" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_24_25" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_24_25" offset="0xBA8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_25_IRQ_25" width="8" begin="23" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_24_IRQ_24" width="8" begin="7" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_26_27" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_26_27" offset="0xBAC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_27_IRQ_27" width="8" begin="23" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_26_IRQ_26" width="8" begin="7" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_28_29" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_28_29" offset="0xBB0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_29_IRQ_29" width="8" begin="23" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_28_IRQ_28" width="8" begin="7" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_30_31" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_30_31" offset="0xBB4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_31_IRQ_31" width="8" begin="23" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_30_IRQ_30" width="8" begin="7" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_32_33" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_32_33" offset="0xBB8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_33_IRQ_33" width="8" begin="23" end="16" resetval="0x22" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_32_IRQ_32" width="8" begin="7" end="0" resetval="0x21" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_34_35" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_34_35" offset="0xBBC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_35_IRQ_35" width="8" begin="23" end="16" resetval="0x24" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_34_IRQ_34" width="8" begin="7" end="0" resetval="0x23" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_36_37" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_36_37" offset="0xBC0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_37_IRQ_37" width="8" begin="23" end="16" resetval="0x26" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_36_IRQ_36" width="8" begin="7" end="0" resetval="0x25" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_38_39" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_38_39" offset="0xBC4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_39_IRQ_39" width="8" begin="23" end="16" resetval="0x28" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_38_IRQ_38" width="8" begin="7" end="0" resetval="0x27" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_40_41" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_40_41" offset="0xBC8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_41_IRQ_41" width="8" begin="23" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_40_IRQ_40" width="8" begin="7" end="0" resetval="0x29" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_42_43" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_42_43" offset="0xBCC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_43_IRQ_43" width="8" begin="23" end="16" resetval="0x2C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_42_IRQ_42" width="8" begin="7" end="0" resetval="0x2B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_44_45" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_44_45" offset="0xBD0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_45_IRQ_45" width="8" begin="23" end="16" resetval="0x2E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_44_IRQ_44" width="8" begin="7" end="0" resetval="0x2D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_46_47" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_46_47" offset="0xBD4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_47_IRQ_47" width="8" begin="23" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_46_IRQ_46" width="8" begin="7" end="0" resetval="0x2F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_48_49" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_48_49" offset="0xBD8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_49_IRQ_49" width="8" begin="23" end="16" resetval="0x32" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_48_IRQ_48" width="8" begin="7" end="0" resetval="0x31" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_50_51" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_50_51" offset="0xBDC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_51_IRQ_51" width="8" begin="23" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_50_IRQ_50" width="8" begin="7" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_52_53" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_52_53" offset="0xBE0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_53_IRQ_53" width="8" begin="23" end="16" resetval="0x36" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_52_IRQ_52" width="8" begin="7" end="0" resetval="0x35" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_54_55" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_54_55" offset="0xBE4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_55_IRQ_55" width="8" begin="23" end="16" resetval="0x38" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_54_IRQ_54" width="8" begin="7" end="0" resetval="0x37" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_56_57" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_56_57" offset="0xBE8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_57_IRQ_57" width="8" begin="23" end="16" resetval="0x3A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_56_IRQ_56" width="8" begin="7" end="0" resetval="0x39" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_58_59" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_58_59" offset="0xBEC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_59_IRQ_59" width="8" begin="23" end="16" resetval="0x3C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_58_IRQ_58" width="8" begin="7" end="0" resetval="0x3B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_60_61" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_60_61" offset="0xBF0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_61_IRQ_61" width="8" begin="23" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_60_IRQ_60" width="8" begin="7" end="0" resetval="0x3D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_62_63" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_62_63" offset="0xBF4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_63_IRQ_63" width="8" begin="23" end="16" resetval="0x40" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_62_IRQ_62" width="8" begin="7" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_64_65" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_64_65" offset="0xBF8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_65_IRQ_65" width="8" begin="23" end="16" resetval="0x42" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_64_IRQ_64" width="8" begin="7" end="0" resetval="0x41" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_66_67" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_66_67" offset="0xBFC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_67_IRQ_67" width="8" begin="23" end="16" resetval="0x44" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_66_IRQ_66" width="8" begin="7" end="0" resetval="0x43" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_68_69" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_68_69" offset="0xC00" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_69_IRQ_69" width="8" begin="23" end="16" resetval="0x46" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_68_IRQ_68" width="8" begin="7" end="0" resetval="0x45" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_70_71" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_70_71" offset="0xC04" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_71_IRQ_71" width="8" begin="23" end="16" resetval="0x48" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_70_IRQ_70" width="8" begin="7" end="0" resetval="0x47" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_72_73" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_72_73" offset="0xC08" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_73_IRQ_73" width="8" begin="23" end="16" resetval="0x4A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_72_IRQ_72" width="8" begin="7" end="0" resetval="0x49" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_74_75" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_74_75" offset="0xC0C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_75_IRQ_75" width="8" begin="23" end="16" resetval="0x4C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_74_IRQ_74" width="8" begin="7" end="0" resetval="0x4B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_76_77" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_76_77" offset="0xC10" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_77_IRQ_77" width="8" begin="23" end="16" resetval="0x4E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_76_IRQ_76" width="8" begin="7" end="0" resetval="0x4D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_78_79" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_78_79" offset="0xC14" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_79_IRQ_79" width="8" begin="23" end="16" resetval="0x50" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_78_IRQ_78" width="8" begin="7" end="0" resetval="0x4F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_80_81" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_80_81" offset="0xC18" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_81_IRQ_81" width="8" begin="23" end="16" resetval="0x52" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_80_IRQ_80" width="8" begin="7" end="0" resetval="0x51" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_82_83" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_82_83" offset="0xC1C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_83_IRQ_83" width="8" begin="23" end="16" resetval="0x54" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_82_IRQ_82" width="8" begin="7" end="0" resetval="0x53" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_84_85" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_84_85" offset="0xC20" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_85_IRQ_85" width="8" begin="23" end="16" resetval="0x56" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_84_IRQ_84" width="8" begin="7" end="0" resetval="0x55" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_86_87" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_86_87" offset="0xC24" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_87_IRQ_87" width="8" begin="23" end="16" resetval="0x58" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_86_IRQ_86" width="8" begin="7" end="0" resetval="0x57" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_88_89" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_88_89" offset="0xC28" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_89_IRQ_89" width="8" begin="23" end="16" resetval="0x5A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_88_IRQ_88" width="8" begin="7" end="0" resetval="0x59" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_90_91" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_90_91" offset="0xC2C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_91_IRQ_91" width="8" begin="23" end="16" resetval="0x5C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_90_IRQ_90" width="8" begin="7" end="0" resetval="0x5B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_92_93" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_92_93" offset="0xC30" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_93_IRQ_93" width="8" begin="23" end="16" resetval="0x5E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_92_IRQ_92" width="8" begin="7" end="0" resetval="0x5D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_94_95" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_94_95" offset="0xC34" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_95_IRQ_95" width="8" begin="23" end="16" resetval="0x60" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_94_IRQ_94" width="8" begin="7" end="0" resetval="0x5F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_96_97" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_96_97" offset="0xC38" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_97_IRQ_97" width="8" begin="23" end="16" resetval="0x62" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_96_IRQ_96" width="8" begin="7" end="0" resetval="0x61" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_98_99" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_98_99" offset="0xC3C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_99_IRQ_99" width="8" begin="23" end="16" resetval="0x64" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_98_IRQ_98" width="8" begin="7" end="0" resetval="0x63" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_100_101" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_100_101" offset="0xC40" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_101_IRQ_101" width="8" begin="23" end="16" resetval="0x66" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_100_IRQ_100" width="8" begin="7" end="0" resetval="0x65" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_102_103" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_102_103" offset="0xC44" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_103_IRQ_103" width="8" begin="23" end="16" resetval="0x68" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_102_IRQ_102" width="8" begin="7" end="0" resetval="0x67" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_104_105" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_104_105" offset="0xC48" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_105_IRQ_105" width="8" begin="23" end="16" resetval="0x6A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_104_IRQ_104" width="8" begin="7" end="0" resetval="0x69" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_106_107" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_106_107" offset="0xC4C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_107_IRQ_107" width="8" begin="23" end="16" resetval="0x6C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_106_IRQ_106" width="8" begin="7" end="0" resetval="0x6B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_108_109" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_108_109" offset="0xC50" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_109_IRQ_109" width="8" begin="23" end="16" resetval="0x6E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_108_IRQ_108" width="8" begin="7" end="0" resetval="0x6D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_110_111" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_110_111" offset="0xC54" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_111_IRQ_111" width="8" begin="23" end="16" resetval="0x70" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_110_IRQ_110" width="8" begin="7" end="0" resetval="0x6F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_112_113" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_112_113" offset="0xC58" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_113_IRQ_113" width="8" begin="23" end="16" resetval="0x72" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_112_IRQ_112" width="8" begin="7" end="0" resetval="0x71" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_114_115" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_114_115" offset="0xC5C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_115_IRQ_115" width="8" begin="23" end="16" resetval="0x74" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_114_IRQ_114" width="8" begin="7" end="0" resetval="0x73" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_116_117" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_116_117" offset="0xC60" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_117_IRQ_117" width="8" begin="23" end="16" resetval="0x76" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_116_IRQ_116" width="8" begin="7" end="0" resetval="0x75" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_118_119" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_118_119" offset="0xC64" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_119_IRQ_119" width="8" begin="23" end="16" resetval="0x78" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_118_IRQ_118" width="8" begin="7" end="0" resetval="0x77" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_120_121" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_120_121" offset="0xC68" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_121_IRQ_121" width="8" begin="23" end="16" resetval="0x7A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_120_IRQ_120" width="8" begin="7" end="0" resetval="0x79" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_122_123" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_122_123" offset="0xC6C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_123_IRQ_123" width="8" begin="23" end="16" resetval="0x7C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_122_IRQ_122" width="8" begin="7" end="0" resetval="0x7B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_124_125" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_124_125" offset="0xC70" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_125_IRQ_125" width="8" begin="23" end="16" resetval="0x7E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_124_IRQ_124" width="8" begin="7" end="0" resetval="0x7D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_SYSTEM_DREQ_126_127" acronym="CTRL_CORE_DMA_SYSTEM_DREQ_126_127" offset="0xC74" width="32" description="">
+    <bitfield id="RESERVED" width="24" begin="31" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_SYSTEM_DREQ_126_IRQ_126" width="8" begin="7" end="0" resetval="0x7F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_0_1" acronym="CTRL_CORE_DMA_EDMA_DREQ_0_1" offset="0xC78" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_1_IRQ_1" width="8" begin="23" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_0_IRQ_0" width="8" begin="7" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_2_3" acronym="CTRL_CORE_DMA_EDMA_DREQ_2_3" offset="0xC7C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_3_IRQ_3" width="8" begin="23" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_2_IRQ_2" width="8" begin="7" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_4_5" acronym="CTRL_CORE_DMA_EDMA_DREQ_4_5" offset="0xC80" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_5_IRQ_5" width="8" begin="23" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_4_IRQ_4" width="8" begin="7" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_6_7" acronym="CTRL_CORE_DMA_EDMA_DREQ_6_7" offset="0xC84" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_7_IRQ_7" width="8" begin="23" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_6_IRQ_6" width="8" begin="7" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_8_9" acronym="CTRL_CORE_DMA_EDMA_DREQ_8_9" offset="0xC88" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_9_IRQ_9" width="8" begin="23" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_8_IRQ_8" width="8" begin="7" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_10_11" acronym="CTRL_CORE_DMA_EDMA_DREQ_10_11" offset="0xC8C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_11_IRQ_11" width="8" begin="23" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_10_IRQ_10" width="8" begin="7" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_12_13" acronym="CTRL_CORE_DMA_EDMA_DREQ_12_13" offset="0xC90" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_13_IRQ_13" width="8" begin="23" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_12_IRQ_12" width="8" begin="7" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_14_15" acronym="CTRL_CORE_DMA_EDMA_DREQ_14_15" offset="0xC94" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_15_IRQ_15" width="8" begin="23" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_14_IRQ_14" width="8" begin="7" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_16_17" acronym="CTRL_CORE_DMA_EDMA_DREQ_16_17" offset="0xC98" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_17_IRQ_17" width="8" begin="23" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_16_IRQ_16" width="8" begin="7" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_18_19" acronym="CTRL_CORE_DMA_EDMA_DREQ_18_19" offset="0xC9C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_19_IRQ_19" width="8" begin="23" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_18_IRQ_18" width="8" begin="7" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_20_21" acronym="CTRL_CORE_DMA_EDMA_DREQ_20_21" offset="0xCA0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_21_IRQ_21" width="8" begin="23" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_20_IRQ_20" width="8" begin="7" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_22_23" acronym="CTRL_CORE_DMA_EDMA_DREQ_22_23" offset="0xCA4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_23_IRQ_23" width="8" begin="23" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_22_IRQ_22" width="8" begin="7" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_24_25" acronym="CTRL_CORE_DMA_EDMA_DREQ_24_25" offset="0xCA8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_25_IRQ_25" width="8" begin="23" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_24_IRQ_24" width="8" begin="7" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_26_27" acronym="CTRL_CORE_DMA_EDMA_DREQ_26_27" offset="0xCAC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_27_IRQ_27" width="8" begin="23" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_26_IRQ_26" width="8" begin="7" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_28_29" acronym="CTRL_CORE_DMA_EDMA_DREQ_28_29" offset="0xCB0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_29_IRQ_29" width="8" begin="23" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_28_IRQ_28" width="8" begin="7" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_30_31" acronym="CTRL_CORE_DMA_EDMA_DREQ_30_31" offset="0xCB4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_31_IRQ_31" width="8" begin="23" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_30_IRQ_30" width="8" begin="7" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_32_33" acronym="CTRL_CORE_DMA_EDMA_DREQ_32_33" offset="0xCB8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_33_IRQ_33" width="8" begin="23" end="16" resetval="0x22" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_32_IRQ_32" width="8" begin="7" end="0" resetval="0x21" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_34_35" acronym="CTRL_CORE_DMA_EDMA_DREQ_34_35" offset="0xCBC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_35_IRQ_35" width="8" begin="23" end="16" resetval="0x24" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_34_IRQ_34" width="8" begin="7" end="0" resetval="0x23" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_36_37" acronym="CTRL_CORE_DMA_EDMA_DREQ_36_37" offset="0xCC0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_37_IRQ_37" width="8" begin="23" end="16" resetval="0x26" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_36_IRQ_36" width="8" begin="7" end="0" resetval="0x25" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_38_39" acronym="CTRL_CORE_DMA_EDMA_DREQ_38_39" offset="0xCC4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_39_IRQ_39" width="8" begin="23" end="16" resetval="0x28" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_38_IRQ_38" width="8" begin="7" end="0" resetval="0x27" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_40_41" acronym="CTRL_CORE_DMA_EDMA_DREQ_40_41" offset="0xCC8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_41_IRQ_41" width="8" begin="23" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_40_IRQ_40" width="8" begin="7" end="0" resetval="0x29" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_42_43" acronym="CTRL_CORE_DMA_EDMA_DREQ_42_43" offset="0xCCC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_43_IRQ_43" width="8" begin="23" end="16" resetval="0x2C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_42_IRQ_42" width="8" begin="7" end="0" resetval="0x2B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_44_45" acronym="CTRL_CORE_DMA_EDMA_DREQ_44_45" offset="0xCD0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_45_IRQ_45" width="8" begin="23" end="16" resetval="0x2E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_44_IRQ_44" width="8" begin="7" end="0" resetval="0x2D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_46_47" acronym="CTRL_CORE_DMA_EDMA_DREQ_46_47" offset="0xCD4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_47_IRQ_47" width="8" begin="23" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_46_IRQ_46" width="8" begin="7" end="0" resetval="0x2F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_48_49" acronym="CTRL_CORE_DMA_EDMA_DREQ_48_49" offset="0xCD8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_49_IRQ_49" width="8" begin="23" end="16" resetval="0x32" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_48_IRQ_48" width="8" begin="7" end="0" resetval="0x31" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_50_51" acronym="CTRL_CORE_DMA_EDMA_DREQ_50_51" offset="0xCDC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_51_IRQ_51" width="8" begin="23" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_50_IRQ_50" width="8" begin="7" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_52_53" acronym="CTRL_CORE_DMA_EDMA_DREQ_52_53" offset="0xCE0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_53_IRQ_53" width="8" begin="23" end="16" resetval="0x36" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_52_IRQ_52" width="8" begin="7" end="0" resetval="0x35" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_54_55" acronym="CTRL_CORE_DMA_EDMA_DREQ_54_55" offset="0xCE4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_55_IRQ_55" width="8" begin="23" end="16" resetval="0x38" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_54_IRQ_54" width="8" begin="7" end="0" resetval="0x37" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_56_57" acronym="CTRL_CORE_DMA_EDMA_DREQ_56_57" offset="0xCE8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_57_IRQ_57" width="8" begin="23" end="16" resetval="0x3A" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_56_IRQ_56" width="8" begin="7" end="0" resetval="0x39" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_58_59" acronym="CTRL_CORE_DMA_EDMA_DREQ_58_59" offset="0xCEC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_59_IRQ_59" width="8" begin="23" end="16" resetval="0x3C" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_58_IRQ_58" width="8" begin="7" end="0" resetval="0x3B" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_60_61" acronym="CTRL_CORE_DMA_EDMA_DREQ_60_61" offset="0xCF0" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_61_IRQ_61" width="8" begin="23" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_60_IRQ_60" width="8" begin="7" end="0" resetval="0x3D" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_EDMA_DREQ_62_63" acronym="CTRL_CORE_DMA_EDMA_DREQ_62_63" offset="0xCF4" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_63_IRQ_63" width="8" begin="23" end="16" resetval="0x40" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_EDMA_DREQ_62_IRQ_62" width="8" begin="7" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_0_1" acronym="CTRL_CORE_DMA_DSP1_DREQ_0_1" offset="0xCF8" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_1_IRQ_1" width="8" begin="23" end="16" resetval="0x81" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_0_IRQ_0" width="8" begin="7" end="0" resetval="0x80" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_2_3" acronym="CTRL_CORE_DMA_DSP1_DREQ_2_3" offset="0xCFC" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_3_IRQ_3" width="8" begin="23" end="16" resetval="0x83" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_2_IRQ_2" width="8" begin="7" end="0" resetval="0x82" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_4_5" acronym="CTRL_CORE_DMA_DSP1_DREQ_4_5" offset="0xD00" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_5_IRQ_5" width="8" begin="23" end="16" resetval="0x85" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_4_IRQ_4" width="8" begin="7" end="0" resetval="0x84" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_6_7" acronym="CTRL_CORE_DMA_DSP1_DREQ_6_7" offset="0xD04" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_7_IRQ_7" width="8" begin="23" end="16" resetval="0x87" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_6_IRQ_6" width="8" begin="7" end="0" resetval="0x86" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_8_9" acronym="CTRL_CORE_DMA_DSP1_DREQ_8_9" offset="0xD08" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_9_IRQ_9" width="8" begin="23" end="16" resetval="0x89" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_8_IRQ_8" width="8" begin="7" end="0" resetval="0x88" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_10_11" acronym="CTRL_CORE_DMA_DSP1_DREQ_10_11" offset="0xD0C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_11_IRQ_11" width="8" begin="23" end="16" resetval="0x8B" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_10_IRQ_10" width="8" begin="7" end="0" resetval="0x8A" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_12_13" acronym="CTRL_CORE_DMA_DSP1_DREQ_12_13" offset="0xD10" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_13_IRQ_13" width="8" begin="23" end="16" resetval="0x8D" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_12_IRQ_12" width="8" begin="7" end="0" resetval="0x8C" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_14_15" acronym="CTRL_CORE_DMA_DSP1_DREQ_14_15" offset="0xD14" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_15_IRQ_15" width="8" begin="23" end="16" resetval="0x8F" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_14_IRQ_14" width="8" begin="7" end="0" resetval="0x8E" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_16_17" acronym="CTRL_CORE_DMA_DSP1_DREQ_16_17" offset="0xD18" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_17_IRQ_17" width="8" begin="23" end="16" resetval="0x9B" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_16_IRQ_16" width="8" begin="7" end="0" resetval="0x9A" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_DMA_DSP1_DREQ_18_19" acronym="CTRL_CORE_DMA_DSP1_DREQ_18_19" offset="0xD1C" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_19_IRQ_19" width="8" begin="23" end="16" resetval="0x9D" description="" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DMA_DSP1_DREQ_18_IRQ_18" width="8" begin="7" end="0" resetval="0x9C" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_OVS_DMARQ_IO_MUX" acronym="CTRL_CORE_OVS_DMARQ_IO_MUX" offset="0xD4C" width="32" description="">
+    <bitfield id="RESERVED" width="16" begin="31" end="16" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="OVS_DMARQ_IO_MUX_2" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="OVS_DMARQ_IO_MUX_1" width="8" begin="7" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_OVS_IRQ_IO_MUX" acronym="CTRL_CORE_OVS_IRQ_IO_MUX" offset="0xD50" width="32" description="">
+    <bitfield id="RESERVED" width="14" begin="31" end="18" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="OVS_IRQ_IO_MUX_2" width="9" begin="17" end="9" resetval="0x0" description="" range="" rwaccess="RW"/>
+    <bitfield id="OVS_IRQ_IO_MUX_1" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_PBIAS" acronym="CTRL_CORE_CONTROL_PBIAS" offset="0xE00" width="32" description="PBIASLITE control">
+    <bitfield id="RESERVED" width="4" begin="31" end="28" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="SDCARD_BIAS_PWRDNZ" width="1" begin="27" end="27" resetval="0x0" description="PWRDNZ control to SDCARD BIAS 0x0 = This signal is used to protect SDCARD BIAS when VDDS is not stable 0x1 = SW keep this bit to 1'b1 after VDDS stabilizing" range="" rwaccess="RW"/>
+    <bitfield id="SDCARD_IO_PWRDNZ" width="1" begin="26" end="26" resetval="0x0" description="PWRDNZ control to SDCARD IO 0x0 = This signal is used to protect SDCARD IOs when VDDS is not stable 0x1 = SW keep this bit to 1'b1 after VDDS stabilizing" range="" rwaccess="RW"/>
+    <bitfield id="SDCARD_BIAS_HIZ_MODE" width="1" begin="25" end="25" resetval="0x0" description="HIZ_MODE from SDCARD PBIAS 0x0 = PBIAS in normal operation mode 0x1 = PBIAS output is in high impedance state" range="" rwaccess="RW"/>
+    <bitfield id="SDCARD_BIAS_SUPPLY_HI_OUT" width="1" begin="24" end="24" resetval="0x0" description="SUPPLY_HI_OUT from SDCARD PBIAS 0x0 = VDDS = 1.8V 0x1 = VDDS = 3.3V" range="" rwaccess="R"/>
+    <bitfield id="SDCARD_BIAS_VMODE_ERROR" width="1" begin="23" end="23" resetval="0x0" description="VMODE ERROR from SDCARD PBIAS 0x0 = VMODE level is same as SUPPLY_HI_OUT 0x1 = VMODE level is not same as SUPPLY_HI_OUT" range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="1" begin="22" end="22" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="SDCARD_BIAS_VMODE" width="1" begin="21" end="21" resetval="0x1" description="VMODE control to SDCARD PBIAS 0x0 = VDDS = 1.8V 0x1 = VDDS = 3.3V" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="21" begin="20" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_HDMI_TX_PHY" acronym="CTRL_CORE_CONTROL_HDMI_TX_PHY" offset="0xE0C" width="32" description="HDMI TX PHY control">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="HDMITXPHY_TXVALID" width="1" begin="30" end="30" resetval="0x0" description="0x1= Valid data on the HDMI_TXPHY input data interface , sampled on the rising edge of TMDSCLK" range="" rwaccess="RW"/>
+    <bitfield id="HDMITXPHY_ENBYPASSCLK" width="1" begin="29" end="29" resetval="0x0" description="0x1 = Enables the HFBYPASSCLK to be used in place of the HFBITCLK" range="" rwaccess="RW"/>
+    <bitfield id="HDMITXPHY_PD_PULLUPDET" width="1" begin="28" end="28" resetval="0x1" description="0x0 = Set this bit to 0x0 if RX connection is required to be detected, even when HDMI_TXPHY is powered down 0x1 = Disables the low power RX detection functionality" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="28" begin="27" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_USB2PHYCORE" acronym="CTRL_CORE_CONTROL_USB2PHYCORE" offset="0xE1C" width="32" description="This register is related to the USB2_PHY1">
+    <bitfield id="USB2PHY_AUTORESUME_EN" width="1" begin="31" end="31" resetval="0x0" description="Auto resume enable 0x0 = disable autoresume 0x1 = enable autoresume" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_DISCHGDET" width="1" begin="30" end="30" resetval="0x1" description="Disable charger detect 0x0 = charger detect function enabled 0x1 = charger detect function disabled" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_GPIOMODE" width="1" begin="29" end="29" resetval="0x0" description="GPIO mode 0x0 = USB mode enabled 0x1 = GPIO mode enabled" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_CHG_DET_EXT_CTL" width="1" begin="28" end="28" resetval="0x0" description="Charge detect external control 0x0 = charger detect internal state machine used 0x1 = charge detect statemachine is bypassed" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_RDM_PD_CHGDET_EN" width="1" begin="27" end="27" resetval="0x0" description="DM Pull down control 0x0 = PD disabled 0x1 = PD enabled" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_RDP_PU_CHGDET_EN" width="1" begin="26" end="26" resetval="0x0" description="DP Pull up control 0x0 = PU disabled 0x1 = PU enabled" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_CHG_VSRC_EN" width="1" begin="25" end="25" resetval="0x0" description="VSRC enable on DP line:Host charger case 0x0 = disable VSRC drive on DP 0x1 = drives VSRC 600mV on DP line" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_CHG_ISINK_EN" width="1" begin="24" end="24" resetval="0x0" description="ISINK enable on DM line:Host charger case 0x0 = disable the isink on DM 0x1 = enables the ISINK (100uA) on DM line" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_CHG_DET_STATUS" width="3" begin="23" end="21" resetval="0x0" description="Status of charger detection 0x0 = Wait state 0x1 = No contact 0x2 = PS/2 0x3 = Unknown error 0x4 = Dedicated charger 0x5 = HOST charger 0x6 = PC 0x7 = Interrupt" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_CHG_DET_DM_COMP" width="1" begin="20" end="20" resetval="0x0" description="Output of the comparator on DM during the resistor host detect protocol 0x0 = DM line is below 0.75V to 0.95V 0x1 = DM line is above 0.75V to 0.95V" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_CHG_DET_DP_COMP" width="1" begin="19" end="19" resetval="0x0" description="Output of the comparator on DP during the resistor host detect protocol 0x0 = DP line is below 0.75V to 0.95V 0x1 = DP line is above 0.75V to 0.95V" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_DATADET" width="1" begin="18" end="18" resetval="0x0" description="Output of the charger detect comparator 0x0 = DM line is below 0.25V to 0.4V 0x1 = DM line is above 0.25V to 0.4V" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_SINKONDP" width="1" begin="17" end="17" resetval="0x0" description="When '1' current sink is connected to DP instead of DM 0x0 = Default value 0x1 = enables the ISINK on DP instead of DM" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_SRCONDM" width="1" begin="16" end="16" resetval="0x0" description="When '1' voltage source is connected to DP instead of DM 0x0 = Default value 0x1 = enable the VSRC on DM instead of DP" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_RESTARTCHGDET" width="1" begin="15" end="15" resetval="0x0" description="restartchgdet = '1' for 1 msec cause the CD_START to reset 0x0 = Default value 0x1 = a high pulse of 1 msec causes the charger detect to restart on negative edge of restartchgdet" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_CHGDETDONE" width="1" begin="14" end="14" resetval="0x0" description="Status indicates that charger detection protocol is over 0x0 = charger detection protocol is not over 0x1 = charger detection protocol is over" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_CHGDETECTED" width="1" begin="13" end="13" resetval="0x0" description="Output of the charger detection protocol 0x0 = charger not detected 0x1 = charger detected" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_MCPCPUEN" width="1" begin="12" end="12" resetval="0x0" description="MCPC Pull up enable 0x0 = disable the MCPC pull up 0x1 = enable the 4.7K to10K pull up on receive line DP when datapolarityn is 0 and DM when datapolarityn is 1" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_MCPCMODEEN" width="1" begin="11" end="11" resetval="0x0" description="MCPC Mode enable 0x0 = disable MCPC mode 0x1 = enable MCPC mode" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_RESETDONEMCLK" width="1" begin="10" end="10" resetval="0x0" description="OCP reset status 0x0 = OCP domain is in reset 0x1 = OCP domain is out of reset" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_UTMIRESETDONE" width="1" begin="9" end="9" resetval="0x0" description="UTMI FSM reset status 0x0 = UTMI FSMs are in reset 0x1 = UTMI FSMs are out of reset" range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="1" begin="8" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_DATAPOLARITYN" width="1" begin="7" end="7" resetval="0x0" description="Data polarity 0x0 = DP functionality is on DP and DM funcationality is on DM 0x1 = DP functionality is on DM and DM functionality is on DP" range="" rwaccess="RW"/>
+    <bitfield id="USBDPLL_FREQLOCK" width="1" begin="6" end="6" resetval="0x0" description="Status from USB DPLL" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_RESETDONETCLK" width="1" begin="5" end="5" resetval="0x0" description="resetdonetclk status from USB2PHY" range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="5" begin="4" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_HDMI_1" acronym="CTRL_CORE_CONTROL_HDMI_1" offset="0xE20" width="32" description="HDMI pads control 1">
+    <bitfield id="HDMI_DDC_SDA_GLFENB" width="1" begin="31" end="31" resetval="0x0" description="Active_high glitch free operation enable pin for hdmi_ddc_sda receiver" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="HDMI_DDC_SDA_GLFENB_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="HDMI_DDC_SDA_GLFENB_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="HDMI_DDC_SDA_PULLUPRESX" width="1" begin="30" end="30" resetval="0x0" description="Active_low internal pull_up resistor enabled for hdmi_ddc_sda" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="HDMI_DDC_SDA_PULLUPRESX_0" description="Enabled"/>
+      <bitenum value="1" id="DISABLE" token="HDMI_DDC_SDA_PULLUPRESX_1" description="Disabled"/>
+    </bitfield>
+    <bitfield id="HDMI_DDC_SCL_GLFENB" width="1" begin="29" end="29" resetval="0x0" description="Active_high glitch free operation enable pin for hdmi_ddc_scl receiver" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="HDMI_DDC_SCL_GLFENB_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="HDMI_DDC_SCL_GLFENB_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="HDMI_DDC_SCL_PULLUPRESX" width="1" begin="28" end="28" resetval="0x0" description="Active_low internal pull_up resistor enabled for hdmi_ddc_scl" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="HDMI_DDC_SCL_PULLUPRESX_0" description="Enabled"/>
+      <bitenum value="1" id="DISABLE" token="HDMI_DDC_SCL_PULLUPRESX_1" description="Disabled"/>
+    </bitfield>
+    <bitfield id="HDMI_DDC_SDA_HSMODE" width="1" begin="27" end="27" resetval="0x0" description="Active-high selection for I2C High-Speed mode" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="HDMI_DDC_SDA_HSMODE_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="HDMI_DDC_SDA_HSMODE_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="HDMI_DDC_SCL_HSMODE" width="1" begin="26" end="26" resetval="0x0" description="Active-high selection for I2C High-Speed mode" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="HDMI_DDC_SCL_HSMODE_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="HDMI_DDC_SCL_HSMODE_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="26" begin="25" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_DDRCACH1_0" acronym="CTRL_CORE_CONTROL_DDRCACH1_0" offset="0xE30" width="32" description="ddrcaCH1 control">
+    <bitfield id="DDRCH1_PART0_I" width="3" begin="31" end="29" resetval="0x2" description="PART0 Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART0_SR" width="3" begin="28" end="26" resetval="0x2" description="PART0 Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART0_WD" width="2" begin="25" end="24" resetval="0x2" description="PART0 Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART5A_I" width="3" begin="23" end="21" resetval="0x2" description="PART5A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART5A_SR" width="3" begin="20" end="18" resetval="0x2" description="PART5A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART5A_WD" width="2" begin="17" end="16" resetval="0x2" description="PART5A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART5B_I" width="3" begin="15" end="13" resetval="0x2" description="PART5B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART5B_SR" width="3" begin="12" end="10" resetval="0x2" description="PART5B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART5B_WD" width="2" begin="9" end="8" resetval="0x2" description="PART5B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART6_I" width="3" begin="7" end="5" resetval="0x2" description="PART6 Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART6_SR" width="3" begin="4" end="2" resetval="0x2" description="PART6 Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART6_WD" width="2" begin="1" end="0" resetval="0x2" description="PART6 Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_DDRCH1_0" acronym="CTRL_CORE_CONTROL_DDRCH1_0" offset="0xE38" width="32" description="DDRCH1 control 0">
+    <bitfield id="DDRCH1_PART1A_I" width="3" begin="31" end="29" resetval="0x2" description="PART1A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART1A_SR" width="3" begin="28" end="26" resetval="0x2" description="PART1A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART1A_WD" width="2" begin="25" end="24" resetval="0x2" description="PART1A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART1B_I" width="3" begin="23" end="21" resetval="0x2" description="PART1B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART1B_SR" width="3" begin="20" end="18" resetval="0x2" description="PART1B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART1B_WD" width="2" begin="17" end="16" resetval="0x2" description="PART1B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART2A_I" width="3" begin="15" end="13" resetval="0x2" description="PART2A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART2A_SR" width="3" begin="12" end="10" resetval="0x2" description="PART2A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART2A_WD" width="2" begin="9" end="8" resetval="0x2" description="PART2A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART2B_I" width="3" begin="7" end="5" resetval="0x2" description="PART2B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART2B_SR" width="3" begin="4" end="2" resetval="0x2" description="PART2B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART2B_WD" width="2" begin="1" end="0" resetval="0x2" description="PART2B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_DDRCH1_1" acronym="CTRL_CORE_CONTROL_DDRCH1_1" offset="0xE3C" width="32" description="DDRCH1 control 1">
+    <bitfield id="DDRCH1_PART3A_I" width="3" begin="31" end="29" resetval="0x2" description="PART3A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART3A_SR" width="3" begin="28" end="26" resetval="0x2" description="PART3A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART3A_WD" width="2" begin="25" end="24" resetval="0x2" description="PART3A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART3B_I" width="3" begin="23" end="21" resetval="0x2" description="PART3B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART3B_SR" width="3" begin="20" end="18" resetval="0x2" description="PART3B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART3B_WD" width="2" begin="17" end="16" resetval="0x2" description="PART3B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART4A_I" width="3" begin="15" end="13" resetval="0x2" description="PART4A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART4A_SR" width="3" begin="12" end="10" resetval="0x2" description="PART4A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART4A_WD" width="2" begin="9" end="8" resetval="0x2" description="PART4A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART4B_I" width="3" begin="7" end="5" resetval="0x2" description="PART4B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART4B_SR" width="3" begin="4" end="2" resetval="0x2" description="PART4B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART4B_WD" width="2" begin="1" end="0" resetval="0x2" description="PART4B Weak driver control WD[1:0] -For single-ended operation 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_DDRCH1_2" acronym="CTRL_CORE_CONTROL_DDRCH1_2" offset="0xE48" width="32" description="">
+    <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DDRCH1_PART7A_I" width="3" begin="23" end="21" resetval="0x2" description="PART7A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART7A_SR" width="3" begin="20" end="18" resetval="0x2" description="PART7A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART7A_WD" width="2" begin="17" end="16" resetval="0x2" description="PART7A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART7B_I" width="3" begin="15" end="13" resetval="0x2" description="PART7B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART7B_SR" width="3" begin="12" end="10" resetval="0x2" description="PART7B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" range="" rwaccess="RW"/>
+    <bitfield id="DDRCH1_PART7B_WD" width="2" begin="9" end="8" resetval="0x2" description="PART7B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="8" begin="7" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_DDRIO_0" acronym="CTRL_CORE_CONTROL_DDRIO_0" offset="0xE50" width="32" description="">
+    <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="DDRCH1_VREF_DQ0_INT_CCAP0" width="1" begin="19" end="19" resetval="0x1" description="Selection for coupling cap connection" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ0_INT_CCAP0_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ0_INT_CCAP0_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="DDRCH1_VREF_DQ0_INT_CCAP1" width="1" begin="18" end="18" resetval="0x0" description="Selection for coupling cap connection" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ0_INT_CCAP1_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ0_INT_CCAP1_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="DDRCH1_VREF_DQ0_INT_TAP0" width="1" begin="17" end="17" resetval="0x0" description="Selection for internal reference voltage drive" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ0_INT_TAP0_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ0_INT_TAP0_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="DDRCH1_VREF_DQ0_INT_TAP1" width="1" begin="16" end="16" resetval="0x1" description="Selection for internal reference voltage drive" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ0_INT_TAP1_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ0_INT_TAP1_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="DDRCH1_VREF_DQ0_INT_EN" width="1" begin="15" end="15" resetval="0x1" description="Enable" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ0_INT_EN_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ0_INT_EN_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="DDRCH1_VREF_DQ1_INT_CCAP0" width="1" begin="14" end="14" resetval="0x1" description="Selection for coupling cap connection" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ1_INT_CCAP0_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ1_INT_CCAP0_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="DDRCH1_VREF_DQ1_INT_CCAP1" width="1" begin="13" end="13" resetval="0x0" description="Selection for coupling cap connection" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ1_INT_CCAP1_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ1_INT_CCAP1_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="DDRCH1_VREF_DQ1_INT_TAP0" width="1" begin="12" end="12" resetval="0x0" description="Selection for internal reference voltage drive" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ1_INT_TAP0_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ1_INT_TAP0_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="DDRCH1_VREF_DQ1_INT_TAP1" width="1" begin="11" end="11" resetval="0x1" description="Selection for internal reference voltage drive" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ1_INT_TAP1_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ1_INT_TAP1_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="DDRCH1_VREF_DQ1_INT_EN" width="1" begin="10" end="10" resetval="0x1" description="Enable" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="DDRCH1_VREF_DQ1_INT_EN_0" description="Disabled"/>
+      <bitenum value="1" id="ENABLE" token="DDRCH1_VREF_DQ1_INT_EN_1" description="Enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="10" begin="9" end="0" resetval="0x260" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_CONTROL_HYST_1" acronym="CTRL_CORE_CONTROL_HYST_1" offset="0xE5C" width="32" description="Register for hysteresis and impedance control of the MMC1 pads. Effective when corresponding MUXMODE field is not configured for MMC operation.">
+    <bitfield id="SDCARD_HYST" width="1" begin="31" end="31" resetval="0x1" description="Hysteresis control for sdcard 0x0 = Disabled 0x1 = Enabled" range="" rwaccess="RW"/>
+    <bitfield id="SDCARD_IC" width="2" begin="30" end="29" resetval="0x0" description="Drive strength control for MMC1 pads In 3.3V signaling mode: 0x0: 50 Ohms Drive Strength 0x1: 33 Ohms Drive Strength 0x2: 66 Ohms Drive Strength 0x3: Reserved In 1.8V signaling mode: 0x0: 44 Ohms Drive Strength 0x1: 33 Ohms Drive Strength 0x2: 58 Ohms Drive Strength 0x3: 100 Ohms Drive Strength" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="29" begin="28" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_SPARE_RW" acronym="CTRL_CORE_SPARE_RW" offset="0xE68" width="32" description="">
+    <bitfield id="CORE_CONTROL_SPARE_RW_MMC1_LOOPBACK" width="1" begin="31" end="31" resetval="0x0" description="Selects the source of loopback clock for mmc1_clk." range="" rwaccess="RW"/>
+    <bitfield id="CORE_CONTROL_SPARE_RW_MMC2_LOOPBACK" width="1" begin="30" end="30" resetval="0x0" description="Selects the source of loopback clock for mmc2_clk. 0x0: Loopback clock from the I/O pad is selected 0x1: Internal loopback clock is selected" range="" rwaccess="RW"/>
+    <bitfield id="CORE_CONTROL_SPARE_RW" width="30" begin="29" end="0" resetval="0x0" description="Spare bits." range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_SPARE_R" acronym="CTRL_CORE_SPARE_R" offset="0xE6C" width="32" description="This register is associated with signals of the circuit for doubling the MLB clock line frequency described in, Doubling the MLB Clock Line Frequency.">
+    <bitfield id="CORE_CONTROL_SPARE_R_MDLL_CODE_RC" width="9" begin="31" end="23" resetval="0x0" description="Master DLL code - post the ratio conversion." range="" rwaccess="R"/>
+    <bitfield id="CORE_CONTROL_SPARE_R_MDLL_CODE_VAL_RC" width="1" begin="22" end="22" resetval="0x0" description="Post ratio conversion code update signal." range="" rwaccess="R"/>
+    <bitfield id="CORE_CONTROL_SPARE_R_MDLL_CODE" width="9" begin="21" end="13" resetval="0x0" description="Master DLL code." range="" rwaccess="R"/>
+    <bitfield id="CORE_CONTROL_SPARE_R_MDLL_CODE_VAL" width="1" begin="12" end="12" resetval="0x0" description="Master DLL code valid status." range="" rwaccess="R"/>
+    <bitfield id="CORE_CONTROL_SPARE_R_INP_CLK_SDL" width="1" begin="11" end="11" resetval="0x0" description="Input clock to slave DLL." range="" rwaccess="R"/>
+    <bitfield id="CORE_CONTROL_SPARE_R_OUT_CLK_SDL" width="1" begin="10" end="10" resetval="0x0" description="Output clock from slave DLL - quarter cycle shifted." range="" rwaccess="R"/>
+    <bitfield id="CORE_CONTROL_SPARE_R_200M_MLB_CLK" width="1" begin="9" end="9" resetval="0x0" description="200MHz clock going to MLB." range="" rwaccess="R"/>
+    <bitfield id="CORE_CONTROL_SPARE_R_SDL1_DBG_OUT" width="1" begin="8" end="8" resetval="0x0" description="Debug output from DCC SDL 1." range="" rwaccess="R"/>
+    <bitfield id="CORE_CONTROL_SPARE_R_SDL2_DBG_OUT" width="1" begin="7" end="7" resetval="0x0" description="Debug output from DCC SDL 2." range="" rwaccess="R"/>
+    <bitfield id="CORE_CONTROL_SPARE_R" width="7" begin="6" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_SRCOMP_NORTH_SIDE" acronym="CTRL_CORE_SRCOMP_NORTH_SIDE" offset="0xE74" width="32" description="This register is related to the USB2_PHY2.">
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_AUTORESUME_EN" width="1" begin="30" end="30" resetval="0x0" description="Auto resume enable 0x0: disable autoresume 0x1: enable autoresume" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_DISCHGDET" width="1" begin="29" end="29" resetval="0x1" description="Disable charger detect 0x0: charger detect function enabled 0x1: charger detect function disabled" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_PD" width="1" begin="28" end="28" resetval="0x0" description="Power down the entire USB2_PHY2 (data, common module and UTMI). 0x0: Normal operation 0x1: Power down the USB2_PHY2" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="7" begin="27" end="21" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_CHG_DET_DM_COMP" width="1" begin="20" end="20" resetval="0x0" description="Output of the comparator on DM during the resistor host detect protocol. 0x0: DM line is below 0.75V to 0.95V 0x1: DM line is above 0.75V to 0.95V" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_CHG_DET_DP_COMP" width="1" begin="19" end="19" resetval="0x0" description="Output of the comparator on DP during the resistor host detect protocol 0x0: DP line is below 0.75V to 0.95V 0x1: DP line is above 0.75V to 0.95V" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_DATADET" width="1" begin="18" end="18" resetval="0x0" description="Output of the charger detect comparator 0x0: DM line is below 0.25V to 0.4V 0x1: DM line is above 0.25V to 0.4V" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_CHGDETDONE" width="1" begin="17" end="17" resetval="0x0" description="Status indicates that charger detection protocol is over 0x0: charger detection protocol is not over 0x1: charger detection protocol is over" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_CHGDETECTED" width="1" begin="16" end="16" resetval="0x0" description="Output of the charger detection protocol 0x0: charger not detected 0x1: charger detected" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_RESETDONEMCLK" width="1" begin="15" end="15" resetval="0x0" description="OCP reset status 0x0: OCP domain is in reset 0x1: OCP domain is out of reset" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_UTMIRESETDONE" width="1" begin="14" end="14" resetval="0x0" description="UTMI FSM reset status 0x0: UTMI FSMs are in reset 0x1: UTMI FSMs are out of reset" range="" rwaccess="R"/>
+    <bitfield id="USBDPLL_FREQLOCK" width="1" begin="13" end="13" resetval="0x0" description="Status from USB DPLL" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_RESETDONETCLK" width="1" begin="12" end="12" resetval="0x0" description="resetdonetclk status from USB2_PHY2" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_GPIOMODE" width="1" begin="11" end="11" resetval="0x0" description="GPIO mode 0x0: USB mode enabled 0x1: GPIO mode enabled" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_CHG_DET_EXT_CTL" width="1" begin="10" end="10" resetval="0x0" description="Charge detect external control 0x0: charger detect internal state machine used 0x1: charge detect statemachine is bypassed" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_RDM_PD_CHGDET_EN" width="1" begin="9" end="9" resetval="0x0" description="DM Pull down control 0x0: PD disabled 0x1: PD enabled" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_RDP_PU_CHGDET_EN" width="1" begin="8" end="8" resetval="0x0" description="DP Pull up control 0x0: PU disabled 0x1: PU enabled" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_CHG_VSRC_EN" width="1" begin="7" end="7" resetval="0x0" description="VSRC enable on DP line: Host charger case 0x0: disable VSRC drive on DP 0x1: drives VSRC 600mV on DP line" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_CHG_ISINK_EN" width="1" begin="6" end="6" resetval="0x0" description="ISINK enable on DM line: Host charger case 0x0: disable the ISINK on DM 0x1: enables the ISINK (100&#181;A) on DM line" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_SINKONDP" width="1" begin="5" end="5" resetval="0x0" description="When '1' current sink is connected to DP instead of DM 0x0: Default value 0x1: enables the ISINK on DP instead of DM" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_SRCONDM" width="1" begin="4" end="4" resetval="0x0" description="When '1' voltage source is connected to DP instead of DM 0x0: Default value 0x1: enable the VSRC on DM instead of DP" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_RESTARTCHGDET" width="1" begin="3" end="3" resetval="0x0" description="restartchgdet: '1' for 1 msec cause the CD_START to reset 0x0: Default value 0x1: a high pulse of 1 msec causes the charger detect to restart on negative edge of restartchgdet" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_MCPCPUEN" width="1" begin="2" end="2" resetval="0x0" description="MCPC Pull up enable 0x0: disable the MCPC pull up 0x1: enable the 4.7K to10K pull up on receive line DP when datapolarityn is 0 and DM when datapolarityn is 1" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_MCPCMODEEN" width="1" begin="1" end="1" resetval="0x0" description="MCPC Mode enable 0x0: disable MCPC mode 0x1: enable MCPC mode" range="" rwaccess="RW"/>
+    <bitfield id="USB2PHY_DATAPOLARITYN" width="1" begin="0" end="0" resetval="0x0" description="Data polarity 0x0: DP functionality is on DP and DM funcationality is on DM 0x1: DP functionality is on DM and DM functionality is on DP" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_SRCOMP_SOUTH_SIDE" acronym="CTRL_CORE_SRCOMP_SOUTH_SIDE" offset="0xE78" width="32" description="This register is related to the USB2_PHY2.">
+    <bitfield id="RESERVED" width="17" begin="31" end="15" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="USB2PHY_CHG_DET_STATUS" width="3" begin="14" end="12" resetval="0x0" description="Status of charger detection 0x0: Wait state 0x1: No contact 0x2: PS/2 0x3: Unknown error 0x4: Dedicated charger 0x5: HOST charger 0x6: PC 0x7: Interrupt" range="" rwaccess="R"/>
+    <bitfield id="RESERVED" width="12" begin="11" end="0" resetval="0x0" description="" range="" rwaccess="R"/>
+  </register>
+  <register id="CTRL_CORE_VIP_MUX_SELECT" acronym="CTRL_CORE_VIP_MUX_SELECT" offset="0xE8C" width="32" description="Select the ports to be used with the VIP.">
+    <bitfield id="RESERVED" width="25" begin="31" end="7" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="VIP_SEL_1A" width="3" begin="6" end="4" resetval="0x0" description="Remaps the vin1a signals. 0x0: The vin1a signals are mapped to GROUP3A pads depending on the selected mux mode 0x1: The vin1a signals are mapped to GROUP5A pads depending on the selected mux mode 0x2: The vin1a signals are mapped to GROUP6A pads depending on the selected mux mode 0x3: The vin1a signals are mapped to GROUP4A pads depending on the selected mux mode 0x4-0x7: CAL Video Port signals are mapped to vin1a signals" range="" rwaccess="RW"/>
+    <bitfield id="VIP_SEL_1B" width="1" begin="3" end="3" resetval="0x0" description="Remaps the vin1b signals. 0x0: The vin1b signals are mapped to GROUP4B pads depending on the selected mux mode 0x1: The vin1b signals are mapped to GROUP3B pads depending on the selected mux mode" range="" rwaccess="RW"/>
+    <bitfield id="VIP_SEL_2A" width="2" begin="2" end="1" resetval="0x0" description="Remaps the vin2a signals. 0x0: The vin2a signals are mapped to GROUP2A pads depending on the selected mux mode 0x1: The vin2a signals are mapped to GROUP4A pads depending on the selected mux mode 0x2-0x3: CAL Video Port signals are mapped to vin2a signals" range="" rwaccess="RW"/>
+    <bitfield id="VIP_SEL_2B" width="1" begin="0" end="0" resetval="0x0" description="Remaps the vin2b signals. 0x0: The vin2b signals are mapped to GROUP2B pads depending on the selected mux mode 0x1: The vin2b signals are mapped to GROUP3B pads depending on the selected mux mode" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_ALT_SELECT_MUX" acronym="CTRL_CORE_ALT_SELECT_MUX" offset="0xE90" width="32" description="">
+    <bitfield id="RESERVED" width="24" begin="31" end="8" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="SEL_ALT_I2C6_SEL" width="1" begin="7" end="7" resetval="0x0" description="0x0: The mcasp4_axr[0:1] pads have normal behavior. This means, the signal mapped to these pads depends on the MUXMODE field. 0x1: The i2c6_scl and i2c6_sda signals are mapped to the mcasp4_axr[0:1] pads, respectively. This setting overrides the MUXMODE setting." range="" rwaccess="RW"/>
+    <bitfield id="SEL_ALT_USB3_USB4" width="1" begin="6" end="6" resetval="0x0" description="0x0: The USB3 signals are mapped to USB_GROUP3 pads. 0x1: The USB3 signals are mapped to USB_GROUP4 pads." range="" rwaccess="RW"/>
+    <bitfield id="SEL_ALT_WAKEUP0_WAKEUP_2" width="1" begin="5" end="5" resetval="0x0" description="0x0: The gpio1_0 signal is on the Wakeup0 pad when MUXMODE = 0xE. 0x1: The sys_nirq2 signal is on the Wakeup0 pad when MUXMODE = 0xE." range="" rwaccess="RW"/>
+    <bitfield id="SEL_ALT_WAKEUP3_WAKEUP_1" width="1" begin="4" end="4" resetval="0x0" description="0x0: The gpio1_3 signal is on Wakeup3 pad when MUXMODE = 0xE. 0x1: The dcan2_rx signal is on the Wakeup3 pad when MUXMODE = 0xE." range="" rwaccess="RW"/>
+    <bitfield id="SEL_ALT_GROUP1" width="1" begin="3" end="3" resetval="0x0" description="0x0: GPIO function is selected on the pads from GROUP1 0x1: New function is selected on the pads from GROUP1 as described in" range="" rwaccess="RW"/>
+    <bitfield id="SEL_ALT_GROUP2" width="1" begin="2" end="2" resetval="0x0" description="Selects a signal as described in" range="" rwaccess="RW"/>
+    <bitfield id="SEL_ALT_GROUP3" width="1" begin="1" end="1" resetval="0x0" description="0x0: GPIO function is selected on the pads from GROUP3 0x1: New function is selected on the pads from GROUP3 as described in" range="" rwaccess="RW"/>
+    <bitfield id="SEL_ALT_GROUP4" width="1" begin="0" end="0" resetval="0x0" description="Selects a signal as described in" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_CAMERRX_CONTROL" acronym="CTRL_CORE_CAMERRX_CONTROL" offset="0xE94" width="32" description="CSI2 PHY control register. Bit-fields CSI0_* control CSI2_PHY1. Bit-fields CSI1_* control CSI2_PHY2.">
+    <bitfield id="RESERVED" width="14" begin="31" end="18" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CSI0_MODE" width="1" begin="17" end="17" resetval="0x0" description="csi0 mode" range="" rwaccess="RW"/>
+    <bitfield id="CSI0_LANEENABLE" width="4" begin="16" end="13" resetval="0x0" description="csi0 camera lane enable 0x0: Lane module disabled 0x1: Lane module enabled" range="" rwaccess="RW"/>
+    <bitfield id="CSI0_CAMMODE" width="2" begin="12" end="11" resetval="0x0" description="csi0 camera mode 0x0: DPHY mode 0x1: Data/Strobe Transmission format 0x2: Data/Clock Transmission format 0x3: GPI mode" range="" rwaccess="RW"/>
+    <bitfield id="CSI0_CTRLCLKEN" width="1" begin="10" end="10" resetval="0x0" description="csi0 camera clock enable control 0x0: Disable for CTRLCLK 0x1: Active high enable for CTRLCLK" range="" rwaccess="RW"/>
+    <bitfield id="RESERVED" width="4" begin="9" end="6" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="CSI1_MODE" width="1" begin="5" end="5" resetval="0x0" description="csi1 mode" range="" rwaccess="RW"/>
+    <bitfield id="CSI1_LANEENABLE" width="2" begin="4" end="3" resetval="0x0" description="csi1 camera lane enable 0x0: Lane module disabled 0x1: Lane module enabled" range="" rwaccess="RW"/>
+    <bitfield id="CSI1_CAMMODE" width="2" begin="2" end="1" resetval="0x0" description="csi1 camera mode 0x0: DPHY mode 0x1: Data/Strobe Transmission format 0x2: Data/Clock Transmission format 0x3: GPI mode" range="" rwaccess="RW"/>
+    <bitfield id="CSI1_CTRLCLKEN" width="1" begin="0" end="0" resetval="0x0" description="csi1 camera clock enable control 0x0: Disable for CTRLCLK 0x1: Active high enable for CTRLCLK" range="" rwaccess="RW"/>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD0" acronym="CTRL_CORE_PAD_GPMC_AD0" offset="0x1400" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD0_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD0_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD0_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD0_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD0_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD0_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD0_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD0_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD0_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD0_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD0_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD0_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD0_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD0_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD0_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD0_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD0_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD0_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD0_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD0_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD0_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD0_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD0_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD0" token="GPMC_AD0_MUXMODE_0" description="gpmc_ad0"/>
+      <bitenum value="2" id="VIN1A_D0" token="GPMC_AD0_MUXMODE_2" description="vin1a_d0"/>
+      <bitenum value="3" id="VOUT3_D0" token="GPMC_AD0_MUXMODE_3" description="vout3_d0"/>
+      <bitenum value="14" id="GPIO1_6" token="GPMC_AD0_MUXMODE_14" description="gpio1_6"/>
+      <bitenum value="15" id="SYSBOOT0" token="GPMC_AD0_MUXMODE_15" description="sysboot0"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD1" acronym="CTRL_CORE_PAD_GPMC_AD1" offset="0x1404" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD1_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD1_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD1_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD1_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD1_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD1_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD1_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD1_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD1_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD1_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD1_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD1_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD1_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD1_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD1_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD1_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD1_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD1_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD1_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD1_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD1_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD1_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD1_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD1" token="GPMC_AD1_MUXMODE_0" description="gpmc_ad1"/>
+      <bitenum value="2" id="VIN1A_D1" token="GPMC_AD1_MUXMODE_2" description="vin1a_d1"/>
+      <bitenum value="3" id="VOUT3_D1" token="GPMC_AD1_MUXMODE_3" description="vout3_d1"/>
+      <bitenum value="14" id="GPIO1_7" token="GPMC_AD1_MUXMODE_14" description="gpio1_7"/>
+      <bitenum value="15" id="SYSBOOT1" token="GPMC_AD1_MUXMODE_15" description="sysboot1"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD2" acronym="CTRL_CORE_PAD_GPMC_AD2" offset="0x1408" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD2_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD2_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD2_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD2_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD2_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD2_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD2_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD2_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD2_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD2_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD2_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD2_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD2_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD2_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD2_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD2_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD2_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD2_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD2_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD2_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD2_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD2_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD2_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD2" token="GPMC_AD2_MUXMODE_0" description="gpmc_ad2"/>
+      <bitenum value="2" id="VIN1A_D2" token="GPMC_AD2_MUXMODE_2" description="vin1a_d2"/>
+      <bitenum value="3" id="VOUT3_D2" token="GPMC_AD2_MUXMODE_3" description="vout3_d2"/>
+      <bitenum value="14" id="GPIO1_8" token="GPMC_AD2_MUXMODE_14" description="gpio1_8"/>
+      <bitenum value="15" id="SYSBOOT2" token="GPMC_AD2_MUXMODE_15" description="sysboot2"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD3" acronym="CTRL_CORE_PAD_GPMC_AD3" offset="0x140C" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD3_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD3_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD3_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD3_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD3_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD3_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD3_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD3_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD3_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD3_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD3_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD3_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD3_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD3_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD3_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD3_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD3_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD3_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD3_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD3_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD3_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD3_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD3_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD3" token="GPMC_AD3_MUXMODE_0" description="gpmc_ad3"/>
+      <bitenum value="2" id="VIN1A_D3" token="GPMC_AD3_MUXMODE_2" description="vin1a_d3"/>
+      <bitenum value="3" id="VOUT3_D3" token="GPMC_AD3_MUXMODE_3" description="vout3_d3"/>
+      <bitenum value="14" id="GPIO1_9" token="GPMC_AD3_MUXMODE_14" description="gpio1_9"/>
+      <bitenum value="15" id="SYSBOOT3" token="GPMC_AD3_MUXMODE_15" description="sysboot3"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD4" acronym="CTRL_CORE_PAD_GPMC_AD4" offset="0x1410" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD4_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD4_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD4_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD4_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD4_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD4_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD4_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD4_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD4_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD4_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD4_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD4_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD4_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD4_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD4_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD4_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD4_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD4_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD4_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD4_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD4_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD4_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD4_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD4" token="GPMC_AD4_MUXMODE_0" description="gpmc_ad4"/>
+      <bitenum value="2" id="VIN1A_D4" token="GPMC_AD4_MUXMODE_2" description="vin1a_d4"/>
+      <bitenum value="3" id="VOUT3_D4" token="GPMC_AD4_MUXMODE_3" description="vout3_d4"/>
+      <bitenum value="14" id="GPIO1_10" token="GPMC_AD4_MUXMODE_14" description="gpio1_10"/>
+      <bitenum value="15" id="SYSBOOT4" token="GPMC_AD4_MUXMODE_15" description="sysboot4"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD5" acronym="CTRL_CORE_PAD_GPMC_AD5" offset="0x1414" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD5_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD5_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD5_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD5_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD5_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD5_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD5_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD5_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD5_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD5_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD5_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD5_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD5_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD5_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD5_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD5_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD5_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD5_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD5_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD5_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD5_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD5_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD5_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD5" token="GPMC_AD5_MUXMODE_0" description="gpmc_ad5"/>
+      <bitenum value="2" id="VIN1A_D5" token="GPMC_AD5_MUXMODE_2" description="vin1a_d5"/>
+      <bitenum value="3" id="VOUT3_D5" token="GPMC_AD5_MUXMODE_3" description="vout3_d5"/>
+      <bitenum value="14" id="GPIO1_11" token="GPMC_AD5_MUXMODE_14" description="gpio1_11"/>
+      <bitenum value="15" id="SYSBOOT5" token="GPMC_AD5_MUXMODE_15" description="sysboot5"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD6" acronym="CTRL_CORE_PAD_GPMC_AD6" offset="0x1418" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD6_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD6_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD6_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD6_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD6_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD6_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD6_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD6_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD6_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD6_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD6_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD6_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD6_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD6_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD6_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD6_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD6_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD6_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD6_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD6_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD6_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD6_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD6_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD6" token="GPMC_AD6_MUXMODE_0" description="gpmc_ad6"/>
+      <bitenum value="2" id="VIN1A_D6" token="GPMC_AD6_MUXMODE_2" description="vin1a_d6"/>
+      <bitenum value="3" id="VOUT3_D6" token="GPMC_AD6_MUXMODE_3" description="vout3_d6"/>
+      <bitenum value="14" id="GPIO1_12" token="GPMC_AD6_MUXMODE_14" description="gpio1_12"/>
+      <bitenum value="15" id="SYSBOOT6" token="GPMC_AD6_MUXMODE_15" description="sysboot6"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD7" acronym="CTRL_CORE_PAD_GPMC_AD7" offset="0x141C" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD7_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD7_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD7_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD7_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD7_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD7_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD7_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD7_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD7_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD7_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD7_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD7_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD7_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD7_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD7_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD7_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD7_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD7_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD7_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD7_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD7_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD7_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD7_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD7" token="GPMC_AD7_MUXMODE_0" description="gpmc_ad7"/>
+      <bitenum value="2" id="VIN1A_D7" token="GPMC_AD7_MUXMODE_2" description="vin1a_d7"/>
+      <bitenum value="3" id="VOUT3_D7" token="GPMC_AD7_MUXMODE_3" description="vout3_d7"/>
+      <bitenum value="14" id="GPIO1_13" token="GPMC_AD7_MUXMODE_14" description="gpio1_13"/>
+      <bitenum value="15" id="SYSBOOT7" token="GPMC_AD7_MUXMODE_15" description="sysboot7"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD8" acronym="CTRL_CORE_PAD_GPMC_AD8" offset="0x1420" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD8_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD8_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD8_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD8_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD8_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD8_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD8_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD8_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD8_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD8_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD8_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD8_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD8_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD8_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD8_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD8_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD8_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD8_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD8_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD8_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD8_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD8_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD8_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD8" token="GPMC_AD8_MUXMODE_0" description="gpmc_ad8"/>
+      <bitenum value="2" id="VIN1A_D8" token="GPMC_AD8_MUXMODE_2" description="vin1a_d8"/>
+      <bitenum value="3" id="VOUT3_D8" token="GPMC_AD8_MUXMODE_3" description="vout3_d8"/>
+      <bitenum value="14" id="GPIO7_18" token="GPMC_AD8_MUXMODE_14" description="gpio7_18"/>
+      <bitenum value="15" id="SYSBOOT8" token="GPMC_AD8_MUXMODE_15" description="sysboot8"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD9" acronym="CTRL_CORE_PAD_GPMC_AD9" offset="0x1424" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD9_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD9_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD9_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD9_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD9_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD9_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD9_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD9_SLEWCONTROL_0" description="Fast slew is selected"/>
+      <bitenum value="1" id="SLOW_SLEW" token="GPMC_AD9_SLEWCONTROL_1" description="Slow slew is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD9_INPUTENABLE" width="1" begin="18" end="18" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD9_INPUTENABLE_0" description="Receive mode is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD9_INPUTENABLE_1" description="Receive mode is enabled"/>
+    </bitfield>
+    <bitfield id="GPMC_AD9_PULLTYPESELECT" width="1" begin="17" end="17" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="PULL_DOWN" token="GPMC_AD9_PULLTYPESELECT_0" description="Pull Down is selected"/>
+      <bitenum value="1" id="PULL_UP" token="GPMC_AD9_PULLTYPESELECT_1" description="Pull Up is selected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD9_PULLUDENABLE" width="1" begin="16" end="16" resetval="0x1" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="ENABLE" token="GPMC_AD9_PULLUDENABLE_0" description="Enables weak Pull Up/Down"/>
+      <bitenum value="1" id="DISABLE" token="GPMC_AD9_PULLUDENABLE_1" description="Disables weak Pull Up/Down"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD9_MODESELECT" width="1" begin="8" end="8" resetval="0x0" description="Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." range="" rwaccess="RW">
+      <bitenum value="0" id="MUX_MODE" token="GPMC_AD9_MODESELECT_0" description="Default IO Timing Mode is used"/>
+      <bitenum value="1" id="DELAY_MODE" token="GPMC_AD9_MODESELECT_1" description="A Virtual or Manual IO Timing Mode is used"/>
+    </bitfield>
+    <bitfield id="GPMC_AD9_DELAYMODE" width="4" begin="7" end="4" resetval="0x0" description="This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." range="" rwaccess="RW"/>
+    <bitfield id="GPMC_AD9_MUXMODE" width="4" begin="3" end="0" resetval="0xF" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="GPMC_AD9" token="GPMC_AD9_MUXMODE_0" description="gpmc_ad9"/>
+      <bitenum value="2" id="VIN1A_D9" token="GPMC_AD9_MUXMODE_2" description="vin1a_d9"/>
+      <bitenum value="3" id="VOUT3_D9" token="GPMC_AD9_MUXMODE_3" description="vout3_d9"/>
+      <bitenum value="14" id="GPIO7_19" token="GPMC_AD9_MUXMODE_14" description="gpio7_19"/>
+      <bitenum value="15" id="SYSBOOT9" token="GPMC_AD9_MUXMODE_15" description="sysboot9"/>
+    </bitfield>
+  </register>
+  <register id="CTRL_CORE_PAD_GPMC_AD10" acronym="CTRL_CORE_PAD_GPMC_AD10" offset="0x1428" width="32" description="">
+    <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD10_WAKEUPEVENT" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">
+      <bitenum value="0" id="NOWAKEUP" token="GPMC_AD10_WAKEUPEVENT_0" description="No wakeup event detected"/>
+      <bitenum value="1" id="WAKEUP" token="GPMC_AD10_WAKEUPEVENT_1" description="Wakeup event detected"/>
+    </bitfield>
+    <bitfield id="GPMC_AD10_WAKEUPENABLE" width="1" begin="24" end="24" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="DISABLE" token="GPMC_AD10_WAKEUPENABLE_0" description="Wakeup is disabled"/>
+      <bitenum value="1" id="ENABLE" token="GPMC_AD10_WAKEUPENABLE_1" description="Wakeup is enabled"/>
+    </bitfield>
+    <bitfield id="RESERVED" width="4" begin="23" end="20" resetval="0x0" description="" range="" rwaccess="R"/>
+    <bitfield id="GPMC_AD10_SLEWCONTROL" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="RW">
+      <bitenum value="0" id="FAST_SLEW" token="GPMC_AD10_SLEWCONTROL_0" description="Fast slew is selected"/>