ARM: AM335X: Split hwmod data accessible only on GP devices On HS/EMU devices, some peripherals are marked secure and cannot be accessed in the pulic world - unless firewall is configured to allow such an access. Create an array of HWMODs for the peripherals that are accessible only on GP devices. If PPA is used to restrict public access for any other peripheral, it must be added to this list. With default PPA, attempt to access Timer0 in public world causes an exception leading to crash during kernel boot. Therefore, its HWMOD data is moved to am33xx_hwmods_gp[]. Signed-off-by: Sanjeev Premi <premi@ti.com>
ARM: AM335X: HS/EMU: Set internal SRAM address and size On HS/EMU devices, only 64K internal SRAM is available. Of this, secure content (including PPA) uses initial portion of the SRAM. This chunk is not (and shouldn't be) accessible from the public code. The minimum size of this chunk (0x350) is used in this patch. Available size is rounded off to 63K. Both values would require a change if size of secure content grows beyond 0x350. Signed-off-by: Sanjeev Premi <premi@ti.com>
ti-sdk-am335x-evm-05.05.00.00 on 04.06.00.07
ARM: OMAP: AM33XX: Low power optimizations As per the design team, in order to reduce VDDS_DDR is suspend state the following things must be done: 1. Set the IOs to work in mDDR mode by setting mDDR_SEL bit in the DDR_IO_CTRL register 2. Enable weak pull down for DQ and DM by configuring the DDR_DATA0/1_IOCTRL registers 3. Disable VTP and also set P and N in VTP_CTRL to 1. In the suspend state, A8 SRAM is configured to OFF state, so to further reduce the power consumption SRAM LDO is also configured to go to RET mode. In the resume path all these registers need to restored back to the pre-suspend state before any access to DDR happens. Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
mmc: omap_hsmmc: Pass on the suspend failure to the PM core In some cases mmc_host_suspend() is not able to claim the host and proceed with the suspend process. The core returns -EBUSY to the host controller driver. Unfortunately, the host controller driver does not pass on this information to the PM core and hence the system suspend process continues. In these cases the MMC core gets to an unexpected state during resume and multiple issues related to MMC crop up. 1. Host controller driver starts accessing the device registers before the clocks are enabled which leads to a prefetch abort. 2. A file copy thread which was launched before suspend gets stuck due to the host not being reclaimed during resume. To avoid such problems pass on the -EBUSY status to the PM core from the host controller driver. With this change, MMC core suspend might still fail but it does not end up making the system unusable. Suspend gets aborted and the user can try suspending the system again. Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
PWM: backlight: Set the PWM frequency to 20KHz. PWM frequency in audible frequency (< 20KHz) range causes some noise on brightness values other than 100%. Also with the the PWM frequency of 100 Hz, flickers are also visible. So this patch fixes PWM frequency to 20KHz (outside audible range) and put lth_brightness value to 21 to obtain a linear scale of brightness from 0 to 100%. Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
ARM: OMAP: AM33XX: CAN: d_can: fix the rx problem This patch fixes the d_can receiver problem after suspend/resume cycle. Details: After resuming from deepsleep Zero DCAN receiver is not exporting packets to userspace. This issue mainly because of RAMINIT sequence is not correct in suspend resume cycle. This patch replace the tristate open_status flag with two state opened flag, which is required with the current implementation. Here we end up with two states one is DCAN is opened or not. If it is opened then we have to do d_can_stop() and d_can_start() otherwise not required. If this flag is not there then some unknow bittimming value is programed to DCAN BTR register which is not expected. This patch also moves the runtime PM calls from open/close APIs to DCAN suspend/resume APIs, required along with DCAN RAMINIT and DEINIT Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
video: da8xx-fb: Reset LCDC before re-enabling "08657ec video: da8xx-fb: correct suspend/resume sequence" moved reset out of raster enable. For proper LCDC enable, reset also has to be done. Reintroduce reset in raster enable. Without this raster enable will not guarantee proper enabling of LCDC (like in the case of blank/unblank). Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
PWM: ehrpwm: Fix polarity polarity of PWM signal. While configuring duty percentage for eHRPWM, polarity is also configured. On reset, counter value is zero. So, on configuring polarity, eHRPWM line goes high as counter is zero. This results in 100% duty cycle and starts eHRPWM even before calling pwm_start. This patch fixes the same. Also this patch moves ehrpwm_pwm_set_pol function definition to starting of the file to avoid prototype declaration. Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
ARM: OMAP: AM33XX: NET: cpsw: Set SYSC for NO_IDLE and NO_STDBY In a successful suspend-resume cycle the register context is lost and hence SYSC will go back to its default value of NO_IDLE and NO_STDBY. However, in a suspend failure/abort due to some or the other reason, the register is set to FORCE_IDLE and FORCE_STDBY but never cleared. If the driver had been fully converted to HWMOD this would have been taken care of in the generic code. For now, after enabling the CPSW clock explicitly set the SYSC of CPSW to NO_IDLE and NO_STDBY. Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
ARM: OMAP: AM33XX: PM: Don't rely on M3 for A8 Standby Relying on M3 to have A8 assert standby is not really necessary. It also needs to unnecessary complexity in the recovery path. So, we write to the CLKCTRL register when A8 is sure that it is going to enter the low power state. Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
cpufreq: OMAP: AM33XX: Use PM notifiers to scale voltage in suspend Use the PM notifiers to scale down the frequency and voltage in the suspend path and then block any further transitions till the system resumes. NOTE: THIS PATCH HAS CHECKPATCH ERRORS WHICH VIM IS NOT WILLING TO REMOVE RIGHT NOW :( Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
ARM: OMAP: AM33XX: PM: Remove voltage scaling from PM code Since the cpufreq driver is a consumer of the regulator that is being used for scaling the voltage during suspend resume, a regulator_set_voltage() without informing cpufreq gets into issues with the min_uV and max_uV that both agree upon. This was leading to suspend getting aborted and system eventually dying. A subsequent patch will add back the scaling using the cpufreq driver itself. Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
ARM: OMAP2+: NAND: Fix for NAND module build support NAND driver fails to build as module with following error. ERROR: "gpmc_calculate_ecc" [drivers/mtd/nand/omap2.ko] undefined! ERROR: "gpmc_enable_hwecc" [drivers/mtd/nand/omap2.ko] undefined! make[1]: *** [__modpost] Error 1 make: *** [modules] Error 2 This fixes the same by using EXPORT_SYMBOL. Note: This patch was actually reverted before moving gpmc from postcore_initcall to module_platform_driver. Since moving is completes, we need this patch. Signed-off-by: Philip, Avinash <avinashphilip@ti.com> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>