AM335XEVM: Volume Keys Support Added.
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / board-am335xevm.c
1 /*
2  * Code for AM335X EVM.
3  *
4  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
36 /* LCD controller is similar to DA850 */
37 #include <video/da8xx-fb.h>
39 #include <mach/hardware.h>
40 #include <mach/board-am335xevm.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/map.h>
45 #include <asm/hardware/asp.h>
47 #include <plat/irqs.h>
48 #include <plat/board.h>
49 #include <plat/common.h>
50 #include <plat/lcdc.h>
51 #include <plat/usb.h>
52 #include <plat/mmc.h>
54 #include "board-flash.h"
55 #include "mux.h"
56 #include "devices.h"
57 #include "hsmmc.h"
59 /* Convert GPIO signal to GPIO pin number */
60 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
62 /* TLK PHY IDs */
63 #define TLK110_PHY_ID           0x2000A201
64 #define TLK110_PHY_MASK         0xfffffff0
66 /* BBB PHY IDs */
67 #define BBB_PHY_ID              0x7c0f1
68 #define BBB_PHY_MASK            0xfffffffe
70 /* TLK110 PHY register offsets */
71 #define TLK110_COARSEGAIN_REG   0x00A3
72 #define TLK110_LPFHPF_REG       0x00AC
73 #define TLK110_SPAREANALOG_REG  0x00B9
74 #define TLK110_VRCR_REG         0x00D0
75 #define TLK110_SETFFE_REG       0x0107
76 #define TLK110_FTSP_REG         0x0154
77 #define TLK110_ALFATPIDL_REG    0x002A
78 #define TLK110_PSCOEF21_REG     0x0096
79 #define TLK110_PSCOEF3_REG      0x0097
80 #define TLK110_ALFAFACTOR1_REG  0x002C
81 #define TLK110_ALFAFACTOR2_REG  0x0023
82 #define TLK110_CFGPS_REG        0x0095
83 #define TLK110_FTSPTXGAIN_REG   0x0150
84 #define TLK110_SWSCR3_REG       0x000B
85 #define TLK110_SCFALLBACK_REG   0x0040
86 #define TLK110_PHYRCR_REG       0x001F
88 /* TLK110 register writes values */
89 #define TLK110_COARSEGAIN_VAL   0x0000
90 #define TLK110_LPFHPF_VAL       0x8000
91 #define TLK110_SPANALOG_VAL     0x0000
92 #define TLK110_VRCR_VAL         0x0008
93 #define TLK110_SETFFE_VAL       0x0605
94 #define TLK110_FTSP_VAL         0x0255
95 #define TLK110_ALFATPIDL_VAL    0x7998
96 #define TLK110_PSCOEF21_VAL     0x3A20
97 #define TLK110_PSCOEF3_VAL      0x003F
98 #define TLK110_ALFACTOR1_VAL    0xFF80
99 #define TLK110_ALFACTOR2_VAL    0x021C
100 #define TLK110_CFGPS_VAL        0x0000
101 #define TLK110_FTSPTXGAIN_VAL   0x6A88
102 #define TLK110_SWSCR3_VAL       0x0000
103 #define TLK110_SCFALLBACK_VAL   0xC11D
104 #define TLK110_PHYRCR_VAL       0x4000
106 #ifdef CONFIG_TLK110_WORKAROUND
107 #define am335x_tlk110_phy_init()\
108         do {    \
109                 phy_register_fixup_for_uid(TLK110_PHY_ID,\
110                                         TLK110_PHY_MASK,\
111                                         am335x_tlk110_phy_fixup);\
112         } while (0);
113 #else
114 #define am335x_tlk110_phy_init() do { } while (0);
115 #endif
117 static const struct display_panel disp_panel = {
118         WVGA,
119         32,
120         32,
121         COLOR_ACTIVE,
122 };
124 static struct lcd_ctrl_config lcd_cfg = {
125         &disp_panel,
126         .ac_bias                = 255,
127         .ac_bias_intrpt         = 0,
128         .dma_burst_sz           = 16,
129         .bpp                    = 32,
130         .fdd                    = 0x80,
131         .tft_alt_mode           = 0,
132         .stn_565_mode           = 0,
133         .mono_8bit_mode         = 0,
134         .invert_line_clock      = 1,
135         .invert_frm_clock       = 1,
136         .sync_edge              = 0,
137         .sync_ctrl              = 1,
138         .raster_order           = 0,
139 };
141 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
142         .manu_name              = "ThreeFive",
143         .controller_data        = &lcd_cfg,
144         .type                   = "TFC_S9700RTWV35TR_01B",
145 };
147 #include "common.h"
149 /* TSc controller */
150 #include <linux/input/ti_tscadc.h>
152 static struct resource tsc_resources[]  = {
153         [0] = {
154                 .start  = AM33XX_TSC_BASE,
155                 .end    = AM33XX_TSC_BASE + SZ_8K - 1,
156                 .flags  = IORESOURCE_MEM,
157         },
158         [1] = {
159                 .start  = AM33XX_IRQ_ADC_GEN,
160                 .end    = AM33XX_IRQ_ADC_GEN,
161                 .flags  = IORESOURCE_IRQ,
162         },
163 };
165 static struct tsc_data am335x_touchscreen_data  = {
166         .wires  = 4,
167         .x_plate_resistance = 200,
168 };
170 static struct platform_device tsc_device = {
171         .name   = "tsc",
172         .id     = -1,
173         .dev    = {
174                         .platform_data  = &am335x_touchscreen_data,
175         },
176         .num_resources  = ARRAY_SIZE(tsc_resources),
177         .resource       = tsc_resources,
178 };
180 static u8 am335x_iis_serializer_direction1[] = {
181         INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,        RX_MODE,
182         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
183         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
184         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
185 };
187 static struct snd_platform_data am335x_evm_snd_data1 = {
188         .tx_dma_offset  = 0x46400000,   /* McASP1 */
189         .rx_dma_offset  = 0x46400000,
190         .op_mode        = DAVINCI_MCASP_IIS_MODE,
191         .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
192         .tdm_slots      = 2,
193         .serial_dir     = am335x_iis_serializer_direction1,
194         .asp_chan_q     = EVENTQ_2,
195         .version        = MCASP_VERSION_3,
196         .txnumevt       = 1,
197         .rxnumevt       = 1,
198 };
200 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
201         {
202                 .mmc            = 1,
203                 .caps           = MMC_CAP_4_BIT_DATA,
204                 .gpio_cd        = GPIO_TO_PIN(0, 6),
205                 .gpio_wp        = GPIO_TO_PIN(3, 18),
206                 .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
207         },
208         {
209                 .mmc            = 0,    /* will be set at runtime */
210         },
211         {
212                 .mmc            = 0,    /* will be set at runtime */
213         },
214         {}      /* Terminator */
215 };
218 #ifdef CONFIG_OMAP_MUX
219 static struct omap_board_mux board_mux[] __initdata = {
220         AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
221                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
222         AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
223                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
224         { .reg_offset = OMAP_MUX_TERMINATOR },
225 };
226 #else
227 #define board_mux       NULL
228 #endif
230 /* module pin mux structure */
231 struct pinmux_config {
232         const char *string_name; /* signal name format */
233         int val; /* Options for the mux register value */
234 };
236 struct evm_dev_cfg {
237         void (*device_init)(int evm_id, int profile);
239 /*
240 * If the device is required on both baseboard & daughter board (ex i2c),
241 * specify DEV_ON_BASEBOARD
242 */
243 #define DEV_ON_BASEBOARD        0
244 #define DEV_ON_DGHTR_BRD        1
245         u32 device_on;
247         u32 profile;    /* Profiles (0-7) in which the module is present */
248 };
250 /* AM335X - CPLD Register Offsets */
251 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
252 #define CPLD_DEVICE_ID  0x04 /* CPLD identification */
253 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
254 #define CPLD_CFG_REG    0x10 /* Configuration Register */
256 static struct i2c_client *cpld_client;
257 static u32 am335x_evm_id;
258 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
259 };
261 /*
262 * EVM Config held in On-Board eeprom device.
264 * Header Format
266 *  Name                 Size    Contents
267 *                       (Bytes)
268 *-------------------------------------------------------------
269 *  Header               4       0xAA, 0x55, 0x33, 0xEE
271 *  Board Name           8       Name for board in ASCII.
272 *                               example "A33515BB" = "AM335X
273                                 Low Cost EVM board"
275 *  Version              4       Hardware version code for board in
276 *                               in ASCII. "1.0A" = rev.01.0A
278 *  Serial Number        12      Serial number of the board. This is a 12
279 *                               character string which is WWYY4P16nnnn, where
280 *                               WW = 2 digit week of the year of production
281 *                               YY = 2 digit year of production
282 *                               nnnn = incrementing board number
284 *  Configuration option 32      Codes(TBD) to show the configuration
285 *                               setup on this board.
287 *  Available            32720   Available space for other non-volatile
288 *                               data.
289 */
290 struct am335x_evm_eeprom_config {
291         u32     header;
292         u8      name[8];
293         char    version[4];
294         u8      serial[12];
295         u8      opt[32];
296 };
298 static struct am335x_evm_eeprom_config config;
299 static bool daughter_brd_detected;
301 #define GP_EVM_REV_IS_1_0               0x1
302 #define GP_EVM_REV_IS_1_1A              0x2
303 #define GP_EVM_REV_IS_UNKNOWN           0xFF
304 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
305 unsigned int gigabit_enable = 1;
307 #define EEPROM_MAC_ADDRESS_OFFSET       60 /* 4+8+4+12+32 */
308 #define EEPROM_NO_OF_MAC_ADDR           3
309 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
311 #define AM335X_EEPROM_HEADER            0xEE3355AA
313 /* current profile if exists else PROFILE_0 on error */
314 static u32 am335x_get_profile_selection(void)
316         int val = 0;
318         if (!cpld_client)
319                 /* error checking is not done in func's calling this routine.
320                 so return profile 0 on error */
321                 return 0;
323         val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
324         if (val < 0)
325                 return 0;       /* default to Profile 0 on Error */
326         else
327                 return val & 0x7;
330 /* Module pin mux for LCDC */
331 static struct pinmux_config lcdc_pin_mux[] = {
332         {"lcd_data0.lcd_data0",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
333                                                        | AM33XX_PULL_DISA},
334         {"lcd_data1.lcd_data1",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
335                                                        | AM33XX_PULL_DISA},
336         {"lcd_data2.lcd_data2",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
337                                                        | AM33XX_PULL_DISA},
338         {"lcd_data3.lcd_data3",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
339                                                        | AM33XX_PULL_DISA},
340         {"lcd_data4.lcd_data4",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
341                                                        | AM33XX_PULL_DISA},
342         {"lcd_data5.lcd_data5",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
343                                                        | AM33XX_PULL_DISA},
344         {"lcd_data6.lcd_data6",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
345                                                        | AM33XX_PULL_DISA},
346         {"lcd_data7.lcd_data7",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
347                                                        | AM33XX_PULL_DISA},
348         {"lcd_data8.lcd_data8",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
349                                                        | AM33XX_PULL_DISA},
350         {"lcd_data9.lcd_data9",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
351                                                        | AM33XX_PULL_DISA},
352         {"lcd_data10.lcd_data10",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
353                                                        | AM33XX_PULL_DISA},
354         {"lcd_data11.lcd_data11",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
355                                                        | AM33XX_PULL_DISA},
356         {"lcd_data12.lcd_data12",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
357                                                        | AM33XX_PULL_DISA},
358         {"lcd_data13.lcd_data13",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
359                                                        | AM33XX_PULL_DISA},
360         {"lcd_data14.lcd_data14",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
361                                                        | AM33XX_PULL_DISA},
362         {"lcd_data15.lcd_data15",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
363                                                        | AM33XX_PULL_DISA},
364         {"gpmc_ad8.lcd_data16",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
365         {"gpmc_ad9.lcd_data17",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
366         {"gpmc_ad10.lcd_data18",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
367         {"gpmc_ad11.lcd_data19",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
368         {"gpmc_ad12.lcd_data20",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
369         {"gpmc_ad13.lcd_data21",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
370         {"gpmc_ad14.lcd_data22",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
371         {"gpmc_ad15.lcd_data23",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
372         {"lcd_vsync.lcd_vsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
373         {"lcd_hsync.lcd_hsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
374         {"lcd_pclk.lcd_pclk",           OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
375         {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
376         {NULL, 0},
377 };
379 static struct pinmux_config tsc_pin_mux[] = {
380         {"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
381         {"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
382         {"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
383         {"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
384         {"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
385         {"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
386         {NULL, 0},
387 };
389 /* Pin mux for nand flash module */
390 static struct pinmux_config nand_pin_mux[] = {
391         {"gpmc_ad0.gpmc_ad0",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
392         {"gpmc_ad1.gpmc_ad1",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
393         {"gpmc_ad2.gpmc_ad2",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
394         {"gpmc_ad3.gpmc_ad3",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
395         {"gpmc_ad4.gpmc_ad4",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
396         {"gpmc_ad5.gpmc_ad5",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
397         {"gpmc_ad6.gpmc_ad6",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
398         {"gpmc_ad7.gpmc_ad7",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
399         {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
400         {"gpmc_wpn.gpmc_wpn",     OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
401         {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
402         {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
403         {"gpmc_oen_ren.gpmc_oen_ren",    OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
404         {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
405         {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
406         {NULL, 0},
407 };
409 /* Module pin mux for SPI fash */
410 static struct pinmux_config spi0_pin_mux[] = {
411         {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
412                                                         | AM33XX_INPUT_EN},
413         {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
414                                                         | AM33XX_INPUT_EN},
415         {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
416                                                         | AM33XX_INPUT_EN},
417         {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
418                                                         | AM33XX_INPUT_EN},
419         {NULL, 0},
420 };
422 /* Module pin mux for SPI flash */
423 static struct pinmux_config spi1_pin_mux[] = {
424         {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
425                 | AM33XX_INPUT_EN},
426         {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
427                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
428         {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
429                 | AM33XX_INPUT_EN},
430         {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
431                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
432         {NULL, 0},
433 };
435 /* Module pin mux for rgmii1 */
436 static struct pinmux_config rgmii1_pin_mux[] = {
437         {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
438         {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
439         {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
440         {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
441         {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
442         {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
443         {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
444         {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
445         {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
446         {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
447         {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
448         {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
449         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
450         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
451         {NULL, 0},
452 };
454 /* Module pin mux for rgmii2 */
455 static struct pinmux_config rgmii2_pin_mux[] = {
456         {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
457         {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
458         {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
459         {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
460         {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
461         {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
462         {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
463         {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
464         {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
465         {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
466         {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
467         {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
468         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
469         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
470         {NULL, 0},
471 };
473 /* Module pin mux for mii1 */
474 static struct pinmux_config mii1_pin_mux[] = {
475         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
476         {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
477         {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
478         {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
479         {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
480         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
481         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
482         {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
483         {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
484         {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
485         {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
486         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
487         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
488         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
489         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
490         {NULL, 0},
491 };
493 /* Module pin mux for rmii1 */
494 static struct pinmux_config rmii1_pin_mux[] = {
495         {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
496         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
497         {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
498         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
499         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
500         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
501         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
502         {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
503         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
504         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
505         {NULL, 0},
506 };
508 static struct pinmux_config i2c1_pin_mux[] = {
509         {"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
510                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
511         {"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
512                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
513         {NULL, 0},
514 };
516 /* Module pin mux for mcasp1 */
517 static struct pinmux_config mcasp1_pin_mux[] = {
518         {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
519         {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
520         {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
521         {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
522                                                 AM33XX_PIN_INPUT_PULLDOWN},
523         {NULL, 0},
524 };
527 /* Module pin mux for mmc0 */
528 static struct pinmux_config mmc0_pin_mux[] = {
529         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
530         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
531         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
532         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
533         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
534         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
535         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
536         {"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
537         {NULL, 0},
538 };
540 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
541         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
542         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
543         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
544         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
545         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
546         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
547         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
548         {NULL, 0},
549 };
551 /* Module pin mux for mmc1 */
552 static struct pinmux_config mmc1_pin_mux[] = {
553         {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
554         {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
555         {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
556         {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
557         {"gpmc_ad3.mmc1_dat3",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
558         {"gpmc_ad2.mmc1_dat2",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
559         {"gpmc_ad1.mmc1_dat1",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
560         {"gpmc_ad0.mmc1_dat0",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
561         {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
562         {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
563         {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
564         {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
565         {NULL, 0},
566 };
568 /* Module pin mux for uart3 */
569 static struct pinmux_config uart3_pin_mux[] = {
570         {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
571         {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
572         {NULL, 0},
573 };
575 static struct pinmux_config d_can_gp_pin_mux[] = {
576         {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
577         {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
578         {NULL, 0},
579 };
581 static struct pinmux_config d_can_ia_pin_mux[] = {
582         {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
583         {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
584         {NULL, 0},
585 };
587 /*
588 * @pin_mux - single module pin-mux structure which defines pin-mux
589 *                       details for all its pins.
590 */
591 static void setup_pin_mux(struct pinmux_config *pin_mux)
593         int i;
595         for (i = 0; pin_mux->string_name != NULL; pin_mux++)
596                 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
600 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
602 /* pinmux for keypad device */
603 static struct pinmux_config matrix_keypad_pin_mux[] = {
604         {"gpmc_a5.gpio1_21",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
605         {"gpmc_a6.gpio1_22",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
606         {"gpmc_a9.gpio1_25",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
607         {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
608         {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
609         {NULL, 0},
610 };
612 /* Keys mapping */
613 static const uint32_t am335x_evm_matrix_keys[] = {
614         KEY(0, 0, KEY_MENU),
615         KEY(1, 0, KEY_BACK),
616         KEY(2, 0, KEY_LEFT),
618         KEY(0, 1, KEY_RIGHT),
619         KEY(1, 1, KEY_ENTER),
620         KEY(2, 1, KEY_DOWN),
621 };
623 const struct matrix_keymap_data am335x_evm_keymap_data = {
624         .keymap      = am335x_evm_matrix_keys,
625         .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
626 };
628 static const unsigned int am335x_evm_keypad_row_gpios[] = {
629         GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
630 };
632 static const unsigned int am335x_evm_keypad_col_gpios[] = {
633         GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
634 };
636 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
637         .keymap_data       = &am335x_evm_keymap_data,
638         .row_gpios         = am335x_evm_keypad_row_gpios,
639         .num_row_gpios     = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
640         .col_gpios         = am335x_evm_keypad_col_gpios,
641         .num_col_gpios     = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
642         .active_low        = false,
643         .debounce_ms       = 5,
644         .col_scan_delay_us = 2,
645 };
647 static struct platform_device am335x_evm_keyboard = {
648         .name  = "matrix-keypad",
649         .id    = -1,
650         .dev   = {
651                 .platform_data = &am335x_evm_keypad_platform_data,
652         },
653 };
655 static void matrix_keypad_init(int evm_id, int profile)
657         int err;
659         setup_pin_mux(matrix_keypad_pin_mux);
660         err = platform_device_register(&am335x_evm_keyboard);
661         if (err) {
662                 pr_err("failed to register matrix keypad (2x3) device\n");
663         }
667 /* pinmux for keypad device */
668 static struct pinmux_config volume_keys_pin_mux[] = {
669         {"spi0_sclk.gpio0_2",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
670         {"spi0_d0.gpio0_3",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
671         {NULL, 0},
672 };
674 /* Configure GPIOs for Volume Keys */
675 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
676         {
677                 .code                   = KEY_VOLUMEUP,
678                 .gpio                   = GPIO_TO_PIN(0, 2),
679                 .active_low             = true,
680                 .desc                   = "volume-up",
681                 .type                   = EV_KEY,
682                 .wakeup                 = 1,
683         },
684         {
685                 .code                   = KEY_VOLUMEDOWN,
686                 .gpio                   = GPIO_TO_PIN(0, 3),
687                 .active_low             = true,
688                 .desc                   = "volume-down",
689                 .type                   = EV_KEY,
690                 .wakeup                 = 1,
691         },
692 };
694 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
695         .buttons        = am335x_evm_volume_gpio_buttons,
696         .nbuttons       = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
697 };
699 static struct platform_device am335x_evm_volume_keys = {
700         .name   = "gpio-keys",
701         .id     = -1,
702         .dev    = {
703                 .platform_data  = &am335x_evm_volume_gpio_key_info,
704         },
705 };
707 static void volume_keys_init(int evm_id, int profile)
709         int err;
711         setup_pin_mux(volume_keys_pin_mux);
712         err = platform_device_register(&am335x_evm_volume_keys);
713         if (err)
714                 pr_err("failed to register matrix keypad (2x3) device\n");
717 /*
718 * @evm_id - evm id which needs to be configured
719 * @dev_cfg - single evm structure which includes
720 *                               all module inits, pin-mux defines
721 * @profile - if present, else PROFILE_NONE
722 * @dghtr_brd_flg - Whether Daughter board is present or not
723 */
724 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
725         int profile)
727         int i;
729         /*
730         * Only General Purpose & Industrial Auto Motro Control
731         * EVM has profiles. So check if this evm has profile.
732         * If not, ignore the profile comparison
733         */
735         /*
736         * If the device is on baseboard, directly configure it. Else (device on
737         * Daughter board), check if the daughter card is detected.
738         */
739         if (profile == PROFILE_NONE) {
740                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
741                         if (dev_cfg->device_on == DEV_ON_BASEBOARD)
742                                 dev_cfg->device_init(evm_id, profile);
743                         else if (daughter_brd_detected == true)
744                                 dev_cfg->device_init(evm_id, profile);
745                 }
746         } else {
747                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
748                         if (dev_cfg->profile & profile) {
749                                 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
750                                         dev_cfg->device_init(evm_id, profile);
751                                 else if (daughter_brd_detected == true)
752                                         dev_cfg->device_init(evm_id, profile);
753                         }
754                 }
755         }
758 #define AM335X_LCD_BL_PIN       GPIO_TO_PIN(0, 7)
760 /* pinmux for usb0 drvvbus */
761 static struct pinmux_config usb0_pin_mux[] = {
762         {"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
763         {NULL, 0},
764 };
766 /* pinmux for usb1 drvvbus */
767 static struct pinmux_config usb1_pin_mux[] = {
768         {"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
769         {NULL, 0},
770 };
772 /* Module pin mux for eCAP0 */
773 static struct pinmux_config ecap0_pin_mux[] = {
774         {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
775         {NULL, 0},
776 };
778 static int backlight_enable;
780 #define AM335XEVM_WLAN_PMENA_GPIO       GPIO_TO_PIN(1, 30)
781 #define AM335XEVM_WLAN_IRQ_GPIO         GPIO_TO_PIN(3, 17)
783 struct wl12xx_platform_data am335xevm_wlan_data = {
784         .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
785         .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
786 };
788 /* Module pin mux for wlan and bluetooth */
789 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
790         {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
791         {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
792         {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
793         {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
794         {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
795         {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
796         {NULL, 0},
797 };
799 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
800         {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
801         {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
802         {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
803         {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
804         {NULL, 0},
805 };
807 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
808         {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
809         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
810         {"mcasp0_ahclkx.gpio0_17", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
811         {NULL, 0},
812  };
814 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
815         {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
816         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
817         {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
818         {NULL, 0},
819  };
821 static void enable_ecap0(int evm_id, int profile)
823         backlight_enable = true;
826 static int __init ecap0_init(void)
828         int status = 0;
830         if (backlight_enable) {
831                 setup_pin_mux(ecap0_pin_mux);
833                 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
834                 if (status < 0)
835                         pr_warn("Failed to request gpio for LCD backlight\n");
837                 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
838         }
839         return status;
841 late_initcall(ecap0_init);
843 static int __init conf_disp_pll(int rate)
845         struct clk *disp_pll;
846         int ret = -EINVAL;
848         disp_pll = clk_get(NULL, "dpll_disp_ck");
849         if (IS_ERR(disp_pll)) {
850                 pr_err("Cannot clk_get disp_pll\n");
851                 goto out;
852         }
854         ret = clk_set_rate(disp_pll, rate);
855         clk_put(disp_pll);
856 out:
857         return ret;
860 static void lcdc_init(int evm_id, int profile)
863         setup_pin_mux(lcdc_pin_mux);
865         if (conf_disp_pll(300000000)) {
866                 pr_info("Failed configure display PLL, not attempting to"
867                                 "register LCDC\n");
868                 return;
869         }
871         if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
872                 pr_info("Failed to register LCDC device\n");
873         return;
876 static void tsc_init(int evm_id, int profile)
878         int err;
880         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
881                 am335x_touchscreen_data.analog_input = 1;
882                 pr_info("TSC connected to beta GP EVM\n");
883         } else {
884                 am335x_touchscreen_data.analog_input = 0;
885                 pr_info("TSC connected to alpha GP EVM\n");
886         }
887         setup_pin_mux(tsc_pin_mux);
888         err = platform_device_register(&tsc_device);
889         if (err)
890                 pr_err("failed to register touchscreen device\n");
893 static void rgmii1_init(int evm_id, int profile)
895         setup_pin_mux(rgmii1_pin_mux);
896         return;
899 static void rgmii2_init(int evm_id, int profile)
901         setup_pin_mux(rgmii2_pin_mux);
902         return;
905 static void mii1_init(int evm_id, int profile)
907         setup_pin_mux(mii1_pin_mux);
908         return;
911 static void rmii1_init(int evm_id, int profile)
913         setup_pin_mux(rmii1_pin_mux);
914         return;
917 static void usb0_init(int evm_id, int profile)
919         setup_pin_mux(usb0_pin_mux);
920         return;
923 static void usb1_init(int evm_id, int profile)
925         setup_pin_mux(usb1_pin_mux);
926         return;
929 /* setup uart3 */
930 static void uart3_init(int evm_id, int profile)
932         setup_pin_mux(uart3_pin_mux);
933         return;
936 /* NAND partition information */
937 static struct mtd_partition am335x_nand_partitions[] = {
938 /* All the partition sizes are listed in terms of NAND block size */
939         {
940                 .name           = "SPL",
941                 .offset         = 0,                    /* Offset = 0x0 */
942                 .size           = SZ_128K,
943         },
944         {
945                 .name           = "SPL.backup1",
946                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x20000 */
947                 .size           = SZ_128K,
948         },
949         {
950                 .name           = "SPL.backup2",
951                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x40000 */
952                 .size           = SZ_128K,
953         },
954         {
955                 .name           = "SPL.backup3",
956                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x60000 */
957                 .size           = SZ_128K,
958         },
959         {
960                 .name           = "U-Boot",
961                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
962                 .size           = 15 * SZ_128K,
963         },
964         {
965                 .name           = "U-Boot Env",
966                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
967                 .size           = 1 * SZ_128K,
968         },
969         {
970                 .name           = "Kernel",
971                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
972                 .size           = 40 * SZ_128K,
973         },
974         {
975                 .name           = "File System",
976                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
977                 .size           = MTDPART_SIZ_FULL,
978         },
979 };
981 /* SPI 0/1 Platform Data */
982 /* SPI flash information */
983 static struct mtd_partition am335x_spi_partitions[] = {
984         /* All the partition sizes are listed in terms of erase size */
985         {
986                 .name       = "SPL",
987                 .offset     = 0,                        /* Offset = 0x0 */
988                 .size       = SZ_128K,
989         },
990         {
991                 .name       = "U-Boot",
992                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x20000 */
993                 .size       = 2 * SZ_128K,
994         },
995         {
996                 .name       = "U-Boot Env",
997                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x60000 */
998                 .size       = 2 * SZ_4K,
999         },
1000         {
1001                 .name       = "Kernel",
1002                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x62000 */
1003                 .size       = 28 * SZ_128K,
1004         },
1005         {
1006                 .name       = "File System",
1007                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x3E2000 */
1008                 .size       = MTDPART_SIZ_FULL,         /* size ~= 4.1 MiB */
1009         }
1010 };
1012 static const struct flash_platform_data am335x_spi_flash = {
1013         .type      = "w25q64",
1014         .name      = "spi_flash",
1015         .parts     = am335x_spi_partitions,
1016         .nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
1017 };
1019 /*
1020  * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1021  * So setup Max speed to be less than that of Controller speed
1022  */
1023 static struct spi_board_info am335x_spi0_slave_info[] = {
1024         {
1025                 .modalias      = "m25p80",
1026                 .platform_data = &am335x_spi_flash,
1027                 .irq           = -1,
1028                 .max_speed_hz  = 24000000,
1029                 .bus_num       = 1,
1030                 .chip_select   = 0,
1031         },
1032 };
1034 static struct spi_board_info am335x_spi1_slave_info[] = {
1035         {
1036                 .modalias      = "m25p80",
1037                 .platform_data = &am335x_spi_flash,
1038                 .irq           = -1,
1039                 .max_speed_hz  = 12000000,
1040                 .bus_num       = 2,
1041                 .chip_select   = 0,
1042         },
1043 };
1045 static void evm_nand_init(int evm_id, int profile)
1047         setup_pin_mux(nand_pin_mux);
1048         board_nand_init(am335x_nand_partitions,
1049                 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1052 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1053         {
1054                 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1055         },
1056 };
1058 static void i2c1_init(int evm_id, int profile)
1060         setup_pin_mux(i2c1_pin_mux);
1061         omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1062                         ARRAY_SIZE(am335x_i2c_boardinfo1));
1063         return;
1066 /* Setup McASP 1 */
1067 static void mcasp1_init(int evm_id, int profile)
1069         /* Configure McASP */
1070         setup_pin_mux(mcasp1_pin_mux);
1071         am335x_register_mcasp1(&am335x_evm_snd_data1);
1072         return;
1075 static void mmc1_init(int evm_id, int profile)
1077         setup_pin_mux(mmc1_pin_mux);
1079         am335x_mmc[1].mmc = 2;
1080         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1081         am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1082         am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1083         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1085         /* mmc will be initialized when mmc0_init is called */
1086         return;
1089 static void mmc2_wl12xx_init(int evm_id, int profile)
1091         setup_pin_mux(mmc2_wl12xx_pin_mux);
1093         am335x_mmc[1].mmc = 3;
1094         am335x_mmc[1].name = "wl1271";
1095         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1096                                 | MMC_PM_KEEP_POWER;
1097         am335x_mmc[1].nonremovable = true;
1098         am335x_mmc[1].gpio_cd = -EINVAL;
1099         am335x_mmc[1].gpio_wp = -EINVAL;
1100         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1102         /* mmc will be initialized when mmc0_init is called */
1103         return;
1106 static void uart1_wl12xx_init(int evm_id, int profile)
1108         setup_pin_mux(uart1_wl12xx_pin_mux);
1111 static void wl12xx_bluetooth_enable(void)
1113         int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1114                 "bt_en\n");
1115         if (status < 0)
1116                 pr_err("Failed to request gpio for bt_enable");
1118         pr_info("Configure Bluetooth Enable pin...\n");
1119         gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1122 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1124         if (on)
1125                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1126         else
1127                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1129         return 0;
1132 static void wl12xx_init(int evm_id, int profile)
1134         struct device *dev;
1135         struct omap_mmc_platform_data *pdata;
1136         int ret;
1138         /* Register WLAN and BT enable pins based on the evm board revision */
1139         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1140                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1141                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(0, 17);
1142         }
1143         else {
1144                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1145                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1146         }
1148         wl12xx_bluetooth_enable();
1150         if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1151                 pr_err("error setting wl12xx data\n");
1153         dev = am335x_mmc[1].dev;
1154         if (!dev) {
1155                 pr_err("wl12xx mmc device initialization failed\n");
1156                 goto out;
1157         }
1159         pdata = dev->platform_data;
1160         if (!pdata) {
1161                 pr_err("Platfrom data of wl12xx device not set\n");
1162                 goto out;
1163         }
1165         ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1166                 GPIOF_OUT_INIT_LOW, "wlan_en");
1167         if (ret) {
1168                 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1169                 goto out;
1170         }
1172         if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1173                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1174         else
1175                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1177         pdata->slots[0].set_power = wl12xx_set_power;
1178 out:
1179         return;
1182 static void d_can_init(int evm_id, int profile)
1184         switch (evm_id) {
1185         case IND_AUT_MTR_EVM:
1186                 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1187                         setup_pin_mux(d_can_ia_pin_mux);
1188                         /* Instance Zero */
1189                         am33xx_d_can_init(0);
1190                 }
1191                 break;
1192         case GEN_PURP_EVM:
1193                 if (profile == PROFILE_1) {
1194                         setup_pin_mux(d_can_gp_pin_mux);
1195                         /* Instance One */
1196                         am33xx_d_can_init(1);
1197                 }
1198                 break;
1199         default:
1200                 break;
1201         }
1204 static void mmc0_init(int evm_id, int profile)
1206         setup_pin_mux(mmc0_pin_mux);
1208         omap2_hsmmc_init(am335x_mmc);
1209         return;
1212 static void mmc0_no_cd_init(int evm_id, int profile)
1214         setup_pin_mux(mmc0_no_cd_pin_mux);
1216         omap2_hsmmc_init(am335x_mmc);
1217         return;
1221 /* setup spi0 */
1222 static void spi0_init(int evm_id, int profile)
1224         setup_pin_mux(spi0_pin_mux);
1225         spi_register_board_info(am335x_spi0_slave_info,
1226                         ARRAY_SIZE(am335x_spi0_slave_info));
1227         return;
1230 /* setup spi1 */
1231 static void spi1_init(int evm_id, int profile)
1233         setup_pin_mux(spi1_pin_mux);
1234         spi_register_board_info(am335x_spi1_slave_info,
1235                         ARRAY_SIZE(am335x_spi1_slave_info));
1236         return;
1240 static int beaglebone_phy_fixup(struct phy_device *phydev)
1242         phydev->supported &= ~(SUPPORTED_100baseT_Half |
1243                                 SUPPORTED_100baseT_Full);
1245         return 0;
1248 #ifdef CONFIG_TLK110_WORKAROUND
1249 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1251         unsigned int val;
1253         /* This is done as a workaround to support TLK110 rev1.0 phy */
1254         val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1255         phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1257         val = phy_read(phydev, TLK110_LPFHPF_REG);
1258         phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1260         val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1261         phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1263         val = phy_read(phydev, TLK110_VRCR_REG);
1264         phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1266         val = phy_read(phydev, TLK110_SETFFE_REG);
1267         phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1269         val = phy_read(phydev, TLK110_FTSP_REG);
1270         phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1272         val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1273         phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1275         val = phy_read(phydev, TLK110_PSCOEF21_REG);
1276         phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1278         val = phy_read(phydev, TLK110_PSCOEF3_REG);
1279         phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1281         val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1282         phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1284         val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1285         phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1287         val = phy_read(phydev, TLK110_CFGPS_REG);
1288         phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1290         val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1291         phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1293         val = phy_read(phydev, TLK110_SWSCR3_REG);
1294         phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1296         val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1297         phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1299         val = phy_read(phydev, TLK110_PHYRCR_REG);
1300         phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1302         return 0;
1304 #endif
1307 /* Low-Cost EVM */
1308 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1309         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1310         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1311         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1312         {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1313         {NULL, 0, 0},
1314 };
1316 /* General Purpose EVM */
1317 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1318         {enable_ecap0,  DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1319                                                 PROFILE_2 | PROFILE_7) },
1320         {lcdc_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1321                                                 PROFILE_2 | PROFILE_7) },
1322         {tsc_init,      DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1323                                                 PROFILE_2 | PROFILE_7) },
1324         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
1325         {rgmii2_init,   DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1326                                                 PROFILE_4 | PROFILE_6) },
1327         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1328         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1329         {evm_nand_init, DEV_ON_DGHTR_BRD,
1330                 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1331         {i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1332         {mcasp1_init,   DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1333         {mmc1_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1334         {mmc2_wl12xx_init,      DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1335                                                                 PROFILE_5)},
1336         {mmc0_init,     DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1337         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_5},
1338         {spi0_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1339         {uart1_wl12xx_init,     DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1340                                                                 PROFILE_5)},
1341         {wl12xx_init,   DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1342         {d_can_init,    DEV_ON_DGHTR_BRD, PROFILE_1},
1343         {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1344         {volume_keys_init,  DEV_ON_DGHTR_BRD, PROFILE_0},
1345         {NULL, 0, 0},
1346 };
1348 /* Industrial Auto Motor Control EVM */
1349 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1350         {mii1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1351         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1352         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1353         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1354         {spi1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1355         {uart3_init,    DEV_ON_DGHTR_BRD, PROFILE_ALL},
1356         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1357         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_ALL},
1358         {NULL, 0, 0},
1359 };
1361 /* IP-Phone EVM */
1362 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1363         {enable_ecap0,  DEV_ON_DGHTR_BRD, PROFILE_NONE},
1364         {lcdc_init,     DEV_ON_DGHTR_BRD, PROFILE_NONE},
1365         {tsc_init,      DEV_ON_DGHTR_BRD, PROFILE_NONE},
1366         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1367         {rgmii2_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1368         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1369         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1370         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1371         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1372         {mcasp1_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1373         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1374         {NULL, 0, 0},
1375 };
1377 /* Beaglebone < Rev A3 */
1378 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1379         {rmii1_init,    DEV_ON_BASEBOARD, PROFILE_NONE},
1380         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1381         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1382         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1383         {NULL, 0, 0},
1384 };
1386 /* Beaglebone Rev A3 and after */
1387 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1388         {mii1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1389         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1390         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1391         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1392         {NULL, 0, 0},
1393 };
1395 static void setup_low_cost_evm(void)
1397         pr_info("The board is a AM335x Low Cost EVM.\n");
1399         _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1402 static void setup_general_purpose_evm(void)
1404         u32 prof_sel = am335x_get_profile_selection();
1405         pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1407         if (!strncmp("1.1A", config.version, 4)) {
1408                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1409         } else if (!strncmp("1.0", config.version, 3)) {
1410                 gp_evm_revision = GP_EVM_REV_IS_1_0;
1411         } else {
1412                 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1413                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1414         }
1416         if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1417                 gigabit_enable = 0;
1418         else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1419                 gigabit_enable = 1;
1421         _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1424 static void setup_ind_auto_motor_ctrl_evm(void)
1426         u32 prof_sel = am335x_get_profile_selection();
1428         pr_info("The board is an industrial automation EVM in profile %d\n",
1429                 prof_sel);
1431         /* Only Profile 0 is supported */
1432         if ((1L << prof_sel) != PROFILE_0) {
1433                 pr_err("AM335X: Only Profile 0 is supported\n");
1434                 pr_err("Assuming profile 0 & continuing\n");
1435                 prof_sel = PROFILE_0;
1436         }
1438         _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1439                 PROFILE_0);
1441         /* Fillup global evmid */
1442         am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1444         /* Initialize TLK110 PHY registers for phy version 1.0 */
1445         am335x_tlk110_phy_init();
1450 static void setup_ip_phone_evm(void)
1452         pr_info("The board is an IP phone EVM\n");
1454         _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1457 /* BeagleBone < Rev A3 */
1458 static void setup_beaglebone_old(void)
1460         pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1462         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1463         am335x_mmc[0].gpio_wp = -EINVAL;
1465         _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1467         phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1468                                         beaglebone_phy_fixup);
1471 /* BeagleBone after Rev A3 */
1472 static void setup_beaglebone(void)
1474         pr_info("The board is a AM335x Beaglebone.\n");
1476         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1477         am335x_mmc[0].gpio_wp = -EINVAL;
1479         _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1483 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1485         u8 tmp;
1486         int ret;
1488         /*
1489          * try reading a byte from the EEPROM to see if it is
1490          * present. We could read a lot more, but that would
1491          * just slow the boot process and we have all the information
1492          * we need from the EEPROM on the base board anyway.
1493          */
1494         ret = m->read(m, &tmp, 0, sizeof(u8));
1495         if (ret == sizeof(u8)) {
1496                 pr_info("Detected a daughter card on AM335x EVM..");
1497                 daughter_brd_detected = true;
1498         } else {
1499                 pr_info("No daughter card found\n");
1500                 daughter_brd_detected = false;
1501         }
1504 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1506         int ret;
1507         char tmp[10];
1509         /* 1st get the MAC address from EEPROM */
1510         ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1511                 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1513         if (ret != sizeof(am335x_mac_addr)) {
1514                 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1515                 return;
1516         }
1518         /* Fillup global mac id */
1519         am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1520                                 &am335x_mac_addr[1][0]);
1522         /* get board specific data */
1523         ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1524         if (ret != sizeof(config)) {
1525                 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1526                 return;
1527         }
1529         if (config.header != AM335X_EEPROM_HEADER) {
1530                 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1531                         config.header, AM335X_EEPROM_HEADER);
1532                 goto out;
1533         }
1535         if (strncmp("A335", config.name, 4)) {
1536                 pr_err("Board %s doesn't look like an AM335x board\n",
1537                         config.name);
1538                 goto out;
1539         }
1541         snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1542         pr_info("Board name: %s\n", tmp);
1543         snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1544         pr_info("Board version: %s\n", tmp);
1546         if (!strncmp("A335BONE", config.name, 8)) {
1547                 daughter_brd_detected = false;
1548                 if(!strncmp("00A1", config.version, 4) ||
1549                    !strncmp("00A2", config.version, 4))
1550                         setup_beaglebone_old();
1551                 else
1552                         setup_beaglebone();
1553         } else {
1554                 /* only 6 characters of options string used for now */
1555                 snprintf(tmp, 7, "%s", config.opt);
1556                 pr_info("SKU: %s\n", tmp);
1558                 if (!strncmp("SKU#00", config.opt, 6))
1559                         setup_low_cost_evm();
1560                 else if (!strncmp("SKU#01", config.opt, 6))
1561                         setup_general_purpose_evm();
1562                 else if (!strncmp("SKU#02", config.opt, 6))
1563                         setup_ind_auto_motor_ctrl_evm();
1564                 else if (!strncmp("SKU#03", config.opt, 6))
1565                         setup_ip_phone_evm();
1566                 else
1567                         goto out;
1568         }
1569         /* Initialize cpsw after board detection is completed as board
1570          * information is required for configuring phy address and hence
1571          * should be call only after board detection
1572          */
1573         am33xx_cpsw_init(gigabit_enable);
1575         return;
1576 out:
1577         /*
1578          * If the EEPROM hasn't been programed or an incorrect header
1579          * or board name are read, assume this is an old beaglebone board
1580          * (< Rev A3)
1581          */
1582         pr_err("Could not detect any board, falling back to: "
1583                 "Beaglebone (< Rev A3) with no daughter card connected\n");
1584         daughter_brd_detected = false;
1585         setup_beaglebone_old();
1587         /* Initialize cpsw after board detection is completed as board
1588          * information is required for configuring phy address and hence
1589          * should be call only after board detection
1590          */
1592         am33xx_cpsw_init(gigabit_enable);
1595 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1596         .byte_len       = (256*1024) / 8,
1597         .page_size      = 64,
1598         .flags          = AT24_FLAG_ADDR16,
1599         .setup          = am335x_setup_daughter_board,
1600         .context        = (void *)NULL,
1601 };
1603 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1604         .byte_len       = (256*1024) / 8,
1605         .page_size      = 64,
1606         .flags          = AT24_FLAG_ADDR16,
1607         .setup          = am335x_evm_setup,
1608         .context        = (void *)NULL,
1609 };
1611 /*
1612 * Daughter board Detection.
1613 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1614 * machine init, starting from daughter board and ending with baseboard.
1615 * Assumptions :
1616 *       1. probe for i2c devices are called in the order they are included in
1617 *          the below struct. Daughter boards eeprom are probed 1st. Baseboard
1618 *          eeprom probe is called last.
1619 */
1620 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1621         {
1622                 /* Daughter Board EEPROM */
1623                 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1624                 .platform_data  = &am335x_daughter_board_eeprom_info,
1625         },
1626         {
1627                 /* Baseboard board EEPROM */
1628                 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1629                 .platform_data  = &am335x_baseboard_eeprom_info,
1630         },
1631         {
1632                 I2C_BOARD_INFO("cpld_reg", 0x35),
1633         },
1634         {
1635                 I2C_BOARD_INFO("tlc59108", 0x40),
1636         },
1638 };
1640 static struct omap_musb_board_data musb_board_data = {
1641         .interface_type = MUSB_INTERFACE_ULPI,
1642         .mode           = MUSB_OTG,
1643         .power          = 500,
1644         .instances      = 1,
1645 };
1647 static int cpld_reg_probe(struct i2c_client *client,
1648             const struct i2c_device_id *id)
1650         cpld_client = client;
1651         return 0;
1654 static int __devexit cpld_reg_remove(struct i2c_client *client)
1656         cpld_client = NULL;
1657         return 0;
1660 static const struct i2c_device_id cpld_reg_id[] = {
1661         { "cpld_reg", 0 },
1662         { }
1663 };
1665 static struct i2c_driver cpld_reg_driver = {
1666         .driver = {
1667                 .name   = "cpld_reg",
1668         },
1669         .probe          = cpld_reg_probe,
1670         .remove         = cpld_reg_remove,
1671         .id_table       = cpld_reg_id,
1672 };
1674 static void evm_init_cpld(void)
1676         i2c_add_driver(&cpld_reg_driver);
1679 static void __init am335x_evm_i2c_init(void)
1681         /* Initially assume Low Cost EVM Config */
1682         am335x_evm_id = LOW_COST_EVM;
1684         evm_init_cpld();
1686         omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1687                                 ARRAY_SIZE(am335x_i2c_boardinfo));
1690 static struct resource am335x_rtc_resources[] = {
1691         {
1692                 .start          = AM33XX_RTC_BASE,
1693                 .end            = AM33XX_RTC_BASE + SZ_4K - 1,
1694                 .flags          = IORESOURCE_MEM,
1695         },
1696         { /* timer irq */
1697                 .start          = AM33XX_IRQ_RTC_TIMER,
1698                 .end            = AM33XX_IRQ_RTC_TIMER,
1699                 .flags          = IORESOURCE_IRQ,
1700         },
1701         { /* alarm irq */
1702                 .start          = AM33XX_IRQ_RTC_ALARM,
1703                 .end            = AM33XX_IRQ_RTC_ALARM,
1704                 .flags          = IORESOURCE_IRQ,
1705         },
1706 };
1708 static struct platform_device am335x_rtc_device = {
1709         .name           = "omap_rtc",
1710         .id             = -1,
1711         .num_resources  = ARRAY_SIZE(am335x_rtc_resources),
1712         .resource       = am335x_rtc_resources,
1713 };
1715 static int am335x_rtc_init(void)
1717         void __iomem *base;
1718         struct clk *clk;
1720         clk = clk_get(NULL, "rtc_fck");
1721         if (IS_ERR(clk)) {
1722                 pr_err("rtc : Failed to get RTC clock\n");
1723                 return -1;
1724         }
1726         if (clk_enable(clk)) {
1727                 pr_err("rtc: Clock Enable Failed\n");
1728                 return -1;
1729         }
1731         base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1733         if (WARN_ON(!base))
1734                 return -ENOMEM;
1736         /* Unlock the rtc's registers */
1737         __raw_writel(0x83e70b13, base + 0x6c);
1738         __raw_writel(0x95a4f1e0, base + 0x70);
1740         /*
1741          * Enable the 32K OSc
1742          * TODO: Need a better way to handle this
1743          * Since we want the clock to be running before mmc init
1744          * we need to do it before the rtc probe happens
1745          */
1746         __raw_writel(0x48, base + 0x54);
1748         iounmap(base);
1750         return  platform_device_register(&am335x_rtc_device);
1753 /* Enable clkout2 */
1754 static struct pinmux_config clkout2_pin_mux[] = {
1755         {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1756         {NULL, 0},
1757 };
1759 static void __init clkout2_enable(void)
1761         struct clk *ck_32;
1763         ck_32 = clk_get(NULL, "clkout2_ck");
1764         if (IS_ERR(ck_32)) {
1765                 pr_err("Cannot clk_get ck_32\n");
1766                 return;
1767         }
1769         clk_enable(ck_32);
1771         setup_pin_mux(clkout2_pin_mux);
1774 static void __init am335x_evm_init(void)
1776         am33xx_mux_init(board_mux);
1777         omap_serial_init();
1778         am335x_rtc_init();
1779         clkout2_enable();
1780         am335x_evm_i2c_init();
1781         omap_sdrc_init(NULL, NULL);
1782         usb_musb_init(&musb_board_data);
1783         omap_board_config = am335x_evm_config;
1784         omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1787 static void __init am335x_evm_map_io(void)
1789         omap2_set_globals_am33xx();
1790         omapam33xx_map_common_io();
1793 MACHINE_START(AM335XEVM, "am335xevm")
1794         /* Maintainer: Texas Instruments */
1795         .atag_offset    = 0x100,
1796         .map_io         = am335x_evm_map_io,
1797         .init_early     = am33xx_init_early,
1798         .init_irq       = ti81xx_init_irq,
1799         .handle_irq     = omap3_intc_handle_irq,
1800         .timer          = &omap3_am33xx_timer,
1801         .init_machine   = am335x_evm_init,
1802 MACHINE_END
1804 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1805         /* Maintainer: Texas Instruments */
1806         .atag_offset    = 0x100,
1807         .map_io         = am335x_evm_map_io,
1808         .init_irq       = ti81xx_init_irq,
1809         .init_early     = am33xx_init_early,
1810         .timer          = &omap3_am33xx_timer,
1811         .init_machine   = am335x_evm_init,
1812 MACHINE_END