ARM: OMAP: AM33XX: Add an API for obtaining the virt EMIF addr
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / board-am335xevm.c
1 /*
2  * Code for AM335X EVM.
3  *
4  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
35 #include <linux/mfd/tps65910.h>
36 #include <linux/pwm_backlight.h>
38 /* LCD controller is similar to DA850 */
39 #include <video/da8xx-fb.h>
41 #include <mach/hardware.h>
42 #include <mach/board-am335xevm.h>
44 #include <asm/mach-types.h>
45 #include <asm/mach/arch.h>
46 #include <asm/mach/map.h>
47 #include <asm/hardware/asp.h>
49 #include <plat/irqs.h>
50 #include <plat/board.h>
51 #include <plat/common.h>
52 #include <plat/lcdc.h>
53 #include <plat/usb.h>
54 #include <plat/mmc.h>
55 #include <plat/emif.h>
57 #include "board-flash.h"
58 #include "cpuidle33xx.h"
59 #include "mux.h"
60 #include "devices.h"
61 #include "hsmmc.h"
63 /* Convert GPIO signal to GPIO pin number */
64 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
66 /* TLK PHY IDs */
67 #define TLK110_PHY_ID           0x2000A201
68 #define TLK110_PHY_MASK         0xfffffff0
70 /* BBB PHY IDs */
71 #define BBB_PHY_ID              0x7c0f1
72 #define BBB_PHY_MASK            0xfffffffe
74 /* TLK110 PHY register offsets */
75 #define TLK110_COARSEGAIN_REG   0x00A3
76 #define TLK110_LPFHPF_REG       0x00AC
77 #define TLK110_SPAREANALOG_REG  0x00B9
78 #define TLK110_VRCR_REG         0x00D0
79 #define TLK110_SETFFE_REG       0x0107
80 #define TLK110_FTSP_REG         0x0154
81 #define TLK110_ALFATPIDL_REG    0x002A
82 #define TLK110_PSCOEF21_REG     0x0096
83 #define TLK110_PSCOEF3_REG      0x0097
84 #define TLK110_ALFAFACTOR1_REG  0x002C
85 #define TLK110_ALFAFACTOR2_REG  0x0023
86 #define TLK110_CFGPS_REG        0x0095
87 #define TLK110_FTSPTXGAIN_REG   0x0150
88 #define TLK110_SWSCR3_REG       0x000B
89 #define TLK110_SCFALLBACK_REG   0x0040
90 #define TLK110_PHYRCR_REG       0x001F
92 /* TLK110 register writes values */
93 #define TLK110_COARSEGAIN_VAL   0x0000
94 #define TLK110_LPFHPF_VAL       0x8000
95 #define TLK110_SPANALOG_VAL     0x0000
96 #define TLK110_VRCR_VAL         0x0008
97 #define TLK110_SETFFE_VAL       0x0605
98 #define TLK110_FTSP_VAL         0x0255
99 #define TLK110_ALFATPIDL_VAL    0x7998
100 #define TLK110_PSCOEF21_VAL     0x3A20
101 #define TLK110_PSCOEF3_VAL      0x003F
102 #define TLK110_ALFACTOR1_VAL    0xFF80
103 #define TLK110_ALFACTOR2_VAL    0x021C
104 #define TLK110_CFGPS_VAL        0x0000
105 #define TLK110_FTSPTXGAIN_VAL   0x6A88
106 #define TLK110_SWSCR3_VAL       0x0000
107 #define TLK110_SCFALLBACK_VAL   0xC11D
108 #define TLK110_PHYRCR_VAL       0x4000
110 #if defined(CONFIG_TLK110_WORKAROUND) || \
111                 defined(CONFIG_TLK110_WORKAROUND_MODULE)
112 #define am335x_tlk110_phy_init()\
113         do {    \
114                 phy_register_fixup_for_uid(TLK110_PHY_ID,\
115                                         TLK110_PHY_MASK,\
116                                         am335x_tlk110_phy_fixup);\
117         } while (0);
118 #else
119 #define am335x_tlk110_phy_init() do { } while (0);
120 #endif
122 static const struct display_panel disp_panel = {
123         WVGA,
124         32,
125         32,
126         COLOR_ACTIVE,
127 };
129 /* LCD backlight platform Data */
130 #define AM335X_BACKLIGHT_MAX_BRIGHTNESS        100
131 #define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS    100
132 #define AM335X_PWM_PERIOD_NANO_SECONDS        (10000 * 10)
134 #define PWM_DEVICE_ID   "ecap.0"
136 static struct platform_pwm_backlight_data am335x_backlight_data = {
137         .pwm_id         = PWM_DEVICE_ID,
138         .ch             = -1,
139         .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
140         .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
141         .pwm_period_ns  = AM335X_PWM_PERIOD_NANO_SECONDS,
142 };
144 static struct lcd_ctrl_config lcd_cfg = {
145         &disp_panel,
146         .ac_bias                = 255,
147         .ac_bias_intrpt         = 0,
148         .dma_burst_sz           = 16,
149         .bpp                    = 32,
150         .fdd                    = 0x80,
151         .tft_alt_mode           = 0,
152         .stn_565_mode           = 0,
153         .mono_8bit_mode         = 0,
154         .invert_line_clock      = 1,
155         .invert_frm_clock       = 1,
156         .sync_edge              = 0,
157         .sync_ctrl              = 1,
158         .raster_order           = 0,
159 };
161 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
162         .manu_name              = "ThreeFive",
163         .controller_data        = &lcd_cfg,
164         .type                   = "TFC_S9700RTWV35TR_01B",
165 };
167 #include "common.h"
169 /* TSc controller */
170 #include <linux/input/ti_tscadc.h>
171 #include <linux/lis3lv02d.h>
173 static struct resource tsc_resources[]  = {
174         [0] = {
175                 .start  = AM33XX_TSC_BASE,
176                 .end    = AM33XX_TSC_BASE + SZ_8K - 1,
177                 .flags  = IORESOURCE_MEM,
178         },
179         [1] = {
180                 .start  = AM33XX_IRQ_ADC_GEN,
181                 .end    = AM33XX_IRQ_ADC_GEN,
182                 .flags  = IORESOURCE_IRQ,
183         },
184 };
186 static struct tsc_data am335x_touchscreen_data  = {
187         .wires  = 4,
188         .x_plate_resistance = 200,
189 };
191 static struct platform_device tsc_device = {
192         .name   = "tsc",
193         .id     = -1,
194         .dev    = {
195                         .platform_data  = &am335x_touchscreen_data,
196         },
197         .num_resources  = ARRAY_SIZE(tsc_resources),
198         .resource       = tsc_resources,
199 };
201 static u8 am335x_iis_serializer_direction1[] = {
202         INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,        RX_MODE,
203         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
204         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
205         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
206 };
208 static struct snd_platform_data am335x_evm_snd_data1 = {
209         .tx_dma_offset  = 0x46400000,   /* McASP1 */
210         .rx_dma_offset  = 0x46400000,
211         .op_mode        = DAVINCI_MCASP_IIS_MODE,
212         .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
213         .tdm_slots      = 2,
214         .serial_dir     = am335x_iis_serializer_direction1,
215         .asp_chan_q     = EVENTQ_2,
216         .version        = MCASP_VERSION_3,
217         .txnumevt       = 1,
218         .rxnumevt       = 1,
219 };
221 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
222         {
223                 .mmc            = 1,
224                 .caps           = MMC_CAP_4_BIT_DATA,
225                 .gpio_cd        = GPIO_TO_PIN(0, 6),
226                 .gpio_wp        = GPIO_TO_PIN(3, 18),
227                 .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
228         },
229         {
230                 .mmc            = 0,    /* will be set at runtime */
231         },
232         {
233                 .mmc            = 0,    /* will be set at runtime */
234         },
235         {}      /* Terminator */
236 };
239 #ifdef CONFIG_OMAP_MUX
240 static struct omap_board_mux board_mux[] __initdata = {
241         AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
242                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
243         AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
244                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
245         { .reg_offset = OMAP_MUX_TERMINATOR },
246 };
247 #else
248 #define board_mux       NULL
249 #endif
251 /* module pin mux structure */
252 struct pinmux_config {
253         const char *string_name; /* signal name format */
254         int val; /* Options for the mux register value */
255 };
257 struct evm_dev_cfg {
258         void (*device_init)(int evm_id, int profile);
260 /*
261 * If the device is required on both baseboard & daughter board (ex i2c),
262 * specify DEV_ON_BASEBOARD
263 */
264 #define DEV_ON_BASEBOARD        0
265 #define DEV_ON_DGHTR_BRD        1
266         u32 device_on;
268         u32 profile;    /* Profiles (0-7) in which the module is present */
269 };
271 /* AM335X - CPLD Register Offsets */
272 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
273 #define CPLD_DEVICE_ID  0x04 /* CPLD identification */
274 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
275 #define CPLD_CFG_REG    0x10 /* Configuration Register */
277 static struct i2c_client *cpld_client;
278 static u32 am335x_evm_id;
279 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
280 };
282 /*
283 * EVM Config held in On-Board eeprom device.
285 * Header Format
287 *  Name                 Size    Contents
288 *                       (Bytes)
289 *-------------------------------------------------------------
290 *  Header               4       0xAA, 0x55, 0x33, 0xEE
292 *  Board Name           8       Name for board in ASCII.
293 *                               example "A33515BB" = "AM335X
294                                 Low Cost EVM board"
296 *  Version              4       Hardware version code for board in
297 *                               in ASCII. "1.0A" = rev.01.0A
299 *  Serial Number        12      Serial number of the board. This is a 12
300 *                               character string which is WWYY4P16nnnn, where
301 *                               WW = 2 digit week of the year of production
302 *                               YY = 2 digit year of production
303 *                               nnnn = incrementing board number
305 *  Configuration option 32      Codes(TBD) to show the configuration
306 *                               setup on this board.
308 *  Available            32720   Available space for other non-volatile
309 *                               data.
310 */
311 struct am335x_evm_eeprom_config {
312         u32     header;
313         u8      name[8];
314         char    version[4];
315         u8      serial[12];
316         u8      opt[32];
317 };
319 static struct am335x_evm_eeprom_config config;
320 static bool daughter_brd_detected;
322 #define GP_EVM_REV_IS_1_0               0x1
323 #define GP_EVM_REV_IS_1_1A              0x2
324 #define GP_EVM_REV_IS_UNKNOWN           0xFF
325 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
326 unsigned int gigabit_enable = 1;
328 #define EEPROM_MAC_ADDRESS_OFFSET       60 /* 4+8+4+12+32 */
329 #define EEPROM_NO_OF_MAC_ADDR           3
330 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
332 #define AM335X_EEPROM_HEADER            0xEE3355AA
334 /* current profile if exists else PROFILE_0 on error */
335 static u32 am335x_get_profile_selection(void)
337         int val = 0;
339         if (!cpld_client)
340                 /* error checking is not done in func's calling this routine.
341                 so return profile 0 on error */
342                 return 0;
344         val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
345         if (val < 0)
346                 return 0;       /* default to Profile 0 on Error */
347         else
348                 return val & 0x7;
351 /* Module pin mux for LCDC */
352 static struct pinmux_config lcdc_pin_mux[] = {
353         {"lcd_data0.lcd_data0",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
354                                                        | AM33XX_PULL_DISA},
355         {"lcd_data1.lcd_data1",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
356                                                        | AM33XX_PULL_DISA},
357         {"lcd_data2.lcd_data2",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
358                                                        | AM33XX_PULL_DISA},
359         {"lcd_data3.lcd_data3",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
360                                                        | AM33XX_PULL_DISA},
361         {"lcd_data4.lcd_data4",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
362                                                        | AM33XX_PULL_DISA},
363         {"lcd_data5.lcd_data5",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
364                                                        | AM33XX_PULL_DISA},
365         {"lcd_data6.lcd_data6",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
366                                                        | AM33XX_PULL_DISA},
367         {"lcd_data7.lcd_data7",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
368                                                        | AM33XX_PULL_DISA},
369         {"lcd_data8.lcd_data8",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
370                                                        | AM33XX_PULL_DISA},
371         {"lcd_data9.lcd_data9",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
372                                                        | AM33XX_PULL_DISA},
373         {"lcd_data10.lcd_data10",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
374                                                        | AM33XX_PULL_DISA},
375         {"lcd_data11.lcd_data11",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
376                                                        | AM33XX_PULL_DISA},
377         {"lcd_data12.lcd_data12",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
378                                                        | AM33XX_PULL_DISA},
379         {"lcd_data13.lcd_data13",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
380                                                        | AM33XX_PULL_DISA},
381         {"lcd_data14.lcd_data14",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
382                                                        | AM33XX_PULL_DISA},
383         {"lcd_data15.lcd_data15",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
384                                                        | AM33XX_PULL_DISA},
385         {"gpmc_ad8.lcd_data16",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
386         {"gpmc_ad9.lcd_data17",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
387         {"gpmc_ad10.lcd_data18",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
388         {"gpmc_ad11.lcd_data19",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
389         {"gpmc_ad12.lcd_data20",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
390         {"gpmc_ad13.lcd_data21",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
391         {"gpmc_ad14.lcd_data22",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
392         {"gpmc_ad15.lcd_data23",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
393         {"lcd_vsync.lcd_vsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
394         {"lcd_hsync.lcd_hsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
395         {"lcd_pclk.lcd_pclk",           OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
396         {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
397         {NULL, 0},
398 };
400 static struct pinmux_config tsc_pin_mux[] = {
401         {"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
402         {"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
403         {"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
404         {"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
405         {"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
406         {"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
407         {NULL, 0},
408 };
410 /* Pin mux for nand flash module */
411 static struct pinmux_config nand_pin_mux[] = {
412         {"gpmc_ad0.gpmc_ad0",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
413         {"gpmc_ad1.gpmc_ad1",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
414         {"gpmc_ad2.gpmc_ad2",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
415         {"gpmc_ad3.gpmc_ad3",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
416         {"gpmc_ad4.gpmc_ad4",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
417         {"gpmc_ad5.gpmc_ad5",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
418         {"gpmc_ad6.gpmc_ad6",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
419         {"gpmc_ad7.gpmc_ad7",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
420         {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
421         {"gpmc_wpn.gpmc_wpn",     OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
422         {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
423         {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
424         {"gpmc_oen_ren.gpmc_oen_ren",    OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
425         {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
426         {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
427         {NULL, 0},
428 };
430 /* Module pin mux for SPI fash */
431 static struct pinmux_config spi0_pin_mux[] = {
432         {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
433                                                         | AM33XX_INPUT_EN},
434         {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
435                                                         | AM33XX_INPUT_EN},
436         {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
437                                                         | AM33XX_INPUT_EN},
438         {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
439                                                         | AM33XX_INPUT_EN},
440         {NULL, 0},
441 };
443 /* Module pin mux for SPI flash */
444 static struct pinmux_config spi1_pin_mux[] = {
445         {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
446                 | AM33XX_INPUT_EN},
447         {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
448                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
449         {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
450                 | AM33XX_INPUT_EN},
451         {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
452                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
453         {NULL, 0},
454 };
456 /* Module pin mux for rgmii1 */
457 static struct pinmux_config rgmii1_pin_mux[] = {
458         {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
459         {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
460         {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
461         {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
462         {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
463         {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
464         {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
465         {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
466         {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
467         {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
468         {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
469         {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
470         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
471         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
472         {NULL, 0},
473 };
475 /* Module pin mux for rgmii2 */
476 static struct pinmux_config rgmii2_pin_mux[] = {
477         {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
478         {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
479         {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
480         {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
481         {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
482         {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
483         {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
484         {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
485         {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
486         {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
487         {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
488         {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
489         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
490         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
491         {NULL, 0},
492 };
494 /* Module pin mux for mii1 */
495 static struct pinmux_config mii1_pin_mux[] = {
496         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
497         {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
498         {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
499         {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
500         {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
501         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
502         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
503         {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
504         {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
505         {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
506         {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
507         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
508         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
509         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
510         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
511         {NULL, 0},
512 };
514 /* Module pin mux for rmii1 */
515 static struct pinmux_config rmii1_pin_mux[] = {
516         {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
517         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
518         {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
519         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
520         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
521         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
522         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
523         {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
524         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
525         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
526         {NULL, 0},
527 };
529 static struct pinmux_config i2c1_pin_mux[] = {
530         {"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
531                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
532         {"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
533                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
534         {NULL, 0},
535 };
537 /* Module pin mux for mcasp1 */
538 static struct pinmux_config mcasp1_pin_mux[] = {
539         {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
540         {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
541         {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
542         {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
543                                                 AM33XX_PIN_INPUT_PULLDOWN},
544         {NULL, 0},
545 };
548 /* Module pin mux for mmc0 */
549 static struct pinmux_config mmc0_pin_mux[] = {
550         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
551         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
552         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
553         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
554         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
555         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
556         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
557         {"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
558         {NULL, 0},
559 };
561 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
562         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
563         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
564         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
565         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
566         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
567         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
568         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
569         {NULL, 0},
570 };
572 /* Module pin mux for mmc1 */
573 static struct pinmux_config mmc1_pin_mux[] = {
574         {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
575         {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
576         {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
577         {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
578         {"gpmc_ad3.mmc1_dat3",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
579         {"gpmc_ad2.mmc1_dat2",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
580         {"gpmc_ad1.mmc1_dat1",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
581         {"gpmc_ad0.mmc1_dat0",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
582         {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
583         {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
584         {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
585         {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
586         {NULL, 0},
587 };
589 /* Module pin mux for uart3 */
590 static struct pinmux_config uart3_pin_mux[] = {
591         {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
592         {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
593         {NULL, 0},
594 };
596 static struct pinmux_config d_can_gp_pin_mux[] = {
597         {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
598         {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
599         {NULL, 0},
600 };
602 static struct pinmux_config d_can_ia_pin_mux[] = {
603         {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
604         {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
605         {NULL, 0},
606 };
608 /* Module pin mux for uart2 */
609 static struct pinmux_config uart2_pin_mux[] = {
610         {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
611                                                 AM33XX_PIN_INPUT_PULLUP},
612         {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
613                                                 AM33XX_PULL_DISA |
614                                                 AM33XX_SLEWCTRL_SLOW},
615         {NULL, 0},
616 };
619 /*
620 * @pin_mux - single module pin-mux structure which defines pin-mux
621 *                       details for all its pins.
622 */
623 static void setup_pin_mux(struct pinmux_config *pin_mux)
625         int i;
627         for (i = 0; pin_mux->string_name != NULL; pin_mux++)
628                 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
632 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
634 /* pinmux for keypad device */
635 static struct pinmux_config matrix_keypad_pin_mux[] = {
636         {"gpmc_a5.gpio1_21",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
637         {"gpmc_a6.gpio1_22",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
638         {"gpmc_a9.gpio1_25",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
639         {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
640         {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
641         {NULL, 0},
642 };
644 /* Keys mapping */
645 static const uint32_t am335x_evm_matrix_keys[] = {
646         KEY(0, 0, KEY_MENU),
647         KEY(1, 0, KEY_BACK),
648         KEY(2, 0, KEY_LEFT),
650         KEY(0, 1, KEY_RIGHT),
651         KEY(1, 1, KEY_ENTER),
652         KEY(2, 1, KEY_DOWN),
653 };
655 const struct matrix_keymap_data am335x_evm_keymap_data = {
656         .keymap      = am335x_evm_matrix_keys,
657         .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
658 };
660 static const unsigned int am335x_evm_keypad_row_gpios[] = {
661         GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
662 };
664 static const unsigned int am335x_evm_keypad_col_gpios[] = {
665         GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
666 };
668 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
669         .keymap_data       = &am335x_evm_keymap_data,
670         .row_gpios         = am335x_evm_keypad_row_gpios,
671         .num_row_gpios     = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
672         .col_gpios         = am335x_evm_keypad_col_gpios,
673         .num_col_gpios     = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
674         .active_low        = false,
675         .debounce_ms       = 5,
676         .col_scan_delay_us = 2,
677 };
679 static struct platform_device am335x_evm_keyboard = {
680         .name  = "matrix-keypad",
681         .id    = -1,
682         .dev   = {
683                 .platform_data = &am335x_evm_keypad_platform_data,
684         },
685 };
687 static void matrix_keypad_init(int evm_id, int profile)
689         int err;
691         setup_pin_mux(matrix_keypad_pin_mux);
692         err = platform_device_register(&am335x_evm_keyboard);
693         if (err) {
694                 pr_err("failed to register matrix keypad (2x3) device\n");
695         }
699 /* pinmux for keypad device */
700 static struct pinmux_config volume_keys_pin_mux[] = {
701         {"spi0_sclk.gpio0_2",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
702         {"spi0_d0.gpio0_3",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
703         {NULL, 0},
704 };
706 /* Configure GPIOs for Volume Keys */
707 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
708         {
709                 .code                   = KEY_VOLUMEUP,
710                 .gpio                   = GPIO_TO_PIN(0, 2),
711                 .active_low             = true,
712                 .desc                   = "volume-up",
713                 .type                   = EV_KEY,
714                 .wakeup                 = 1,
715         },
716         {
717                 .code                   = KEY_VOLUMEDOWN,
718                 .gpio                   = GPIO_TO_PIN(0, 3),
719                 .active_low             = true,
720                 .desc                   = "volume-down",
721                 .type                   = EV_KEY,
722                 .wakeup                 = 1,
723         },
724 };
726 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
727         .buttons        = am335x_evm_volume_gpio_buttons,
728         .nbuttons       = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
729 };
731 static struct platform_device am335x_evm_volume_keys = {
732         .name   = "gpio-keys",
733         .id     = -1,
734         .dev    = {
735                 .platform_data  = &am335x_evm_volume_gpio_key_info,
736         },
737 };
739 static void volume_keys_init(int evm_id, int profile)
741         int err;
743         setup_pin_mux(volume_keys_pin_mux);
744         err = platform_device_register(&am335x_evm_volume_keys);
745         if (err)
746                 pr_err("failed to register matrix keypad (2x3) device\n");
749 /*
750 * @evm_id - evm id which needs to be configured
751 * @dev_cfg - single evm structure which includes
752 *                               all module inits, pin-mux defines
753 * @profile - if present, else PROFILE_NONE
754 * @dghtr_brd_flg - Whether Daughter board is present or not
755 */
756 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
757         int profile)
759         int i;
761         /*
762         * Only General Purpose & Industrial Auto Motro Control
763         * EVM has profiles. So check if this evm has profile.
764         * If not, ignore the profile comparison
765         */
767         /*
768         * If the device is on baseboard, directly configure it. Else (device on
769         * Daughter board), check if the daughter card is detected.
770         */
771         if (profile == PROFILE_NONE) {
772                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
773                         if (dev_cfg->device_on == DEV_ON_BASEBOARD)
774                                 dev_cfg->device_init(evm_id, profile);
775                         else if (daughter_brd_detected == true)
776                                 dev_cfg->device_init(evm_id, profile);
777                 }
778         } else {
779                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
780                         if (dev_cfg->profile & profile) {
781                                 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
782                                         dev_cfg->device_init(evm_id, profile);
783                                 else if (daughter_brd_detected == true)
784                                         dev_cfg->device_init(evm_id, profile);
785                         }
786                 }
787         }
791 /* pinmux for usb0 drvvbus */
792 static struct pinmux_config usb0_pin_mux[] = {
793         {"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
794         {NULL, 0},
795 };
797 /* pinmux for usb1 drvvbus */
798 static struct pinmux_config usb1_pin_mux[] = {
799         {"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
800         {NULL, 0},
801 };
803 /* pinmux for profibus */
804 static struct pinmux_config profibus_pin_mux[] = {
805         {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
806         {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
807         {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
808         {NULL, 0},
809 };
811 /* Module pin mux for eCAP0 */
812 static struct pinmux_config ecap0_pin_mux[] = {
813         {"ecap0_in_pwm0_out.ecap0_in_pwm0_out",
814                 OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
815         {NULL, 0},
816 };
818 static int backlight_enable;
820 #define AM335XEVM_WLAN_PMENA_GPIO       GPIO_TO_PIN(1, 30)
821 #define AM335XEVM_WLAN_IRQ_GPIO         GPIO_TO_PIN(3, 17)
823 struct wl12xx_platform_data am335xevm_wlan_data = {
824         .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
825         .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
826 };
828 /* Module pin mux for wlan and bluetooth */
829 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
830         {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
831         {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
832         {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
833         {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
834         {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
835         {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
836         {NULL, 0},
837 };
839 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
840         {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
841         {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
842         {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
843         {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
844         {NULL, 0},
845 };
847 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
848         {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
849         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
850         {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
851         {NULL, 0},
852  };
854 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
855         {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
856         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
857         {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
858         {NULL, 0},
859  };
861 static void enable_ecap0(int evm_id, int profile)
863         backlight_enable = true;
866 /* Setup pwm-backlight */
867 static struct platform_device am335x_backlight = {
868         .name           = "pwm-backlight",
869         .id             = -1,
870         .dev            = {
871                 .platform_data  = &am335x_backlight_data,
872         }
873 };
875 static int __init ecap0_init(void)
877         int status = 0;
879         if (backlight_enable) {
880                 setup_pin_mux(ecap0_pin_mux);
881                 platform_device_register(&am335x_backlight);
882         }
883         return status;
885 late_initcall(ecap0_init);
887 static int __init conf_disp_pll(int rate)
889         struct clk *disp_pll;
890         int ret = -EINVAL;
892         disp_pll = clk_get(NULL, "dpll_disp_ck");
893         if (IS_ERR(disp_pll)) {
894                 pr_err("Cannot clk_get disp_pll\n");
895                 goto out;
896         }
898         ret = clk_set_rate(disp_pll, rate);
899         clk_put(disp_pll);
900 out:
901         return ret;
904 static void lcdc_init(int evm_id, int profile)
907         setup_pin_mux(lcdc_pin_mux);
909         if (conf_disp_pll(300000000)) {
910                 pr_info("Failed configure display PLL, not attempting to"
911                                 "register LCDC\n");
912                 return;
913         }
915         if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
916                 pr_info("Failed to register LCDC device\n");
917         return;
920 static void tsc_init(int evm_id, int profile)
922         int err;
924         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
925                 am335x_touchscreen_data.analog_input = 1;
926                 pr_info("TSC connected to beta GP EVM\n");
927         } else {
928                 am335x_touchscreen_data.analog_input = 0;
929                 pr_info("TSC connected to alpha GP EVM\n");
930         }
931         setup_pin_mux(tsc_pin_mux);
932         err = platform_device_register(&tsc_device);
933         if (err)
934                 pr_err("failed to register touchscreen device\n");
937 static void rgmii1_init(int evm_id, int profile)
939         setup_pin_mux(rgmii1_pin_mux);
940         return;
943 static void rgmii2_init(int evm_id, int profile)
945         setup_pin_mux(rgmii2_pin_mux);
946         return;
949 static void mii1_init(int evm_id, int profile)
951         setup_pin_mux(mii1_pin_mux);
952         return;
955 static void rmii1_init(int evm_id, int profile)
957         setup_pin_mux(rmii1_pin_mux);
958         return;
961 static void usb0_init(int evm_id, int profile)
963         setup_pin_mux(usb0_pin_mux);
964         return;
967 static void usb1_init(int evm_id, int profile)
969         setup_pin_mux(usb1_pin_mux);
970         return;
973 /* setup uart3 */
974 static void uart3_init(int evm_id, int profile)
976         setup_pin_mux(uart3_pin_mux);
977         return;
980 /* setup uart2 */
981 static void uart2_init(int evm_id, int profile)
983         setup_pin_mux(uart2_pin_mux);
984         return;
987 /* NAND partition information */
988 static struct mtd_partition am335x_nand_partitions[] = {
989 /* All the partition sizes are listed in terms of NAND block size */
990         {
991                 .name           = "SPL",
992                 .offset         = 0,                    /* Offset = 0x0 */
993                 .size           = SZ_128K,
994         },
995         {
996                 .name           = "SPL.backup1",
997                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x20000 */
998                 .size           = SZ_128K,
999         },
1000         {
1001                 .name           = "SPL.backup2",
1002                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x40000 */
1003                 .size           = SZ_128K,
1004         },
1005         {
1006                 .name           = "SPL.backup3",
1007                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x60000 */
1008                 .size           = SZ_128K,
1009         },
1010         {
1011                 .name           = "U-Boot",
1012                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
1013                 .size           = 15 * SZ_128K,
1014         },
1015         {
1016                 .name           = "U-Boot Env",
1017                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
1018                 .size           = 1 * SZ_128K,
1019         },
1020         {
1021                 .name           = "Kernel",
1022                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
1023                 .size           = 40 * SZ_128K,
1024         },
1025         {
1026                 .name           = "File System",
1027                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
1028                 .size           = MTDPART_SIZ_FULL,
1029         },
1030 };
1032 /* SPI 0/1 Platform Data */
1033 /* SPI flash information */
1034 static struct mtd_partition am335x_spi_partitions[] = {
1035         /* All the partition sizes are listed in terms of erase size */
1036         {
1037                 .name       = "SPL",
1038                 .offset     = 0,                        /* Offset = 0x0 */
1039                 .size       = SZ_128K,
1040         },
1041         {
1042                 .name       = "U-Boot",
1043                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x20000 */
1044                 .size       = 2 * SZ_128K,
1045         },
1046         {
1047                 .name       = "U-Boot Env",
1048                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x60000 */
1049                 .size       = 2 * SZ_4K,
1050         },
1051         {
1052                 .name       = "Kernel",
1053                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x62000 */
1054                 .size       = 28 * SZ_128K,
1055         },
1056         {
1057                 .name       = "File System",
1058                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x3E2000 */
1059                 .size       = MTDPART_SIZ_FULL,         /* size ~= 4.1 MiB */
1060         }
1061 };
1063 static const struct flash_platform_data am335x_spi_flash = {
1064         .type      = "w25q64",
1065         .name      = "spi_flash",
1066         .parts     = am335x_spi_partitions,
1067         .nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
1068 };
1070 /*
1071  * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1072  * So setup Max speed to be less than that of Controller speed
1073  */
1074 static struct spi_board_info am335x_spi0_slave_info[] = {
1075         {
1076                 .modalias      = "m25p80",
1077                 .platform_data = &am335x_spi_flash,
1078                 .irq           = -1,
1079                 .max_speed_hz  = 24000000,
1080                 .bus_num       = 1,
1081                 .chip_select   = 0,
1082         },
1083 };
1085 static struct spi_board_info am335x_spi1_slave_info[] = {
1086         {
1087                 .modalias      = "m25p80",
1088                 .platform_data = &am335x_spi_flash,
1089                 .irq           = -1,
1090                 .max_speed_hz  = 12000000,
1091                 .bus_num       = 2,
1092                 .chip_select   = 0,
1093         },
1094 };
1096 static void evm_nand_init(int evm_id, int profile)
1098         setup_pin_mux(nand_pin_mux);
1099         board_nand_init(am335x_nand_partitions,
1100                 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1103 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1104         .click_flags = LIS3_CLICK_SINGLE_X |
1105                         LIS3_CLICK_SINGLE_Y |
1106                         LIS3_CLICK_SINGLE_Z,
1107         .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1108                         LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1109                         LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1110         .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1111         .wakeup_thresh  = 10,
1112         .click_thresh_x = 10,
1113         .click_thresh_y = 10,
1114         .click_thresh_z = 10,
1115         .g_range        = 2,
1116         .st_min_limits[0] = 120,
1117         .st_min_limits[1] = 120,
1118         .st_min_limits[2] = 140,
1119         .st_max_limits[0] = 550,
1120         .st_max_limits[1] = 550,
1121         .st_max_limits[2] = 750,
1122 };
1124 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1125         {
1126                 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1127         },
1128         {
1129                 I2C_BOARD_INFO("lis331dlh", 0x18),
1130                 .platform_data = &lis331dlh_pdata,
1131         },
1132         {
1133                 I2C_BOARD_INFO("tsl2550", 0x39),
1134         },
1135         {
1136                 I2C_BOARD_INFO("tmp275", 0x48),
1137         },
1138 };
1140 static void i2c1_init(int evm_id, int profile)
1142         setup_pin_mux(i2c1_pin_mux);
1143         omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1144                         ARRAY_SIZE(am335x_i2c_boardinfo1));
1145         return;
1148 /* Setup McASP 1 */
1149 static void mcasp1_init(int evm_id, int profile)
1151         /* Configure McASP */
1152         setup_pin_mux(mcasp1_pin_mux);
1153         am335x_register_mcasp1(&am335x_evm_snd_data1);
1154         return;
1157 static void mmc1_init(int evm_id, int profile)
1159         setup_pin_mux(mmc1_pin_mux);
1161         am335x_mmc[1].mmc = 2;
1162         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1163         am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1164         am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1165         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1167         /* mmc will be initialized when mmc0_init is called */
1168         return;
1171 static void mmc2_wl12xx_init(int evm_id, int profile)
1173         setup_pin_mux(mmc2_wl12xx_pin_mux);
1175         am335x_mmc[1].mmc = 3;
1176         am335x_mmc[1].name = "wl1271";
1177         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1178                                 | MMC_PM_KEEP_POWER;
1179         am335x_mmc[1].nonremovable = true;
1180         am335x_mmc[1].gpio_cd = -EINVAL;
1181         am335x_mmc[1].gpio_wp = -EINVAL;
1182         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1184         /* mmc will be initialized when mmc0_init is called */
1185         return;
1188 static void uart1_wl12xx_init(int evm_id, int profile)
1190         setup_pin_mux(uart1_wl12xx_pin_mux);
1193 static void wl12xx_bluetooth_enable(void)
1195         int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1196                 "bt_en\n");
1197         if (status < 0)
1198                 pr_err("Failed to request gpio for bt_enable");
1200         pr_info("Configure Bluetooth Enable pin...\n");
1201         gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1204 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1206         if (on) {
1207                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1208                 mdelay(70);
1209         }
1210         else
1211                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1213         return 0;
1216 static void wl12xx_init(int evm_id, int profile)
1218         struct device *dev;
1219         struct omap_mmc_platform_data *pdata;
1220         int ret;
1222         /* Register WLAN and BT enable pins based on the evm board revision */
1223         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1224                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1225                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1226         }
1227         else {
1228                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1229                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1230         }
1232         wl12xx_bluetooth_enable();
1234         if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1235                 pr_err("error setting wl12xx data\n");
1237         dev = am335x_mmc[1].dev;
1238         if (!dev) {
1239                 pr_err("wl12xx mmc device initialization failed\n");
1240                 goto out;
1241         }
1243         pdata = dev->platform_data;
1244         if (!pdata) {
1245                 pr_err("Platfrom data of wl12xx device not set\n");
1246                 goto out;
1247         }
1249         ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1250                 GPIOF_OUT_INIT_LOW, "wlan_en");
1251         if (ret) {
1252                 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1253                 goto out;
1254         }
1256         if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1257                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1258         else
1259                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1261         pdata->slots[0].set_power = wl12xx_set_power;
1262 out:
1263         return;
1266 static void d_can_init(int evm_id, int profile)
1268         switch (evm_id) {
1269         case IND_AUT_MTR_EVM:
1270                 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1271                         setup_pin_mux(d_can_ia_pin_mux);
1272                         /* Instance Zero */
1273                         am33xx_d_can_init(0);
1274                 }
1275                 break;
1276         case GEN_PURP_EVM:
1277                 if (profile == PROFILE_1) {
1278                         setup_pin_mux(d_can_gp_pin_mux);
1279                         /* Instance One */
1280                         am33xx_d_can_init(1);
1281                 }
1282                 break;
1283         default:
1284                 break;
1285         }
1288 static void mmc0_init(int evm_id, int profile)
1290         setup_pin_mux(mmc0_pin_mux);
1292         omap2_hsmmc_init(am335x_mmc);
1293         return;
1296 static void mmc0_no_cd_init(int evm_id, int profile)
1298         setup_pin_mux(mmc0_no_cd_pin_mux);
1300         omap2_hsmmc_init(am335x_mmc);
1301         return;
1305 /* setup spi0 */
1306 static void spi0_init(int evm_id, int profile)
1308         setup_pin_mux(spi0_pin_mux);
1309         spi_register_board_info(am335x_spi0_slave_info,
1310                         ARRAY_SIZE(am335x_spi0_slave_info));
1311         return;
1314 /* setup spi1 */
1315 static void spi1_init(int evm_id, int profile)
1317         setup_pin_mux(spi1_pin_mux);
1318         spi_register_board_info(am335x_spi1_slave_info,
1319                         ARRAY_SIZE(am335x_spi1_slave_info));
1320         return;
1324 static int beaglebone_phy_fixup(struct phy_device *phydev)
1326         phydev->supported &= ~(SUPPORTED_100baseT_Half |
1327                                 SUPPORTED_100baseT_Full);
1329         return 0;
1332 #if defined(CONFIG_TLK110_WORKAROUND) || \
1333                         defined(CONFIG_TLK110_WORKAROUND_MODULE)
1334 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1336         unsigned int val;
1338         /* This is done as a workaround to support TLK110 rev1.0 phy */
1339         val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1340         phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1342         val = phy_read(phydev, TLK110_LPFHPF_REG);
1343         phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1345         val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1346         phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1348         val = phy_read(phydev, TLK110_VRCR_REG);
1349         phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1351         val = phy_read(phydev, TLK110_SETFFE_REG);
1352         phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1354         val = phy_read(phydev, TLK110_FTSP_REG);
1355         phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1357         val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1358         phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1360         val = phy_read(phydev, TLK110_PSCOEF21_REG);
1361         phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1363         val = phy_read(phydev, TLK110_PSCOEF3_REG);
1364         phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1366         val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1367         phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1369         val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1370         phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1372         val = phy_read(phydev, TLK110_CFGPS_REG);
1373         phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1375         val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1376         phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1378         val = phy_read(phydev, TLK110_SWSCR3_REG);
1379         phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1381         val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1382         phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1384         val = phy_read(phydev, TLK110_PHYRCR_REG);
1385         phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1387         return 0;
1389 #endif
1391 static void profibus_init(int evm_id, int profile)
1393         setup_pin_mux(profibus_pin_mux);
1394         return;
1397 /* Low-Cost EVM */
1398 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1399         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1400         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1401         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1402         {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1403         {NULL, 0, 0},
1404 };
1406 /* General Purpose EVM */
1407 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1408         {enable_ecap0,  DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1409                                                 PROFILE_2 | PROFILE_7) },
1410         {lcdc_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1411                                                 PROFILE_2 | PROFILE_7) },
1412         {tsc_init,      DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1413                                                 PROFILE_2 | PROFILE_7) },
1414         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
1415         {rgmii2_init,   DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1416                                                 PROFILE_4 | PROFILE_6) },
1417         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1418         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1419         {evm_nand_init, DEV_ON_DGHTR_BRD,
1420                 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1421         {i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1422         {mcasp1_init,   DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1423         {mmc1_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1424         {mmc2_wl12xx_init,      DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1425                                                                 PROFILE_5)},
1426         {mmc0_init,     DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1427         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_5},
1428         {spi0_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1429         {uart1_wl12xx_init,     DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1430                                                                 PROFILE_5)},
1431         {wl12xx_init,   DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1432         {d_can_init,    DEV_ON_DGHTR_BRD, PROFILE_1},
1433         {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1434         {volume_keys_init,  DEV_ON_DGHTR_BRD, PROFILE_0},
1435         {uart2_init,    DEV_ON_DGHTR_BRD, PROFILE_3},
1436         {NULL, 0, 0},
1437 };
1439 /* Industrial Auto Motor Control EVM */
1440 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1441         {mii1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1442         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1443         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1444         {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1445         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1446         {spi1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1447         {uart3_init,    DEV_ON_DGHTR_BRD, PROFILE_ALL},
1448         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1449         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_ALL},
1450         {NULL, 0, 0},
1451 };
1453 /* IP-Phone EVM */
1454 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1455         {enable_ecap0,  DEV_ON_DGHTR_BRD, PROFILE_NONE},
1456         {lcdc_init,     DEV_ON_DGHTR_BRD, PROFILE_NONE},
1457         {tsc_init,      DEV_ON_DGHTR_BRD, PROFILE_NONE},
1458         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1459         {rgmii2_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1460         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1461         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1462         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1463         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1464         {mcasp1_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1465         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1466         {NULL, 0, 0},
1467 };
1469 /* Beaglebone < Rev A3 */
1470 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1471         {rmii1_init,    DEV_ON_BASEBOARD, PROFILE_NONE},
1472         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1473         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1474         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1475         {NULL, 0, 0},
1476 };
1478 /* Beaglebone Rev A3 and after */
1479 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1480         {mii1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1481         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1482         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1483         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1484         {NULL, 0, 0},
1485 };
1487 static void setup_low_cost_evm(void)
1489         pr_info("The board is a AM335x Low Cost EVM.\n");
1491         _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1494 static void setup_general_purpose_evm(void)
1496         u32 prof_sel = am335x_get_profile_selection();
1497         pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1499         if (!strncmp("1.1A", config.version, 4)) {
1500                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1501         } else if (!strncmp("1.0", config.version, 3)) {
1502                 gp_evm_revision = GP_EVM_REV_IS_1_0;
1503         } else {
1504                 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1505                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1506         }
1508         if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1509                 gigabit_enable = 0;
1510         else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1511                 gigabit_enable = 1;
1513         _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1516 static void setup_ind_auto_motor_ctrl_evm(void)
1518         u32 prof_sel = am335x_get_profile_selection();
1520         pr_info("The board is an industrial automation EVM in profile %d\n",
1521                 prof_sel);
1523         /* Only Profile 0 is supported */
1524         if ((1L << prof_sel) != PROFILE_0) {
1525                 pr_err("AM335X: Only Profile 0 is supported\n");
1526                 pr_err("Assuming profile 0 & continuing\n");
1527                 prof_sel = PROFILE_0;
1528         }
1530         _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1531                 PROFILE_0);
1533         /* Fillup global evmid */
1534         am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1536         /* Initialize TLK110 PHY registers for phy version 1.0 */
1537         am335x_tlk110_phy_init();
1542 static void setup_ip_phone_evm(void)
1544         pr_info("The board is an IP phone EVM\n");
1546         _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1549 /* BeagleBone < Rev A3 */
1550 static void setup_beaglebone_old(void)
1552         pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1554         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1555         am335x_mmc[0].gpio_wp = -EINVAL;
1557         _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1559         phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1560                                         beaglebone_phy_fixup);
1562         /* Fill up global evmid */
1563         am33xx_evmid_fillup(BEAGLE_BONE_OLD);
1566 /* BeagleBone after Rev A3 */
1567 static void setup_beaglebone(void)
1569         pr_info("The board is a AM335x Beaglebone.\n");
1571         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1572         am335x_mmc[0].gpio_wp = -EINVAL;
1574         _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1576         /* Fill up global evmid */
1577         am33xx_evmid_fillup(BEAGLE_BONE_A3);
1581 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1583         u8 tmp;
1584         int ret;
1586         /*
1587          * try reading a byte from the EEPROM to see if it is
1588          * present. We could read a lot more, but that would
1589          * just slow the boot process and we have all the information
1590          * we need from the EEPROM on the base board anyway.
1591          */
1592         ret = m->read(m, &tmp, 0, sizeof(u8));
1593         if (ret == sizeof(u8)) {
1594                 pr_info("Detected a daughter card on AM335x EVM..");
1595                 daughter_brd_detected = true;
1596         } else {
1597                 pr_info("No daughter card found\n");
1598                 daughter_brd_detected = false;
1599         }
1602 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1604         int ret;
1605         char tmp[10];
1607         /* 1st get the MAC address from EEPROM */
1608         ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1609                 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1611         if (ret != sizeof(am335x_mac_addr)) {
1612                 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1613                 return;
1614         }
1616         /* Fillup global mac id */
1617         am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1618                                 &am335x_mac_addr[1][0]);
1620         /* get board specific data */
1621         ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1622         if (ret != sizeof(config)) {
1623                 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1624                 return;
1625         }
1627         if (config.header != AM335X_EEPROM_HEADER) {
1628                 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1629                         config.header, AM335X_EEPROM_HEADER);
1630                 goto out;
1631         }
1633         if (strncmp("A335", config.name, 4)) {
1634                 pr_err("Board %s doesn't look like an AM335x board\n",
1635                         config.name);
1636                 goto out;
1637         }
1639         snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1640         pr_info("Board name: %s\n", tmp);
1641         snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1642         pr_info("Board version: %s\n", tmp);
1644         if (!strncmp("A335BONE", config.name, 8)) {
1645                 daughter_brd_detected = false;
1646                 if(!strncmp("00A1", config.version, 4) ||
1647                    !strncmp("00A2", config.version, 4))
1648                         setup_beaglebone_old();
1649                 else
1650                         setup_beaglebone();
1651         } else {
1652                 /* only 6 characters of options string used for now */
1653                 snprintf(tmp, 7, "%s", config.opt);
1654                 pr_info("SKU: %s\n", tmp);
1656                 if (!strncmp("SKU#00", config.opt, 6))
1657                         setup_low_cost_evm();
1658                 else if (!strncmp("SKU#01", config.opt, 6))
1659                         setup_general_purpose_evm();
1660                 else if (!strncmp("SKU#02", config.opt, 6))
1661                         setup_ind_auto_motor_ctrl_evm();
1662                 else if (!strncmp("SKU#03", config.opt, 6))
1663                         setup_ip_phone_evm();
1664                 else
1665                         goto out;
1666         }
1667         /* Initialize cpsw after board detection is completed as board
1668          * information is required for configuring phy address and hence
1669          * should be call only after board detection
1670          */
1671         am33xx_cpsw_init(gigabit_enable);
1673         return;
1674 out:
1675         /*
1676          * If the EEPROM hasn't been programed or an incorrect header
1677          * or board name are read, assume this is an old beaglebone board
1678          * (< Rev A3)
1679          */
1680         pr_err("Could not detect any board, falling back to: "
1681                 "Beaglebone (< Rev A3) with no daughter card connected\n");
1682         daughter_brd_detected = false;
1683         setup_beaglebone_old();
1685         /* Initialize cpsw after board detection is completed as board
1686          * information is required for configuring phy address and hence
1687          * should be call only after board detection
1688          */
1690         am33xx_cpsw_init(gigabit_enable);
1693 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1694         .byte_len       = (256*1024) / 8,
1695         .page_size      = 64,
1696         .flags          = AT24_FLAG_ADDR16,
1697         .setup          = am335x_setup_daughter_board,
1698         .context        = (void *)NULL,
1699 };
1701 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1702         .byte_len       = (256*1024) / 8,
1703         .page_size      = 64,
1704         .flags          = AT24_FLAG_ADDR16,
1705         .setup          = am335x_evm_setup,
1706         .context        = (void *)NULL,
1707 };
1709 static struct regulator_init_data am335x_dummy = {
1710         .constraints.always_on  = true,
1711 };
1713 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
1714         REGULATOR_SUPPLY("vdd_mpu", NULL),
1715 };
1717 static struct regulator_init_data am335x_vdd1 = {
1718         .constraints = {
1719                 .min_uV                 = 600000,
1720                 .max_uV                 = 1500000,
1721                 .valid_modes_mask       = REGULATOR_MODE_NORMAL,
1722                 .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
1723                 .always_on              = 1,
1724         },
1725         .num_consumer_supplies  = ARRAY_SIZE(am335x_vdd1_supply),
1726         .consumer_supplies      = am335x_vdd1_supply,
1727 };
1729 static struct tps65910_board am335x_tps65910_info = {
1730         .tps65910_pmic_init_data[TPS65910_REG_VRTC]     = &am335x_dummy,
1731         .tps65910_pmic_init_data[TPS65910_REG_VIO]      = &am335x_dummy,
1732         .tps65910_pmic_init_data[TPS65910_REG_VDD1]     = &am335x_vdd1,
1733         .tps65910_pmic_init_data[TPS65910_REG_VDD2]     = &am335x_dummy,
1734         .tps65910_pmic_init_data[TPS65910_REG_VDD3]     = &am335x_dummy,
1735         .tps65910_pmic_init_data[TPS65910_REG_VDIG1]    = &am335x_dummy,
1736         .tps65910_pmic_init_data[TPS65910_REG_VDIG2]    = &am335x_dummy,
1737         .tps65910_pmic_init_data[TPS65910_REG_VPLL]     = &am335x_dummy,
1738         .tps65910_pmic_init_data[TPS65910_REG_VDAC]     = &am335x_dummy,
1739         .tps65910_pmic_init_data[TPS65910_REG_VAUX1]    = &am335x_dummy,
1740         .tps65910_pmic_init_data[TPS65910_REG_VAUX2]    = &am335x_dummy,
1741         .tps65910_pmic_init_data[TPS65910_REG_VAUX33]   = &am335x_dummy,
1742         .tps65910_pmic_init_data[TPS65910_REG_VMMC]     = &am335x_dummy,
1743 };
1745 /*
1746 * Daughter board Detection.
1747 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1748 * machine init, starting from daughter board and ending with baseboard.
1749 * Assumptions :
1750 *       1. probe for i2c devices are called in the order they are included in
1751 *          the below struct. Daughter boards eeprom are probed 1st. Baseboard
1752 *          eeprom probe is called last.
1753 */
1754 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1755         {
1756                 /* Daughter Board EEPROM */
1757                 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1758                 .platform_data  = &am335x_daughter_board_eeprom_info,
1759         },
1760         {
1761                 /* Baseboard board EEPROM */
1762                 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1763                 .platform_data  = &am335x_baseboard_eeprom_info,
1764         },
1765         {
1766                 I2C_BOARD_INFO("cpld_reg", 0x35),
1767         },
1768         {
1769                 I2C_BOARD_INFO("tlc59108", 0x40),
1770         },
1771         {
1772                 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
1773                 .platform_data  = &am335x_tps65910_info,
1774         },
1776 };
1778 static struct omap_musb_board_data musb_board_data = {
1779         .interface_type = MUSB_INTERFACE_ULPI,
1780         /*
1781          * mode[0:3] = USB0PORT's mode
1782          * mode[4:7] = USB1PORT's mode
1783          * AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
1784          */
1785         .mode           = (MUSB_HOST << 4) | MUSB_OTG,
1786         .power          = 500,
1787         .instances      = 1,
1788 };
1790 static int cpld_reg_probe(struct i2c_client *client,
1791             const struct i2c_device_id *id)
1793         cpld_client = client;
1794         return 0;
1797 static int __devexit cpld_reg_remove(struct i2c_client *client)
1799         cpld_client = NULL;
1800         return 0;
1803 static const struct i2c_device_id cpld_reg_id[] = {
1804         { "cpld_reg", 0 },
1805         { }
1806 };
1808 static struct i2c_driver cpld_reg_driver = {
1809         .driver = {
1810                 .name   = "cpld_reg",
1811         },
1812         .probe          = cpld_reg_probe,
1813         .remove         = cpld_reg_remove,
1814         .id_table       = cpld_reg_id,
1815 };
1817 static void evm_init_cpld(void)
1819         i2c_add_driver(&cpld_reg_driver);
1822 static void __init am335x_evm_i2c_init(void)
1824         /* Initially assume Low Cost EVM Config */
1825         am335x_evm_id = LOW_COST_EVM;
1827         evm_init_cpld();
1829         omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1830                                 ARRAY_SIZE(am335x_i2c_boardinfo));
1833 static struct resource am335x_rtc_resources[] = {
1834         {
1835                 .start          = AM33XX_RTC_BASE,
1836                 .end            = AM33XX_RTC_BASE + SZ_4K - 1,
1837                 .flags          = IORESOURCE_MEM,
1838         },
1839         { /* timer irq */
1840                 .start          = AM33XX_IRQ_RTC_TIMER,
1841                 .end            = AM33XX_IRQ_RTC_TIMER,
1842                 .flags          = IORESOURCE_IRQ,
1843         },
1844         { /* alarm irq */
1845                 .start          = AM33XX_IRQ_RTC_ALARM,
1846                 .end            = AM33XX_IRQ_RTC_ALARM,
1847                 .flags          = IORESOURCE_IRQ,
1848         },
1849 };
1851 static struct platform_device am335x_rtc_device = {
1852         .name           = "omap_rtc",
1853         .id             = -1,
1854         .num_resources  = ARRAY_SIZE(am335x_rtc_resources),
1855         .resource       = am335x_rtc_resources,
1856 };
1858 static int am335x_rtc_init(void)
1860         void __iomem *base;
1861         struct clk *clk;
1863         clk = clk_get(NULL, "rtc_fck");
1864         if (IS_ERR(clk)) {
1865                 pr_err("rtc : Failed to get RTC clock\n");
1866                 return -1;
1867         }
1869         if (clk_enable(clk)) {
1870                 pr_err("rtc: Clock Enable Failed\n");
1871                 return -1;
1872         }
1874         base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1876         if (WARN_ON(!base))
1877                 return -ENOMEM;
1879         /* Unlock the rtc's registers */
1880         __raw_writel(0x83e70b13, base + 0x6c);
1881         __raw_writel(0x95a4f1e0, base + 0x70);
1883         /*
1884          * Enable the 32K OSc
1885          * TODO: Need a better way to handle this
1886          * Since we want the clock to be running before mmc init
1887          * we need to do it before the rtc probe happens
1888          */
1889         __raw_writel(0x48, base + 0x54);
1891         iounmap(base);
1893         return  platform_device_register(&am335x_rtc_device);
1896 /* Enable clkout2 */
1897 static struct pinmux_config clkout2_pin_mux[] = {
1898         {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1899         {NULL, 0},
1900 };
1902 static void __init clkout2_enable(void)
1904         struct clk *ck_32;
1906         ck_32 = clk_get(NULL, "clkout2_ck");
1907         if (IS_ERR(ck_32)) {
1908                 pr_err("Cannot clk_get ck_32\n");
1909                 return;
1910         }
1912         clk_enable(ck_32);
1914         setup_pin_mux(clkout2_pin_mux);
1917 void __iomem *am33xx_emif_base;
1919 void __iomem * __init am33xx_get_mem_ctlr(void)
1922         am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1924         if (!am33xx_emif_base)
1925                 pr_warning("%s: Unable to map DDR2 controller", __func__);
1927         return am33xx_emif_base;
1930 void __iomem *am33xx_get_ram_base(void)
1932         return am33xx_emif_base;
1935 static struct resource am33xx_cpuidle_resources[] = {
1936         {
1937                 .start          = AM33XX_EMIF0_BASE,
1938                 .end            = AM33XX_EMIF0_BASE + SZ_32K - 1,
1939                 .flags          = IORESOURCE_MEM,
1940         },
1941 };
1943 /* AM33XX devices support DDR2 power down */
1944 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1945         .ddr2_pdown     = 1,
1946 };
1948 static struct platform_device am33xx_cpuidle_device = {
1949         .name                   = "cpuidle-am33xx",
1950         .num_resources          = ARRAY_SIZE(am33xx_cpuidle_resources),
1951         .resource               = am33xx_cpuidle_resources,
1952         .dev = {
1953                 .platform_data  = &am33xx_cpuidle_pdata,
1954         },
1955 };
1957 static void __init am33xx_cpuidle_init(void)
1959         int ret;
1961         am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1963         ret = platform_device_register(&am33xx_cpuidle_device);
1965         if (ret)
1966                 pr_warning("AM33XX cpuidle registration failed\n");
1970 static void __init am335x_evm_init(void)
1972         am33xx_cpuidle_init();
1973         am33xx_mux_init(board_mux);
1974         omap_serial_init();
1975         am335x_rtc_init();
1976         clkout2_enable();
1977         am335x_evm_i2c_init();
1978         omap_sdrc_init(NULL, NULL);
1979         usb_musb_init(&musb_board_data);
1980         omap_board_config = am335x_evm_config;
1981         omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1982         /* Create an alias for icss clock */
1983         if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1984                 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1985         /* Create an alias for gfx/sgx clock */
1986         if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1987                 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1990 static void __init am335x_evm_map_io(void)
1992         omap2_set_globals_am33xx();
1993         omapam33xx_map_common_io();
1996 MACHINE_START(AM335XEVM, "am335xevm")
1997         /* Maintainer: Texas Instruments */
1998         .atag_offset    = 0x100,
1999         .map_io         = am335x_evm_map_io,
2000         .init_early     = am33xx_init_early,
2001         .init_irq       = ti81xx_init_irq,
2002         .handle_irq     = omap3_intc_handle_irq,
2003         .timer          = &omap3_am33xx_timer,
2004         .init_machine   = am335x_evm_init,
2005 MACHINE_END
2007 MACHINE_START(AM335XIAEVM, "am335xiaevm")
2008         /* Maintainer: Texas Instruments */
2009         .atag_offset    = 0x100,
2010         .map_io         = am335x_evm_map_io,
2011         .init_irq       = ti81xx_init_irq,
2012         .init_early     = am33xx_init_early,
2013         .timer          = &omap3_am33xx_timer,
2014         .init_machine   = am335x_evm_init,
2015 MACHINE_END