1 /*
2 * Code for AM335X EVM.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/err.h>
30 #include <linux/wl12xx.h>
31 #include <linux/ethtool.h>
33 /* LCD controller is similar to DA850 */
34 #include <video/da8xx-fb.h>
36 #include <mach/hardware.h>
37 #include <mach/board-am335xevm.h>
39 #include <asm/mach-types.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/map.h>
42 #include <asm/hardware/asp.h>
44 #include <plat/irqs.h>
45 #include <plat/board.h>
46 #include <plat/common.h>
47 #include <plat/lcdc.h>
48 #include <plat/usb.h>
49 #include <plat/mmc.h>
51 #include "board-flash.h"
52 #include "mux.h"
53 #include "devices.h"
54 #include "hsmmc.h"
56 /* Convert GPIO signal to GPIO pin number */
57 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
59 /* TLK PHY IDs */
60 #define TLK110_PHY_ID 0x2000A201
61 #define TLK110_PHY_MASK 0xfffffff0
63 /* BBB PHY IDs */
64 #define BBB_PHY_ID 0x7c0f1
65 #define BBB_PHY_MASK 0xfffffffe
67 /* TLK110 PHY register offsets */
68 #define TLK110_COARSEGAIN_REG 0x00A3
69 #define TLK110_LPFHPF_REG 0x00AC
70 #define TLK110_SPAREANALOG_REG 0x00B9
71 #define TLK110_VRCR_REG 0x00D0
72 #define TLK110_SETFFE_REG 0x0107
73 #define TLK110_FTSP_REG 0x0154
74 #define TLK110_ALFATPIDL_REG 0x002A
75 #define TLK110_PSCOEF21_REG 0x0096
76 #define TLK110_PSCOEF3_REG 0x0097
77 #define TLK110_ALFAFACTOR1_REG 0x002C
78 #define TLK110_ALFAFACTOR2_REG 0x0023
79 #define TLK110_CFGPS_REG 0x0095
80 #define TLK110_FTSPTXGAIN_REG 0x0150
81 #define TLK110_SWSCR3_REG 0x000B
82 #define TLK110_SCFALLBACK_REG 0x0040
83 #define TLK110_PHYRCR_REG 0x001F
85 /* TLK110 register writes values */
86 #define TLK110_COARSEGAIN_VAL 0x0000
87 #define TLK110_LPFHPF_VAL 0x8000
88 #define TLK110_SPANALOG_VAL 0x0000
89 #define TLK110_VRCR_VAL 0x0008
90 #define TLK110_SETFFE_VAL 0x0605
91 #define TLK110_FTSP_VAL 0x0255
92 #define TLK110_ALFATPIDL_VAL 0x7998
93 #define TLK110_PSCOEF21_VAL 0x3A20
94 #define TLK110_PSCOEF3_VAL 0x003F
95 #define TLK110_ALFACTOR1_VAL 0xFF80
96 #define TLK110_ALFACTOR2_VAL 0x021C
97 #define TLK110_CFGPS_VAL 0x0000
98 #define TLK110_FTSPTXGAIN_VAL 0x6A88
99 #define TLK110_SWSCR3_VAL 0x0000
100 #define TLK110_SCFALLBACK_VAL 0xC11D
101 #define TLK110_PHYRCR_VAL 0x4000
103 #ifdef CONFIG_TLK110_WORKAROUND
104 #define am335x_tlk110_phy_init()\
105 do { \
106 phy_register_fixup_for_uid(TLK110_PHY_ID,\
107 TLK110_PHY_MASK,\
108 am335x_tlk110_phy_fixup);\
109 } while (0);
110 #else
111 #define am335x_tlk110_phy_init() do { } while (0);
112 #endif
114 static const struct display_panel disp_panel = {
115 WVGA,
116 32,
117 32,
118 COLOR_ACTIVE,
119 };
121 static struct lcd_ctrl_config lcd_cfg = {
122 &disp_panel,
123 .ac_bias = 255,
124 .ac_bias_intrpt = 0,
125 .dma_burst_sz = 16,
126 .bpp = 32,
127 .fdd = 0x80,
128 .tft_alt_mode = 0,
129 .stn_565_mode = 0,
130 .mono_8bit_mode = 0,
131 .invert_line_clock = 1,
132 .invert_frm_clock = 1,
133 .sync_edge = 0,
134 .sync_ctrl = 1,
135 .raster_order = 0,
136 };
138 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
139 .manu_name = "ThreeFive",
140 .controller_data = &lcd_cfg,
141 .type = "TFC_S9700RTWV35TR_01B",
142 };
144 #include "common.h"
146 /* TSc controller */
147 #include <linux/input/ti_tscadc.h>
149 static struct resource tsc_resources[] = {
150 [0] = {
151 .start = AM33XX_TSC_BASE,
152 .end = AM33XX_TSC_BASE + SZ_8K - 1,
153 .flags = IORESOURCE_MEM,
154 },
155 [1] = {
156 .start = AM33XX_IRQ_ADC_GEN,
157 .end = AM33XX_IRQ_ADC_GEN,
158 .flags = IORESOURCE_IRQ,
159 },
160 };
162 static struct tsc_data am335x_touchscreen_data = {
163 .wires = 4,
164 .x_plate_resistance = 200,
165 };
167 static struct platform_device tsc_device = {
168 .name = "tsc",
169 .id = -1,
170 .dev = {
171 .platform_data = &am335x_touchscreen_data,
172 },
173 .num_resources = ARRAY_SIZE(tsc_resources),
174 .resource = tsc_resources,
175 };
177 static u8 am335x_iis_serializer_direction1[] = {
178 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
179 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
180 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
181 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
182 };
184 static struct snd_platform_data am335x_evm_snd_data1 = {
185 .tx_dma_offset = 0x46400000, /* McASP1 */
186 .rx_dma_offset = 0x46400000,
187 .op_mode = DAVINCI_MCASP_IIS_MODE,
188 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
189 .tdm_slots = 2,
190 .serial_dir = am335x_iis_serializer_direction1,
191 .asp_chan_q = EVENTQ_2,
192 .version = MCASP_VERSION_3,
193 .txnumevt = 1,
194 .rxnumevt = 1,
195 };
197 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
198 {
199 .mmc = 1,
200 .caps = MMC_CAP_4_BIT_DATA,
201 .gpio_cd = GPIO_TO_PIN(0, 6),
202 .gpio_wp = GPIO_TO_PIN(3, 18),
203 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
204 },
205 {
206 .mmc = 0, /* will be set at runtime */
207 },
208 {
209 .mmc = 0, /* will be set at runtime */
210 },
211 {} /* Terminator */
212 };
215 #ifdef CONFIG_OMAP_MUX
216 static struct omap_board_mux board_mux[] __initdata = {
217 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
218 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
219 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
220 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
221 { .reg_offset = OMAP_MUX_TERMINATOR },
222 };
223 #else
224 #define board_mux NULL
225 #endif
227 /* module pin mux structure */
228 struct pinmux_config {
229 const char *string_name; /* signal name format */
230 int val; /* Options for the mux register value */
231 };
233 struct evm_dev_cfg {
234 void (*device_init)(int evm_id, int profile);
236 /*
237 * If the device is required on both baseboard & daughter board (ex i2c),
238 * specify DEV_ON_BASEBOARD
239 */
240 #define DEV_ON_BASEBOARD 0
241 #define DEV_ON_DGHTR_BRD 1
242 u32 device_on;
244 u32 profile; /* Profiles (0-7) in which the module is present */
245 };
247 /* AM335X - CPLD Register Offsets */
248 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
249 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
250 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
251 #define CPLD_CFG_REG 0x10 /* Configuration Register */
253 static struct i2c_client *cpld_client;
254 static u32 am335x_evm_id;
255 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
256 };
258 /*
259 * EVM Config held in On-Board eeprom device.
260 *
261 * Header Format
262 *
263 * Name Size Contents
264 * (Bytes)
265 *-------------------------------------------------------------
266 * Header 4 0xAA, 0x55, 0x33, 0xEE
267 *
268 * Board Name 8 Name for board in ASCII.
269 * example "A33515BB" = "AM335X
270 Low Cost EVM board"
271 *
272 * Version 4 Hardware version code for board in
273 * in ASCII. "1.0A" = rev.01.0A
274 *
275 * Serial Number 12 Serial number of the board. This is a 12
276 * character string which is WWYY4P16nnnn, where
277 * WW = 2 digit week of the year of production
278 * YY = 2 digit year of production
279 * nnnn = incrementing board number
280 *
281 * Configuration option 32 Codes(TBD) to show the configuration
282 * setup on this board.
283 *
284 * Available 32720 Available space for other non-volatile
285 * data.
286 */
287 struct am335x_evm_eeprom_config {
288 u32 header;
289 u8 name[8];
290 char version[4];
291 u8 serial[12];
292 u8 opt[32];
293 };
295 static struct am335x_evm_eeprom_config config;
296 static bool daughter_brd_detected;
298 #define GP_EVM_REV_IS_1_0 0x1
299 #define GP_EVM_REV_IS_1_1A 0x2
300 #define GP_EVM_REV_IS_UNKNOWN 0xFF
301 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
302 unsigned int gigabit_enable = 1;
304 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
305 #define EEPROM_NO_OF_MAC_ADDR 3
306 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
308 #define AM335X_EEPROM_HEADER 0xEE3355AA
310 /* current profile if exists else PROFILE_0 on error */
311 static u32 am335x_get_profile_selection(void)
312 {
313 int val = 0;
315 if (!cpld_client)
316 /* error checking is not done in func's calling this routine.
317 so return profile 0 on error */
318 return 0;
320 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
321 if (val < 0)
322 return 0; /* default to Profile 0 on Error */
323 else
324 return val & 0x7;
325 }
327 /* Module pin mux for LCDC */
328 static struct pinmux_config lcdc_pin_mux[] = {
329 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
330 | AM33XX_PULL_DISA},
331 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
332 | AM33XX_PULL_DISA},
333 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
334 | AM33XX_PULL_DISA},
335 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
336 | AM33XX_PULL_DISA},
337 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
338 | AM33XX_PULL_DISA},
339 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
340 | AM33XX_PULL_DISA},
341 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
342 | AM33XX_PULL_DISA},
343 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
344 | AM33XX_PULL_DISA},
345 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
346 | AM33XX_PULL_DISA},
347 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
348 | AM33XX_PULL_DISA},
349 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
350 | AM33XX_PULL_DISA},
351 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
352 | AM33XX_PULL_DISA},
353 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
354 | AM33XX_PULL_DISA},
355 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
356 | AM33XX_PULL_DISA},
357 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
358 | AM33XX_PULL_DISA},
359 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
360 | AM33XX_PULL_DISA},
361 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
362 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
363 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
364 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
365 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
366 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
367 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
368 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
369 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
370 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
371 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
372 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
373 {NULL, 0},
374 };
376 static struct pinmux_config tsc_pin_mux[] = {
377 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
378 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
379 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
380 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
381 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
382 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
383 {NULL, 0},
384 };
386 /* Pin mux for nand flash module */
387 static struct pinmux_config nand_pin_mux[] = {
388 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
389 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
390 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
391 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
392 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
393 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
394 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
395 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
396 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
397 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
398 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
399 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
400 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
401 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
402 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
403 {NULL, 0},
404 };
406 /* Module pin mux for SPI fash */
407 static struct pinmux_config spi0_pin_mux[] = {
408 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
409 | AM33XX_INPUT_EN},
410 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
411 | AM33XX_INPUT_EN},
412 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
413 | AM33XX_INPUT_EN},
414 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
415 | AM33XX_INPUT_EN},
416 {NULL, 0},
417 };
419 /* Module pin mux for SPI flash */
420 static struct pinmux_config spi1_pin_mux[] = {
421 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
422 | AM33XX_INPUT_EN},
423 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
424 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
425 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
426 | AM33XX_INPUT_EN},
427 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
428 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
429 {NULL, 0},
430 };
432 /* Module pin mux for rgmii1 */
433 static struct pinmux_config rgmii1_pin_mux[] = {
434 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
435 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
436 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
437 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
438 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
439 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
440 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
441 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
442 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
443 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
444 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
445 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
446 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
447 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
448 {NULL, 0},
449 };
451 /* Module pin mux for rgmii2 */
452 static struct pinmux_config rgmii2_pin_mux[] = {
453 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
454 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
455 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
456 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
457 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
458 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
459 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
460 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
461 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
462 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
463 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
464 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
465 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
466 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
467 {NULL, 0},
468 };
470 /* Module pin mux for mii1 */
471 static struct pinmux_config mii1_pin_mux[] = {
472 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
473 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
474 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
475 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
476 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
477 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
478 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
479 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
480 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
481 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
482 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
483 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
484 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
485 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
486 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
487 {NULL, 0},
488 };
490 /* Module pin mux for rmii1 */
491 static struct pinmux_config rmii1_pin_mux[] = {
492 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
493 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
494 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
495 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
496 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
497 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
498 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
499 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
500 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
501 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
502 {NULL, 0},
503 };
505 static struct pinmux_config i2c1_pin_mux[] = {
506 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
507 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
508 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
509 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
510 {NULL, 0},
511 };
513 /* Module pin mux for mcasp1 */
514 static struct pinmux_config mcasp1_pin_mux[] = {
515 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
516 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
517 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
518 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
519 AM33XX_PIN_INPUT_PULLDOWN},
520 {NULL, 0},
521 };
524 /* Module pin mux for mmc0 */
525 static struct pinmux_config mmc0_pin_mux[] = {
526 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
527 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
528 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
529 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
530 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
531 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
532 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
533 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
534 {NULL, 0},
535 };
537 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
538 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
539 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
540 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
541 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
542 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
543 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
544 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
545 {NULL, 0},
546 };
548 /* Module pin mux for mmc1 */
549 static struct pinmux_config mmc1_pin_mux[] = {
550 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
551 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
552 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
553 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
554 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
555 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
556 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
557 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
558 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
559 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
560 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
561 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
562 {NULL, 0},
563 };
565 /* Module pin mux for uart3 */
566 static struct pinmux_config uart3_pin_mux[] = {
567 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
568 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
569 {NULL, 0},
570 };
572 static struct pinmux_config d_can_gp_pin_mux[] = {
573 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
574 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
575 {NULL, 0},
576 };
578 static struct pinmux_config d_can_ia_pin_mux[] = {
579 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
580 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
581 {NULL, 0},
582 };
584 /*
585 * @pin_mux - single module pin-mux structure which defines pin-mux
586 * details for all its pins.
587 */
588 static void setup_pin_mux(struct pinmux_config *pin_mux)
589 {
590 int i;
592 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
593 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
595 }
597 /*
598 * @evm_id - evm id which needs to be configured
599 * @dev_cfg - single evm structure which includes
600 * all module inits, pin-mux defines
601 * @profile - if present, else PROFILE_NONE
602 * @dghtr_brd_flg - Whether Daughter board is present or not
603 */
604 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
605 int profile)
606 {
607 int i;
609 /*
610 * Only General Purpose & Industrial Auto Motro Control
611 * EVM has profiles. So check if this evm has profile.
612 * If not, ignore the profile comparison
613 */
615 /*
616 * If the device is on baseboard, directly configure it. Else (device on
617 * Daughter board), check if the daughter card is detected.
618 */
619 if (profile == PROFILE_NONE) {
620 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
621 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
622 dev_cfg->device_init(evm_id, profile);
623 else if (daughter_brd_detected == true)
624 dev_cfg->device_init(evm_id, profile);
625 }
626 } else {
627 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
628 if (dev_cfg->profile & profile) {
629 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
630 dev_cfg->device_init(evm_id, profile);
631 else if (daughter_brd_detected == true)
632 dev_cfg->device_init(evm_id, profile);
633 }
634 }
635 }
636 }
638 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
640 /* pinmux for usb0 drvvbus */
641 static struct pinmux_config usb0_pin_mux[] = {
642 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
643 {NULL, 0},
644 };
646 /* pinmux for usb1 drvvbus */
647 static struct pinmux_config usb1_pin_mux[] = {
648 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
649 {NULL, 0},
650 };
652 /* Module pin mux for eCAP0 */
653 static struct pinmux_config ecap0_pin_mux[] = {
654 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
655 {NULL, 0},
656 };
658 static int backlight_enable;
660 #define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
661 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
663 struct wl12xx_platform_data am335xevm_wlan_data = {
664 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
665 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
666 };
668 /* Module pin mux for wlan and bluetooth */
669 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
670 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
671 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
672 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
673 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
674 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
675 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
676 {NULL, 0},
677 };
679 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
680 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
681 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
682 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
683 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
684 {NULL, 0},
685 };
687 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
688 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
689 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
690 {"mcasp0_ahclkx.gpio0_17", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
691 {NULL, 0},
692 };
694 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
695 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
696 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
697 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
698 {NULL, 0},
699 };
701 static void enable_ecap0(int evm_id, int profile)
702 {
703 backlight_enable = true;
704 }
706 static int __init ecap0_init(void)
707 {
708 int status = 0;
710 if (backlight_enable) {
711 setup_pin_mux(ecap0_pin_mux);
713 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
714 if (status < 0)
715 pr_warn("Failed to request gpio for LCD backlight\n");
717 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
718 }
719 return status;
720 }
721 late_initcall(ecap0_init);
723 static int __init conf_disp_pll(int rate)
724 {
725 struct clk *disp_pll;
726 int ret = -EINVAL;
728 disp_pll = clk_get(NULL, "dpll_disp_ck");
729 if (IS_ERR(disp_pll)) {
730 pr_err("Cannot clk_get disp_pll\n");
731 goto out;
732 }
734 ret = clk_set_rate(disp_pll, rate);
735 clk_put(disp_pll);
736 out:
737 return ret;
738 }
740 static void lcdc_init(int evm_id, int profile)
741 {
743 setup_pin_mux(lcdc_pin_mux);
745 if (conf_disp_pll(300000000)) {
746 pr_info("Failed configure display PLL, not attempting to"
747 "register LCDC\n");
748 return;
749 }
751 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
752 pr_info("Failed to register LCDC device\n");
753 return;
754 }
756 static void tsc_init(int evm_id, int profile)
757 {
758 int err;
760 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
761 am335x_touchscreen_data.analog_input = 1;
762 pr_info("TSC connected to beta GP EVM\n");
763 } else {
764 am335x_touchscreen_data.analog_input = 0;
765 pr_info("TSC connected to alpha GP EVM\n");
766 }
767 setup_pin_mux(tsc_pin_mux);
768 err = platform_device_register(&tsc_device);
769 if (err)
770 pr_err("failed to register touchscreen device\n");
771 }
773 static void rgmii1_init(int evm_id, int profile)
774 {
775 setup_pin_mux(rgmii1_pin_mux);
776 return;
777 }
779 static void rgmii2_init(int evm_id, int profile)
780 {
781 setup_pin_mux(rgmii2_pin_mux);
782 return;
783 }
785 static void mii1_init(int evm_id, int profile)
786 {
787 setup_pin_mux(mii1_pin_mux);
788 return;
789 }
791 static void rmii1_init(int evm_id, int profile)
792 {
793 setup_pin_mux(rmii1_pin_mux);
794 return;
795 }
797 static void usb0_init(int evm_id, int profile)
798 {
799 setup_pin_mux(usb0_pin_mux);
800 return;
801 }
803 static void usb1_init(int evm_id, int profile)
804 {
805 setup_pin_mux(usb1_pin_mux);
806 return;
807 }
809 /* setup uart3 */
810 static void uart3_init(int evm_id, int profile)
811 {
812 setup_pin_mux(uart3_pin_mux);
813 return;
814 }
816 /* NAND partition information */
817 static struct mtd_partition am335x_nand_partitions[] = {
818 /* All the partition sizes are listed in terms of NAND block size */
819 {
820 .name = "SPL",
821 .offset = 0, /* Offset = 0x0 */
822 .size = SZ_128K,
823 },
824 {
825 .name = "SPL.backup1",
826 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
827 .size = SZ_128K,
828 },
829 {
830 .name = "SPL.backup2",
831 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
832 .size = SZ_128K,
833 },
834 {
835 .name = "SPL.backup3",
836 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
837 .size = SZ_128K,
838 },
839 {
840 .name = "U-Boot",
841 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
842 .size = 15 * SZ_128K,
843 },
844 {
845 .name = "U-Boot Env",
846 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
847 .size = 1 * SZ_128K,
848 },
849 {
850 .name = "Kernel",
851 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
852 .size = 40 * SZ_128K,
853 },
854 {
855 .name = "File System",
856 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
857 .size = MTDPART_SIZ_FULL,
858 },
859 };
861 /* SPI 0/1 Platform Data */
862 /* SPI flash information */
863 static struct mtd_partition am335x_spi_partitions[] = {
864 /* All the partition sizes are listed in terms of erase size */
865 {
866 .name = "SPL",
867 .offset = 0, /* Offset = 0x0 */
868 .size = SZ_128K,
869 },
870 {
871 .name = "U-Boot",
872 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
873 .size = 2 * SZ_128K,
874 },
875 {
876 .name = "U-Boot Env",
877 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
878 .size = 2 * SZ_4K,
879 },
880 {
881 .name = "Kernel",
882 .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
883 .size = 28 * SZ_128K,
884 },
885 {
886 .name = "File System",
887 .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
888 .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
889 }
890 };
892 static const struct flash_platform_data am335x_spi_flash = {
893 .type = "w25q64",
894 .name = "spi_flash",
895 .parts = am335x_spi_partitions,
896 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
897 };
899 /*
900 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
901 * So setup Max speed to be less than that of Controller speed
902 */
903 static struct spi_board_info am335x_spi0_slave_info[] = {
904 {
905 .modalias = "m25p80",
906 .platform_data = &am335x_spi_flash,
907 .irq = -1,
908 .max_speed_hz = 24000000,
909 .bus_num = 1,
910 .chip_select = 0,
911 },
912 };
914 static struct spi_board_info am335x_spi1_slave_info[] = {
915 {
916 .modalias = "m25p80",
917 .platform_data = &am335x_spi_flash,
918 .irq = -1,
919 .max_speed_hz = 12000000,
920 .bus_num = 2,
921 .chip_select = 0,
922 },
923 };
925 static void evm_nand_init(int evm_id, int profile)
926 {
927 setup_pin_mux(nand_pin_mux);
928 board_nand_init(am335x_nand_partitions,
929 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
930 }
932 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
933 {
934 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
935 },
936 };
938 static void i2c1_init(int evm_id, int profile)
939 {
940 setup_pin_mux(i2c1_pin_mux);
941 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
942 ARRAY_SIZE(am335x_i2c_boardinfo1));
943 return;
944 }
946 /* Setup McASP 1 */
947 static void mcasp1_init(int evm_id, int profile)
948 {
949 /* Configure McASP */
950 setup_pin_mux(mcasp1_pin_mux);
951 am335x_register_mcasp1(&am335x_evm_snd_data1);
952 return;
953 }
955 static void mmc1_init(int evm_id, int profile)
956 {
957 setup_pin_mux(mmc1_pin_mux);
959 am335x_mmc[1].mmc = 2;
960 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
961 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
962 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
963 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
965 /* mmc will be initialized when mmc0_init is called */
966 return;
967 }
969 static void mmc2_wl12xx_init(int evm_id, int profile)
970 {
971 setup_pin_mux(mmc2_wl12xx_pin_mux);
973 am335x_mmc[1].mmc = 3;
974 am335x_mmc[1].name = "wl1271";
975 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
976 | MMC_PM_KEEP_POWER;
977 am335x_mmc[1].nonremovable = true;
978 am335x_mmc[1].gpio_cd = -EINVAL;
979 am335x_mmc[1].gpio_wp = -EINVAL;
980 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
982 /* mmc will be initialized when mmc0_init is called */
983 return;
984 }
986 static void uart1_wl12xx_init(int evm_id, int profile)
987 {
988 setup_pin_mux(uart1_wl12xx_pin_mux);
989 }
991 static void wl12xx_bluetooth_enable(void)
992 {
993 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
994 "bt_en\n");
995 if (status < 0)
996 pr_err("Failed to request gpio for bt_enable");
998 pr_info("Configure Bluetooth Enable pin...\n");
999 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1000 }
1002 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1003 {
1004 if (on)
1005 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1006 else
1007 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1009 return 0;
1010 }
1012 static void wl12xx_init(int evm_id, int profile)
1013 {
1014 struct device *dev;
1015 struct omap_mmc_platform_data *pdata;
1016 int ret;
1018 /* Register WLAN and BT enable pins based on the evm board revision */
1019 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1020 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1021 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(0, 17);
1022 }
1023 else {
1024 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1025 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1026 }
1028 wl12xx_bluetooth_enable();
1030 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1031 pr_err("error setting wl12xx data\n");
1033 dev = am335x_mmc[1].dev;
1034 if (!dev) {
1035 pr_err("wl12xx mmc device initialization failed\n");
1036 goto out;
1037 }
1039 pdata = dev->platform_data;
1040 if (!pdata) {
1041 pr_err("Platfrom data of wl12xx device not set\n");
1042 goto out;
1043 }
1045 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1046 GPIOF_OUT_INIT_LOW, "wlan_en");
1047 if (ret) {
1048 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1049 goto out;
1050 }
1052 if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1053 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1054 else
1055 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1057 pdata->slots[0].set_power = wl12xx_set_power;
1058 out:
1059 return;
1060 }
1062 static void d_can_init(int evm_id, int profile)
1063 {
1064 switch (evm_id) {
1065 case IND_AUT_MTR_EVM:
1066 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1067 setup_pin_mux(d_can_ia_pin_mux);
1068 /* Instance Zero */
1069 am33xx_d_can_init(0);
1070 }
1071 break;
1072 case GEN_PURP_EVM:
1073 if (profile == PROFILE_1) {
1074 setup_pin_mux(d_can_gp_pin_mux);
1075 /* Instance One */
1076 am33xx_d_can_init(1);
1077 }
1078 break;
1079 default:
1080 break;
1081 }
1082 }
1084 static void mmc0_init(int evm_id, int profile)
1085 {
1086 setup_pin_mux(mmc0_pin_mux);
1088 omap2_hsmmc_init(am335x_mmc);
1089 return;
1090 }
1092 static void mmc0_no_cd_init(int evm_id, int profile)
1093 {
1094 setup_pin_mux(mmc0_no_cd_pin_mux);
1096 omap2_hsmmc_init(am335x_mmc);
1097 return;
1098 }
1101 /* setup spi0 */
1102 static void spi0_init(int evm_id, int profile)
1103 {
1104 setup_pin_mux(spi0_pin_mux);
1105 spi_register_board_info(am335x_spi0_slave_info,
1106 ARRAY_SIZE(am335x_spi0_slave_info));
1107 return;
1108 }
1110 /* setup spi1 */
1111 static void spi1_init(int evm_id, int profile)
1112 {
1113 setup_pin_mux(spi1_pin_mux);
1114 spi_register_board_info(am335x_spi1_slave_info,
1115 ARRAY_SIZE(am335x_spi1_slave_info));
1116 return;
1117 }
1120 static int beaglebone_phy_fixup(struct phy_device *phydev)
1121 {
1122 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1123 SUPPORTED_100baseT_Full);
1125 return 0;
1126 }
1128 #ifdef CONFIG_TLK110_WORKAROUND
1129 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1130 {
1131 unsigned int val;
1133 /* This is done as a workaround to support TLK110 rev1.0 phy */
1134 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1135 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1137 val = phy_read(phydev, TLK110_LPFHPF_REG);
1138 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1140 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1141 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1143 val = phy_read(phydev, TLK110_VRCR_REG);
1144 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1146 val = phy_read(phydev, TLK110_SETFFE_REG);
1147 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1149 val = phy_read(phydev, TLK110_FTSP_REG);
1150 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1152 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1153 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1155 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1156 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1158 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1159 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1161 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1162 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1164 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1165 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1167 val = phy_read(phydev, TLK110_CFGPS_REG);
1168 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1170 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1171 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1173 val = phy_read(phydev, TLK110_SWSCR3_REG);
1174 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1176 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1177 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1179 val = phy_read(phydev, TLK110_PHYRCR_REG);
1180 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1182 return 0;
1183 }
1184 #endif
1187 /* Low-Cost EVM */
1188 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1189 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1190 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1191 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1192 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1193 {NULL, 0, 0},
1194 };
1196 /* General Purpose EVM */
1197 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1198 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1199 PROFILE_2 | PROFILE_7) },
1200 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1201 PROFILE_2 | PROFILE_7) },
1202 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1203 PROFILE_2 | PROFILE_7) },
1204 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1205 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1206 PROFILE_4 | PROFILE_6) },
1207 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1208 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1209 {evm_nand_init, DEV_ON_DGHTR_BRD,
1210 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1211 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1212 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1213 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1214 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1215 PROFILE_5)},
1216 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1217 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1218 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1219 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1220 PROFILE_5)},
1221 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1222 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
1223 {NULL, 0, 0},
1224 };
1226 /* Industrial Auto Motor Control EVM */
1227 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1228 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1229 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1230 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1231 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1232 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1233 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1234 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1235 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1236 {NULL, 0, 0},
1237 };
1239 /* IP-Phone EVM */
1240 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1241 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1242 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1243 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1244 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1245 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1246 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1247 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1248 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1249 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1250 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1251 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1252 {NULL, 0, 0},
1253 };
1255 /* Beaglebone < Rev A3 */
1256 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1257 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1258 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1259 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1260 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1261 {NULL, 0, 0},
1262 };
1264 /* Beaglebone Rev A3 and after */
1265 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1266 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1267 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1268 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1269 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1270 {NULL, 0, 0},
1271 };
1273 static void setup_low_cost_evm(void)
1274 {
1275 pr_info("The board is a AM335x Low Cost EVM.\n");
1277 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1278 }
1280 static void setup_general_purpose_evm(void)
1281 {
1282 u32 prof_sel = am335x_get_profile_selection();
1283 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1285 if (!strncmp("1.1A", config.version, 4)) {
1286 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1287 } else if (!strncmp("1.0", config.version, 3)) {
1288 gp_evm_revision = GP_EVM_REV_IS_1_0;
1289 } else {
1290 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1291 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1292 }
1294 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1295 gigabit_enable = 0;
1296 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1297 gigabit_enable = 1;
1299 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1300 }
1302 static void setup_ind_auto_motor_ctrl_evm(void)
1303 {
1304 u32 prof_sel = am335x_get_profile_selection();
1306 pr_info("The board is an industrial automation EVM in profile %d\n",
1307 prof_sel);
1309 /* Only Profile 0 is supported */
1310 if ((1L << prof_sel) != PROFILE_0) {
1311 pr_err("AM335X: Only Profile 0 is supported\n");
1312 pr_err("Assuming profile 0 & continuing\n");
1313 prof_sel = PROFILE_0;
1314 }
1316 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1317 PROFILE_0);
1319 /* Fillup global evmid */
1320 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1322 /* Initialize TLK110 PHY registers for phy version 1.0 */
1323 am335x_tlk110_phy_init();
1326 }
1328 static void setup_ip_phone_evm(void)
1329 {
1330 pr_info("The board is an IP phone EVM\n");
1332 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1333 }
1335 /* BeagleBone < Rev A3 */
1336 static void setup_beaglebone_old(void)
1337 {
1338 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1340 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1341 am335x_mmc[0].gpio_wp = -EINVAL;
1343 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1345 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1346 beaglebone_phy_fixup);
1347 }
1349 /* BeagleBone after Rev A3 */
1350 static void setup_beaglebone(void)
1351 {
1352 pr_info("The board is a AM335x Beaglebone.\n");
1354 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1355 am335x_mmc[0].gpio_wp = -EINVAL;
1357 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1358 }
1361 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1362 {
1363 u8 tmp;
1364 int ret;
1366 /*
1367 * try reading a byte from the EEPROM to see if it is
1368 * present. We could read a lot more, but that would
1369 * just slow the boot process and we have all the information
1370 * we need from the EEPROM on the base board anyway.
1371 */
1372 ret = m->read(m, &tmp, 0, sizeof(u8));
1373 if (ret == sizeof(u8)) {
1374 pr_info("Detected a daughter card on AM335x EVM..");
1375 daughter_brd_detected = true;
1376 } else {
1377 pr_info("No daughter card found\n");
1378 daughter_brd_detected = false;
1379 }
1380 }
1382 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1383 {
1384 int ret;
1385 char tmp[10];
1387 /* 1st get the MAC address from EEPROM */
1388 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1389 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1391 if (ret != sizeof(am335x_mac_addr)) {
1392 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1393 return;
1394 }
1396 /* Fillup global mac id */
1397 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1398 &am335x_mac_addr[1][0]);
1400 /* get board specific data */
1401 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1402 if (ret != sizeof(config)) {
1403 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1404 return;
1405 }
1407 if (config.header != AM335X_EEPROM_HEADER) {
1408 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1409 config.header, AM335X_EEPROM_HEADER);
1410 goto out;
1411 }
1413 if (strncmp("A335", config.name, 4)) {
1414 pr_err("Board %s doesn't look like an AM335x board\n",
1415 config.name);
1416 goto out;
1417 }
1419 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1420 pr_info("Board name: %s\n", tmp);
1421 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1422 pr_info("Board version: %s\n", tmp);
1424 if (!strncmp("A335BONE", config.name, 8)) {
1425 daughter_brd_detected = false;
1426 if(!strncmp("00A1", config.version, 4) ||
1427 !strncmp("00A2", config.version, 4))
1428 setup_beaglebone_old();
1429 else
1430 setup_beaglebone();
1431 } else {
1432 /* only 6 characters of options string used for now */
1433 snprintf(tmp, 7, "%s", config.opt);
1434 pr_info("SKU: %s\n", tmp);
1436 if (!strncmp("SKU#00", config.opt, 6))
1437 setup_low_cost_evm();
1438 else if (!strncmp("SKU#01", config.opt, 6))
1439 setup_general_purpose_evm();
1440 else if (!strncmp("SKU#02", config.opt, 6))
1441 setup_ind_auto_motor_ctrl_evm();
1442 else if (!strncmp("SKU#03", config.opt, 6))
1443 setup_ip_phone_evm();
1444 else
1445 goto out;
1446 }
1447 /* Initialize cpsw after board detection is completed as board
1448 * information is required for configuring phy address and hence
1449 * should be call only after board detection
1450 */
1451 am33xx_cpsw_init(gigabit_enable);
1453 return;
1454 out:
1455 /*
1456 * If the EEPROM hasn't been programed or an incorrect header
1457 * or board name are read, assume this is an old beaglebone board
1458 * (< Rev A3)
1459 */
1460 pr_err("Could not detect any board, falling back to: "
1461 "Beaglebone (< Rev A3) with no daughter card connected\n");
1462 daughter_brd_detected = false;
1463 setup_beaglebone_old();
1465 /* Initialize cpsw after board detection is completed as board
1466 * information is required for configuring phy address and hence
1467 * should be call only after board detection
1468 */
1470 am33xx_cpsw_init(gigabit_enable);
1471 }
1473 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1474 .byte_len = (256*1024) / 8,
1475 .page_size = 64,
1476 .flags = AT24_FLAG_ADDR16,
1477 .setup = am335x_setup_daughter_board,
1478 .context = (void *)NULL,
1479 };
1481 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1482 .byte_len = (256*1024) / 8,
1483 .page_size = 64,
1484 .flags = AT24_FLAG_ADDR16,
1485 .setup = am335x_evm_setup,
1486 .context = (void *)NULL,
1487 };
1489 /*
1490 * Daughter board Detection.
1491 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1492 * machine init, starting from daughter board and ending with baseboard.
1493 * Assumptions :
1494 * 1. probe for i2c devices are called in the order they are included in
1495 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
1496 * eeprom probe is called last.
1497 */
1498 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1499 {
1500 /* Daughter Board EEPROM */
1501 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1502 .platform_data = &am335x_daughter_board_eeprom_info,
1503 },
1504 {
1505 /* Baseboard board EEPROM */
1506 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1507 .platform_data = &am335x_baseboard_eeprom_info,
1508 },
1509 {
1510 I2C_BOARD_INFO("cpld_reg", 0x35),
1511 },
1512 {
1513 I2C_BOARD_INFO("tlc59108", 0x40),
1514 },
1516 };
1518 static struct omap_musb_board_data musb_board_data = {
1519 .interface_type = MUSB_INTERFACE_ULPI,
1520 .mode = MUSB_OTG,
1521 .power = 500,
1522 .instances = 1,
1523 };
1525 static int cpld_reg_probe(struct i2c_client *client,
1526 const struct i2c_device_id *id)
1527 {
1528 cpld_client = client;
1529 return 0;
1530 }
1532 static int __devexit cpld_reg_remove(struct i2c_client *client)
1533 {
1534 cpld_client = NULL;
1535 return 0;
1536 }
1538 static const struct i2c_device_id cpld_reg_id[] = {
1539 { "cpld_reg", 0 },
1540 { }
1541 };
1543 static struct i2c_driver cpld_reg_driver = {
1544 .driver = {
1545 .name = "cpld_reg",
1546 },
1547 .probe = cpld_reg_probe,
1548 .remove = cpld_reg_remove,
1549 .id_table = cpld_reg_id,
1550 };
1552 static void evm_init_cpld(void)
1553 {
1554 i2c_add_driver(&cpld_reg_driver);
1555 }
1557 static void __init am335x_evm_i2c_init(void)
1558 {
1559 /* Initially assume Low Cost EVM Config */
1560 am335x_evm_id = LOW_COST_EVM;
1562 evm_init_cpld();
1564 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1565 ARRAY_SIZE(am335x_i2c_boardinfo));
1566 }
1568 static struct resource am335x_rtc_resources[] = {
1569 {
1570 .start = AM33XX_RTC_BASE,
1571 .end = AM33XX_RTC_BASE + SZ_4K - 1,
1572 .flags = IORESOURCE_MEM,
1573 },
1574 { /* timer irq */
1575 .start = AM33XX_IRQ_RTC_TIMER,
1576 .end = AM33XX_IRQ_RTC_TIMER,
1577 .flags = IORESOURCE_IRQ,
1578 },
1579 { /* alarm irq */
1580 .start = AM33XX_IRQ_RTC_ALARM,
1581 .end = AM33XX_IRQ_RTC_ALARM,
1582 .flags = IORESOURCE_IRQ,
1583 },
1584 };
1586 static struct platform_device am335x_rtc_device = {
1587 .name = "omap_rtc",
1588 .id = -1,
1589 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
1590 .resource = am335x_rtc_resources,
1591 };
1593 static int am335x_rtc_init(void)
1594 {
1595 void __iomem *base;
1596 struct clk *clk;
1598 clk = clk_get(NULL, "rtc_fck");
1599 if (IS_ERR(clk)) {
1600 pr_err("rtc : Failed to get RTC clock\n");
1601 return -1;
1602 }
1604 if (clk_enable(clk)) {
1605 pr_err("rtc: Clock Enable Failed\n");
1606 return -1;
1607 }
1609 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1611 if (WARN_ON(!base))
1612 return -ENOMEM;
1614 /* Unlock the rtc's registers */
1615 __raw_writel(0x83e70b13, base + 0x6c);
1616 __raw_writel(0x95a4f1e0, base + 0x70);
1618 /*
1619 * Enable the 32K OSc
1620 * TODO: Need a better way to handle this
1621 * Since we want the clock to be running before mmc init
1622 * we need to do it before the rtc probe happens
1623 */
1624 __raw_writel(0x48, base + 0x54);
1626 iounmap(base);
1628 return platform_device_register(&am335x_rtc_device);
1629 }
1631 /* Enable clkout2 */
1632 static struct pinmux_config clkout2_pin_mux[] = {
1633 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1634 {NULL, 0},
1635 };
1637 static void __init clkout2_enable(void)
1638 {
1639 struct clk *ck_32;
1641 ck_32 = clk_get(NULL, "clkout2_ck");
1642 if (IS_ERR(ck_32)) {
1643 pr_err("Cannot clk_get ck_32\n");
1644 return;
1645 }
1647 clk_enable(ck_32);
1649 setup_pin_mux(clkout2_pin_mux);
1650 }
1652 static void __init am335x_evm_init(void)
1653 {
1654 am33xx_mux_init(board_mux);
1655 omap_serial_init();
1656 am335x_rtc_init();
1657 clkout2_enable();
1658 am335x_evm_i2c_init();
1659 omap_sdrc_init(NULL, NULL);
1660 usb_musb_init(&musb_board_data);
1661 omap_board_config = am335x_evm_config;
1662 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1663 }
1665 static void __init am335x_evm_map_io(void)
1666 {
1667 omap2_set_globals_am33xx();
1668 omapam33xx_map_common_io();
1669 }
1671 MACHINE_START(AM335XEVM, "am335xevm")
1672 /* Maintainer: Texas Instruments */
1673 .atag_offset = 0x100,
1674 .map_io = am335x_evm_map_io,
1675 .init_early = am33xx_init_early,
1676 .init_irq = ti81xx_init_irq,
1677 .handle_irq = omap3_intc_handle_irq,
1678 .timer = &omap3_am33xx_timer,
1679 .init_machine = am335x_evm_init,
1680 MACHINE_END
1682 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1683 /* Maintainer: Texas Instruments */
1684 .atag_offset = 0x100,
1685 .map_io = am335x_evm_map_io,
1686 .init_irq = ti81xx_init_irq,
1687 .init_early = am33xx_init_early,
1688 .timer = &omap3_am33xx_timer,
1689 .init_machine = am335x_evm_init,
1690 MACHINE_END