1 /*
2 * Code for AM335X EVM.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
35 #include <linux/mfd/tps65910.h>
36 #include <linux/mfd/tps65217.h>
37 #include <linux/pwm_backlight.h>
39 /* LCD controller is similar to DA850 */
40 #include <video/da8xx-fb.h>
42 #include <mach/hardware.h>
43 #include <mach/board-am335xevm.h>
45 #include <asm/mach-types.h>
46 #include <asm/mach/arch.h>
47 #include <asm/mach/map.h>
48 #include <asm/hardware/asp.h>
50 #include <plat/irqs.h>
51 #include <plat/board.h>
52 #include <plat/common.h>
53 #include <plat/lcdc.h>
54 #include <plat/usb.h>
55 #include <plat/mmc.h>
56 #include <plat/emif.h>
58 #include "board-flash.h"
59 #include "cpuidle33xx.h"
60 #include "mux.h"
61 #include "devices.h"
62 #include "hsmmc.h"
64 /* Convert GPIO signal to GPIO pin number */
65 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
67 /* TLK PHY IDs */
68 #define TLK110_PHY_ID 0x2000A201
69 #define TLK110_PHY_MASK 0xfffffff0
71 /* BBB PHY IDs */
72 #define BBB_PHY_ID 0x7c0f1
73 #define BBB_PHY_MASK 0xfffffffe
75 /* TLK110 PHY register offsets */
76 #define TLK110_COARSEGAIN_REG 0x00A3
77 #define TLK110_LPFHPF_REG 0x00AC
78 #define TLK110_SPAREANALOG_REG 0x00B9
79 #define TLK110_VRCR_REG 0x00D0
80 #define TLK110_SETFFE_REG 0x0107
81 #define TLK110_FTSP_REG 0x0154
82 #define TLK110_ALFATPIDL_REG 0x002A
83 #define TLK110_PSCOEF21_REG 0x0096
84 #define TLK110_PSCOEF3_REG 0x0097
85 #define TLK110_ALFAFACTOR1_REG 0x002C
86 #define TLK110_ALFAFACTOR2_REG 0x0023
87 #define TLK110_CFGPS_REG 0x0095
88 #define TLK110_FTSPTXGAIN_REG 0x0150
89 #define TLK110_SWSCR3_REG 0x000B
90 #define TLK110_SCFALLBACK_REG 0x0040
91 #define TLK110_PHYRCR_REG 0x001F
93 /* TLK110 register writes values */
94 #define TLK110_COARSEGAIN_VAL 0x0000
95 #define TLK110_LPFHPF_VAL 0x8000
96 #define TLK110_SPANALOG_VAL 0x0000
97 #define TLK110_VRCR_VAL 0x0008
98 #define TLK110_SETFFE_VAL 0x0605
99 #define TLK110_FTSP_VAL 0x0255
100 #define TLK110_ALFATPIDL_VAL 0x7998
101 #define TLK110_PSCOEF21_VAL 0x3A20
102 #define TLK110_PSCOEF3_VAL 0x003F
103 #define TLK110_ALFACTOR1_VAL 0xFF80
104 #define TLK110_ALFACTOR2_VAL 0x021C
105 #define TLK110_CFGPS_VAL 0x0000
106 #define TLK110_FTSPTXGAIN_VAL 0x6A88
107 #define TLK110_SWSCR3_VAL 0x0000
108 #define TLK110_SCFALLBACK_VAL 0xC11D
109 #define TLK110_PHYRCR_VAL 0x4000
111 #if defined(CONFIG_TLK110_WORKAROUND) || \
112 defined(CONFIG_TLK110_WORKAROUND_MODULE)
113 #define am335x_tlk110_phy_init()\
114 do { \
115 phy_register_fixup_for_uid(TLK110_PHY_ID,\
116 TLK110_PHY_MASK,\
117 am335x_tlk110_phy_fixup);\
118 } while (0);
119 #else
120 #define am335x_tlk110_phy_init() do { } while (0);
121 #endif
123 static const struct display_panel disp_panel = {
124 WVGA,
125 32,
126 32,
127 COLOR_ACTIVE,
128 };
130 /* LCD backlight platform Data */
131 #define AM335X_BACKLIGHT_MAX_BRIGHTNESS 100
132 #define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS 100
133 #define AM335X_PWM_PERIOD_NANO_SECONDS (1000000 * 10)
135 #define PWM_DEVICE_ID "ecap.0"
137 static struct platform_pwm_backlight_data am335x_backlight_data = {
138 .pwm_id = PWM_DEVICE_ID,
139 .ch = -1,
140 .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
141 .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
142 .pwm_period_ns = AM335X_PWM_PERIOD_NANO_SECONDS,
143 };
145 static struct lcd_ctrl_config lcd_cfg = {
146 &disp_panel,
147 .ac_bias = 255,
148 .ac_bias_intrpt = 0,
149 .dma_burst_sz = 16,
150 .bpp = 32,
151 .fdd = 0x80,
152 .tft_alt_mode = 0,
153 .stn_565_mode = 0,
154 .mono_8bit_mode = 0,
155 .invert_line_clock = 1,
156 .invert_frm_clock = 1,
157 .sync_edge = 0,
158 .sync_ctrl = 1,
159 .raster_order = 0,
160 };
162 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
163 .manu_name = "ThreeFive",
164 .controller_data = &lcd_cfg,
165 .type = "TFC_S9700RTWV35TR_01B",
166 };
168 #include "common.h"
170 /* TSc controller */
171 #include <linux/input/ti_tscadc.h>
172 #include <linux/lis3lv02d.h>
174 static struct resource tsc_resources[] = {
175 [0] = {
176 .start = AM33XX_TSC_BASE,
177 .end = AM33XX_TSC_BASE + SZ_8K - 1,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = AM33XX_IRQ_ADC_GEN,
182 .end = AM33XX_IRQ_ADC_GEN,
183 .flags = IORESOURCE_IRQ,
184 },
185 };
187 static struct tsc_data am335x_touchscreen_data = {
188 .wires = 4,
189 .x_plate_resistance = 200,
190 };
192 static struct platform_device tsc_device = {
193 .name = "tsc",
194 .id = -1,
195 .dev = {
196 .platform_data = &am335x_touchscreen_data,
197 },
198 .num_resources = ARRAY_SIZE(tsc_resources),
199 .resource = tsc_resources,
200 };
202 static u8 am335x_iis_serializer_direction1[] = {
203 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
204 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
205 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
206 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
207 };
209 static struct snd_platform_data am335x_evm_snd_data1 = {
210 .tx_dma_offset = 0x46400000, /* McASP1 */
211 .rx_dma_offset = 0x46400000,
212 .op_mode = DAVINCI_MCASP_IIS_MODE,
213 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
214 .tdm_slots = 2,
215 .serial_dir = am335x_iis_serializer_direction1,
216 .asp_chan_q = EVENTQ_2,
217 .version = MCASP_VERSION_3,
218 .txnumevt = 1,
219 .rxnumevt = 1,
220 };
222 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
223 {
224 .mmc = 1,
225 .caps = MMC_CAP_4_BIT_DATA,
226 .gpio_cd = GPIO_TO_PIN(0, 6),
227 .gpio_wp = GPIO_TO_PIN(3, 18),
228 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
229 },
230 {
231 .mmc = 0, /* will be set at runtime */
232 },
233 {
234 .mmc = 0, /* will be set at runtime */
235 },
236 {} /* Terminator */
237 };
240 #ifdef CONFIG_OMAP_MUX
241 static struct omap_board_mux board_mux[] __initdata = {
242 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
243 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
244 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
245 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
246 { .reg_offset = OMAP_MUX_TERMINATOR },
247 };
248 #else
249 #define board_mux NULL
250 #endif
252 /* module pin mux structure */
253 struct pinmux_config {
254 const char *string_name; /* signal name format */
255 int val; /* Options for the mux register value */
256 };
258 struct evm_dev_cfg {
259 void (*device_init)(int evm_id, int profile);
261 /*
262 * If the device is required on both baseboard & daughter board (ex i2c),
263 * specify DEV_ON_BASEBOARD
264 */
265 #define DEV_ON_BASEBOARD 0
266 #define DEV_ON_DGHTR_BRD 1
267 u32 device_on;
269 u32 profile; /* Profiles (0-7) in which the module is present */
270 };
272 /* AM335X - CPLD Register Offsets */
273 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
274 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
275 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
276 #define CPLD_CFG_REG 0x10 /* Configuration Register */
278 static struct i2c_client *cpld_client;
279 static u32 am335x_evm_id;
280 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
281 };
283 /*
284 * EVM Config held in On-Board eeprom device.
285 *
286 * Header Format
287 *
288 * Name Size Contents
289 * (Bytes)
290 *-------------------------------------------------------------
291 * Header 4 0xAA, 0x55, 0x33, 0xEE
292 *
293 * Board Name 8 Name for board in ASCII.
294 * example "A33515BB" = "AM335X
295 Low Cost EVM board"
296 *
297 * Version 4 Hardware version code for board in
298 * in ASCII. "1.0A" = rev.01.0A
299 *
300 * Serial Number 12 Serial number of the board. This is a 12
301 * character string which is WWYY4P16nnnn, where
302 * WW = 2 digit week of the year of production
303 * YY = 2 digit year of production
304 * nnnn = incrementing board number
305 *
306 * Configuration option 32 Codes(TBD) to show the configuration
307 * setup on this board.
308 *
309 * Available 32720 Available space for other non-volatile
310 * data.
311 */
312 struct am335x_evm_eeprom_config {
313 u32 header;
314 u8 name[8];
315 char version[4];
316 u8 serial[12];
317 u8 opt[32];
318 };
320 static struct am335x_evm_eeprom_config config;
321 static bool daughter_brd_detected;
323 #define GP_EVM_REV_IS_1_0 0x1
324 #define GP_EVM_REV_IS_1_1A 0x2
325 #define GP_EVM_REV_IS_UNKNOWN 0xFF
326 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
327 unsigned int gigabit_enable = 1;
329 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
330 #define EEPROM_NO_OF_MAC_ADDR 3
331 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
333 #define AM335X_EEPROM_HEADER 0xEE3355AA
335 /* current profile if exists else PROFILE_0 on error */
336 static u32 am335x_get_profile_selection(void)
337 {
338 int val = 0;
340 if (!cpld_client)
341 /* error checking is not done in func's calling this routine.
342 so return profile 0 on error */
343 return 0;
345 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
346 if (val < 0)
347 return 0; /* default to Profile 0 on Error */
348 else
349 return val & 0x7;
350 }
352 static struct pinmux_config haptics_pin_mux[] = {
353 {"gpmc_ad9.ehrpwm2B", OMAP_MUX_MODE4 |
354 AM33XX_PIN_OUTPUT},
355 {NULL, 0},
356 };
358 /* Module pin mux for LCDC */
359 static struct pinmux_config lcdc_pin_mux[] = {
360 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
361 | AM33XX_PULL_DISA},
362 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
363 | AM33XX_PULL_DISA},
364 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
365 | AM33XX_PULL_DISA},
366 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
367 | AM33XX_PULL_DISA},
368 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
369 | AM33XX_PULL_DISA},
370 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
371 | AM33XX_PULL_DISA},
372 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
373 | AM33XX_PULL_DISA},
374 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
375 | AM33XX_PULL_DISA},
376 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
377 | AM33XX_PULL_DISA},
378 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
379 | AM33XX_PULL_DISA},
380 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
381 | AM33XX_PULL_DISA},
382 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
383 | AM33XX_PULL_DISA},
384 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
385 | AM33XX_PULL_DISA},
386 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
387 | AM33XX_PULL_DISA},
388 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
389 | AM33XX_PULL_DISA},
390 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
391 | AM33XX_PULL_DISA},
392 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
393 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
394 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
395 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
396 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
397 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
398 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
399 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
400 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
401 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
402 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
403 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
404 {NULL, 0},
405 };
407 static struct pinmux_config tsc_pin_mux[] = {
408 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
409 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
410 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
411 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
412 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
413 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
414 {NULL, 0},
415 };
417 /* Pin mux for nand flash module */
418 static struct pinmux_config nand_pin_mux[] = {
419 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
420 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
421 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
422 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
423 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
424 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
425 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
426 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
427 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
428 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
429 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
430 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
431 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
432 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
433 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
434 {NULL, 0},
435 };
437 /* Module pin mux for SPI fash */
438 static struct pinmux_config spi0_pin_mux[] = {
439 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
440 | AM33XX_INPUT_EN},
441 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
442 | AM33XX_INPUT_EN},
443 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
444 | AM33XX_INPUT_EN},
445 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
446 | AM33XX_INPUT_EN},
447 {NULL, 0},
448 };
450 /* Module pin mux for SPI flash */
451 static struct pinmux_config spi1_pin_mux[] = {
452 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
453 | AM33XX_INPUT_EN},
454 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
455 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
456 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
457 | AM33XX_INPUT_EN},
458 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
459 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
460 {NULL, 0},
461 };
463 /* Module pin mux for rgmii1 */
464 static struct pinmux_config rgmii1_pin_mux[] = {
465 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
466 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
467 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
468 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
469 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
470 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
471 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
472 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
473 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
474 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
475 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
476 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
477 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
478 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
479 {NULL, 0},
480 };
482 /* Module pin mux for rgmii2 */
483 static struct pinmux_config rgmii2_pin_mux[] = {
484 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
485 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
486 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
487 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
488 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
489 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
490 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
491 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
492 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
493 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
494 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
495 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
496 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
497 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
498 {NULL, 0},
499 };
501 /* Module pin mux for mii1 */
502 static struct pinmux_config mii1_pin_mux[] = {
503 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
504 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
505 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
506 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
507 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
508 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
509 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
510 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
511 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
512 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
513 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
514 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
515 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
516 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
517 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
518 {NULL, 0},
519 };
521 /* Module pin mux for rmii1 */
522 static struct pinmux_config rmii1_pin_mux[] = {
523 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
524 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
525 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
526 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
527 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
528 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
529 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
530 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
531 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
532 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
533 {NULL, 0},
534 };
536 static struct pinmux_config i2c1_pin_mux[] = {
537 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
538 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
539 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
540 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
541 {NULL, 0},
542 };
544 /* Module pin mux for mcasp1 */
545 static struct pinmux_config mcasp1_pin_mux[] = {
546 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
547 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
548 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
549 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
550 AM33XX_PIN_INPUT_PULLDOWN},
551 {NULL, 0},
552 };
555 /* Module pin mux for mmc0 */
556 static struct pinmux_config mmc0_pin_mux[] = {
557 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
558 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
559 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
560 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
561 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
562 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
563 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
564 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
565 {NULL, 0},
566 };
568 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
569 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
570 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
571 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
572 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
573 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
574 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
575 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
576 {NULL, 0},
577 };
579 /* Module pin mux for mmc1 */
580 static struct pinmux_config mmc1_pin_mux[] = {
581 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
582 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
583 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
584 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
585 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
586 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
587 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
588 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
589 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
590 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
591 {"gpmc_csn0.gpio1_29", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
592 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
593 {NULL, 0},
594 };
596 /* Module pin mux for uart3 */
597 static struct pinmux_config uart3_pin_mux[] = {
598 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
599 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
600 {NULL, 0},
601 };
603 static struct pinmux_config d_can_gp_pin_mux[] = {
604 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
605 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
606 {NULL, 0},
607 };
609 static struct pinmux_config d_can_ia_pin_mux[] = {
610 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
611 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
612 {NULL, 0},
613 };
615 /* Module pin mux for uart2 */
616 static struct pinmux_config uart2_pin_mux[] = {
617 {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
618 AM33XX_PIN_INPUT_PULLUP},
619 {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
620 AM33XX_PULL_DISA |
621 AM33XX_SLEWCTRL_SLOW},
622 {NULL, 0},
623 };
626 /*
627 * @pin_mux - single module pin-mux structure which defines pin-mux
628 * details for all its pins.
629 */
630 static void setup_pin_mux(struct pinmux_config *pin_mux)
631 {
632 int i;
634 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
635 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
637 }
639 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
641 /* pinmux for keypad device */
642 static struct pinmux_config matrix_keypad_pin_mux[] = {
643 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
644 {"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
645 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
646 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
647 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
648 {NULL, 0},
649 };
651 /* Keys mapping */
652 static const uint32_t am335x_evm_matrix_keys[] = {
653 KEY(0, 0, KEY_MENU),
654 KEY(1, 0, KEY_BACK),
655 KEY(2, 0, KEY_LEFT),
657 KEY(0, 1, KEY_RIGHT),
658 KEY(1, 1, KEY_ENTER),
659 KEY(2, 1, KEY_DOWN),
660 };
662 const struct matrix_keymap_data am335x_evm_keymap_data = {
663 .keymap = am335x_evm_matrix_keys,
664 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
665 };
667 static const unsigned int am335x_evm_keypad_row_gpios[] = {
668 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
669 };
671 static const unsigned int am335x_evm_keypad_col_gpios[] = {
672 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
673 };
675 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
676 .keymap_data = &am335x_evm_keymap_data,
677 .row_gpios = am335x_evm_keypad_row_gpios,
678 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
679 .col_gpios = am335x_evm_keypad_col_gpios,
680 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
681 .active_low = false,
682 .debounce_ms = 5,
683 .col_scan_delay_us = 2,
684 };
686 static struct platform_device am335x_evm_keyboard = {
687 .name = "matrix-keypad",
688 .id = -1,
689 .dev = {
690 .platform_data = &am335x_evm_keypad_platform_data,
691 },
692 };
694 static void matrix_keypad_init(int evm_id, int profile)
695 {
696 int err;
698 setup_pin_mux(matrix_keypad_pin_mux);
699 err = platform_device_register(&am335x_evm_keyboard);
700 if (err) {
701 pr_err("failed to register matrix keypad (2x3) device\n");
702 }
703 }
706 /* pinmux for keypad device */
707 static struct pinmux_config volume_keys_pin_mux[] = {
708 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
709 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
710 {NULL, 0},
711 };
713 /* Configure GPIOs for Volume Keys */
714 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
715 {
716 .code = KEY_VOLUMEUP,
717 .gpio = GPIO_TO_PIN(0, 2),
718 .active_low = true,
719 .desc = "volume-up",
720 .type = EV_KEY,
721 .wakeup = 1,
722 },
723 {
724 .code = KEY_VOLUMEDOWN,
725 .gpio = GPIO_TO_PIN(0, 3),
726 .active_low = true,
727 .desc = "volume-down",
728 .type = EV_KEY,
729 .wakeup = 1,
730 },
731 };
733 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
734 .buttons = am335x_evm_volume_gpio_buttons,
735 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
736 };
738 static struct platform_device am335x_evm_volume_keys = {
739 .name = "gpio-keys",
740 .id = -1,
741 .dev = {
742 .platform_data = &am335x_evm_volume_gpio_key_info,
743 },
744 };
746 static void volume_keys_init(int evm_id, int profile)
747 {
748 int err;
750 setup_pin_mux(volume_keys_pin_mux);
751 err = platform_device_register(&am335x_evm_volume_keys);
752 if (err)
753 pr_err("failed to register matrix keypad (2x3) device\n");
754 }
756 /*
757 * @evm_id - evm id which needs to be configured
758 * @dev_cfg - single evm structure which includes
759 * all module inits, pin-mux defines
760 * @profile - if present, else PROFILE_NONE
761 * @dghtr_brd_flg - Whether Daughter board is present or not
762 */
763 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
764 int profile)
765 {
766 int i;
768 /*
769 * Only General Purpose & Industrial Auto Motro Control
770 * EVM has profiles. So check if this evm has profile.
771 * If not, ignore the profile comparison
772 */
774 /*
775 * If the device is on baseboard, directly configure it. Else (device on
776 * Daughter board), check if the daughter card is detected.
777 */
778 if (profile == PROFILE_NONE) {
779 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
780 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
781 dev_cfg->device_init(evm_id, profile);
782 else if (daughter_brd_detected == true)
783 dev_cfg->device_init(evm_id, profile);
784 }
785 } else {
786 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
787 if (dev_cfg->profile & profile) {
788 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
789 dev_cfg->device_init(evm_id, profile);
790 else if (daughter_brd_detected == true)
791 dev_cfg->device_init(evm_id, profile);
792 }
793 }
794 }
795 }
798 /* pinmux for usb0 drvvbus */
799 static struct pinmux_config usb0_pin_mux[] = {
800 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
801 {NULL, 0},
802 };
804 /* pinmux for usb1 drvvbus */
805 static struct pinmux_config usb1_pin_mux[] = {
806 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
807 {NULL, 0},
808 };
810 /* pinmux for profibus */
811 static struct pinmux_config profibus_pin_mux[] = {
812 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
813 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
814 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
815 {NULL, 0},
816 };
818 /* Module pin mux for eCAP0 */
819 static struct pinmux_config ecap0_pin_mux[] = {
820 {"ecap0_in_pwm0_out.ecap0_in_pwm0_out",
821 OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
822 {NULL, 0},
823 };
825 static int backlight_enable;
827 #define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
828 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
830 struct wl12xx_platform_data am335xevm_wlan_data = {
831 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
832 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
833 };
835 /* Module pin mux for wlan and bluetooth */
836 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
837 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
838 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
839 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
840 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
841 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
842 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
843 {NULL, 0},
844 };
846 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
847 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
848 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
849 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
850 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
851 {NULL, 0},
852 };
854 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
855 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
856 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
857 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
858 {NULL, 0},
859 };
861 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
862 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
863 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
864 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
865 {NULL, 0},
866 };
868 static void enable_ecap0(int evm_id, int profile)
869 {
870 backlight_enable = true;
871 }
873 /* Setup pwm-backlight */
874 static struct platform_device am335x_backlight = {
875 .name = "pwm-backlight",
876 .id = -1,
877 .dev = {
878 .platform_data = &am335x_backlight_data,
879 }
880 };
882 static int __init ecap0_init(void)
883 {
884 int status = 0;
886 if (backlight_enable) {
887 setup_pin_mux(ecap0_pin_mux);
888 platform_device_register(&am335x_backlight);
889 }
890 return status;
891 }
892 late_initcall(ecap0_init);
894 static int __init conf_disp_pll(int rate)
895 {
896 struct clk *disp_pll;
897 int ret = -EINVAL;
899 disp_pll = clk_get(NULL, "dpll_disp_ck");
900 if (IS_ERR(disp_pll)) {
901 pr_err("Cannot clk_get disp_pll\n");
902 goto out;
903 }
905 ret = clk_set_rate(disp_pll, rate);
906 clk_put(disp_pll);
907 out:
908 return ret;
909 }
911 static void lcdc_init(int evm_id, int profile)
912 {
914 setup_pin_mux(lcdc_pin_mux);
916 if (conf_disp_pll(300000000)) {
917 pr_info("Failed configure display PLL, not attempting to"
918 "register LCDC\n");
919 return;
920 }
922 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
923 pr_info("Failed to register LCDC device\n");
924 return;
925 }
927 static void tsc_init(int evm_id, int profile)
928 {
929 int err;
931 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
932 am335x_touchscreen_data.analog_input = 1;
933 pr_info("TSC connected to beta GP EVM\n");
934 } else {
935 am335x_touchscreen_data.analog_input = 0;
936 pr_info("TSC connected to alpha GP EVM\n");
937 }
938 setup_pin_mux(tsc_pin_mux);
939 err = platform_device_register(&tsc_device);
940 if (err)
941 pr_err("failed to register touchscreen device\n");
942 }
944 static void rgmii1_init(int evm_id, int profile)
945 {
946 setup_pin_mux(rgmii1_pin_mux);
947 return;
948 }
950 static void rgmii2_init(int evm_id, int profile)
951 {
952 setup_pin_mux(rgmii2_pin_mux);
953 return;
954 }
956 static void mii1_init(int evm_id, int profile)
957 {
958 setup_pin_mux(mii1_pin_mux);
959 return;
960 }
962 static void rmii1_init(int evm_id, int profile)
963 {
964 setup_pin_mux(rmii1_pin_mux);
965 return;
966 }
968 static void usb0_init(int evm_id, int profile)
969 {
970 setup_pin_mux(usb0_pin_mux);
971 return;
972 }
974 static void usb1_init(int evm_id, int profile)
975 {
976 setup_pin_mux(usb1_pin_mux);
977 return;
978 }
980 /* setup uart3 */
981 static void uart3_init(int evm_id, int profile)
982 {
983 setup_pin_mux(uart3_pin_mux);
984 return;
985 }
987 /* setup uart2 */
988 static void uart2_init(int evm_id, int profile)
989 {
990 setup_pin_mux(uart2_pin_mux);
991 return;
992 }
994 /* setup haptics */
995 #define HAPTICS_MAX_FREQ (250)
997 static void haptics_init(int evm_id, int profile)
998 {
999 setup_pin_mux(haptics_pin_mux);
1000 register_ehrpwm(HAPTICS_MAX_FREQ);
1001 return;
1002 }
1004 /* NAND partition information */
1005 static struct mtd_partition am335x_nand_partitions[] = {
1006 /* All the partition sizes are listed in terms of NAND block size */
1007 {
1008 .name = "SPL",
1009 .offset = 0, /* Offset = 0x0 */
1010 .size = SZ_128K,
1011 },
1012 {
1013 .name = "SPL.backup1",
1014 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
1015 .size = SZ_128K,
1016 },
1017 {
1018 .name = "SPL.backup2",
1019 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
1020 .size = SZ_128K,
1021 },
1022 {
1023 .name = "SPL.backup3",
1024 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
1025 .size = SZ_128K,
1026 },
1027 {
1028 .name = "U-Boot",
1029 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
1030 .size = 15 * SZ_128K,
1031 },
1032 {
1033 .name = "U-Boot Env",
1034 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
1035 .size = 1 * SZ_128K,
1036 },
1037 {
1038 .name = "Kernel",
1039 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
1040 .size = 40 * SZ_128K,
1041 },
1042 {
1043 .name = "File System",
1044 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
1045 .size = MTDPART_SIZ_FULL,
1046 },
1047 };
1049 /* SPI 0/1 Platform Data */
1050 /* SPI flash information */
1051 static struct mtd_partition am335x_spi_partitions[] = {
1052 /* All the partition sizes are listed in terms of erase size */
1053 {
1054 .name = "SPL",
1055 .offset = 0, /* Offset = 0x0 */
1056 .size = SZ_128K,
1057 },
1058 {
1059 .name = "U-Boot",
1060 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
1061 .size = 2 * SZ_128K,
1062 },
1063 {
1064 .name = "U-Boot Env",
1065 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
1066 .size = 2 * SZ_4K,
1067 },
1068 {
1069 .name = "Kernel",
1070 .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
1071 .size = 28 * SZ_128K,
1072 },
1073 {
1074 .name = "File System",
1075 .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
1076 .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
1077 }
1078 };
1080 static const struct flash_platform_data am335x_spi_flash = {
1081 .type = "w25q64",
1082 .name = "spi_flash",
1083 .parts = am335x_spi_partitions,
1084 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
1085 };
1087 /*
1088 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1089 * So setup Max speed to be less than that of Controller speed
1090 */
1091 static struct spi_board_info am335x_spi0_slave_info[] = {
1092 {
1093 .modalias = "m25p80",
1094 .platform_data = &am335x_spi_flash,
1095 .irq = -1,
1096 .max_speed_hz = 24000000,
1097 .bus_num = 1,
1098 .chip_select = 0,
1099 },
1100 };
1102 static struct spi_board_info am335x_spi1_slave_info[] = {
1103 {
1104 .modalias = "m25p80",
1105 .platform_data = &am335x_spi_flash,
1106 .irq = -1,
1107 .max_speed_hz = 12000000,
1108 .bus_num = 2,
1109 .chip_select = 0,
1110 },
1111 };
1113 static void evm_nand_init(int evm_id, int profile)
1114 {
1115 setup_pin_mux(nand_pin_mux);
1116 board_nand_init(am335x_nand_partitions,
1117 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1118 }
1120 /* TPS65217 voltage regulator support */
1122 /* 1.8V */
1123 static struct regulator_consumer_supply tps65217_dcdc1_consumers[] = {
1124 {
1125 .supply = "vdds_osc",
1126 },
1127 {
1128 .supply = "vdds_pll_ddr",
1129 },
1130 {
1131 .supply = "vdds_pll_mpu",
1132 },
1133 {
1134 .supply = "vdds_pll_core_lcd",
1135 },
1136 {
1137 .supply = "vdds_sram_mpu_bb",
1138 },
1139 {
1140 .supply = "vdds_sram_core_bg",
1141 },
1142 {
1143 .supply = "vdda_usb0_1p8v",
1144 },
1145 {
1146 .supply = "vdds_ddr",
1147 },
1148 {
1149 .supply = "vdds",
1150 },
1151 {
1152 .supply = "vdds_hvx_1p8v",
1153 },
1154 {
1155 .supply = "vdda_adc",
1156 },
1157 {
1158 .supply = "ddr2",
1159 },
1160 };
1162 /* 1.1V */
1163 static struct regulator_consumer_supply tps65217_dcdc2_consumers[] = {
1164 {
1165 .supply = "vdd_mpu",
1166 },
1167 };
1169 /* 1.1V */
1170 static struct regulator_consumer_supply tps65217_dcdc3_consumers[] = {
1171 {
1172 .supply = "vdd_core",
1173 },
1174 };
1176 /* 1.8V LDO */
1177 static struct regulator_consumer_supply tps65217_ldo1_consumers[] = {
1178 {
1179 .supply = "vdds_rtc",
1180 },
1181 };
1183 /* 3.3V LDO */
1184 static struct regulator_consumer_supply tps65217_ldo2_consumers[] = {
1185 {
1186 .supply = "vdds_any_pn",
1187 },
1188 };
1190 /* 3.3V LDO */
1191 static struct regulator_consumer_supply tps65217_ldo3_consumers[] = {
1192 {
1193 .supply = "vdds_hvx_ldo3_3p3v",
1194 },
1195 {
1196 .supply = "vdda_usb0_3p3v",
1197 },
1198 };
1200 /* 3.3V LDO */
1201 static struct regulator_consumer_supply tps65217_ldo4_consumers[] = {
1202 {
1203 .supply = "vdds_hvx_ldo4_3p3v",
1204 },
1205 };
1207 static struct regulator_init_data tps65217_regulator_data[] = {
1208 /* dcdc1 */
1209 {
1210 .constraints = {
1211 .min_uV = 900000,
1212 .max_uV = 1800000,
1213 .boot_on = 1,
1214 .always_on = 1,
1215 },
1216 .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc1_consumers),
1217 .consumer_supplies = tps65217_dcdc1_consumers,
1218 },
1220 /* dcdc2 */
1221 {
1222 .constraints = {
1223 .min_uV = 900000,
1224 .max_uV = 3300000,
1225 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1226 REGULATOR_CHANGE_STATUS),
1227 .boot_on = 1,
1228 .always_on = 1,
1229 },
1230 .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc2_consumers),
1231 .consumer_supplies = tps65217_dcdc2_consumers,
1232 },
1234 /* dcdc3 */
1235 {
1236 .constraints = {
1237 .min_uV = 900000,
1238 .max_uV = 1500000,
1239 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1240 REGULATOR_CHANGE_STATUS),
1241 .boot_on = 1,
1242 .always_on = 1,
1243 },
1244 .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc3_consumers),
1245 .consumer_supplies = tps65217_dcdc3_consumers,
1246 },
1248 /* ldo1 */
1249 {
1250 .constraints = {
1251 .min_uV = 1000000,
1252 .max_uV = 3300000,
1253 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1254 .boot_on = 1,
1255 .always_on = 1,
1256 },
1257 .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo1_consumers),
1258 .consumer_supplies = tps65217_ldo1_consumers,
1259 },
1261 /* ldo2 */
1262 {
1263 .constraints = {
1264 .min_uV = 900000,
1265 .max_uV = 3300000,
1266 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1267 REGULATOR_CHANGE_STATUS),
1268 .boot_on = 1,
1269 .always_on = 1,
1270 },
1271 .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo2_consumers),
1272 .consumer_supplies = tps65217_ldo2_consumers,
1273 },
1275 /* ldo3 */
1276 {
1277 .constraints = {
1278 .min_uV = 1800000,
1279 .max_uV = 3300000,
1280 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1281 REGULATOR_CHANGE_STATUS),
1282 .boot_on = 1,
1283 .always_on = 1,
1284 },
1285 .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo3_consumers),
1286 .consumer_supplies = tps65217_ldo3_consumers,
1287 },
1289 /* ldo4 */
1290 {
1291 .constraints = {
1292 .min_uV = 1800000,
1293 .max_uV = 3300000,
1294 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1295 REGULATOR_CHANGE_STATUS),
1296 .boot_on = 1,
1297 .always_on = 1,
1298 },
1299 .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo4_consumers),
1300 .consumer_supplies = tps65217_ldo4_consumers,
1301 },
1302 };
1304 static struct tps65217_board beaglebone_tps65217_info = {
1305 .tps65217_init_data = &tps65217_regulator_data[0],
1306 };
1308 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1309 .click_flags = LIS3_CLICK_SINGLE_X |
1310 LIS3_CLICK_SINGLE_Y |
1311 LIS3_CLICK_SINGLE_Z,
1312 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1313 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1314 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1315 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1316 .wakeup_thresh = 10,
1317 .click_thresh_x = 10,
1318 .click_thresh_y = 10,
1319 .click_thresh_z = 10,
1320 .g_range = 2,
1321 .st_min_limits[0] = 120,
1322 .st_min_limits[1] = 120,
1323 .st_min_limits[2] = 140,
1324 .st_max_limits[0] = 550,
1325 .st_max_limits[1] = 550,
1326 .st_max_limits[2] = 750,
1327 };
1329 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1330 {
1331 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1332 },
1333 {
1334 I2C_BOARD_INFO("lis331dlh", 0x18),
1335 .platform_data = &lis331dlh_pdata,
1336 },
1337 {
1338 I2C_BOARD_INFO("tsl2550", 0x39),
1339 },
1340 {
1341 I2C_BOARD_INFO("tmp275", 0x48),
1342 },
1343 };
1345 static void i2c1_init(int evm_id, int profile)
1346 {
1347 setup_pin_mux(i2c1_pin_mux);
1348 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1349 ARRAY_SIZE(am335x_i2c_boardinfo1));
1350 return;
1351 }
1353 /* Setup McASP 1 */
1354 static void mcasp1_init(int evm_id, int profile)
1355 {
1356 /* Configure McASP */
1357 setup_pin_mux(mcasp1_pin_mux);
1358 am335x_register_mcasp1(&am335x_evm_snd_data1);
1359 return;
1360 }
1362 static void mmc1_init(int evm_id, int profile)
1363 {
1364 setup_pin_mux(mmc1_pin_mux);
1366 am335x_mmc[1].mmc = 2;
1367 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1368 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1369 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1370 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1372 /* mmc will be initialized when mmc0_init is called */
1373 return;
1374 }
1376 static void mmc2_wl12xx_init(int evm_id, int profile)
1377 {
1378 setup_pin_mux(mmc2_wl12xx_pin_mux);
1380 am335x_mmc[1].mmc = 3;
1381 am335x_mmc[1].name = "wl1271";
1382 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1383 | MMC_PM_KEEP_POWER;
1384 am335x_mmc[1].nonremovable = true;
1385 am335x_mmc[1].gpio_cd = -EINVAL;
1386 am335x_mmc[1].gpio_wp = -EINVAL;
1387 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1389 /* mmc will be initialized when mmc0_init is called */
1390 return;
1391 }
1393 static void uart1_wl12xx_init(int evm_id, int profile)
1394 {
1395 setup_pin_mux(uart1_wl12xx_pin_mux);
1396 }
1398 static void wl12xx_bluetooth_enable(void)
1399 {
1400 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1401 "bt_en\n");
1402 if (status < 0)
1403 pr_err("Failed to request gpio for bt_enable");
1405 pr_info("Configure Bluetooth Enable pin...\n");
1406 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1407 }
1409 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1410 {
1411 if (on) {
1412 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1413 mdelay(70);
1414 }
1415 else
1416 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1418 return 0;
1419 }
1421 static void wl12xx_init(int evm_id, int profile)
1422 {
1423 struct device *dev;
1424 struct omap_mmc_platform_data *pdata;
1425 int ret;
1427 /* Register WLAN and BT enable pins based on the evm board revision */
1428 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1429 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1430 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1431 }
1432 else {
1433 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1434 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1435 }
1437 wl12xx_bluetooth_enable();
1439 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1440 pr_err("error setting wl12xx data\n");
1442 dev = am335x_mmc[1].dev;
1443 if (!dev) {
1444 pr_err("wl12xx mmc device initialization failed\n");
1445 goto out;
1446 }
1448 pdata = dev->platform_data;
1449 if (!pdata) {
1450 pr_err("Platfrom data of wl12xx device not set\n");
1451 goto out;
1452 }
1454 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1455 GPIOF_OUT_INIT_LOW, "wlan_en");
1456 if (ret) {
1457 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1458 goto out;
1459 }
1461 if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1462 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1463 else
1464 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1466 pdata->slots[0].set_power = wl12xx_set_power;
1467 out:
1468 return;
1469 }
1471 static void d_can_init(int evm_id, int profile)
1472 {
1473 switch (evm_id) {
1474 case IND_AUT_MTR_EVM:
1475 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1476 setup_pin_mux(d_can_ia_pin_mux);
1477 /* Instance Zero */
1478 am33xx_d_can_init(0);
1479 }
1480 break;
1481 case GEN_PURP_EVM:
1482 if (profile == PROFILE_1) {
1483 setup_pin_mux(d_can_gp_pin_mux);
1484 /* Instance One */
1485 am33xx_d_can_init(1);
1486 }
1487 break;
1488 default:
1489 break;
1490 }
1491 }
1493 static void mmc0_init(int evm_id, int profile)
1494 {
1495 setup_pin_mux(mmc0_pin_mux);
1497 omap2_hsmmc_init(am335x_mmc);
1498 return;
1499 }
1501 static struct i2c_board_info tps65217_i2c_boardinfo[] = {
1502 {
1503 I2C_BOARD_INFO("tps65217", TPS65217_I2C_ID),
1504 .platform_data = &beaglebone_tps65217_info,
1505 },
1506 };
1508 static void tps65217_init(int evm_id, int profile)
1509 {
1510 struct i2c_adapter *adapter;
1511 struct i2c_client *client;
1513 /* I2C1 adapter request */
1514 adapter = i2c_get_adapter(1);
1515 if (!adapter) {
1516 pr_err("failed to get adapter i2c1\n");
1517 return;
1518 }
1520 client = i2c_new_device(adapter, tps65217_i2c_boardinfo);
1521 if (!client)
1522 pr_err("failed to register tps65217 to i2c1\n");
1524 i2c_put_adapter(adapter);
1525 }
1527 static void mmc0_no_cd_init(int evm_id, int profile)
1528 {
1529 setup_pin_mux(mmc0_no_cd_pin_mux);
1531 omap2_hsmmc_init(am335x_mmc);
1532 return;
1533 }
1536 /* setup spi0 */
1537 static void spi0_init(int evm_id, int profile)
1538 {
1539 setup_pin_mux(spi0_pin_mux);
1540 spi_register_board_info(am335x_spi0_slave_info,
1541 ARRAY_SIZE(am335x_spi0_slave_info));
1542 return;
1543 }
1545 /* setup spi1 */
1546 static void spi1_init(int evm_id, int profile)
1547 {
1548 setup_pin_mux(spi1_pin_mux);
1549 spi_register_board_info(am335x_spi1_slave_info,
1550 ARRAY_SIZE(am335x_spi1_slave_info));
1551 return;
1552 }
1555 static int beaglebone_phy_fixup(struct phy_device *phydev)
1556 {
1557 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1558 SUPPORTED_100baseT_Full);
1560 return 0;
1561 }
1563 #if defined(CONFIG_TLK110_WORKAROUND) || \
1564 defined(CONFIG_TLK110_WORKAROUND_MODULE)
1565 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1566 {
1567 unsigned int val;
1569 /* This is done as a workaround to support TLK110 rev1.0 phy */
1570 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1571 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1573 val = phy_read(phydev, TLK110_LPFHPF_REG);
1574 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1576 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1577 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1579 val = phy_read(phydev, TLK110_VRCR_REG);
1580 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1582 val = phy_read(phydev, TLK110_SETFFE_REG);
1583 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1585 val = phy_read(phydev, TLK110_FTSP_REG);
1586 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1588 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1589 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1591 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1592 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1594 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1595 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1597 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1598 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1600 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1601 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1603 val = phy_read(phydev, TLK110_CFGPS_REG);
1604 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1606 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1607 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1609 val = phy_read(phydev, TLK110_SWSCR3_REG);
1610 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1612 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1613 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1615 val = phy_read(phydev, TLK110_PHYRCR_REG);
1616 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1618 return 0;
1619 }
1620 #endif
1622 static void profibus_init(int evm_id, int profile)
1623 {
1624 setup_pin_mux(profibus_pin_mux);
1625 return;
1626 }
1628 /* Low-Cost EVM */
1629 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1630 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1631 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1632 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1633 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1634 {NULL, 0, 0},
1635 };
1637 /* General Purpose EVM */
1638 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1639 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1640 PROFILE_2 | PROFILE_7) },
1641 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1642 PROFILE_2 | PROFILE_7) },
1643 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1644 PROFILE_2 | PROFILE_7) },
1645 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1646 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1647 PROFILE_4 | PROFILE_6) },
1648 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1649 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1650 {evm_nand_init, DEV_ON_DGHTR_BRD,
1651 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1652 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1653 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1654 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1655 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1656 PROFILE_5)},
1657 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1658 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1659 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1660 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1661 PROFILE_5)},
1662 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1663 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
1664 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1665 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1666 {uart2_init, DEV_ON_DGHTR_BRD, PROFILE_3},
1667 {haptics_init, DEV_ON_DGHTR_BRD, (PROFILE_4)},
1668 {NULL, 0, 0},
1669 };
1671 /* Industrial Auto Motor Control EVM */
1672 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1673 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1674 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1675 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1676 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1677 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1678 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1679 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1680 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1681 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1682 {NULL, 0, 0},
1683 };
1685 /* IP-Phone EVM */
1686 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1687 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1688 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1689 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1690 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1691 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1692 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1693 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1694 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1695 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1696 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1697 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1698 {NULL, 0, 0},
1699 };
1701 /* Beaglebone < Rev A3 */
1702 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1703 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1704 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1705 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1706 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1707 {NULL, 0, 0},
1708 };
1710 /* Beaglebone Rev A3 and after */
1711 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1712 {tps65217_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1713 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1714 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1715 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1716 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1717 {NULL, 0, 0},
1718 };
1720 static void setup_low_cost_evm(void)
1721 {
1722 pr_info("The board is a AM335x Low Cost EVM.\n");
1724 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1725 }
1727 static void setup_general_purpose_evm(void)
1728 {
1729 u32 prof_sel = am335x_get_profile_selection();
1730 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1732 if (!strncmp("1.1A", config.version, 4)) {
1733 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1734 } else if (!strncmp("1.0", config.version, 3)) {
1735 gp_evm_revision = GP_EVM_REV_IS_1_0;
1736 } else {
1737 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1738 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1739 }
1741 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1742 gigabit_enable = 0;
1743 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1744 gigabit_enable = 1;
1746 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1747 }
1749 static void setup_ind_auto_motor_ctrl_evm(void)
1750 {
1751 u32 prof_sel = am335x_get_profile_selection();
1753 pr_info("The board is an industrial automation EVM in profile %d\n",
1754 prof_sel);
1756 /* Only Profile 0 is supported */
1757 if ((1L << prof_sel) != PROFILE_0) {
1758 pr_err("AM335X: Only Profile 0 is supported\n");
1759 pr_err("Assuming profile 0 & continuing\n");
1760 prof_sel = PROFILE_0;
1761 }
1763 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1764 PROFILE_0);
1766 /* Fillup global evmid */
1767 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1769 /* Initialize TLK110 PHY registers for phy version 1.0 */
1770 am335x_tlk110_phy_init();
1773 }
1775 static void setup_ip_phone_evm(void)
1776 {
1777 pr_info("The board is an IP phone EVM\n");
1779 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1780 }
1782 /* BeagleBone < Rev A3 */
1783 static void setup_beaglebone_old(void)
1784 {
1785 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1787 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1788 am335x_mmc[0].gpio_wp = -EINVAL;
1790 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1792 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1793 beaglebone_phy_fixup);
1795 /* Fill up global evmid */
1796 am33xx_evmid_fillup(BEAGLE_BONE_OLD);
1797 }
1799 /* BeagleBone after Rev A3 */
1800 static void setup_beaglebone(void)
1801 {
1802 pr_info("The board is a AM335x Beaglebone.\n");
1804 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1805 am335x_mmc[0].gpio_wp = -EINVAL;
1807 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1809 /* TPS65217 regulator has full constraints */
1810 regulator_has_full_constraints();
1812 /* Fill up global evmid */
1813 am33xx_evmid_fillup(BEAGLE_BONE_A3);
1814 }
1817 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1818 {
1819 u8 tmp;
1820 int ret;
1822 /*
1823 * try reading a byte from the EEPROM to see if it is
1824 * present. We could read a lot more, but that would
1825 * just slow the boot process and we have all the information
1826 * we need from the EEPROM on the base board anyway.
1827 */
1828 ret = m->read(m, &tmp, 0, sizeof(u8));
1829 if (ret == sizeof(u8)) {
1830 pr_info("Detected a daughter card on AM335x EVM..");
1831 daughter_brd_detected = true;
1832 } else {
1833 pr_info("No daughter card found\n");
1834 daughter_brd_detected = false;
1835 }
1836 }
1838 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1839 {
1840 int ret;
1841 char tmp[10];
1843 /* 1st get the MAC address from EEPROM */
1844 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1845 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1847 if (ret != sizeof(am335x_mac_addr)) {
1848 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1849 return;
1850 }
1852 /* Fillup global mac id */
1853 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1854 &am335x_mac_addr[1][0]);
1856 /* get board specific data */
1857 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1858 if (ret != sizeof(config)) {
1859 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1860 return;
1861 }
1863 if (config.header != AM335X_EEPROM_HEADER) {
1864 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1865 config.header, AM335X_EEPROM_HEADER);
1866 goto out;
1867 }
1869 if (strncmp("A335", config.name, 4)) {
1870 pr_err("Board %s doesn't look like an AM335x board\n",
1871 config.name);
1872 goto out;
1873 }
1875 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1876 pr_info("Board name: %s\n", tmp);
1877 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1878 pr_info("Board version: %s\n", tmp);
1880 if (!strncmp("A335BONE", config.name, 8)) {
1881 daughter_brd_detected = false;
1882 if(!strncmp("00A1", config.version, 4) ||
1883 !strncmp("00A2", config.version, 4))
1884 setup_beaglebone_old();
1885 else
1886 setup_beaglebone();
1887 } else {
1888 /* only 6 characters of options string used for now */
1889 snprintf(tmp, 7, "%s", config.opt);
1890 pr_info("SKU: %s\n", tmp);
1892 if (!strncmp("SKU#00", config.opt, 6))
1893 setup_low_cost_evm();
1894 else if (!strncmp("SKU#01", config.opt, 6))
1895 setup_general_purpose_evm();
1896 else if (!strncmp("SKU#02", config.opt, 6))
1897 setup_ind_auto_motor_ctrl_evm();
1898 else if (!strncmp("SKU#03", config.opt, 6))
1899 setup_ip_phone_evm();
1900 else
1901 goto out;
1902 }
1903 /* Initialize cpsw after board detection is completed as board
1904 * information is required for configuring phy address and hence
1905 * should be call only after board detection
1906 */
1907 am33xx_cpsw_init(gigabit_enable);
1909 return;
1910 out:
1911 /*
1912 * If the EEPROM hasn't been programed or an incorrect header
1913 * or board name are read, assume this is an old beaglebone board
1914 * (< Rev A3)
1915 */
1916 pr_err("Could not detect any board, falling back to: "
1917 "Beaglebone (< Rev A3) with no daughter card connected\n");
1918 daughter_brd_detected = false;
1919 setup_beaglebone_old();
1921 /* Initialize cpsw after board detection is completed as board
1922 * information is required for configuring phy address and hence
1923 * should be call only after board detection
1924 */
1926 am33xx_cpsw_init(gigabit_enable);
1927 }
1929 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1930 .byte_len = (256*1024) / 8,
1931 .page_size = 64,
1932 .flags = AT24_FLAG_ADDR16,
1933 .setup = am335x_setup_daughter_board,
1934 .context = (void *)NULL,
1935 };
1937 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1938 .byte_len = (256*1024) / 8,
1939 .page_size = 64,
1940 .flags = AT24_FLAG_ADDR16,
1941 .setup = am335x_evm_setup,
1942 .context = (void *)NULL,
1943 };
1945 static struct regulator_init_data am335x_dummy = {
1946 .constraints.always_on = true,
1947 };
1949 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
1950 REGULATOR_SUPPLY("vdd_mpu", NULL),
1951 };
1953 static struct regulator_init_data am335x_vdd1 = {
1954 .constraints = {
1955 .min_uV = 600000,
1956 .max_uV = 1500000,
1957 .valid_modes_mask = REGULATOR_MODE_NORMAL,
1958 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
1959 .always_on = 1,
1960 },
1961 .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply),
1962 .consumer_supplies = am335x_vdd1_supply,
1963 };
1965 static struct tps65910_board am335x_tps65910_info = {
1966 .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy,
1967 .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy,
1968 .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1,
1969 .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy,
1970 .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy,
1971 .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy,
1972 .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy,
1973 .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy,
1974 .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy,
1975 .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy,
1976 .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy,
1977 .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy,
1978 .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy,
1979 };
1981 /*
1982 * Daughter board Detection.
1983 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1984 * machine init, starting from daughter board and ending with baseboard.
1985 * Assumptions :
1986 * 1. probe for i2c devices are called in the order they are included in
1987 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
1988 * eeprom probe is called last.
1989 */
1990 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1991 {
1992 /* Daughter Board EEPROM */
1993 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1994 .platform_data = &am335x_daughter_board_eeprom_info,
1995 },
1996 {
1997 /* Baseboard board EEPROM */
1998 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1999 .platform_data = &am335x_baseboard_eeprom_info,
2000 },
2001 {
2002 I2C_BOARD_INFO("cpld_reg", 0x35),
2003 },
2004 {
2005 I2C_BOARD_INFO("tlc59108", 0x40),
2006 },
2007 {
2008 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
2009 .platform_data = &am335x_tps65910_info,
2010 },
2011 };
2013 static struct omap_musb_board_data musb_board_data = {
2014 .interface_type = MUSB_INTERFACE_ULPI,
2015 /*
2016 * mode[0:3] = USB0PORT's mode
2017 * mode[4:7] = USB1PORT's mode
2018 * AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
2019 */
2020 .mode = (MUSB_HOST << 4) | MUSB_OTG,
2021 .power = 500,
2022 .instances = 1,
2023 };
2025 static int cpld_reg_probe(struct i2c_client *client,
2026 const struct i2c_device_id *id)
2027 {
2028 cpld_client = client;
2029 return 0;
2030 }
2032 static int __devexit cpld_reg_remove(struct i2c_client *client)
2033 {
2034 cpld_client = NULL;
2035 return 0;
2036 }
2038 static const struct i2c_device_id cpld_reg_id[] = {
2039 { "cpld_reg", 0 },
2040 { }
2041 };
2043 static struct i2c_driver cpld_reg_driver = {
2044 .driver = {
2045 .name = "cpld_reg",
2046 },
2047 .probe = cpld_reg_probe,
2048 .remove = cpld_reg_remove,
2049 .id_table = cpld_reg_id,
2050 };
2052 static void evm_init_cpld(void)
2053 {
2054 i2c_add_driver(&cpld_reg_driver);
2055 }
2057 static void __init am335x_evm_i2c_init(void)
2058 {
2059 /* Initially assume Low Cost EVM Config */
2060 am335x_evm_id = LOW_COST_EVM;
2062 evm_init_cpld();
2064 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
2065 ARRAY_SIZE(am335x_i2c_boardinfo));
2066 }
2068 static struct resource am335x_rtc_resources[] = {
2069 {
2070 .start = AM33XX_RTC_BASE,
2071 .end = AM33XX_RTC_BASE + SZ_4K - 1,
2072 .flags = IORESOURCE_MEM,
2073 },
2074 { /* timer irq */
2075 .start = AM33XX_IRQ_RTC_TIMER,
2076 .end = AM33XX_IRQ_RTC_TIMER,
2077 .flags = IORESOURCE_IRQ,
2078 },
2079 { /* alarm irq */
2080 .start = AM33XX_IRQ_RTC_ALARM,
2081 .end = AM33XX_IRQ_RTC_ALARM,
2082 .flags = IORESOURCE_IRQ,
2083 },
2084 };
2086 static struct platform_device am335x_rtc_device = {
2087 .name = "omap_rtc",
2088 .id = -1,
2089 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
2090 .resource = am335x_rtc_resources,
2091 };
2093 static int am335x_rtc_init(void)
2094 {
2095 void __iomem *base;
2096 struct clk *clk;
2098 clk = clk_get(NULL, "rtc_fck");
2099 if (IS_ERR(clk)) {
2100 pr_err("rtc : Failed to get RTC clock\n");
2101 return -1;
2102 }
2104 if (clk_enable(clk)) {
2105 pr_err("rtc: Clock Enable Failed\n");
2106 return -1;
2107 }
2109 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
2111 if (WARN_ON(!base))
2112 return -ENOMEM;
2114 /* Unlock the rtc's registers */
2115 __raw_writel(0x83e70b13, base + 0x6c);
2116 __raw_writel(0x95a4f1e0, base + 0x70);
2118 /*
2119 * Enable the 32K OSc
2120 * TODO: Need a better way to handle this
2121 * Since we want the clock to be running before mmc init
2122 * we need to do it before the rtc probe happens
2123 */
2124 __raw_writel(0x48, base + 0x54);
2126 iounmap(base);
2128 return platform_device_register(&am335x_rtc_device);
2129 }
2131 /* Enable clkout2 */
2132 static struct pinmux_config clkout2_pin_mux[] = {
2133 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
2134 {NULL, 0},
2135 };
2137 static void __init clkout2_enable(void)
2138 {
2139 struct clk *ck_32;
2141 ck_32 = clk_get(NULL, "clkout2_ck");
2142 if (IS_ERR(ck_32)) {
2143 pr_err("Cannot clk_get ck_32\n");
2144 return;
2145 }
2147 clk_enable(ck_32);
2149 setup_pin_mux(clkout2_pin_mux);
2150 }
2152 void __iomem *am33xx_emif_base;
2154 void __iomem * __init am33xx_get_mem_ctlr(void)
2155 {
2157 am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
2159 if (!am33xx_emif_base)
2160 pr_warning("%s: Unable to map DDR2 controller", __func__);
2162 return am33xx_emif_base;
2163 }
2165 void __iomem *am33xx_get_ram_base(void)
2166 {
2167 return am33xx_emif_base;
2168 }
2170 static struct resource am33xx_cpuidle_resources[] = {
2171 {
2172 .start = AM33XX_EMIF0_BASE,
2173 .end = AM33XX_EMIF0_BASE + SZ_32K - 1,
2174 .flags = IORESOURCE_MEM,
2175 },
2176 };
2178 /* AM33XX devices support DDR2 power down */
2179 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
2180 .ddr2_pdown = 1,
2181 };
2183 static struct platform_device am33xx_cpuidle_device = {
2184 .name = "cpuidle-am33xx",
2185 .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
2186 .resource = am33xx_cpuidle_resources,
2187 .dev = {
2188 .platform_data = &am33xx_cpuidle_pdata,
2189 },
2190 };
2192 static void __init am33xx_cpuidle_init(void)
2193 {
2194 int ret;
2196 am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
2198 ret = platform_device_register(&am33xx_cpuidle_device);
2200 if (ret)
2201 pr_warning("AM33XX cpuidle registration failed\n");
2203 }
2205 static void __init am335x_evm_init(void)
2206 {
2207 am33xx_cpuidle_init();
2208 am33xx_mux_init(board_mux);
2209 omap_serial_init();
2210 am335x_rtc_init();
2211 clkout2_enable();
2212 am335x_evm_i2c_init();
2213 omap_sdrc_init(NULL, NULL);
2214 usb_musb_init(&musb_board_data);
2215 omap_board_config = am335x_evm_config;
2216 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
2217 /* Create an alias for icss clock */
2218 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
2219 pr_warn("failed to create an alias: icss_uart_gclk --> pruss\n");
2220 if (clk_add_alias("pruss", NULL, "icss_fck", NULL))
2221 pr_warn("failed to create an alias: icss_fck --> pruss\n");
2222 /* Create an alias for gfx/sgx clock */
2223 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
2224 pr_warn("failed to create an alias: gfx_fclk --> sgx_ck\n");
2225 }
2227 static void __init am335x_evm_map_io(void)
2228 {
2229 omap2_set_globals_am33xx();
2230 omapam33xx_map_common_io();
2231 }
2233 MACHINE_START(AM335XEVM, "am335xevm")
2234 /* Maintainer: Texas Instruments */
2235 .atag_offset = 0x100,
2236 .map_io = am335x_evm_map_io,
2237 .init_early = am33xx_init_early,
2238 .init_irq = ti81xx_init_irq,
2239 .handle_irq = omap3_intc_handle_irq,
2240 .timer = &omap3_am33xx_timer,
2241 .init_machine = am335x_evm_init,
2242 MACHINE_END
2244 MACHINE_START(AM335XIAEVM, "am335xiaevm")
2245 /* Maintainer: Texas Instruments */
2246 .atag_offset = 0x100,
2247 .map_io = am335x_evm_map_io,
2248 .init_irq = ti81xx_init_irq,
2249 .init_early = am33xx_init_early,
2250 .timer = &omap3_am33xx_timer,
2251 .init_machine = am335x_evm_init,
2252 MACHINE_END