588917333ca3ea090a1175aa15f15c4fdb88542b
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / board-am335xevm.c
1 /*
2  * Code for AM335X EVM.
3  *
4  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
36 /* LCD controller is similar to DA850 */
37 #include <video/da8xx-fb.h>
39 #include <mach/hardware.h>
40 #include <mach/board-am335xevm.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/map.h>
45 #include <asm/hardware/asp.h>
47 #include <plat/irqs.h>
48 #include <plat/board.h>
49 #include <plat/common.h>
50 #include <plat/lcdc.h>
51 #include <plat/usb.h>
52 #include <plat/mmc.h>
54 #include "board-flash.h"
55 #include "cpuidle33xx.h"
56 #include "mux.h"
57 #include "devices.h"
58 #include "hsmmc.h"
60 /* Convert GPIO signal to GPIO pin number */
61 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
63 /* TLK PHY IDs */
64 #define TLK110_PHY_ID           0x2000A201
65 #define TLK110_PHY_MASK         0xfffffff0
67 /* BBB PHY IDs */
68 #define BBB_PHY_ID              0x7c0f1
69 #define BBB_PHY_MASK            0xfffffffe
71 /* TLK110 PHY register offsets */
72 #define TLK110_COARSEGAIN_REG   0x00A3
73 #define TLK110_LPFHPF_REG       0x00AC
74 #define TLK110_SPAREANALOG_REG  0x00B9
75 #define TLK110_VRCR_REG         0x00D0
76 #define TLK110_SETFFE_REG       0x0107
77 #define TLK110_FTSP_REG         0x0154
78 #define TLK110_ALFATPIDL_REG    0x002A
79 #define TLK110_PSCOEF21_REG     0x0096
80 #define TLK110_PSCOEF3_REG      0x0097
81 #define TLK110_ALFAFACTOR1_REG  0x002C
82 #define TLK110_ALFAFACTOR2_REG  0x0023
83 #define TLK110_CFGPS_REG        0x0095
84 #define TLK110_FTSPTXGAIN_REG   0x0150
85 #define TLK110_SWSCR3_REG       0x000B
86 #define TLK110_SCFALLBACK_REG   0x0040
87 #define TLK110_PHYRCR_REG       0x001F
89 /* TLK110 register writes values */
90 #define TLK110_COARSEGAIN_VAL   0x0000
91 #define TLK110_LPFHPF_VAL       0x8000
92 #define TLK110_SPANALOG_VAL     0x0000
93 #define TLK110_VRCR_VAL         0x0008
94 #define TLK110_SETFFE_VAL       0x0605
95 #define TLK110_FTSP_VAL         0x0255
96 #define TLK110_ALFATPIDL_VAL    0x7998
97 #define TLK110_PSCOEF21_VAL     0x3A20
98 #define TLK110_PSCOEF3_VAL      0x003F
99 #define TLK110_ALFACTOR1_VAL    0xFF80
100 #define TLK110_ALFACTOR2_VAL    0x021C
101 #define TLK110_CFGPS_VAL        0x0000
102 #define TLK110_FTSPTXGAIN_VAL   0x6A88
103 #define TLK110_SWSCR3_VAL       0x0000
104 #define TLK110_SCFALLBACK_VAL   0xC11D
105 #define TLK110_PHYRCR_VAL       0x4000
107 #ifdef CONFIG_TLK110_WORKAROUND
108 #define am335x_tlk110_phy_init()\
109         do {    \
110                 phy_register_fixup_for_uid(TLK110_PHY_ID,\
111                                         TLK110_PHY_MASK,\
112                                         am335x_tlk110_phy_fixup);\
113         } while (0);
114 #else
115 #define am335x_tlk110_phy_init() do { } while (0);
116 #endif
118 static const struct display_panel disp_panel = {
119         WVGA,
120         32,
121         32,
122         COLOR_ACTIVE,
123 };
125 static struct lcd_ctrl_config lcd_cfg = {
126         &disp_panel,
127         .ac_bias                = 255,
128         .ac_bias_intrpt         = 0,
129         .dma_burst_sz           = 16,
130         .bpp                    = 32,
131         .fdd                    = 0x80,
132         .tft_alt_mode           = 0,
133         .stn_565_mode           = 0,
134         .mono_8bit_mode         = 0,
135         .invert_line_clock      = 1,
136         .invert_frm_clock       = 1,
137         .sync_edge              = 0,
138         .sync_ctrl              = 1,
139         .raster_order           = 0,
140 };
142 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
143         .manu_name              = "ThreeFive",
144         .controller_data        = &lcd_cfg,
145         .type                   = "TFC_S9700RTWV35TR_01B",
146 };
148 #include "common.h"
150 /* TSc controller */
151 #include <linux/input/ti_tscadc.h>
152 #include <linux/lis3lv02d.h>
154 static struct resource tsc_resources[]  = {
155         [0] = {
156                 .start  = AM33XX_TSC_BASE,
157                 .end    = AM33XX_TSC_BASE + SZ_8K - 1,
158                 .flags  = IORESOURCE_MEM,
159         },
160         [1] = {
161                 .start  = AM33XX_IRQ_ADC_GEN,
162                 .end    = AM33XX_IRQ_ADC_GEN,
163                 .flags  = IORESOURCE_IRQ,
164         },
165 };
167 static struct tsc_data am335x_touchscreen_data  = {
168         .wires  = 4,
169         .x_plate_resistance = 200,
170 };
172 static struct platform_device tsc_device = {
173         .name   = "tsc",
174         .id     = -1,
175         .dev    = {
176                         .platform_data  = &am335x_touchscreen_data,
177         },
178         .num_resources  = ARRAY_SIZE(tsc_resources),
179         .resource       = tsc_resources,
180 };
182 static u8 am335x_iis_serializer_direction1[] = {
183         INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,        RX_MODE,
184         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
185         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
186         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
187 };
189 static struct snd_platform_data am335x_evm_snd_data1 = {
190         .tx_dma_offset  = 0x46400000,   /* McASP1 */
191         .rx_dma_offset  = 0x46400000,
192         .op_mode        = DAVINCI_MCASP_IIS_MODE,
193         .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
194         .tdm_slots      = 2,
195         .serial_dir     = am335x_iis_serializer_direction1,
196         .asp_chan_q     = EVENTQ_2,
197         .version        = MCASP_VERSION_3,
198         .txnumevt       = 1,
199         .rxnumevt       = 1,
200 };
202 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
203         {
204                 .mmc            = 1,
205                 .caps           = MMC_CAP_4_BIT_DATA,
206                 .gpio_cd        = GPIO_TO_PIN(0, 6),
207                 .gpio_wp        = GPIO_TO_PIN(3, 18),
208                 .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
209         },
210         {
211                 .mmc            = 0,    /* will be set at runtime */
212         },
213         {
214                 .mmc            = 0,    /* will be set at runtime */
215         },
216         {}      /* Terminator */
217 };
220 #ifdef CONFIG_OMAP_MUX
221 static struct omap_board_mux board_mux[] __initdata = {
222         AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
223                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
224         AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
225                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
226         { .reg_offset = OMAP_MUX_TERMINATOR },
227 };
228 #else
229 #define board_mux       NULL
230 #endif
232 /* module pin mux structure */
233 struct pinmux_config {
234         const char *string_name; /* signal name format */
235         int val; /* Options for the mux register value */
236 };
238 struct evm_dev_cfg {
239         void (*device_init)(int evm_id, int profile);
241 /*
242 * If the device is required on both baseboard & daughter board (ex i2c),
243 * specify DEV_ON_BASEBOARD
244 */
245 #define DEV_ON_BASEBOARD        0
246 #define DEV_ON_DGHTR_BRD        1
247         u32 device_on;
249         u32 profile;    /* Profiles (0-7) in which the module is present */
250 };
252 /* AM335X - CPLD Register Offsets */
253 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
254 #define CPLD_DEVICE_ID  0x04 /* CPLD identification */
255 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
256 #define CPLD_CFG_REG    0x10 /* Configuration Register */
258 static struct i2c_client *cpld_client;
259 static u32 am335x_evm_id;
260 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
261 };
263 /*
264 * EVM Config held in On-Board eeprom device.
266 * Header Format
268 *  Name                 Size    Contents
269 *                       (Bytes)
270 *-------------------------------------------------------------
271 *  Header               4       0xAA, 0x55, 0x33, 0xEE
273 *  Board Name           8       Name for board in ASCII.
274 *                               example "A33515BB" = "AM335X
275                                 Low Cost EVM board"
277 *  Version              4       Hardware version code for board in
278 *                               in ASCII. "1.0A" = rev.01.0A
280 *  Serial Number        12      Serial number of the board. This is a 12
281 *                               character string which is WWYY4P16nnnn, where
282 *                               WW = 2 digit week of the year of production
283 *                               YY = 2 digit year of production
284 *                               nnnn = incrementing board number
286 *  Configuration option 32      Codes(TBD) to show the configuration
287 *                               setup on this board.
289 *  Available            32720   Available space for other non-volatile
290 *                               data.
291 */
292 struct am335x_evm_eeprom_config {
293         u32     header;
294         u8      name[8];
295         char    version[4];
296         u8      serial[12];
297         u8      opt[32];
298 };
300 static struct am335x_evm_eeprom_config config;
301 static bool daughter_brd_detected;
303 #define GP_EVM_REV_IS_1_0               0x1
304 #define GP_EVM_REV_IS_1_1A              0x2
305 #define GP_EVM_REV_IS_UNKNOWN           0xFF
306 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
307 unsigned int gigabit_enable = 1;
309 #define EEPROM_MAC_ADDRESS_OFFSET       60 /* 4+8+4+12+32 */
310 #define EEPROM_NO_OF_MAC_ADDR           3
311 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
313 #define AM335X_EEPROM_HEADER            0xEE3355AA
315 /* current profile if exists else PROFILE_0 on error */
316 static u32 am335x_get_profile_selection(void)
318         int val = 0;
320         if (!cpld_client)
321                 /* error checking is not done in func's calling this routine.
322                 so return profile 0 on error */
323                 return 0;
325         val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
326         if (val < 0)
327                 return 0;       /* default to Profile 0 on Error */
328         else
329                 return val & 0x7;
332 /* Module pin mux for LCDC */
333 static struct pinmux_config lcdc_pin_mux[] = {
334         {"lcd_data0.lcd_data0",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
335                                                        | AM33XX_PULL_DISA},
336         {"lcd_data1.lcd_data1",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
337                                                        | AM33XX_PULL_DISA},
338         {"lcd_data2.lcd_data2",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
339                                                        | AM33XX_PULL_DISA},
340         {"lcd_data3.lcd_data3",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
341                                                        | AM33XX_PULL_DISA},
342         {"lcd_data4.lcd_data4",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
343                                                        | AM33XX_PULL_DISA},
344         {"lcd_data5.lcd_data5",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
345                                                        | AM33XX_PULL_DISA},
346         {"lcd_data6.lcd_data6",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
347                                                        | AM33XX_PULL_DISA},
348         {"lcd_data7.lcd_data7",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
349                                                        | AM33XX_PULL_DISA},
350         {"lcd_data8.lcd_data8",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
351                                                        | AM33XX_PULL_DISA},
352         {"lcd_data9.lcd_data9",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
353                                                        | AM33XX_PULL_DISA},
354         {"lcd_data10.lcd_data10",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
355                                                        | AM33XX_PULL_DISA},
356         {"lcd_data11.lcd_data11",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
357                                                        | AM33XX_PULL_DISA},
358         {"lcd_data12.lcd_data12",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
359                                                        | AM33XX_PULL_DISA},
360         {"lcd_data13.lcd_data13",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
361                                                        | AM33XX_PULL_DISA},
362         {"lcd_data14.lcd_data14",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
363                                                        | AM33XX_PULL_DISA},
364         {"lcd_data15.lcd_data15",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
365                                                        | AM33XX_PULL_DISA},
366         {"gpmc_ad8.lcd_data16",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
367         {"gpmc_ad9.lcd_data17",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
368         {"gpmc_ad10.lcd_data18",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
369         {"gpmc_ad11.lcd_data19",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
370         {"gpmc_ad12.lcd_data20",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
371         {"gpmc_ad13.lcd_data21",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
372         {"gpmc_ad14.lcd_data22",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
373         {"gpmc_ad15.lcd_data23",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
374         {"lcd_vsync.lcd_vsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
375         {"lcd_hsync.lcd_hsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
376         {"lcd_pclk.lcd_pclk",           OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
377         {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
378         {NULL, 0},
379 };
381 static struct pinmux_config tsc_pin_mux[] = {
382         {"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
383         {"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
384         {"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
385         {"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
386         {"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
387         {"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
388         {NULL, 0},
389 };
391 /* Pin mux for nand flash module */
392 static struct pinmux_config nand_pin_mux[] = {
393         {"gpmc_ad0.gpmc_ad0",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
394         {"gpmc_ad1.gpmc_ad1",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
395         {"gpmc_ad2.gpmc_ad2",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
396         {"gpmc_ad3.gpmc_ad3",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
397         {"gpmc_ad4.gpmc_ad4",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
398         {"gpmc_ad5.gpmc_ad5",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
399         {"gpmc_ad6.gpmc_ad6",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
400         {"gpmc_ad7.gpmc_ad7",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
401         {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
402         {"gpmc_wpn.gpmc_wpn",     OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
403         {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
404         {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
405         {"gpmc_oen_ren.gpmc_oen_ren",    OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
406         {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
407         {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
408         {NULL, 0},
409 };
411 /* Module pin mux for SPI fash */
412 static struct pinmux_config spi0_pin_mux[] = {
413         {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
414                                                         | AM33XX_INPUT_EN},
415         {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
416                                                         | AM33XX_INPUT_EN},
417         {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
418                                                         | AM33XX_INPUT_EN},
419         {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
420                                                         | AM33XX_INPUT_EN},
421         {NULL, 0},
422 };
424 /* Module pin mux for SPI flash */
425 static struct pinmux_config spi1_pin_mux[] = {
426         {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
427                 | AM33XX_INPUT_EN},
428         {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
429                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
430         {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
431                 | AM33XX_INPUT_EN},
432         {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
433                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
434         {NULL, 0},
435 };
437 /* Module pin mux for rgmii1 */
438 static struct pinmux_config rgmii1_pin_mux[] = {
439         {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
440         {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
441         {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
442         {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
443         {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
444         {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
445         {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
446         {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
447         {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
448         {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
449         {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
450         {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
451         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
452         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
453         {NULL, 0},
454 };
456 /* Module pin mux for rgmii2 */
457 static struct pinmux_config rgmii2_pin_mux[] = {
458         {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
459         {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
460         {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
461         {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
462         {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
463         {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
464         {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
465         {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
466         {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
467         {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
468         {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
469         {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
470         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
471         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
472         {NULL, 0},
473 };
475 /* Module pin mux for mii1 */
476 static struct pinmux_config mii1_pin_mux[] = {
477         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
478         {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
479         {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
480         {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
481         {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
482         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
483         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
484         {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
485         {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
486         {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
487         {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
488         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
489         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
490         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
491         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
492         {NULL, 0},
493 };
495 /* Module pin mux for rmii1 */
496 static struct pinmux_config rmii1_pin_mux[] = {
497         {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
498         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
499         {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
500         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
501         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
502         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
503         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
504         {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
505         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
506         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
507         {NULL, 0},
508 };
510 static struct pinmux_config i2c1_pin_mux[] = {
511         {"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
512                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
513         {"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
514                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
515         {NULL, 0},
516 };
518 /* Module pin mux for mcasp1 */
519 static struct pinmux_config mcasp1_pin_mux[] = {
520         {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
521         {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
522         {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
523         {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
524                                                 AM33XX_PIN_INPUT_PULLDOWN},
525         {NULL, 0},
526 };
529 /* Module pin mux for mmc0 */
530 static struct pinmux_config mmc0_pin_mux[] = {
531         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
532         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
533         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
534         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
535         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
536         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
537         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
538         {"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
539         {NULL, 0},
540 };
542 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
543         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
544         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
545         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
546         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
547         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
548         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
549         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
550         {NULL, 0},
551 };
553 /* Module pin mux for mmc1 */
554 static struct pinmux_config mmc1_pin_mux[] = {
555         {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
556         {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
557         {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
558         {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
559         {"gpmc_ad3.mmc1_dat3",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
560         {"gpmc_ad2.mmc1_dat2",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
561         {"gpmc_ad1.mmc1_dat1",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
562         {"gpmc_ad0.mmc1_dat0",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
563         {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
564         {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
565         {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
566         {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
567         {NULL, 0},
568 };
570 /* Module pin mux for uart3 */
571 static struct pinmux_config uart3_pin_mux[] = {
572         {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
573         {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
574         {NULL, 0},
575 };
577 static struct pinmux_config d_can_gp_pin_mux[] = {
578         {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
579         {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
580         {NULL, 0},
581 };
583 static struct pinmux_config d_can_ia_pin_mux[] = {
584         {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
585         {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
586         {NULL, 0},
587 };
589 /* Module pin mux for uart2 */
590 static struct pinmux_config uart2_pin_mux[] = {
591         {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
592                                                 AM33XX_PIN_INPUT_PULLUP},
593         {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
594                                                 AM33XX_PULL_DISA |
595                                                 AM33XX_SLEWCTRL_SLOW},
596         {NULL, 0},
597 };
600 /*
601 * @pin_mux - single module pin-mux structure which defines pin-mux
602 *                       details for all its pins.
603 */
604 static void setup_pin_mux(struct pinmux_config *pin_mux)
606         int i;
608         for (i = 0; pin_mux->string_name != NULL; pin_mux++)
609                 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
613 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
615 /* pinmux for keypad device */
616 static struct pinmux_config matrix_keypad_pin_mux[] = {
617         {"gpmc_a5.gpio1_21",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
618         {"gpmc_a6.gpio1_22",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
619         {"gpmc_a9.gpio1_25",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
620         {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
621         {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
622         {NULL, 0},
623 };
625 /* Keys mapping */
626 static const uint32_t am335x_evm_matrix_keys[] = {
627         KEY(0, 0, KEY_MENU),
628         KEY(1, 0, KEY_BACK),
629         KEY(2, 0, KEY_LEFT),
631         KEY(0, 1, KEY_RIGHT),
632         KEY(1, 1, KEY_ENTER),
633         KEY(2, 1, KEY_DOWN),
634 };
636 const struct matrix_keymap_data am335x_evm_keymap_data = {
637         .keymap      = am335x_evm_matrix_keys,
638         .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
639 };
641 static const unsigned int am335x_evm_keypad_row_gpios[] = {
642         GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
643 };
645 static const unsigned int am335x_evm_keypad_col_gpios[] = {
646         GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
647 };
649 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
650         .keymap_data       = &am335x_evm_keymap_data,
651         .row_gpios         = am335x_evm_keypad_row_gpios,
652         .num_row_gpios     = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
653         .col_gpios         = am335x_evm_keypad_col_gpios,
654         .num_col_gpios     = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
655         .active_low        = false,
656         .debounce_ms       = 5,
657         .col_scan_delay_us = 2,
658 };
660 static struct platform_device am335x_evm_keyboard = {
661         .name  = "matrix-keypad",
662         .id    = -1,
663         .dev   = {
664                 .platform_data = &am335x_evm_keypad_platform_data,
665         },
666 };
668 static void matrix_keypad_init(int evm_id, int profile)
670         int err;
672         setup_pin_mux(matrix_keypad_pin_mux);
673         err = platform_device_register(&am335x_evm_keyboard);
674         if (err) {
675                 pr_err("failed to register matrix keypad (2x3) device\n");
676         }
680 /* pinmux for keypad device */
681 static struct pinmux_config volume_keys_pin_mux[] = {
682         {"spi0_sclk.gpio0_2",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
683         {"spi0_d0.gpio0_3",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
684         {NULL, 0},
685 };
687 /* Configure GPIOs for Volume Keys */
688 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
689         {
690                 .code                   = KEY_VOLUMEUP,
691                 .gpio                   = GPIO_TO_PIN(0, 2),
692                 .active_low             = true,
693                 .desc                   = "volume-up",
694                 .type                   = EV_KEY,
695                 .wakeup                 = 1,
696         },
697         {
698                 .code                   = KEY_VOLUMEDOWN,
699                 .gpio                   = GPIO_TO_PIN(0, 3),
700                 .active_low             = true,
701                 .desc                   = "volume-down",
702                 .type                   = EV_KEY,
703                 .wakeup                 = 1,
704         },
705 };
707 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
708         .buttons        = am335x_evm_volume_gpio_buttons,
709         .nbuttons       = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
710 };
712 static struct platform_device am335x_evm_volume_keys = {
713         .name   = "gpio-keys",
714         .id     = -1,
715         .dev    = {
716                 .platform_data  = &am335x_evm_volume_gpio_key_info,
717         },
718 };
720 static void volume_keys_init(int evm_id, int profile)
722         int err;
724         setup_pin_mux(volume_keys_pin_mux);
725         err = platform_device_register(&am335x_evm_volume_keys);
726         if (err)
727                 pr_err("failed to register matrix keypad (2x3) device\n");
730 /*
731 * @evm_id - evm id which needs to be configured
732 * @dev_cfg - single evm structure which includes
733 *                               all module inits, pin-mux defines
734 * @profile - if present, else PROFILE_NONE
735 * @dghtr_brd_flg - Whether Daughter board is present or not
736 */
737 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
738         int profile)
740         int i;
742         /*
743         * Only General Purpose & Industrial Auto Motro Control
744         * EVM has profiles. So check if this evm has profile.
745         * If not, ignore the profile comparison
746         */
748         /*
749         * If the device is on baseboard, directly configure it. Else (device on
750         * Daughter board), check if the daughter card is detected.
751         */
752         if (profile == PROFILE_NONE) {
753                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
754                         if (dev_cfg->device_on == DEV_ON_BASEBOARD)
755                                 dev_cfg->device_init(evm_id, profile);
756                         else if (daughter_brd_detected == true)
757                                 dev_cfg->device_init(evm_id, profile);
758                 }
759         } else {
760                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
761                         if (dev_cfg->profile & profile) {
762                                 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
763                                         dev_cfg->device_init(evm_id, profile);
764                                 else if (daughter_brd_detected == true)
765                                         dev_cfg->device_init(evm_id, profile);
766                         }
767                 }
768         }
771 #define AM335X_LCD_BL_PIN       GPIO_TO_PIN(0, 7)
773 /* pinmux for usb0 drvvbus */
774 static struct pinmux_config usb0_pin_mux[] = {
775         {"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
776         {NULL, 0},
777 };
779 /* pinmux for usb1 drvvbus */
780 static struct pinmux_config usb1_pin_mux[] = {
781         {"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
782         {NULL, 0},
783 };
785 /* pinmux for profibus */
786 static struct pinmux_config profibus_pin_mux[] = {
787         {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
788         {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
789         {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
790         {NULL, 0},
791 };
793 /* Module pin mux for eCAP0 */
794 static struct pinmux_config ecap0_pin_mux[] = {
795         {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
796         {NULL, 0},
797 };
799 static int backlight_enable;
801 #define AM335XEVM_WLAN_PMENA_GPIO       GPIO_TO_PIN(1, 30)
802 #define AM335XEVM_WLAN_IRQ_GPIO         GPIO_TO_PIN(3, 17)
804 struct wl12xx_platform_data am335xevm_wlan_data = {
805         .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
806         .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
807 };
809 /* Module pin mux for wlan and bluetooth */
810 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
811         {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
812         {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
813         {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
814         {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
815         {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
816         {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
817         {NULL, 0},
818 };
820 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
821         {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
822         {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
823         {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
824         {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
825         {NULL, 0},
826 };
828 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
829         {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
830         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
831         {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
832         {NULL, 0},
833  };
835 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
836         {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
837         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
838         {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
839         {NULL, 0},
840  };
842 static void enable_ecap0(int evm_id, int profile)
844         backlight_enable = true;
847 static int __init ecap0_init(void)
849         int status = 0;
851         if (backlight_enable) {
852                 setup_pin_mux(ecap0_pin_mux);
854                 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
855                 if (status < 0)
856                         pr_warn("Failed to request gpio for LCD backlight\n");
858                 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
859         }
860         return status;
862 late_initcall(ecap0_init);
864 static int __init conf_disp_pll(int rate)
866         struct clk *disp_pll;
867         int ret = -EINVAL;
869         disp_pll = clk_get(NULL, "dpll_disp_ck");
870         if (IS_ERR(disp_pll)) {
871                 pr_err("Cannot clk_get disp_pll\n");
872                 goto out;
873         }
875         ret = clk_set_rate(disp_pll, rate);
876         clk_put(disp_pll);
877 out:
878         return ret;
881 static void lcdc_init(int evm_id, int profile)
884         setup_pin_mux(lcdc_pin_mux);
886         if (conf_disp_pll(300000000)) {
887                 pr_info("Failed configure display PLL, not attempting to"
888                                 "register LCDC\n");
889                 return;
890         }
892         if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
893                 pr_info("Failed to register LCDC device\n");
894         return;
897 static void tsc_init(int evm_id, int profile)
899         int err;
901         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
902                 am335x_touchscreen_data.analog_input = 1;
903                 pr_info("TSC connected to beta GP EVM\n");
904         } else {
905                 am335x_touchscreen_data.analog_input = 0;
906                 pr_info("TSC connected to alpha GP EVM\n");
907         }
908         setup_pin_mux(tsc_pin_mux);
909         err = platform_device_register(&tsc_device);
910         if (err)
911                 pr_err("failed to register touchscreen device\n");
914 static void rgmii1_init(int evm_id, int profile)
916         setup_pin_mux(rgmii1_pin_mux);
917         return;
920 static void rgmii2_init(int evm_id, int profile)
922         setup_pin_mux(rgmii2_pin_mux);
923         return;
926 static void mii1_init(int evm_id, int profile)
928         setup_pin_mux(mii1_pin_mux);
929         return;
932 static void rmii1_init(int evm_id, int profile)
934         setup_pin_mux(rmii1_pin_mux);
935         return;
938 static void usb0_init(int evm_id, int profile)
940         setup_pin_mux(usb0_pin_mux);
941         return;
944 static void usb1_init(int evm_id, int profile)
946         setup_pin_mux(usb1_pin_mux);
947         return;
950 /* setup uart3 */
951 static void uart3_init(int evm_id, int profile)
953         setup_pin_mux(uart3_pin_mux);
954         return;
957 /* setup uart2 */
958 static void uart2_init(int evm_id, int profile)
960         setup_pin_mux(uart2_pin_mux);
961         return;
964 /* NAND partition information */
965 static struct mtd_partition am335x_nand_partitions[] = {
966 /* All the partition sizes are listed in terms of NAND block size */
967         {
968                 .name           = "SPL",
969                 .offset         = 0,                    /* Offset = 0x0 */
970                 .size           = SZ_128K,
971         },
972         {
973                 .name           = "SPL.backup1",
974                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x20000 */
975                 .size           = SZ_128K,
976         },
977         {
978                 .name           = "SPL.backup2",
979                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x40000 */
980                 .size           = SZ_128K,
981         },
982         {
983                 .name           = "SPL.backup3",
984                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x60000 */
985                 .size           = SZ_128K,
986         },
987         {
988                 .name           = "U-Boot",
989                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
990                 .size           = 15 * SZ_128K,
991         },
992         {
993                 .name           = "U-Boot Env",
994                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
995                 .size           = 1 * SZ_128K,
996         },
997         {
998                 .name           = "Kernel",
999                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
1000                 .size           = 40 * SZ_128K,
1001         },
1002         {
1003                 .name           = "File System",
1004                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
1005                 .size           = MTDPART_SIZ_FULL,
1006         },
1007 };
1009 /* SPI 0/1 Platform Data */
1010 /* SPI flash information */
1011 static struct mtd_partition am335x_spi_partitions[] = {
1012         /* All the partition sizes are listed in terms of erase size */
1013         {
1014                 .name       = "SPL",
1015                 .offset     = 0,                        /* Offset = 0x0 */
1016                 .size       = SZ_128K,
1017         },
1018         {
1019                 .name       = "U-Boot",
1020                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x20000 */
1021                 .size       = 2 * SZ_128K,
1022         },
1023         {
1024                 .name       = "U-Boot Env",
1025                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x60000 */
1026                 .size       = 2 * SZ_4K,
1027         },
1028         {
1029                 .name       = "Kernel",
1030                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x62000 */
1031                 .size       = 28 * SZ_128K,
1032         },
1033         {
1034                 .name       = "File System",
1035                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x3E2000 */
1036                 .size       = MTDPART_SIZ_FULL,         /* size ~= 4.1 MiB */
1037         }
1038 };
1040 static const struct flash_platform_data am335x_spi_flash = {
1041         .type      = "w25q64",
1042         .name      = "spi_flash",
1043         .parts     = am335x_spi_partitions,
1044         .nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
1045 };
1047 /*
1048  * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1049  * So setup Max speed to be less than that of Controller speed
1050  */
1051 static struct spi_board_info am335x_spi0_slave_info[] = {
1052         {
1053                 .modalias      = "m25p80",
1054                 .platform_data = &am335x_spi_flash,
1055                 .irq           = -1,
1056                 .max_speed_hz  = 24000000,
1057                 .bus_num       = 1,
1058                 .chip_select   = 0,
1059         },
1060 };
1062 static struct spi_board_info am335x_spi1_slave_info[] = {
1063         {
1064                 .modalias      = "m25p80",
1065                 .platform_data = &am335x_spi_flash,
1066                 .irq           = -1,
1067                 .max_speed_hz  = 12000000,
1068                 .bus_num       = 2,
1069                 .chip_select   = 0,
1070         },
1071 };
1073 static void evm_nand_init(int evm_id, int profile)
1075         setup_pin_mux(nand_pin_mux);
1076         board_nand_init(am335x_nand_partitions,
1077                 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1080 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1081         .click_flags = LIS3_CLICK_SINGLE_X |
1082                         LIS3_CLICK_SINGLE_Y |
1083                         LIS3_CLICK_SINGLE_Z,
1084         .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1085                         LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1086                         LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1087         .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1088         .wakeup_thresh  = 10,
1089         .click_thresh_x = 10,
1090         .click_thresh_y = 10,
1091         .click_thresh_z = 10,
1092         .g_range        = 2,
1093         .st_min_limits[0] = 120,
1094         .st_min_limits[1] = 120,
1095         .st_min_limits[2] = 140,
1096         .st_max_limits[0] = 550,
1097         .st_max_limits[1] = 550,
1098         .st_max_limits[2] = 750,
1099 };
1101 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1102         {
1103                 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1104         },
1105         {
1106                 I2C_BOARD_INFO("lis331dlh", 0x18),
1107                 .platform_data = &lis331dlh_pdata,
1108         },
1109         {
1110                 I2C_BOARD_INFO("tsl2550", 0x39),
1111         },
1112         {
1113                 I2C_BOARD_INFO("tmp275", 0x48),
1114         },
1115 };
1117 static void i2c1_init(int evm_id, int profile)
1119         setup_pin_mux(i2c1_pin_mux);
1120         omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1121                         ARRAY_SIZE(am335x_i2c_boardinfo1));
1122         return;
1125 /* Setup McASP 1 */
1126 static void mcasp1_init(int evm_id, int profile)
1128         /* Configure McASP */
1129         setup_pin_mux(mcasp1_pin_mux);
1130         am335x_register_mcasp1(&am335x_evm_snd_data1);
1131         return;
1134 static void mmc1_init(int evm_id, int profile)
1136         setup_pin_mux(mmc1_pin_mux);
1138         am335x_mmc[1].mmc = 2;
1139         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1140         am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1141         am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1142         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1144         /* mmc will be initialized when mmc0_init is called */
1145         return;
1148 static void mmc2_wl12xx_init(int evm_id, int profile)
1150         setup_pin_mux(mmc2_wl12xx_pin_mux);
1152         am335x_mmc[1].mmc = 3;
1153         am335x_mmc[1].name = "wl1271";
1154         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1155                                 | MMC_PM_KEEP_POWER;
1156         am335x_mmc[1].nonremovable = true;
1157         am335x_mmc[1].gpio_cd = -EINVAL;
1158         am335x_mmc[1].gpio_wp = -EINVAL;
1159         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1161         /* mmc will be initialized when mmc0_init is called */
1162         return;
1165 static void uart1_wl12xx_init(int evm_id, int profile)
1167         setup_pin_mux(uart1_wl12xx_pin_mux);
1170 static void wl12xx_bluetooth_enable(void)
1172         int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1173                 "bt_en\n");
1174         if (status < 0)
1175                 pr_err("Failed to request gpio for bt_enable");
1177         pr_info("Configure Bluetooth Enable pin...\n");
1178         gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1181 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1183         if (on) {
1184                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1185                 mdelay(70);
1186         }
1187         else
1188                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1190         return 0;
1193 static void wl12xx_init(int evm_id, int profile)
1195         struct device *dev;
1196         struct omap_mmc_platform_data *pdata;
1197         int ret;
1199         /* Register WLAN and BT enable pins based on the evm board revision */
1200         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1201                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1202                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1203         }
1204         else {
1205                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1206                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1207         }
1209         wl12xx_bluetooth_enable();
1211         if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1212                 pr_err("error setting wl12xx data\n");
1214         dev = am335x_mmc[1].dev;
1215         if (!dev) {
1216                 pr_err("wl12xx mmc device initialization failed\n");
1217                 goto out;
1218         }
1220         pdata = dev->platform_data;
1221         if (!pdata) {
1222                 pr_err("Platfrom data of wl12xx device not set\n");
1223                 goto out;
1224         }
1226         ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1227                 GPIOF_OUT_INIT_LOW, "wlan_en");
1228         if (ret) {
1229                 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1230                 goto out;
1231         }
1233         if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1234                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1235         else
1236                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1238         pdata->slots[0].set_power = wl12xx_set_power;
1239 out:
1240         return;
1243 static void d_can_init(int evm_id, int profile)
1245         switch (evm_id) {
1246         case IND_AUT_MTR_EVM:
1247                 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1248                         setup_pin_mux(d_can_ia_pin_mux);
1249                         /* Instance Zero */
1250                         am33xx_d_can_init(0);
1251                 }
1252                 break;
1253         case GEN_PURP_EVM:
1254                 if (profile == PROFILE_1) {
1255                         setup_pin_mux(d_can_gp_pin_mux);
1256                         /* Instance One */
1257                         am33xx_d_can_init(1);
1258                 }
1259                 break;
1260         default:
1261                 break;
1262         }
1265 static void mmc0_init(int evm_id, int profile)
1267         setup_pin_mux(mmc0_pin_mux);
1269         omap2_hsmmc_init(am335x_mmc);
1270         return;
1273 static void mmc0_no_cd_init(int evm_id, int profile)
1275         setup_pin_mux(mmc0_no_cd_pin_mux);
1277         omap2_hsmmc_init(am335x_mmc);
1278         return;
1282 /* setup spi0 */
1283 static void spi0_init(int evm_id, int profile)
1285         setup_pin_mux(spi0_pin_mux);
1286         spi_register_board_info(am335x_spi0_slave_info,
1287                         ARRAY_SIZE(am335x_spi0_slave_info));
1288         return;
1291 /* setup spi1 */
1292 static void spi1_init(int evm_id, int profile)
1294         setup_pin_mux(spi1_pin_mux);
1295         spi_register_board_info(am335x_spi1_slave_info,
1296                         ARRAY_SIZE(am335x_spi1_slave_info));
1297         return;
1301 static int beaglebone_phy_fixup(struct phy_device *phydev)
1303         phydev->supported &= ~(SUPPORTED_100baseT_Half |
1304                                 SUPPORTED_100baseT_Full);
1306         return 0;
1309 #ifdef CONFIG_TLK110_WORKAROUND
1310 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1312         unsigned int val;
1314         /* This is done as a workaround to support TLK110 rev1.0 phy */
1315         val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1316         phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1318         val = phy_read(phydev, TLK110_LPFHPF_REG);
1319         phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1321         val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1322         phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1324         val = phy_read(phydev, TLK110_VRCR_REG);
1325         phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1327         val = phy_read(phydev, TLK110_SETFFE_REG);
1328         phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1330         val = phy_read(phydev, TLK110_FTSP_REG);
1331         phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1333         val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1334         phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1336         val = phy_read(phydev, TLK110_PSCOEF21_REG);
1337         phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1339         val = phy_read(phydev, TLK110_PSCOEF3_REG);
1340         phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1342         val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1343         phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1345         val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1346         phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1348         val = phy_read(phydev, TLK110_CFGPS_REG);
1349         phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1351         val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1352         phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1354         val = phy_read(phydev, TLK110_SWSCR3_REG);
1355         phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1357         val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1358         phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1360         val = phy_read(phydev, TLK110_PHYRCR_REG);
1361         phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1363         return 0;
1365 #endif
1367 static void profibus_init(int evm_id, int profile)
1369         setup_pin_mux(profibus_pin_mux);
1370         return;
1373 /* Low-Cost EVM */
1374 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1375         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1376         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1377         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1378         {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1379         {NULL, 0, 0},
1380 };
1382 /* General Purpose EVM */
1383 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1384         {enable_ecap0,  DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1385                                                 PROFILE_2 | PROFILE_7) },
1386         {lcdc_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1387                                                 PROFILE_2 | PROFILE_7) },
1388         {tsc_init,      DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1389                                                 PROFILE_2 | PROFILE_7) },
1390         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
1391         {rgmii2_init,   DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1392                                                 PROFILE_4 | PROFILE_6) },
1393         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1394         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1395         {evm_nand_init, DEV_ON_DGHTR_BRD,
1396                 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1397         {i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1398         {mcasp1_init,   DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1399         {mmc1_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1400         {mmc2_wl12xx_init,      DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1401                                                                 PROFILE_5)},
1402         {mmc0_init,     DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1403         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_5},
1404         {spi0_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1405         {uart1_wl12xx_init,     DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1406                                                                 PROFILE_5)},
1407         {wl12xx_init,   DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1408         {d_can_init,    DEV_ON_DGHTR_BRD, PROFILE_1},
1409         {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1410         {volume_keys_init,  DEV_ON_DGHTR_BRD, PROFILE_0},
1411         {uart2_init,    DEV_ON_DGHTR_BRD, PROFILE_3},
1412         {NULL, 0, 0},
1413 };
1415 /* Industrial Auto Motor Control EVM */
1416 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1417         {mii1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1418         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1419         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1420         {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1421         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1422         {spi1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1423         {uart3_init,    DEV_ON_DGHTR_BRD, PROFILE_ALL},
1424         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1425         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_ALL},
1426         {NULL, 0, 0},
1427 };
1429 /* IP-Phone EVM */
1430 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1431         {enable_ecap0,  DEV_ON_DGHTR_BRD, PROFILE_NONE},
1432         {lcdc_init,     DEV_ON_DGHTR_BRD, PROFILE_NONE},
1433         {tsc_init,      DEV_ON_DGHTR_BRD, PROFILE_NONE},
1434         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1435         {rgmii2_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1436         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1437         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1438         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1439         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1440         {mcasp1_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1441         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1442         {NULL, 0, 0},
1443 };
1445 /* Beaglebone < Rev A3 */
1446 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1447         {rmii1_init,    DEV_ON_BASEBOARD, PROFILE_NONE},
1448         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1449         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1450         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1451         {NULL, 0, 0},
1452 };
1454 /* Beaglebone Rev A3 and after */
1455 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1456         {mii1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1457         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1458         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1459         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1460         {NULL, 0, 0},
1461 };
1463 static void setup_low_cost_evm(void)
1465         pr_info("The board is a AM335x Low Cost EVM.\n");
1467         _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1470 static void setup_general_purpose_evm(void)
1472         u32 prof_sel = am335x_get_profile_selection();
1473         pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1475         if (!strncmp("1.1A", config.version, 4)) {
1476                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1477         } else if (!strncmp("1.0", config.version, 3)) {
1478                 gp_evm_revision = GP_EVM_REV_IS_1_0;
1479         } else {
1480                 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1481                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1482         }
1484         if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1485                 gigabit_enable = 0;
1486         else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1487                 gigabit_enable = 1;
1489         _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1492 static void setup_ind_auto_motor_ctrl_evm(void)
1494         u32 prof_sel = am335x_get_profile_selection();
1496         pr_info("The board is an industrial automation EVM in profile %d\n",
1497                 prof_sel);
1499         /* Only Profile 0 is supported */
1500         if ((1L << prof_sel) != PROFILE_0) {
1501                 pr_err("AM335X: Only Profile 0 is supported\n");
1502                 pr_err("Assuming profile 0 & continuing\n");
1503                 prof_sel = PROFILE_0;
1504         }
1506         _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1507                 PROFILE_0);
1509         /* Fillup global evmid */
1510         am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1512         /* Initialize TLK110 PHY registers for phy version 1.0 */
1513         am335x_tlk110_phy_init();
1518 static void setup_ip_phone_evm(void)
1520         pr_info("The board is an IP phone EVM\n");
1522         _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1525 /* BeagleBone < Rev A3 */
1526 static void setup_beaglebone_old(void)
1528         pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1530         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1531         am335x_mmc[0].gpio_wp = -EINVAL;
1533         _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1535         phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1536                                         beaglebone_phy_fixup);
1539 /* BeagleBone after Rev A3 */
1540 static void setup_beaglebone(void)
1542         pr_info("The board is a AM335x Beaglebone.\n");
1544         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1545         am335x_mmc[0].gpio_wp = -EINVAL;
1547         _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1551 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1553         u8 tmp;
1554         int ret;
1556         /*
1557          * try reading a byte from the EEPROM to see if it is
1558          * present. We could read a lot more, but that would
1559          * just slow the boot process and we have all the information
1560          * we need from the EEPROM on the base board anyway.
1561          */
1562         ret = m->read(m, &tmp, 0, sizeof(u8));
1563         if (ret == sizeof(u8)) {
1564                 pr_info("Detected a daughter card on AM335x EVM..");
1565                 daughter_brd_detected = true;
1566         } else {
1567                 pr_info("No daughter card found\n");
1568                 daughter_brd_detected = false;
1569         }
1572 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1574         int ret;
1575         char tmp[10];
1577         /* 1st get the MAC address from EEPROM */
1578         ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1579                 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1581         if (ret != sizeof(am335x_mac_addr)) {
1582                 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1583                 return;
1584         }
1586         /* Fillup global mac id */
1587         am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1588                                 &am335x_mac_addr[1][0]);
1590         /* get board specific data */
1591         ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1592         if (ret != sizeof(config)) {
1593                 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1594                 return;
1595         }
1597         if (config.header != AM335X_EEPROM_HEADER) {
1598                 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1599                         config.header, AM335X_EEPROM_HEADER);
1600                 goto out;
1601         }
1603         if (strncmp("A335", config.name, 4)) {
1604                 pr_err("Board %s doesn't look like an AM335x board\n",
1605                         config.name);
1606                 goto out;
1607         }
1609         snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1610         pr_info("Board name: %s\n", tmp);
1611         snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1612         pr_info("Board version: %s\n", tmp);
1614         if (!strncmp("A335BONE", config.name, 8)) {
1615                 daughter_brd_detected = false;
1616                 if(!strncmp("00A1", config.version, 4) ||
1617                    !strncmp("00A2", config.version, 4))
1618                         setup_beaglebone_old();
1619                 else
1620                         setup_beaglebone();
1621         } else {
1622                 /* only 6 characters of options string used for now */
1623                 snprintf(tmp, 7, "%s", config.opt);
1624                 pr_info("SKU: %s\n", tmp);
1626                 if (!strncmp("SKU#00", config.opt, 6))
1627                         setup_low_cost_evm();
1628                 else if (!strncmp("SKU#01", config.opt, 6))
1629                         setup_general_purpose_evm();
1630                 else if (!strncmp("SKU#02", config.opt, 6))
1631                         setup_ind_auto_motor_ctrl_evm();
1632                 else if (!strncmp("SKU#03", config.opt, 6))
1633                         setup_ip_phone_evm();
1634                 else
1635                         goto out;
1636         }
1637         /* Initialize cpsw after board detection is completed as board
1638          * information is required for configuring phy address and hence
1639          * should be call only after board detection
1640          */
1641         am33xx_cpsw_init(gigabit_enable);
1643         return;
1644 out:
1645         /*
1646          * If the EEPROM hasn't been programed or an incorrect header
1647          * or board name are read, assume this is an old beaglebone board
1648          * (< Rev A3)
1649          */
1650         pr_err("Could not detect any board, falling back to: "
1651                 "Beaglebone (< Rev A3) with no daughter card connected\n");
1652         daughter_brd_detected = false;
1653         setup_beaglebone_old();
1655         /* Initialize cpsw after board detection is completed as board
1656          * information is required for configuring phy address and hence
1657          * should be call only after board detection
1658          */
1660         am33xx_cpsw_init(gigabit_enable);
1663 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1664         .byte_len       = (256*1024) / 8,
1665         .page_size      = 64,
1666         .flags          = AT24_FLAG_ADDR16,
1667         .setup          = am335x_setup_daughter_board,
1668         .context        = (void *)NULL,
1669 };
1671 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1672         .byte_len       = (256*1024) / 8,
1673         .page_size      = 64,
1674         .flags          = AT24_FLAG_ADDR16,
1675         .setup          = am335x_evm_setup,
1676         .context        = (void *)NULL,
1677 };
1679 /*
1680 * Daughter board Detection.
1681 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1682 * machine init, starting from daughter board and ending with baseboard.
1683 * Assumptions :
1684 *       1. probe for i2c devices are called in the order they are included in
1685 *          the below struct. Daughter boards eeprom are probed 1st. Baseboard
1686 *          eeprom probe is called last.
1687 */
1688 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1689         {
1690                 /* Daughter Board EEPROM */
1691                 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1692                 .platform_data  = &am335x_daughter_board_eeprom_info,
1693         },
1694         {
1695                 /* Baseboard board EEPROM */
1696                 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1697                 .platform_data  = &am335x_baseboard_eeprom_info,
1698         },
1699         {
1700                 I2C_BOARD_INFO("cpld_reg", 0x35),
1701         },
1702         {
1703                 I2C_BOARD_INFO("tlc59108", 0x40),
1704         },
1706 };
1708 static struct omap_musb_board_data musb_board_data = {
1709         .interface_type = MUSB_INTERFACE_ULPI,
1710         .mode           = MUSB_OTG,
1711         .power          = 500,
1712         .instances      = 1,
1713 };
1715 static int cpld_reg_probe(struct i2c_client *client,
1716             const struct i2c_device_id *id)
1718         cpld_client = client;
1719         return 0;
1722 static int __devexit cpld_reg_remove(struct i2c_client *client)
1724         cpld_client = NULL;
1725         return 0;
1728 static const struct i2c_device_id cpld_reg_id[] = {
1729         { "cpld_reg", 0 },
1730         { }
1731 };
1733 static struct i2c_driver cpld_reg_driver = {
1734         .driver = {
1735                 .name   = "cpld_reg",
1736         },
1737         .probe          = cpld_reg_probe,
1738         .remove         = cpld_reg_remove,
1739         .id_table       = cpld_reg_id,
1740 };
1742 static void evm_init_cpld(void)
1744         i2c_add_driver(&cpld_reg_driver);
1747 static void __init am335x_evm_i2c_init(void)
1749         /* Initially assume Low Cost EVM Config */
1750         am335x_evm_id = LOW_COST_EVM;
1752         evm_init_cpld();
1754         omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1755                                 ARRAY_SIZE(am335x_i2c_boardinfo));
1758 static struct resource am335x_rtc_resources[] = {
1759         {
1760                 .start          = AM33XX_RTC_BASE,
1761                 .end            = AM33XX_RTC_BASE + SZ_4K - 1,
1762                 .flags          = IORESOURCE_MEM,
1763         },
1764         { /* timer irq */
1765                 .start          = AM33XX_IRQ_RTC_TIMER,
1766                 .end            = AM33XX_IRQ_RTC_TIMER,
1767                 .flags          = IORESOURCE_IRQ,
1768         },
1769         { /* alarm irq */
1770                 .start          = AM33XX_IRQ_RTC_ALARM,
1771                 .end            = AM33XX_IRQ_RTC_ALARM,
1772                 .flags          = IORESOURCE_IRQ,
1773         },
1774 };
1776 static struct platform_device am335x_rtc_device = {
1777         .name           = "omap_rtc",
1778         .id             = -1,
1779         .num_resources  = ARRAY_SIZE(am335x_rtc_resources),
1780         .resource       = am335x_rtc_resources,
1781 };
1783 static int am335x_rtc_init(void)
1785         void __iomem *base;
1786         struct clk *clk;
1788         clk = clk_get(NULL, "rtc_fck");
1789         if (IS_ERR(clk)) {
1790                 pr_err("rtc : Failed to get RTC clock\n");
1791                 return -1;
1792         }
1794         if (clk_enable(clk)) {
1795                 pr_err("rtc: Clock Enable Failed\n");
1796                 return -1;
1797         }
1799         base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1801         if (WARN_ON(!base))
1802                 return -ENOMEM;
1804         /* Unlock the rtc's registers */
1805         __raw_writel(0x83e70b13, base + 0x6c);
1806         __raw_writel(0x95a4f1e0, base + 0x70);
1808         /*
1809          * Enable the 32K OSc
1810          * TODO: Need a better way to handle this
1811          * Since we want the clock to be running before mmc init
1812          * we need to do it before the rtc probe happens
1813          */
1814         __raw_writel(0x48, base + 0x54);
1816         iounmap(base);
1818         return  platform_device_register(&am335x_rtc_device);
1821 /* Enable clkout2 */
1822 static struct pinmux_config clkout2_pin_mux[] = {
1823         {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1824         {NULL, 0},
1825 };
1827 static void __init clkout2_enable(void)
1829         struct clk *ck_32;
1831         ck_32 = clk_get(NULL, "clkout2_ck");
1832         if (IS_ERR(ck_32)) {
1833                 pr_err("Cannot clk_get ck_32\n");
1834                 return;
1835         }
1837         clk_enable(ck_32);
1839         setup_pin_mux(clkout2_pin_mux);
1842 void __iomem * __init am33xx_get_mem_ctlr(void)
1844         void __iomem *am33xx_emif_base;
1846         am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1848         if (!am33xx_emif_base)
1849                 pr_warning("%s: Unable to map DDR2 controller", __func__);
1851         return am33xx_emif_base;
1854 static struct resource am33xx_cpuidle_resources[] = {
1855         {
1856                 .start          = AM33XX_EMIF0_BASE,
1857                 .end            = AM33XX_EMIF0_BASE + SZ_32K - 1,
1858                 .flags          = IORESOURCE_MEM,
1859         },
1860 };
1862 /* AM33XX devices support DDR2 power down */
1863 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1864         .ddr2_pdown     = 1,
1865 };
1867 static struct platform_device am33xx_cpuidle_device = {
1868         .name                   = "cpuidle-am33xx",
1869         .num_resources          = ARRAY_SIZE(am33xx_cpuidle_resources),
1870         .resource               = am33xx_cpuidle_resources,
1871         .dev = {
1872                 .platform_data  = &am33xx_cpuidle_pdata,
1873         },
1874 };
1876 static void __init am33xx_cpuidle_init(void)
1878         int ret;
1880         am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1882         ret = platform_device_register(&am33xx_cpuidle_device);
1884         if (ret)
1885                 pr_warning("AM33XX cpuidle registration failed\n");
1889 static void __init am335x_evm_init(void)
1891         am33xx_cpuidle_init();
1892         am33xx_mux_init(board_mux);
1893         omap_serial_init();
1894         am335x_rtc_init();
1895         clkout2_enable();
1896         am335x_evm_i2c_init();
1897         omap_sdrc_init(NULL, NULL);
1898         usb_musb_init(&musb_board_data);
1899         omap_board_config = am335x_evm_config;
1900         omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1901         /* Create an alias for icss clock */
1902         if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1903                 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1904         /* Create an alias for gfx/sgx clock */
1905         if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1906                 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1909 static void __init am335x_evm_map_io(void)
1911         omap2_set_globals_am33xx();
1912         omapam33xx_map_common_io();
1915 MACHINE_START(AM335XEVM, "am335xevm")
1916         /* Maintainer: Texas Instruments */
1917         .atag_offset    = 0x100,
1918         .map_io         = am335x_evm_map_io,
1919         .init_early     = am33xx_init_early,
1920         .init_irq       = ti81xx_init_irq,
1921         .handle_irq     = omap3_intc_handle_irq,
1922         .timer          = &omap3_am33xx_timer,
1923         .init_machine   = am335x_evm_init,
1924 MACHINE_END
1926 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1927         /* Maintainer: Texas Instruments */
1928         .atag_offset    = 0x100,
1929         .map_io         = am335x_evm_map_io,
1930         .init_irq       = ti81xx_init_irq,
1931         .init_early     = am33xx_init_early,
1932         .timer          = &omap3_am33xx_timer,
1933         .init_machine   = am335x_evm_init,
1934 MACHINE_END