1 /*
2 * Code for AM335X EVM.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
35 #include <linux/mfd/tps65910.h>
37 /* LCD controller is similar to DA850 */
38 #include <video/da8xx-fb.h>
40 #include <mach/hardware.h>
41 #include <mach/board-am335xevm.h>
43 #include <asm/mach-types.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/map.h>
46 #include <asm/hardware/asp.h>
48 #include <plat/irqs.h>
49 #include <plat/board.h>
50 #include <plat/common.h>
51 #include <plat/lcdc.h>
52 #include <plat/usb.h>
53 #include <plat/mmc.h>
55 #include "board-flash.h"
56 #include "cpuidle33xx.h"
57 #include "mux.h"
58 #include "devices.h"
59 #include "hsmmc.h"
61 /* Convert GPIO signal to GPIO pin number */
62 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
64 /* TLK PHY IDs */
65 #define TLK110_PHY_ID 0x2000A201
66 #define TLK110_PHY_MASK 0xfffffff0
68 /* BBB PHY IDs */
69 #define BBB_PHY_ID 0x7c0f1
70 #define BBB_PHY_MASK 0xfffffffe
72 /* TLK110 PHY register offsets */
73 #define TLK110_COARSEGAIN_REG 0x00A3
74 #define TLK110_LPFHPF_REG 0x00AC
75 #define TLK110_SPAREANALOG_REG 0x00B9
76 #define TLK110_VRCR_REG 0x00D0
77 #define TLK110_SETFFE_REG 0x0107
78 #define TLK110_FTSP_REG 0x0154
79 #define TLK110_ALFATPIDL_REG 0x002A
80 #define TLK110_PSCOEF21_REG 0x0096
81 #define TLK110_PSCOEF3_REG 0x0097
82 #define TLK110_ALFAFACTOR1_REG 0x002C
83 #define TLK110_ALFAFACTOR2_REG 0x0023
84 #define TLK110_CFGPS_REG 0x0095
85 #define TLK110_FTSPTXGAIN_REG 0x0150
86 #define TLK110_SWSCR3_REG 0x000B
87 #define TLK110_SCFALLBACK_REG 0x0040
88 #define TLK110_PHYRCR_REG 0x001F
90 /* TLK110 register writes values */
91 #define TLK110_COARSEGAIN_VAL 0x0000
92 #define TLK110_LPFHPF_VAL 0x8000
93 #define TLK110_SPANALOG_VAL 0x0000
94 #define TLK110_VRCR_VAL 0x0008
95 #define TLK110_SETFFE_VAL 0x0605
96 #define TLK110_FTSP_VAL 0x0255
97 #define TLK110_ALFATPIDL_VAL 0x7998
98 #define TLK110_PSCOEF21_VAL 0x3A20
99 #define TLK110_PSCOEF3_VAL 0x003F
100 #define TLK110_ALFACTOR1_VAL 0xFF80
101 #define TLK110_ALFACTOR2_VAL 0x021C
102 #define TLK110_CFGPS_VAL 0x0000
103 #define TLK110_FTSPTXGAIN_VAL 0x6A88
104 #define TLK110_SWSCR3_VAL 0x0000
105 #define TLK110_SCFALLBACK_VAL 0xC11D
106 #define TLK110_PHYRCR_VAL 0x4000
108 #if defined(CONFIG_TLK110_WORKAROUND) || \
109 defined(CONFIG_TLK110_WORKAROUND_MODULE)
110 #define am335x_tlk110_phy_init()\
111 do { \
112 phy_register_fixup_for_uid(TLK110_PHY_ID,\
113 TLK110_PHY_MASK,\
114 am335x_tlk110_phy_fixup);\
115 } while (0);
116 #else
117 #define am335x_tlk110_phy_init() do { } while (0);
118 #endif
120 static const struct display_panel disp_panel = {
121 WVGA,
122 32,
123 32,
124 COLOR_ACTIVE,
125 };
127 static struct lcd_ctrl_config lcd_cfg = {
128 &disp_panel,
129 .ac_bias = 255,
130 .ac_bias_intrpt = 0,
131 .dma_burst_sz = 16,
132 .bpp = 32,
133 .fdd = 0x80,
134 .tft_alt_mode = 0,
135 .stn_565_mode = 0,
136 .mono_8bit_mode = 0,
137 .invert_line_clock = 1,
138 .invert_frm_clock = 1,
139 .sync_edge = 0,
140 .sync_ctrl = 1,
141 .raster_order = 0,
142 };
144 static void am335x_gpio_bl_ctrl(int val);
146 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
147 .manu_name = "ThreeFive",
148 .controller_data = &lcd_cfg,
149 .type = "TFC_S9700RTWV35TR_01B",
150 .panel_power_ctrl = am335x_gpio_bl_ctrl,
151 };
153 #include "common.h"
155 /* TSc controller */
156 #include <linux/input/ti_tscadc.h>
157 #include <linux/lis3lv02d.h>
159 static struct resource tsc_resources[] = {
160 [0] = {
161 .start = AM33XX_TSC_BASE,
162 .end = AM33XX_TSC_BASE + SZ_8K - 1,
163 .flags = IORESOURCE_MEM,
164 },
165 [1] = {
166 .start = AM33XX_IRQ_ADC_GEN,
167 .end = AM33XX_IRQ_ADC_GEN,
168 .flags = IORESOURCE_IRQ,
169 },
170 };
172 static struct tsc_data am335x_touchscreen_data = {
173 .wires = 4,
174 .x_plate_resistance = 200,
175 };
177 static struct platform_device tsc_device = {
178 .name = "tsc",
179 .id = -1,
180 .dev = {
181 .platform_data = &am335x_touchscreen_data,
182 },
183 .num_resources = ARRAY_SIZE(tsc_resources),
184 .resource = tsc_resources,
185 };
187 static u8 am335x_iis_serializer_direction1[] = {
188 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
189 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
190 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
191 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
192 };
194 static struct snd_platform_data am335x_evm_snd_data1 = {
195 .tx_dma_offset = 0x46400000, /* McASP1 */
196 .rx_dma_offset = 0x46400000,
197 .op_mode = DAVINCI_MCASP_IIS_MODE,
198 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
199 .tdm_slots = 2,
200 .serial_dir = am335x_iis_serializer_direction1,
201 .asp_chan_q = EVENTQ_2,
202 .version = MCASP_VERSION_3,
203 .txnumevt = 1,
204 .rxnumevt = 1,
205 };
207 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
208 {
209 .mmc = 1,
210 .caps = MMC_CAP_4_BIT_DATA,
211 .gpio_cd = GPIO_TO_PIN(0, 6),
212 .gpio_wp = GPIO_TO_PIN(3, 18),
213 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
214 },
215 {
216 .mmc = 0, /* will be set at runtime */
217 },
218 {
219 .mmc = 0, /* will be set at runtime */
220 },
221 {} /* Terminator */
222 };
225 #ifdef CONFIG_OMAP_MUX
226 static struct omap_board_mux board_mux[] __initdata = {
227 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
228 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
229 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
230 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
231 { .reg_offset = OMAP_MUX_TERMINATOR },
232 };
233 #else
234 #define board_mux NULL
235 #endif
237 /* module pin mux structure */
238 struct pinmux_config {
239 const char *string_name; /* signal name format */
240 int val; /* Options for the mux register value */
241 };
243 struct evm_dev_cfg {
244 void (*device_init)(int evm_id, int profile);
246 /*
247 * If the device is required on both baseboard & daughter board (ex i2c),
248 * specify DEV_ON_BASEBOARD
249 */
250 #define DEV_ON_BASEBOARD 0
251 #define DEV_ON_DGHTR_BRD 1
252 u32 device_on;
254 u32 profile; /* Profiles (0-7) in which the module is present */
255 };
257 /* AM335X - CPLD Register Offsets */
258 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
259 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
260 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
261 #define CPLD_CFG_REG 0x10 /* Configuration Register */
263 static struct i2c_client *cpld_client;
264 static u32 am335x_evm_id;
265 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
266 };
268 /*
269 * EVM Config held in On-Board eeprom device.
270 *
271 * Header Format
272 *
273 * Name Size Contents
274 * (Bytes)
275 *-------------------------------------------------------------
276 * Header 4 0xAA, 0x55, 0x33, 0xEE
277 *
278 * Board Name 8 Name for board in ASCII.
279 * example "A33515BB" = "AM335X
280 Low Cost EVM board"
281 *
282 * Version 4 Hardware version code for board in
283 * in ASCII. "1.0A" = rev.01.0A
284 *
285 * Serial Number 12 Serial number of the board. This is a 12
286 * character string which is WWYY4P16nnnn, where
287 * WW = 2 digit week of the year of production
288 * YY = 2 digit year of production
289 * nnnn = incrementing board number
290 *
291 * Configuration option 32 Codes(TBD) to show the configuration
292 * setup on this board.
293 *
294 * Available 32720 Available space for other non-volatile
295 * data.
296 */
297 struct am335x_evm_eeprom_config {
298 u32 header;
299 u8 name[8];
300 char version[4];
301 u8 serial[12];
302 u8 opt[32];
303 };
305 static struct am335x_evm_eeprom_config config;
306 static bool daughter_brd_detected;
308 #define GP_EVM_REV_IS_1_0 0x1
309 #define GP_EVM_REV_IS_1_1A 0x2
310 #define GP_EVM_REV_IS_UNKNOWN 0xFF
311 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
312 unsigned int gigabit_enable = 1;
314 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
315 #define EEPROM_NO_OF_MAC_ADDR 3
316 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
318 #define AM335X_EEPROM_HEADER 0xEE3355AA
320 /* current profile if exists else PROFILE_0 on error */
321 static u32 am335x_get_profile_selection(void)
322 {
323 int val = 0;
325 if (!cpld_client)
326 /* error checking is not done in func's calling this routine.
327 so return profile 0 on error */
328 return 0;
330 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
331 if (val < 0)
332 return 0; /* default to Profile 0 on Error */
333 else
334 return val & 0x7;
335 }
337 /* Module pin mux for LCDC */
338 static struct pinmux_config lcdc_pin_mux[] = {
339 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
340 | AM33XX_PULL_DISA},
341 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
342 | AM33XX_PULL_DISA},
343 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
344 | AM33XX_PULL_DISA},
345 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
346 | AM33XX_PULL_DISA},
347 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
348 | AM33XX_PULL_DISA},
349 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
350 | AM33XX_PULL_DISA},
351 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
352 | AM33XX_PULL_DISA},
353 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
354 | AM33XX_PULL_DISA},
355 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
356 | AM33XX_PULL_DISA},
357 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
358 | AM33XX_PULL_DISA},
359 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
360 | AM33XX_PULL_DISA},
361 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
362 | AM33XX_PULL_DISA},
363 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
364 | AM33XX_PULL_DISA},
365 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
366 | AM33XX_PULL_DISA},
367 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
368 | AM33XX_PULL_DISA},
369 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
370 | AM33XX_PULL_DISA},
371 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
372 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
373 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
374 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
375 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
376 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
377 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
378 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
379 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
380 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
381 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
382 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
383 {NULL, 0},
384 };
386 static struct pinmux_config tsc_pin_mux[] = {
387 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
388 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
389 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
390 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
391 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
392 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
393 {NULL, 0},
394 };
396 /* Pin mux for nand flash module */
397 static struct pinmux_config nand_pin_mux[] = {
398 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
399 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
400 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
401 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
402 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
403 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
404 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
405 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
406 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
407 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
408 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
409 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
410 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
411 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
412 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
413 {NULL, 0},
414 };
416 /* Module pin mux for SPI fash */
417 static struct pinmux_config spi0_pin_mux[] = {
418 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
419 | AM33XX_INPUT_EN},
420 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
421 | AM33XX_INPUT_EN},
422 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
423 | AM33XX_INPUT_EN},
424 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
425 | AM33XX_INPUT_EN},
426 {NULL, 0},
427 };
429 /* Module pin mux for SPI flash */
430 static struct pinmux_config spi1_pin_mux[] = {
431 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
432 | AM33XX_INPUT_EN},
433 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
434 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
435 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
436 | AM33XX_INPUT_EN},
437 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
438 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
439 {NULL, 0},
440 };
442 /* Module pin mux for rgmii1 */
443 static struct pinmux_config rgmii1_pin_mux[] = {
444 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
445 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
446 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
447 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
448 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
449 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
450 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
451 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
452 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
453 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
454 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
455 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
456 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
457 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
458 {NULL, 0},
459 };
461 /* Module pin mux for rgmii2 */
462 static struct pinmux_config rgmii2_pin_mux[] = {
463 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
464 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
465 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
466 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
467 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
468 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
469 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
470 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
471 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
472 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
473 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
474 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
475 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
476 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
477 {NULL, 0},
478 };
480 /* Module pin mux for mii1 */
481 static struct pinmux_config mii1_pin_mux[] = {
482 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
483 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
484 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
485 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
486 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
487 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
488 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
489 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
490 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
491 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
492 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
493 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
494 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
495 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
496 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
497 {NULL, 0},
498 };
500 /* Module pin mux for rmii1 */
501 static struct pinmux_config rmii1_pin_mux[] = {
502 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
503 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
504 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
505 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
506 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
507 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
508 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
509 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
510 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
511 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
512 {NULL, 0},
513 };
515 static struct pinmux_config i2c1_pin_mux[] = {
516 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
517 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
518 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
519 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
520 {NULL, 0},
521 };
523 /* Module pin mux for mcasp1 */
524 static struct pinmux_config mcasp1_pin_mux[] = {
525 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
526 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
527 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
528 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
529 AM33XX_PIN_INPUT_PULLDOWN},
530 {NULL, 0},
531 };
534 /* Module pin mux for mmc0 */
535 static struct pinmux_config mmc0_pin_mux[] = {
536 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
537 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
538 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
539 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
540 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
541 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
542 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
543 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
544 {NULL, 0},
545 };
547 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
548 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
549 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
550 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
551 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
552 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
553 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
554 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
555 {NULL, 0},
556 };
558 /* Module pin mux for mmc1 */
559 static struct pinmux_config mmc1_pin_mux[] = {
560 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
561 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
562 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
563 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
564 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
565 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
566 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
567 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
568 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
569 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
570 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
571 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
572 {NULL, 0},
573 };
575 /* Module pin mux for uart3 */
576 static struct pinmux_config uart3_pin_mux[] = {
577 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
578 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
579 {NULL, 0},
580 };
582 static struct pinmux_config d_can_gp_pin_mux[] = {
583 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
584 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
585 {NULL, 0},
586 };
588 static struct pinmux_config d_can_ia_pin_mux[] = {
589 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
590 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
591 {NULL, 0},
592 };
594 /* Module pin mux for uart2 */
595 static struct pinmux_config uart2_pin_mux[] = {
596 {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
597 AM33XX_PIN_INPUT_PULLUP},
598 {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
599 AM33XX_PULL_DISA |
600 AM33XX_SLEWCTRL_SLOW},
601 {NULL, 0},
602 };
605 /*
606 * @pin_mux - single module pin-mux structure which defines pin-mux
607 * details for all its pins.
608 */
609 static void setup_pin_mux(struct pinmux_config *pin_mux)
610 {
611 int i;
613 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
614 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
616 }
618 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
620 /* pinmux for keypad device */
621 static struct pinmux_config matrix_keypad_pin_mux[] = {
622 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
623 {"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
624 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
625 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
626 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
627 {NULL, 0},
628 };
630 /* Keys mapping */
631 static const uint32_t am335x_evm_matrix_keys[] = {
632 KEY(0, 0, KEY_MENU),
633 KEY(1, 0, KEY_BACK),
634 KEY(2, 0, KEY_LEFT),
636 KEY(0, 1, KEY_RIGHT),
637 KEY(1, 1, KEY_ENTER),
638 KEY(2, 1, KEY_DOWN),
639 };
641 const struct matrix_keymap_data am335x_evm_keymap_data = {
642 .keymap = am335x_evm_matrix_keys,
643 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
644 };
646 static const unsigned int am335x_evm_keypad_row_gpios[] = {
647 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
648 };
650 static const unsigned int am335x_evm_keypad_col_gpios[] = {
651 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
652 };
654 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
655 .keymap_data = &am335x_evm_keymap_data,
656 .row_gpios = am335x_evm_keypad_row_gpios,
657 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
658 .col_gpios = am335x_evm_keypad_col_gpios,
659 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
660 .active_low = false,
661 .debounce_ms = 5,
662 .col_scan_delay_us = 2,
663 };
665 static struct platform_device am335x_evm_keyboard = {
666 .name = "matrix-keypad",
667 .id = -1,
668 .dev = {
669 .platform_data = &am335x_evm_keypad_platform_data,
670 },
671 };
673 static void matrix_keypad_init(int evm_id, int profile)
674 {
675 int err;
677 setup_pin_mux(matrix_keypad_pin_mux);
678 err = platform_device_register(&am335x_evm_keyboard);
679 if (err) {
680 pr_err("failed to register matrix keypad (2x3) device\n");
681 }
682 }
685 /* pinmux for keypad device */
686 static struct pinmux_config volume_keys_pin_mux[] = {
687 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
688 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
689 {NULL, 0},
690 };
692 /* Configure GPIOs for Volume Keys */
693 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
694 {
695 .code = KEY_VOLUMEUP,
696 .gpio = GPIO_TO_PIN(0, 2),
697 .active_low = true,
698 .desc = "volume-up",
699 .type = EV_KEY,
700 .wakeup = 1,
701 },
702 {
703 .code = KEY_VOLUMEDOWN,
704 .gpio = GPIO_TO_PIN(0, 3),
705 .active_low = true,
706 .desc = "volume-down",
707 .type = EV_KEY,
708 .wakeup = 1,
709 },
710 };
712 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
713 .buttons = am335x_evm_volume_gpio_buttons,
714 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
715 };
717 static struct platform_device am335x_evm_volume_keys = {
718 .name = "gpio-keys",
719 .id = -1,
720 .dev = {
721 .platform_data = &am335x_evm_volume_gpio_key_info,
722 },
723 };
725 static void volume_keys_init(int evm_id, int profile)
726 {
727 int err;
729 setup_pin_mux(volume_keys_pin_mux);
730 err = platform_device_register(&am335x_evm_volume_keys);
731 if (err)
732 pr_err("failed to register matrix keypad (2x3) device\n");
733 }
735 /*
736 * @evm_id - evm id which needs to be configured
737 * @dev_cfg - single evm structure which includes
738 * all module inits, pin-mux defines
739 * @profile - if present, else PROFILE_NONE
740 * @dghtr_brd_flg - Whether Daughter board is present or not
741 */
742 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
743 int profile)
744 {
745 int i;
747 /*
748 * Only General Purpose & Industrial Auto Motro Control
749 * EVM has profiles. So check if this evm has profile.
750 * If not, ignore the profile comparison
751 */
753 /*
754 * If the device is on baseboard, directly configure it. Else (device on
755 * Daughter board), check if the daughter card is detected.
756 */
757 if (profile == PROFILE_NONE) {
758 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
759 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
760 dev_cfg->device_init(evm_id, profile);
761 else if (daughter_brd_detected == true)
762 dev_cfg->device_init(evm_id, profile);
763 }
764 } else {
765 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
766 if (dev_cfg->profile & profile) {
767 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
768 dev_cfg->device_init(evm_id, profile);
769 else if (daughter_brd_detected == true)
770 dev_cfg->device_init(evm_id, profile);
771 }
772 }
773 }
774 }
776 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
778 /* pinmux for usb0 drvvbus */
779 static struct pinmux_config usb0_pin_mux[] = {
780 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
781 {NULL, 0},
782 };
784 /* pinmux for usb1 drvvbus */
785 static struct pinmux_config usb1_pin_mux[] = {
786 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
787 {NULL, 0},
788 };
790 /* pinmux for profibus */
791 static struct pinmux_config profibus_pin_mux[] = {
792 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
793 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
794 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
795 {NULL, 0},
796 };
798 /* Module pin mux for eCAP0 */
799 static struct pinmux_config ecap0_pin_mux[] = {
800 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
801 {NULL, 0},
802 };
804 static int backlight_enable;
806 #define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
807 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
809 struct wl12xx_platform_data am335xevm_wlan_data = {
810 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
811 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
812 };
814 /* Module pin mux for wlan and bluetooth */
815 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
816 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
817 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
818 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
819 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
820 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
821 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
822 {NULL, 0},
823 };
825 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
826 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
827 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
828 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
829 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
830 {NULL, 0},
831 };
833 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
834 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
835 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
836 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
837 {NULL, 0},
838 };
840 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
841 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
842 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
843 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
844 {NULL, 0},
845 };
847 static void enable_ecap0(int evm_id, int profile)
848 {
849 backlight_enable = true;
850 }
852 static void am335x_gpio_bl_ctrl(int val)
853 {
854 /* lcd backlight */
855 gpio_set_value(AM335X_LCD_BL_PIN, val);
856 }
858 static int __init ecap0_init(void)
859 {
860 int status = 0;
862 if (backlight_enable) {
863 setup_pin_mux(ecap0_pin_mux);
865 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
866 if (status < 0)
867 pr_warn("Failed to request gpio for LCD backlight\n");
869 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
870 }
871 return status;
872 }
873 late_initcall(ecap0_init);
875 static int __init conf_disp_pll(int rate)
876 {
877 struct clk *disp_pll;
878 int ret = -EINVAL;
880 disp_pll = clk_get(NULL, "dpll_disp_ck");
881 if (IS_ERR(disp_pll)) {
882 pr_err("Cannot clk_get disp_pll\n");
883 goto out;
884 }
886 ret = clk_set_rate(disp_pll, rate);
887 clk_put(disp_pll);
888 out:
889 return ret;
890 }
892 static void lcdc_init(int evm_id, int profile)
893 {
895 setup_pin_mux(lcdc_pin_mux);
897 if (conf_disp_pll(300000000)) {
898 pr_info("Failed configure display PLL, not attempting to"
899 "register LCDC\n");
900 return;
901 }
903 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
904 pr_info("Failed to register LCDC device\n");
905 return;
906 }
908 static void tsc_init(int evm_id, int profile)
909 {
910 int err;
912 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
913 am335x_touchscreen_data.analog_input = 1;
914 pr_info("TSC connected to beta GP EVM\n");
915 } else {
916 am335x_touchscreen_data.analog_input = 0;
917 pr_info("TSC connected to alpha GP EVM\n");
918 }
919 setup_pin_mux(tsc_pin_mux);
920 err = platform_device_register(&tsc_device);
921 if (err)
922 pr_err("failed to register touchscreen device\n");
923 }
925 static void rgmii1_init(int evm_id, int profile)
926 {
927 setup_pin_mux(rgmii1_pin_mux);
928 return;
929 }
931 static void rgmii2_init(int evm_id, int profile)
932 {
933 setup_pin_mux(rgmii2_pin_mux);
934 return;
935 }
937 static void mii1_init(int evm_id, int profile)
938 {
939 setup_pin_mux(mii1_pin_mux);
940 return;
941 }
943 static void rmii1_init(int evm_id, int profile)
944 {
945 setup_pin_mux(rmii1_pin_mux);
946 return;
947 }
949 static void usb0_init(int evm_id, int profile)
950 {
951 setup_pin_mux(usb0_pin_mux);
952 return;
953 }
955 static void usb1_init(int evm_id, int profile)
956 {
957 setup_pin_mux(usb1_pin_mux);
958 return;
959 }
961 /* setup uart3 */
962 static void uart3_init(int evm_id, int profile)
963 {
964 setup_pin_mux(uart3_pin_mux);
965 return;
966 }
968 /* setup uart2 */
969 static void uart2_init(int evm_id, int profile)
970 {
971 setup_pin_mux(uart2_pin_mux);
972 return;
973 }
975 /* NAND partition information */
976 static struct mtd_partition am335x_nand_partitions[] = {
977 /* All the partition sizes are listed in terms of NAND block size */
978 {
979 .name = "SPL",
980 .offset = 0, /* Offset = 0x0 */
981 .size = SZ_128K,
982 },
983 {
984 .name = "SPL.backup1",
985 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
986 .size = SZ_128K,
987 },
988 {
989 .name = "SPL.backup2",
990 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
991 .size = SZ_128K,
992 },
993 {
994 .name = "SPL.backup3",
995 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
996 .size = SZ_128K,
997 },
998 {
999 .name = "U-Boot",
1000 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
1001 .size = 15 * SZ_128K,
1002 },
1003 {
1004 .name = "U-Boot Env",
1005 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
1006 .size = 1 * SZ_128K,
1007 },
1008 {
1009 .name = "Kernel",
1010 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
1011 .size = 40 * SZ_128K,
1012 },
1013 {
1014 .name = "File System",
1015 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
1016 .size = MTDPART_SIZ_FULL,
1017 },
1018 };
1020 /* SPI 0/1 Platform Data */
1021 /* SPI flash information */
1022 static struct mtd_partition am335x_spi_partitions[] = {
1023 /* All the partition sizes are listed in terms of erase size */
1024 {
1025 .name = "SPL",
1026 .offset = 0, /* Offset = 0x0 */
1027 .size = SZ_128K,
1028 },
1029 {
1030 .name = "U-Boot",
1031 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
1032 .size = 2 * SZ_128K,
1033 },
1034 {
1035 .name = "U-Boot Env",
1036 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
1037 .size = 2 * SZ_4K,
1038 },
1039 {
1040 .name = "Kernel",
1041 .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
1042 .size = 28 * SZ_128K,
1043 },
1044 {
1045 .name = "File System",
1046 .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
1047 .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
1048 }
1049 };
1051 static const struct flash_platform_data am335x_spi_flash = {
1052 .type = "w25q64",
1053 .name = "spi_flash",
1054 .parts = am335x_spi_partitions,
1055 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
1056 };
1058 /*
1059 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1060 * So setup Max speed to be less than that of Controller speed
1061 */
1062 static struct spi_board_info am335x_spi0_slave_info[] = {
1063 {
1064 .modalias = "m25p80",
1065 .platform_data = &am335x_spi_flash,
1066 .irq = -1,
1067 .max_speed_hz = 24000000,
1068 .bus_num = 1,
1069 .chip_select = 0,
1070 },
1071 };
1073 static struct spi_board_info am335x_spi1_slave_info[] = {
1074 {
1075 .modalias = "m25p80",
1076 .platform_data = &am335x_spi_flash,
1077 .irq = -1,
1078 .max_speed_hz = 12000000,
1079 .bus_num = 2,
1080 .chip_select = 0,
1081 },
1082 };
1084 static void evm_nand_init(int evm_id, int profile)
1085 {
1086 setup_pin_mux(nand_pin_mux);
1087 board_nand_init(am335x_nand_partitions,
1088 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1089 }
1091 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1092 .click_flags = LIS3_CLICK_SINGLE_X |
1093 LIS3_CLICK_SINGLE_Y |
1094 LIS3_CLICK_SINGLE_Z,
1095 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1096 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1097 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1098 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1099 .wakeup_thresh = 10,
1100 .click_thresh_x = 10,
1101 .click_thresh_y = 10,
1102 .click_thresh_z = 10,
1103 .g_range = 2,
1104 .st_min_limits[0] = 120,
1105 .st_min_limits[1] = 120,
1106 .st_min_limits[2] = 140,
1107 .st_max_limits[0] = 550,
1108 .st_max_limits[1] = 550,
1109 .st_max_limits[2] = 750,
1110 };
1112 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1113 {
1114 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1115 },
1116 {
1117 I2C_BOARD_INFO("lis331dlh", 0x18),
1118 .platform_data = &lis331dlh_pdata,
1119 },
1120 {
1121 I2C_BOARD_INFO("tsl2550", 0x39),
1122 },
1123 {
1124 I2C_BOARD_INFO("tmp275", 0x48),
1125 },
1126 };
1128 static void i2c1_init(int evm_id, int profile)
1129 {
1130 setup_pin_mux(i2c1_pin_mux);
1131 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1132 ARRAY_SIZE(am335x_i2c_boardinfo1));
1133 return;
1134 }
1136 /* Setup McASP 1 */
1137 static void mcasp1_init(int evm_id, int profile)
1138 {
1139 /* Configure McASP */
1140 setup_pin_mux(mcasp1_pin_mux);
1141 am335x_register_mcasp1(&am335x_evm_snd_data1);
1142 return;
1143 }
1145 static void mmc1_init(int evm_id, int profile)
1146 {
1147 setup_pin_mux(mmc1_pin_mux);
1149 am335x_mmc[1].mmc = 2;
1150 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1151 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1152 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1153 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1155 /* mmc will be initialized when mmc0_init is called */
1156 return;
1157 }
1159 static void mmc2_wl12xx_init(int evm_id, int profile)
1160 {
1161 setup_pin_mux(mmc2_wl12xx_pin_mux);
1163 am335x_mmc[1].mmc = 3;
1164 am335x_mmc[1].name = "wl1271";
1165 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1166 | MMC_PM_KEEP_POWER;
1167 am335x_mmc[1].nonremovable = true;
1168 am335x_mmc[1].gpio_cd = -EINVAL;
1169 am335x_mmc[1].gpio_wp = -EINVAL;
1170 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1172 /* mmc will be initialized when mmc0_init is called */
1173 return;
1174 }
1176 static void uart1_wl12xx_init(int evm_id, int profile)
1177 {
1178 setup_pin_mux(uart1_wl12xx_pin_mux);
1179 }
1181 static void wl12xx_bluetooth_enable(void)
1182 {
1183 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1184 "bt_en\n");
1185 if (status < 0)
1186 pr_err("Failed to request gpio for bt_enable");
1188 pr_info("Configure Bluetooth Enable pin...\n");
1189 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1190 }
1192 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1193 {
1194 if (on) {
1195 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1196 mdelay(70);
1197 }
1198 else
1199 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1201 return 0;
1202 }
1204 static void wl12xx_init(int evm_id, int profile)
1205 {
1206 struct device *dev;
1207 struct omap_mmc_platform_data *pdata;
1208 int ret;
1210 /* Register WLAN and BT enable pins based on the evm board revision */
1211 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1212 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1213 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1214 }
1215 else {
1216 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1217 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1218 }
1220 wl12xx_bluetooth_enable();
1222 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1223 pr_err("error setting wl12xx data\n");
1225 dev = am335x_mmc[1].dev;
1226 if (!dev) {
1227 pr_err("wl12xx mmc device initialization failed\n");
1228 goto out;
1229 }
1231 pdata = dev->platform_data;
1232 if (!pdata) {
1233 pr_err("Platfrom data of wl12xx device not set\n");
1234 goto out;
1235 }
1237 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1238 GPIOF_OUT_INIT_LOW, "wlan_en");
1239 if (ret) {
1240 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1241 goto out;
1242 }
1244 if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1245 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1246 else
1247 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1249 pdata->slots[0].set_power = wl12xx_set_power;
1250 out:
1251 return;
1252 }
1254 static void d_can_init(int evm_id, int profile)
1255 {
1256 switch (evm_id) {
1257 case IND_AUT_MTR_EVM:
1258 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1259 setup_pin_mux(d_can_ia_pin_mux);
1260 /* Instance Zero */
1261 am33xx_d_can_init(0);
1262 }
1263 break;
1264 case GEN_PURP_EVM:
1265 if (profile == PROFILE_1) {
1266 setup_pin_mux(d_can_gp_pin_mux);
1267 /* Instance One */
1268 am33xx_d_can_init(1);
1269 }
1270 break;
1271 default:
1272 break;
1273 }
1274 }
1276 static void mmc0_init(int evm_id, int profile)
1277 {
1278 setup_pin_mux(mmc0_pin_mux);
1280 omap2_hsmmc_init(am335x_mmc);
1281 return;
1282 }
1284 static void mmc0_no_cd_init(int evm_id, int profile)
1285 {
1286 setup_pin_mux(mmc0_no_cd_pin_mux);
1288 omap2_hsmmc_init(am335x_mmc);
1289 return;
1290 }
1293 /* setup spi0 */
1294 static void spi0_init(int evm_id, int profile)
1295 {
1296 setup_pin_mux(spi0_pin_mux);
1297 spi_register_board_info(am335x_spi0_slave_info,
1298 ARRAY_SIZE(am335x_spi0_slave_info));
1299 return;
1300 }
1302 /* setup spi1 */
1303 static void spi1_init(int evm_id, int profile)
1304 {
1305 setup_pin_mux(spi1_pin_mux);
1306 spi_register_board_info(am335x_spi1_slave_info,
1307 ARRAY_SIZE(am335x_spi1_slave_info));
1308 return;
1309 }
1312 static int beaglebone_phy_fixup(struct phy_device *phydev)
1313 {
1314 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1315 SUPPORTED_100baseT_Full);
1317 return 0;
1318 }
1320 #if defined(CONFIG_TLK110_WORKAROUND) || \
1321 defined(CONFIG_TLK110_WORKAROUND_MODULE)
1322 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1323 {
1324 unsigned int val;
1326 /* This is done as a workaround to support TLK110 rev1.0 phy */
1327 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1328 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1330 val = phy_read(phydev, TLK110_LPFHPF_REG);
1331 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1333 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1334 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1336 val = phy_read(phydev, TLK110_VRCR_REG);
1337 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1339 val = phy_read(phydev, TLK110_SETFFE_REG);
1340 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1342 val = phy_read(phydev, TLK110_FTSP_REG);
1343 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1345 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1346 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1348 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1349 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1351 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1352 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1354 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1355 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1357 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1358 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1360 val = phy_read(phydev, TLK110_CFGPS_REG);
1361 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1363 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1364 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1366 val = phy_read(phydev, TLK110_SWSCR3_REG);
1367 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1369 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1370 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1372 val = phy_read(phydev, TLK110_PHYRCR_REG);
1373 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1375 return 0;
1376 }
1377 #endif
1379 static void profibus_init(int evm_id, int profile)
1380 {
1381 setup_pin_mux(profibus_pin_mux);
1382 return;
1383 }
1385 /* Low-Cost EVM */
1386 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1387 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1388 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1389 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1390 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1391 {NULL, 0, 0},
1392 };
1394 /* General Purpose EVM */
1395 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1396 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1397 PROFILE_2 | PROFILE_7) },
1398 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1399 PROFILE_2 | PROFILE_7) },
1400 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1401 PROFILE_2 | PROFILE_7) },
1402 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1403 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1404 PROFILE_4 | PROFILE_6) },
1405 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1406 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1407 {evm_nand_init, DEV_ON_DGHTR_BRD,
1408 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1409 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1410 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1411 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1412 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1413 PROFILE_5)},
1414 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1415 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1416 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1417 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1418 PROFILE_5)},
1419 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1420 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
1421 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1422 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1423 {uart2_init, DEV_ON_DGHTR_BRD, PROFILE_3},
1424 {NULL, 0, 0},
1425 };
1427 /* Industrial Auto Motor Control EVM */
1428 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1429 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1430 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1431 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1432 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1433 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1434 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1435 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1436 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1437 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1438 {NULL, 0, 0},
1439 };
1441 /* IP-Phone EVM */
1442 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1443 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1444 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1445 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1446 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1447 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1448 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1449 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1450 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1451 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1452 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1453 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1454 {NULL, 0, 0},
1455 };
1457 /* Beaglebone < Rev A3 */
1458 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1459 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1460 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1461 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1462 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1463 {NULL, 0, 0},
1464 };
1466 /* Beaglebone Rev A3 and after */
1467 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1468 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1469 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1470 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1471 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1472 {NULL, 0, 0},
1473 };
1475 static void setup_low_cost_evm(void)
1476 {
1477 pr_info("The board is a AM335x Low Cost EVM.\n");
1479 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1480 }
1482 static void setup_general_purpose_evm(void)
1483 {
1484 u32 prof_sel = am335x_get_profile_selection();
1485 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1487 if (!strncmp("1.1A", config.version, 4)) {
1488 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1489 } else if (!strncmp("1.0", config.version, 3)) {
1490 gp_evm_revision = GP_EVM_REV_IS_1_0;
1491 } else {
1492 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1493 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1494 }
1496 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1497 gigabit_enable = 0;
1498 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1499 gigabit_enable = 1;
1501 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1502 }
1504 static void setup_ind_auto_motor_ctrl_evm(void)
1505 {
1506 u32 prof_sel = am335x_get_profile_selection();
1508 pr_info("The board is an industrial automation EVM in profile %d\n",
1509 prof_sel);
1511 /* Only Profile 0 is supported */
1512 if ((1L << prof_sel) != PROFILE_0) {
1513 pr_err("AM335X: Only Profile 0 is supported\n");
1514 pr_err("Assuming profile 0 & continuing\n");
1515 prof_sel = PROFILE_0;
1516 }
1518 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1519 PROFILE_0);
1521 /* Fillup global evmid */
1522 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1524 /* Initialize TLK110 PHY registers for phy version 1.0 */
1525 am335x_tlk110_phy_init();
1528 }
1530 static void setup_ip_phone_evm(void)
1531 {
1532 pr_info("The board is an IP phone EVM\n");
1534 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1535 }
1537 /* BeagleBone < Rev A3 */
1538 static void setup_beaglebone_old(void)
1539 {
1540 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1542 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1543 am335x_mmc[0].gpio_wp = -EINVAL;
1545 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1547 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1548 beaglebone_phy_fixup);
1550 /* Fill up global evmid */
1551 am33xx_evmid_fillup(BEAGLE_BONE_OLD);
1552 }
1554 /* BeagleBone after Rev A3 */
1555 static void setup_beaglebone(void)
1556 {
1557 pr_info("The board is a AM335x Beaglebone.\n");
1559 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1560 am335x_mmc[0].gpio_wp = -EINVAL;
1562 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1564 /* Fill up global evmid */
1565 am33xx_evmid_fillup(BEAGLE_BONE_A3);
1566 }
1569 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1570 {
1571 u8 tmp;
1572 int ret;
1574 /*
1575 * try reading a byte from the EEPROM to see if it is
1576 * present. We could read a lot more, but that would
1577 * just slow the boot process and we have all the information
1578 * we need from the EEPROM on the base board anyway.
1579 */
1580 ret = m->read(m, &tmp, 0, sizeof(u8));
1581 if (ret == sizeof(u8)) {
1582 pr_info("Detected a daughter card on AM335x EVM..");
1583 daughter_brd_detected = true;
1584 } else {
1585 pr_info("No daughter card found\n");
1586 daughter_brd_detected = false;
1587 }
1588 }
1590 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1591 {
1592 int ret;
1593 char tmp[10];
1595 /* 1st get the MAC address from EEPROM */
1596 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1597 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1599 if (ret != sizeof(am335x_mac_addr)) {
1600 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1601 return;
1602 }
1604 /* Fillup global mac id */
1605 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1606 &am335x_mac_addr[1][0]);
1608 /* get board specific data */
1609 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1610 if (ret != sizeof(config)) {
1611 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1612 return;
1613 }
1615 if (config.header != AM335X_EEPROM_HEADER) {
1616 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1617 config.header, AM335X_EEPROM_HEADER);
1618 goto out;
1619 }
1621 if (strncmp("A335", config.name, 4)) {
1622 pr_err("Board %s doesn't look like an AM335x board\n",
1623 config.name);
1624 goto out;
1625 }
1627 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1628 pr_info("Board name: %s\n", tmp);
1629 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1630 pr_info("Board version: %s\n", tmp);
1632 if (!strncmp("A335BONE", config.name, 8)) {
1633 daughter_brd_detected = false;
1634 if(!strncmp("00A1", config.version, 4) ||
1635 !strncmp("00A2", config.version, 4))
1636 setup_beaglebone_old();
1637 else
1638 setup_beaglebone();
1639 } else {
1640 /* only 6 characters of options string used for now */
1641 snprintf(tmp, 7, "%s", config.opt);
1642 pr_info("SKU: %s\n", tmp);
1644 if (!strncmp("SKU#00", config.opt, 6))
1645 setup_low_cost_evm();
1646 else if (!strncmp("SKU#01", config.opt, 6))
1647 setup_general_purpose_evm();
1648 else if (!strncmp("SKU#02", config.opt, 6))
1649 setup_ind_auto_motor_ctrl_evm();
1650 else if (!strncmp("SKU#03", config.opt, 6))
1651 setup_ip_phone_evm();
1652 else
1653 goto out;
1654 }
1655 /* Initialize cpsw after board detection is completed as board
1656 * information is required for configuring phy address and hence
1657 * should be call only after board detection
1658 */
1659 am33xx_cpsw_init(gigabit_enable);
1661 return;
1662 out:
1663 /*
1664 * If the EEPROM hasn't been programed or an incorrect header
1665 * or board name are read, assume this is an old beaglebone board
1666 * (< Rev A3)
1667 */
1668 pr_err("Could not detect any board, falling back to: "
1669 "Beaglebone (< Rev A3) with no daughter card connected\n");
1670 daughter_brd_detected = false;
1671 setup_beaglebone_old();
1673 /* Initialize cpsw after board detection is completed as board
1674 * information is required for configuring phy address and hence
1675 * should be call only after board detection
1676 */
1678 am33xx_cpsw_init(gigabit_enable);
1679 }
1681 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1682 .byte_len = (256*1024) / 8,
1683 .page_size = 64,
1684 .flags = AT24_FLAG_ADDR16,
1685 .setup = am335x_setup_daughter_board,
1686 .context = (void *)NULL,
1687 };
1689 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1690 .byte_len = (256*1024) / 8,
1691 .page_size = 64,
1692 .flags = AT24_FLAG_ADDR16,
1693 .setup = am335x_evm_setup,
1694 .context = (void *)NULL,
1695 };
1697 static struct regulator_init_data am335x_dummy = {
1698 .constraints.always_on = true,
1699 };
1701 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
1702 REGULATOR_SUPPLY("vdd_mpu", NULL),
1703 };
1705 static struct regulator_init_data am335x_vdd1 = {
1706 .constraints = {
1707 .min_uV = 600000,
1708 .max_uV = 1500000,
1709 .valid_modes_mask = REGULATOR_MODE_NORMAL,
1710 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
1711 .always_on = 1,
1712 },
1713 .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply),
1714 .consumer_supplies = am335x_vdd1_supply,
1715 };
1717 static struct tps65910_board am335x_tps65910_info = {
1718 .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy,
1719 .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy,
1720 .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1,
1721 .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy,
1722 .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy,
1723 .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy,
1724 .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy,
1725 .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy,
1726 .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy,
1727 .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy,
1728 .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy,
1729 .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy,
1730 .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy,
1731 };
1733 /*
1734 * Daughter board Detection.
1735 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1736 * machine init, starting from daughter board and ending with baseboard.
1737 * Assumptions :
1738 * 1. probe for i2c devices are called in the order they are included in
1739 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
1740 * eeprom probe is called last.
1741 */
1742 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1743 {
1744 /* Daughter Board EEPROM */
1745 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1746 .platform_data = &am335x_daughter_board_eeprom_info,
1747 },
1748 {
1749 /* Baseboard board EEPROM */
1750 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1751 .platform_data = &am335x_baseboard_eeprom_info,
1752 },
1753 {
1754 I2C_BOARD_INFO("cpld_reg", 0x35),
1755 },
1756 {
1757 I2C_BOARD_INFO("tlc59108", 0x40),
1758 },
1759 {
1760 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
1761 .platform_data = &am335x_tps65910_info,
1762 },
1764 };
1766 static struct omap_musb_board_data musb_board_data = {
1767 .interface_type = MUSB_INTERFACE_ULPI,
1768 /*
1769 * mode[0:3] = USB0PORT's mode
1770 * mode[4:7] = USB1PORT's mode
1771 * AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
1772 */
1773 .mode = (MUSB_HOST << 4) | MUSB_OTG,
1774 .power = 500,
1775 .instances = 1,
1776 };
1778 static int cpld_reg_probe(struct i2c_client *client,
1779 const struct i2c_device_id *id)
1780 {
1781 cpld_client = client;
1782 return 0;
1783 }
1785 static int __devexit cpld_reg_remove(struct i2c_client *client)
1786 {
1787 cpld_client = NULL;
1788 return 0;
1789 }
1791 static const struct i2c_device_id cpld_reg_id[] = {
1792 { "cpld_reg", 0 },
1793 { }
1794 };
1796 static struct i2c_driver cpld_reg_driver = {
1797 .driver = {
1798 .name = "cpld_reg",
1799 },
1800 .probe = cpld_reg_probe,
1801 .remove = cpld_reg_remove,
1802 .id_table = cpld_reg_id,
1803 };
1805 static void evm_init_cpld(void)
1806 {
1807 i2c_add_driver(&cpld_reg_driver);
1808 }
1810 static void __init am335x_evm_i2c_init(void)
1811 {
1812 /* Initially assume Low Cost EVM Config */
1813 am335x_evm_id = LOW_COST_EVM;
1815 evm_init_cpld();
1817 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1818 ARRAY_SIZE(am335x_i2c_boardinfo));
1819 }
1821 static struct resource am335x_rtc_resources[] = {
1822 {
1823 .start = AM33XX_RTC_BASE,
1824 .end = AM33XX_RTC_BASE + SZ_4K - 1,
1825 .flags = IORESOURCE_MEM,
1826 },
1827 { /* timer irq */
1828 .start = AM33XX_IRQ_RTC_TIMER,
1829 .end = AM33XX_IRQ_RTC_TIMER,
1830 .flags = IORESOURCE_IRQ,
1831 },
1832 { /* alarm irq */
1833 .start = AM33XX_IRQ_RTC_ALARM,
1834 .end = AM33XX_IRQ_RTC_ALARM,
1835 .flags = IORESOURCE_IRQ,
1836 },
1837 };
1839 static struct platform_device am335x_rtc_device = {
1840 .name = "omap_rtc",
1841 .id = -1,
1842 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
1843 .resource = am335x_rtc_resources,
1844 };
1846 static int am335x_rtc_init(void)
1847 {
1848 void __iomem *base;
1849 struct clk *clk;
1851 clk = clk_get(NULL, "rtc_fck");
1852 if (IS_ERR(clk)) {
1853 pr_err("rtc : Failed to get RTC clock\n");
1854 return -1;
1855 }
1857 if (clk_enable(clk)) {
1858 pr_err("rtc: Clock Enable Failed\n");
1859 return -1;
1860 }
1862 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1864 if (WARN_ON(!base))
1865 return -ENOMEM;
1867 /* Unlock the rtc's registers */
1868 __raw_writel(0x83e70b13, base + 0x6c);
1869 __raw_writel(0x95a4f1e0, base + 0x70);
1871 /*
1872 * Enable the 32K OSc
1873 * TODO: Need a better way to handle this
1874 * Since we want the clock to be running before mmc init
1875 * we need to do it before the rtc probe happens
1876 */
1877 __raw_writel(0x48, base + 0x54);
1879 iounmap(base);
1881 return platform_device_register(&am335x_rtc_device);
1882 }
1884 /* Enable clkout2 */
1885 static struct pinmux_config clkout2_pin_mux[] = {
1886 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1887 {NULL, 0},
1888 };
1890 static void __init clkout2_enable(void)
1891 {
1892 struct clk *ck_32;
1894 ck_32 = clk_get(NULL, "clkout2_ck");
1895 if (IS_ERR(ck_32)) {
1896 pr_err("Cannot clk_get ck_32\n");
1897 return;
1898 }
1900 clk_enable(ck_32);
1902 setup_pin_mux(clkout2_pin_mux);
1903 }
1905 void __iomem * __init am33xx_get_mem_ctlr(void)
1906 {
1907 void __iomem *am33xx_emif_base;
1909 am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1911 if (!am33xx_emif_base)
1912 pr_warning("%s: Unable to map DDR2 controller", __func__);
1914 return am33xx_emif_base;
1915 }
1917 static struct resource am33xx_cpuidle_resources[] = {
1918 {
1919 .start = AM33XX_EMIF0_BASE,
1920 .end = AM33XX_EMIF0_BASE + SZ_32K - 1,
1921 .flags = IORESOURCE_MEM,
1922 },
1923 };
1925 /* AM33XX devices support DDR2 power down */
1926 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1927 .ddr2_pdown = 1,
1928 };
1930 static struct platform_device am33xx_cpuidle_device = {
1931 .name = "cpuidle-am33xx",
1932 .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
1933 .resource = am33xx_cpuidle_resources,
1934 .dev = {
1935 .platform_data = &am33xx_cpuidle_pdata,
1936 },
1937 };
1939 static void __init am33xx_cpuidle_init(void)
1940 {
1941 int ret;
1943 am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1945 ret = platform_device_register(&am33xx_cpuidle_device);
1947 if (ret)
1948 pr_warning("AM33XX cpuidle registration failed\n");
1950 }
1952 static void __init am335x_evm_init(void)
1953 {
1954 am33xx_cpuidle_init();
1955 am33xx_mux_init(board_mux);
1956 omap_serial_init();
1957 am335x_rtc_init();
1958 clkout2_enable();
1959 am335x_evm_i2c_init();
1960 omap_sdrc_init(NULL, NULL);
1961 usb_musb_init(&musb_board_data);
1962 omap_board_config = am335x_evm_config;
1963 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1964 /* Create an alias for icss clock */
1965 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1966 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1967 /* Create an alias for gfx/sgx clock */
1968 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1969 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1970 }
1972 static void __init am335x_evm_map_io(void)
1973 {
1974 omap2_set_globals_am33xx();
1975 omapam33xx_map_common_io();
1976 }
1978 MACHINE_START(AM335XEVM, "am335xevm")
1979 /* Maintainer: Texas Instruments */
1980 .atag_offset = 0x100,
1981 .map_io = am335x_evm_map_io,
1982 .init_early = am33xx_init_early,
1983 .init_irq = ti81xx_init_irq,
1984 .handle_irq = omap3_intc_handle_irq,
1985 .timer = &omap3_am33xx_timer,
1986 .init_machine = am335x_evm_init,
1987 MACHINE_END
1989 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1990 /* Maintainer: Texas Instruments */
1991 .atag_offset = 0x100,
1992 .map_io = am335x_evm_map_io,
1993 .init_irq = ti81xx_init_irq,
1994 .init_early = am33xx_init_early,
1995 .timer = &omap3_am33xx_timer,
1996 .init_machine = am335x_evm_init,
1997 MACHINE_END