81d9b84afde2aac2eecc16d04940b16b85f06fcd
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / board-am335xevm.c
1 /*
2  * Code for AM335X EVM.
3  *
4  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
35 #include <linux/mfd/tps65910.h>
36 #include <linux/pwm_backlight.h>
38 /* LCD controller is similar to DA850 */
39 #include <video/da8xx-fb.h>
41 #include <mach/hardware.h>
42 #include <mach/board-am335xevm.h>
44 #include <asm/mach-types.h>
45 #include <asm/mach/arch.h>
46 #include <asm/mach/map.h>
47 #include <asm/hardware/asp.h>
49 #include <plat/irqs.h>
50 #include <plat/board.h>
51 #include <plat/common.h>
52 #include <plat/lcdc.h>
53 #include <plat/usb.h>
54 #include <plat/mmc.h>
56 #include "board-flash.h"
57 #include "cpuidle33xx.h"
58 #include "mux.h"
59 #include "devices.h"
60 #include "hsmmc.h"
62 /* Convert GPIO signal to GPIO pin number */
63 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
65 /* TLK PHY IDs */
66 #define TLK110_PHY_ID           0x2000A201
67 #define TLK110_PHY_MASK         0xfffffff0
69 /* BBB PHY IDs */
70 #define BBB_PHY_ID              0x7c0f1
71 #define BBB_PHY_MASK            0xfffffffe
73 /* TLK110 PHY register offsets */
74 #define TLK110_COARSEGAIN_REG   0x00A3
75 #define TLK110_LPFHPF_REG       0x00AC
76 #define TLK110_SPAREANALOG_REG  0x00B9
77 #define TLK110_VRCR_REG         0x00D0
78 #define TLK110_SETFFE_REG       0x0107
79 #define TLK110_FTSP_REG         0x0154
80 #define TLK110_ALFATPIDL_REG    0x002A
81 #define TLK110_PSCOEF21_REG     0x0096
82 #define TLK110_PSCOEF3_REG      0x0097
83 #define TLK110_ALFAFACTOR1_REG  0x002C
84 #define TLK110_ALFAFACTOR2_REG  0x0023
85 #define TLK110_CFGPS_REG        0x0095
86 #define TLK110_FTSPTXGAIN_REG   0x0150
87 #define TLK110_SWSCR3_REG       0x000B
88 #define TLK110_SCFALLBACK_REG   0x0040
89 #define TLK110_PHYRCR_REG       0x001F
91 /* TLK110 register writes values */
92 #define TLK110_COARSEGAIN_VAL   0x0000
93 #define TLK110_LPFHPF_VAL       0x8000
94 #define TLK110_SPANALOG_VAL     0x0000
95 #define TLK110_VRCR_VAL         0x0008
96 #define TLK110_SETFFE_VAL       0x0605
97 #define TLK110_FTSP_VAL         0x0255
98 #define TLK110_ALFATPIDL_VAL    0x7998
99 #define TLK110_PSCOEF21_VAL     0x3A20
100 #define TLK110_PSCOEF3_VAL      0x003F
101 #define TLK110_ALFACTOR1_VAL    0xFF80
102 #define TLK110_ALFACTOR2_VAL    0x021C
103 #define TLK110_CFGPS_VAL        0x0000
104 #define TLK110_FTSPTXGAIN_VAL   0x6A88
105 #define TLK110_SWSCR3_VAL       0x0000
106 #define TLK110_SCFALLBACK_VAL   0xC11D
107 #define TLK110_PHYRCR_VAL       0x4000
109 #if defined(CONFIG_TLK110_WORKAROUND) || \
110                 defined(CONFIG_TLK110_WORKAROUND_MODULE)
111 #define am335x_tlk110_phy_init()\
112         do {    \
113                 phy_register_fixup_for_uid(TLK110_PHY_ID,\
114                                         TLK110_PHY_MASK,\
115                                         am335x_tlk110_phy_fixup);\
116         } while (0);
117 #else
118 #define am335x_tlk110_phy_init() do { } while (0);
119 #endif
121 static const struct display_panel disp_panel = {
122         WVGA,
123         32,
124         32,
125         COLOR_ACTIVE,
126 };
128 /* LCD backlight platform Data */
129 #define AM335X_BACKLIGHT_MAX_BRIGHTNESS        100
130 #define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS    100
131 #define AM335X_PWM_PERIOD_NANO_SECONDS        (10000 * 10)
133 #define PWM_DEVICE_ID   "ecap.0"
135 static struct platform_pwm_backlight_data am335x_backlight_data = {
136         .pwm_id         = PWM_DEVICE_ID,
137         .ch             = -1,
138         .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
139         .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
140         .pwm_period_ns  = AM335X_PWM_PERIOD_NANO_SECONDS,
141 };
143 static struct lcd_ctrl_config lcd_cfg = {
144         &disp_panel,
145         .ac_bias                = 255,
146         .ac_bias_intrpt         = 0,
147         .dma_burst_sz           = 16,
148         .bpp                    = 32,
149         .fdd                    = 0x80,
150         .tft_alt_mode           = 0,
151         .stn_565_mode           = 0,
152         .mono_8bit_mode         = 0,
153         .invert_line_clock      = 1,
154         .invert_frm_clock       = 1,
155         .sync_edge              = 0,
156         .sync_ctrl              = 1,
157         .raster_order           = 0,
158 };
160 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
161         .manu_name              = "ThreeFive",
162         .controller_data        = &lcd_cfg,
163         .type                   = "TFC_S9700RTWV35TR_01B",
164 };
166 #include "common.h"
168 /* TSc controller */
169 #include <linux/input/ti_tscadc.h>
170 #include <linux/lis3lv02d.h>
172 static struct resource tsc_resources[]  = {
173         [0] = {
174                 .start  = AM33XX_TSC_BASE,
175                 .end    = AM33XX_TSC_BASE + SZ_8K - 1,
176                 .flags  = IORESOURCE_MEM,
177         },
178         [1] = {
179                 .start  = AM33XX_IRQ_ADC_GEN,
180                 .end    = AM33XX_IRQ_ADC_GEN,
181                 .flags  = IORESOURCE_IRQ,
182         },
183 };
185 static struct tsc_data am335x_touchscreen_data  = {
186         .wires  = 4,
187         .x_plate_resistance = 200,
188 };
190 static struct platform_device tsc_device = {
191         .name   = "tsc",
192         .id     = -1,
193         .dev    = {
194                         .platform_data  = &am335x_touchscreen_data,
195         },
196         .num_resources  = ARRAY_SIZE(tsc_resources),
197         .resource       = tsc_resources,
198 };
200 static u8 am335x_iis_serializer_direction1[] = {
201         INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,        RX_MODE,
202         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
203         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
204         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
205 };
207 static struct snd_platform_data am335x_evm_snd_data1 = {
208         .tx_dma_offset  = 0x46400000,   /* McASP1 */
209         .rx_dma_offset  = 0x46400000,
210         .op_mode        = DAVINCI_MCASP_IIS_MODE,
211         .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
212         .tdm_slots      = 2,
213         .serial_dir     = am335x_iis_serializer_direction1,
214         .asp_chan_q     = EVENTQ_2,
215         .version        = MCASP_VERSION_3,
216         .txnumevt       = 1,
217         .rxnumevt       = 1,
218 };
220 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
221         {
222                 .mmc            = 1,
223                 .caps           = MMC_CAP_4_BIT_DATA,
224                 .gpio_cd        = GPIO_TO_PIN(0, 6),
225                 .gpio_wp        = GPIO_TO_PIN(3, 18),
226                 .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
227         },
228         {
229                 .mmc            = 0,    /* will be set at runtime */
230         },
231         {
232                 .mmc            = 0,    /* will be set at runtime */
233         },
234         {}      /* Terminator */
235 };
238 #ifdef CONFIG_OMAP_MUX
239 static struct omap_board_mux board_mux[] __initdata = {
240         AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
241                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
242         AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
243                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
244         { .reg_offset = OMAP_MUX_TERMINATOR },
245 };
246 #else
247 #define board_mux       NULL
248 #endif
250 /* module pin mux structure */
251 struct pinmux_config {
252         const char *string_name; /* signal name format */
253         int val; /* Options for the mux register value */
254 };
256 struct evm_dev_cfg {
257         void (*device_init)(int evm_id, int profile);
259 /*
260 * If the device is required on both baseboard & daughter board (ex i2c),
261 * specify DEV_ON_BASEBOARD
262 */
263 #define DEV_ON_BASEBOARD        0
264 #define DEV_ON_DGHTR_BRD        1
265         u32 device_on;
267         u32 profile;    /* Profiles (0-7) in which the module is present */
268 };
270 /* AM335X - CPLD Register Offsets */
271 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
272 #define CPLD_DEVICE_ID  0x04 /* CPLD identification */
273 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
274 #define CPLD_CFG_REG    0x10 /* Configuration Register */
276 static struct i2c_client *cpld_client;
277 static u32 am335x_evm_id;
278 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
279 };
281 /*
282 * EVM Config held in On-Board eeprom device.
284 * Header Format
286 *  Name                 Size    Contents
287 *                       (Bytes)
288 *-------------------------------------------------------------
289 *  Header               4       0xAA, 0x55, 0x33, 0xEE
291 *  Board Name           8       Name for board in ASCII.
292 *                               example "A33515BB" = "AM335X
293                                 Low Cost EVM board"
295 *  Version              4       Hardware version code for board in
296 *                               in ASCII. "1.0A" = rev.01.0A
298 *  Serial Number        12      Serial number of the board. This is a 12
299 *                               character string which is WWYY4P16nnnn, where
300 *                               WW = 2 digit week of the year of production
301 *                               YY = 2 digit year of production
302 *                               nnnn = incrementing board number
304 *  Configuration option 32      Codes(TBD) to show the configuration
305 *                               setup on this board.
307 *  Available            32720   Available space for other non-volatile
308 *                               data.
309 */
310 struct am335x_evm_eeprom_config {
311         u32     header;
312         u8      name[8];
313         char    version[4];
314         u8      serial[12];
315         u8      opt[32];
316 };
318 static struct am335x_evm_eeprom_config config;
319 static bool daughter_brd_detected;
321 #define GP_EVM_REV_IS_1_0               0x1
322 #define GP_EVM_REV_IS_1_1A              0x2
323 #define GP_EVM_REV_IS_UNKNOWN           0xFF
324 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
325 unsigned int gigabit_enable = 1;
327 #define EEPROM_MAC_ADDRESS_OFFSET       60 /* 4+8+4+12+32 */
328 #define EEPROM_NO_OF_MAC_ADDR           3
329 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
331 #define AM335X_EEPROM_HEADER            0xEE3355AA
333 /* current profile if exists else PROFILE_0 on error */
334 static u32 am335x_get_profile_selection(void)
336         int val = 0;
338         if (!cpld_client)
339                 /* error checking is not done in func's calling this routine.
340                 so return profile 0 on error */
341                 return 0;
343         val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
344         if (val < 0)
345                 return 0;       /* default to Profile 0 on Error */
346         else
347                 return val & 0x7;
350 /* Module pin mux for LCDC */
351 static struct pinmux_config lcdc_pin_mux[] = {
352         {"lcd_data0.lcd_data0",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
353                                                        | AM33XX_PULL_DISA},
354         {"lcd_data1.lcd_data1",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
355                                                        | AM33XX_PULL_DISA},
356         {"lcd_data2.lcd_data2",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
357                                                        | AM33XX_PULL_DISA},
358         {"lcd_data3.lcd_data3",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
359                                                        | AM33XX_PULL_DISA},
360         {"lcd_data4.lcd_data4",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
361                                                        | AM33XX_PULL_DISA},
362         {"lcd_data5.lcd_data5",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
363                                                        | AM33XX_PULL_DISA},
364         {"lcd_data6.lcd_data6",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
365                                                        | AM33XX_PULL_DISA},
366         {"lcd_data7.lcd_data7",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
367                                                        | AM33XX_PULL_DISA},
368         {"lcd_data8.lcd_data8",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
369                                                        | AM33XX_PULL_DISA},
370         {"lcd_data9.lcd_data9",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
371                                                        | AM33XX_PULL_DISA},
372         {"lcd_data10.lcd_data10",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
373                                                        | AM33XX_PULL_DISA},
374         {"lcd_data11.lcd_data11",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
375                                                        | AM33XX_PULL_DISA},
376         {"lcd_data12.lcd_data12",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
377                                                        | AM33XX_PULL_DISA},
378         {"lcd_data13.lcd_data13",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
379                                                        | AM33XX_PULL_DISA},
380         {"lcd_data14.lcd_data14",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
381                                                        | AM33XX_PULL_DISA},
382         {"lcd_data15.lcd_data15",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
383                                                        | AM33XX_PULL_DISA},
384         {"gpmc_ad8.lcd_data16",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
385         {"gpmc_ad9.lcd_data17",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
386         {"gpmc_ad10.lcd_data18",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
387         {"gpmc_ad11.lcd_data19",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
388         {"gpmc_ad12.lcd_data20",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
389         {"gpmc_ad13.lcd_data21",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
390         {"gpmc_ad14.lcd_data22",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
391         {"gpmc_ad15.lcd_data23",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
392         {"lcd_vsync.lcd_vsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
393         {"lcd_hsync.lcd_hsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
394         {"lcd_pclk.lcd_pclk",           OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
395         {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
396         {NULL, 0},
397 };
399 static struct pinmux_config tsc_pin_mux[] = {
400         {"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
401         {"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
402         {"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
403         {"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
404         {"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
405         {"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
406         {NULL, 0},
407 };
409 /* Pin mux for nand flash module */
410 static struct pinmux_config nand_pin_mux[] = {
411         {"gpmc_ad0.gpmc_ad0",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
412         {"gpmc_ad1.gpmc_ad1",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
413         {"gpmc_ad2.gpmc_ad2",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
414         {"gpmc_ad3.gpmc_ad3",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
415         {"gpmc_ad4.gpmc_ad4",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
416         {"gpmc_ad5.gpmc_ad5",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
417         {"gpmc_ad6.gpmc_ad6",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
418         {"gpmc_ad7.gpmc_ad7",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
419         {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
420         {"gpmc_wpn.gpmc_wpn",     OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
421         {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
422         {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
423         {"gpmc_oen_ren.gpmc_oen_ren",    OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
424         {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
425         {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
426         {NULL, 0},
427 };
429 /* Module pin mux for SPI fash */
430 static struct pinmux_config spi0_pin_mux[] = {
431         {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
432                                                         | AM33XX_INPUT_EN},
433         {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
434                                                         | AM33XX_INPUT_EN},
435         {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
436                                                         | AM33XX_INPUT_EN},
437         {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
438                                                         | AM33XX_INPUT_EN},
439         {NULL, 0},
440 };
442 /* Module pin mux for SPI flash */
443 static struct pinmux_config spi1_pin_mux[] = {
444         {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
445                 | AM33XX_INPUT_EN},
446         {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
447                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
448         {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
449                 | AM33XX_INPUT_EN},
450         {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
451                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
452         {NULL, 0},
453 };
455 /* Module pin mux for rgmii1 */
456 static struct pinmux_config rgmii1_pin_mux[] = {
457         {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
458         {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
459         {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
460         {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
461         {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
462         {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
463         {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
464         {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
465         {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
466         {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
467         {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
468         {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
469         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
470         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
471         {NULL, 0},
472 };
474 /* Module pin mux for rgmii2 */
475 static struct pinmux_config rgmii2_pin_mux[] = {
476         {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
477         {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
478         {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
479         {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
480         {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
481         {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
482         {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
483         {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
484         {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
485         {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
486         {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
487         {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
488         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
489         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
490         {NULL, 0},
491 };
493 /* Module pin mux for mii1 */
494 static struct pinmux_config mii1_pin_mux[] = {
495         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
496         {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
497         {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
498         {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
499         {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
500         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
501         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
502         {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
503         {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
504         {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
505         {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
506         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
507         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
508         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
509         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
510         {NULL, 0},
511 };
513 /* Module pin mux for rmii1 */
514 static struct pinmux_config rmii1_pin_mux[] = {
515         {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
516         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
517         {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
518         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
519         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
520         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
521         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
522         {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
523         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
524         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
525         {NULL, 0},
526 };
528 static struct pinmux_config i2c1_pin_mux[] = {
529         {"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
530                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
531         {"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
532                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
533         {NULL, 0},
534 };
536 /* Module pin mux for mcasp1 */
537 static struct pinmux_config mcasp1_pin_mux[] = {
538         {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
539         {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
540         {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
541         {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
542                                                 AM33XX_PIN_INPUT_PULLDOWN},
543         {NULL, 0},
544 };
547 /* Module pin mux for mmc0 */
548 static struct pinmux_config mmc0_pin_mux[] = {
549         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
550         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
551         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
552         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
553         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
554         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
555         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
556         {"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
557         {NULL, 0},
558 };
560 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
561         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
562         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
563         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
564         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
565         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
566         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
567         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
568         {NULL, 0},
569 };
571 /* Module pin mux for mmc1 */
572 static struct pinmux_config mmc1_pin_mux[] = {
573         {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
574         {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
575         {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
576         {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
577         {"gpmc_ad3.mmc1_dat3",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
578         {"gpmc_ad2.mmc1_dat2",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
579         {"gpmc_ad1.mmc1_dat1",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
580         {"gpmc_ad0.mmc1_dat0",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
581         {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
582         {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
583         {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
584         {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
585         {NULL, 0},
586 };
588 /* Module pin mux for uart3 */
589 static struct pinmux_config uart3_pin_mux[] = {
590         {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
591         {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
592         {NULL, 0},
593 };
595 static struct pinmux_config d_can_gp_pin_mux[] = {
596         {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
597         {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
598         {NULL, 0},
599 };
601 static struct pinmux_config d_can_ia_pin_mux[] = {
602         {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
603         {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
604         {NULL, 0},
605 };
607 /* Module pin mux for uart2 */
608 static struct pinmux_config uart2_pin_mux[] = {
609         {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
610                                                 AM33XX_PIN_INPUT_PULLUP},
611         {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
612                                                 AM33XX_PULL_DISA |
613                                                 AM33XX_SLEWCTRL_SLOW},
614         {NULL, 0},
615 };
618 /*
619 * @pin_mux - single module pin-mux structure which defines pin-mux
620 *                       details for all its pins.
621 */
622 static void setup_pin_mux(struct pinmux_config *pin_mux)
624         int i;
626         for (i = 0; pin_mux->string_name != NULL; pin_mux++)
627                 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
631 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
633 /* pinmux for keypad device */
634 static struct pinmux_config matrix_keypad_pin_mux[] = {
635         {"gpmc_a5.gpio1_21",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
636         {"gpmc_a6.gpio1_22",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
637         {"gpmc_a9.gpio1_25",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
638         {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
639         {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
640         {NULL, 0},
641 };
643 /* Keys mapping */
644 static const uint32_t am335x_evm_matrix_keys[] = {
645         KEY(0, 0, KEY_MENU),
646         KEY(1, 0, KEY_BACK),
647         KEY(2, 0, KEY_LEFT),
649         KEY(0, 1, KEY_RIGHT),
650         KEY(1, 1, KEY_ENTER),
651         KEY(2, 1, KEY_DOWN),
652 };
654 const struct matrix_keymap_data am335x_evm_keymap_data = {
655         .keymap      = am335x_evm_matrix_keys,
656         .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
657 };
659 static const unsigned int am335x_evm_keypad_row_gpios[] = {
660         GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
661 };
663 static const unsigned int am335x_evm_keypad_col_gpios[] = {
664         GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
665 };
667 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
668         .keymap_data       = &am335x_evm_keymap_data,
669         .row_gpios         = am335x_evm_keypad_row_gpios,
670         .num_row_gpios     = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
671         .col_gpios         = am335x_evm_keypad_col_gpios,
672         .num_col_gpios     = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
673         .active_low        = false,
674         .debounce_ms       = 5,
675         .col_scan_delay_us = 2,
676 };
678 static struct platform_device am335x_evm_keyboard = {
679         .name  = "matrix-keypad",
680         .id    = -1,
681         .dev   = {
682                 .platform_data = &am335x_evm_keypad_platform_data,
683         },
684 };
686 static void matrix_keypad_init(int evm_id, int profile)
688         int err;
690         setup_pin_mux(matrix_keypad_pin_mux);
691         err = platform_device_register(&am335x_evm_keyboard);
692         if (err) {
693                 pr_err("failed to register matrix keypad (2x3) device\n");
694         }
698 /* pinmux for keypad device */
699 static struct pinmux_config volume_keys_pin_mux[] = {
700         {"spi0_sclk.gpio0_2",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
701         {"spi0_d0.gpio0_3",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
702         {NULL, 0},
703 };
705 /* Configure GPIOs for Volume Keys */
706 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
707         {
708                 .code                   = KEY_VOLUMEUP,
709                 .gpio                   = GPIO_TO_PIN(0, 2),
710                 .active_low             = true,
711                 .desc                   = "volume-up",
712                 .type                   = EV_KEY,
713                 .wakeup                 = 1,
714         },
715         {
716                 .code                   = KEY_VOLUMEDOWN,
717                 .gpio                   = GPIO_TO_PIN(0, 3),
718                 .active_low             = true,
719                 .desc                   = "volume-down",
720                 .type                   = EV_KEY,
721                 .wakeup                 = 1,
722         },
723 };
725 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
726         .buttons        = am335x_evm_volume_gpio_buttons,
727         .nbuttons       = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
728 };
730 static struct platform_device am335x_evm_volume_keys = {
731         .name   = "gpio-keys",
732         .id     = -1,
733         .dev    = {
734                 .platform_data  = &am335x_evm_volume_gpio_key_info,
735         },
736 };
738 static void volume_keys_init(int evm_id, int profile)
740         int err;
742         setup_pin_mux(volume_keys_pin_mux);
743         err = platform_device_register(&am335x_evm_volume_keys);
744         if (err)
745                 pr_err("failed to register matrix keypad (2x3) device\n");
748 /*
749 * @evm_id - evm id which needs to be configured
750 * @dev_cfg - single evm structure which includes
751 *                               all module inits, pin-mux defines
752 * @profile - if present, else PROFILE_NONE
753 * @dghtr_brd_flg - Whether Daughter board is present or not
754 */
755 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
756         int profile)
758         int i;
760         /*
761         * Only General Purpose & Industrial Auto Motro Control
762         * EVM has profiles. So check if this evm has profile.
763         * If not, ignore the profile comparison
764         */
766         /*
767         * If the device is on baseboard, directly configure it. Else (device on
768         * Daughter board), check if the daughter card is detected.
769         */
770         if (profile == PROFILE_NONE) {
771                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
772                         if (dev_cfg->device_on == DEV_ON_BASEBOARD)
773                                 dev_cfg->device_init(evm_id, profile);
774                         else if (daughter_brd_detected == true)
775                                 dev_cfg->device_init(evm_id, profile);
776                 }
777         } else {
778                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
779                         if (dev_cfg->profile & profile) {
780                                 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
781                                         dev_cfg->device_init(evm_id, profile);
782                                 else if (daughter_brd_detected == true)
783                                         dev_cfg->device_init(evm_id, profile);
784                         }
785                 }
786         }
790 /* pinmux for usb0 drvvbus */
791 static struct pinmux_config usb0_pin_mux[] = {
792         {"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
793         {NULL, 0},
794 };
796 /* pinmux for usb1 drvvbus */
797 static struct pinmux_config usb1_pin_mux[] = {
798         {"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
799         {NULL, 0},
800 };
802 /* pinmux for profibus */
803 static struct pinmux_config profibus_pin_mux[] = {
804         {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
805         {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
806         {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
807         {NULL, 0},
808 };
810 /* Module pin mux for eCAP0 */
811 static struct pinmux_config ecap0_pin_mux[] = {
812         {"ecap0_in_pwm0_out.ecap0_in_pwm0_out",
813                 OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
814         {NULL, 0},
815 };
817 static int backlight_enable;
819 #define AM335XEVM_WLAN_PMENA_GPIO       GPIO_TO_PIN(1, 30)
820 #define AM335XEVM_WLAN_IRQ_GPIO         GPIO_TO_PIN(3, 17)
822 struct wl12xx_platform_data am335xevm_wlan_data = {
823         .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
824         .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
825 };
827 /* Module pin mux for wlan and bluetooth */
828 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
829         {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
830         {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
831         {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
832         {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
833         {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
834         {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
835         {NULL, 0},
836 };
838 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
839         {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
840         {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
841         {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
842         {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
843         {NULL, 0},
844 };
846 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
847         {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
848         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
849         {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
850         {NULL, 0},
851  };
853 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
854         {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
855         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
856         {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
857         {NULL, 0},
858  };
860 static void enable_ecap0(int evm_id, int profile)
862         backlight_enable = true;
865 /* Setup pwm-backlight */
866 static struct platform_device am335x_backlight = {
867         .name           = "pwm-backlight",
868         .id             = -1,
869         .dev            = {
870                 .platform_data  = &am335x_backlight_data,
871         }
872 };
874 static int __init ecap0_init(void)
876         int status = 0;
878         if (backlight_enable) {
879                 setup_pin_mux(ecap0_pin_mux);
880                 platform_device_register(&am335x_backlight);
881         }
882         return status;
884 late_initcall(ecap0_init);
886 static int __init conf_disp_pll(int rate)
888         struct clk *disp_pll;
889         int ret = -EINVAL;
891         disp_pll = clk_get(NULL, "dpll_disp_ck");
892         if (IS_ERR(disp_pll)) {
893                 pr_err("Cannot clk_get disp_pll\n");
894                 goto out;
895         }
897         ret = clk_set_rate(disp_pll, rate);
898         clk_put(disp_pll);
899 out:
900         return ret;
903 static void lcdc_init(int evm_id, int profile)
906         setup_pin_mux(lcdc_pin_mux);
908         if (conf_disp_pll(300000000)) {
909                 pr_info("Failed configure display PLL, not attempting to"
910                                 "register LCDC\n");
911                 return;
912         }
914         if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
915                 pr_info("Failed to register LCDC device\n");
916         return;
919 static void tsc_init(int evm_id, int profile)
921         int err;
923         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
924                 am335x_touchscreen_data.analog_input = 1;
925                 pr_info("TSC connected to beta GP EVM\n");
926         } else {
927                 am335x_touchscreen_data.analog_input = 0;
928                 pr_info("TSC connected to alpha GP EVM\n");
929         }
930         setup_pin_mux(tsc_pin_mux);
931         err = platform_device_register(&tsc_device);
932         if (err)
933                 pr_err("failed to register touchscreen device\n");
936 static void rgmii1_init(int evm_id, int profile)
938         setup_pin_mux(rgmii1_pin_mux);
939         return;
942 static void rgmii2_init(int evm_id, int profile)
944         setup_pin_mux(rgmii2_pin_mux);
945         return;
948 static void mii1_init(int evm_id, int profile)
950         setup_pin_mux(mii1_pin_mux);
951         return;
954 static void rmii1_init(int evm_id, int profile)
956         setup_pin_mux(rmii1_pin_mux);
957         return;
960 static void usb0_init(int evm_id, int profile)
962         setup_pin_mux(usb0_pin_mux);
963         return;
966 static void usb1_init(int evm_id, int profile)
968         setup_pin_mux(usb1_pin_mux);
969         return;
972 /* setup uart3 */
973 static void uart3_init(int evm_id, int profile)
975         setup_pin_mux(uart3_pin_mux);
976         return;
979 /* setup uart2 */
980 static void uart2_init(int evm_id, int profile)
982         setup_pin_mux(uart2_pin_mux);
983         return;
986 /* NAND partition information */
987 static struct mtd_partition am335x_nand_partitions[] = {
988 /* All the partition sizes are listed in terms of NAND block size */
989         {
990                 .name           = "SPL",
991                 .offset         = 0,                    /* Offset = 0x0 */
992                 .size           = SZ_128K,
993         },
994         {
995                 .name           = "SPL.backup1",
996                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x20000 */
997                 .size           = SZ_128K,
998         },
999         {
1000                 .name           = "SPL.backup2",
1001                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x40000 */
1002                 .size           = SZ_128K,
1003         },
1004         {
1005                 .name           = "SPL.backup3",
1006                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x60000 */
1007                 .size           = SZ_128K,
1008         },
1009         {
1010                 .name           = "U-Boot",
1011                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
1012                 .size           = 15 * SZ_128K,
1013         },
1014         {
1015                 .name           = "U-Boot Env",
1016                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
1017                 .size           = 1 * SZ_128K,
1018         },
1019         {
1020                 .name           = "Kernel",
1021                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
1022                 .size           = 40 * SZ_128K,
1023         },
1024         {
1025                 .name           = "File System",
1026                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
1027                 .size           = MTDPART_SIZ_FULL,
1028         },
1029 };
1031 /* SPI 0/1 Platform Data */
1032 /* SPI flash information */
1033 static struct mtd_partition am335x_spi_partitions[] = {
1034         /* All the partition sizes are listed in terms of erase size */
1035         {
1036                 .name       = "SPL",
1037                 .offset     = 0,                        /* Offset = 0x0 */
1038                 .size       = SZ_128K,
1039         },
1040         {
1041                 .name       = "U-Boot",
1042                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x20000 */
1043                 .size       = 2 * SZ_128K,
1044         },
1045         {
1046                 .name       = "U-Boot Env",
1047                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x60000 */
1048                 .size       = 2 * SZ_4K,
1049         },
1050         {
1051                 .name       = "Kernel",
1052                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x62000 */
1053                 .size       = 28 * SZ_128K,
1054         },
1055         {
1056                 .name       = "File System",
1057                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x3E2000 */
1058                 .size       = MTDPART_SIZ_FULL,         /* size ~= 4.1 MiB */
1059         }
1060 };
1062 static const struct flash_platform_data am335x_spi_flash = {
1063         .type      = "w25q64",
1064         .name      = "spi_flash",
1065         .parts     = am335x_spi_partitions,
1066         .nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
1067 };
1069 /*
1070  * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1071  * So setup Max speed to be less than that of Controller speed
1072  */
1073 static struct spi_board_info am335x_spi0_slave_info[] = {
1074         {
1075                 .modalias      = "m25p80",
1076                 .platform_data = &am335x_spi_flash,
1077                 .irq           = -1,
1078                 .max_speed_hz  = 24000000,
1079                 .bus_num       = 1,
1080                 .chip_select   = 0,
1081         },
1082 };
1084 static struct spi_board_info am335x_spi1_slave_info[] = {
1085         {
1086                 .modalias      = "m25p80",
1087                 .platform_data = &am335x_spi_flash,
1088                 .irq           = -1,
1089                 .max_speed_hz  = 12000000,
1090                 .bus_num       = 2,
1091                 .chip_select   = 0,
1092         },
1093 };
1095 static void evm_nand_init(int evm_id, int profile)
1097         setup_pin_mux(nand_pin_mux);
1098         board_nand_init(am335x_nand_partitions,
1099                 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1102 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1103         .click_flags = LIS3_CLICK_SINGLE_X |
1104                         LIS3_CLICK_SINGLE_Y |
1105                         LIS3_CLICK_SINGLE_Z,
1106         .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1107                         LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1108                         LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1109         .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1110         .wakeup_thresh  = 10,
1111         .click_thresh_x = 10,
1112         .click_thresh_y = 10,
1113         .click_thresh_z = 10,
1114         .g_range        = 2,
1115         .st_min_limits[0] = 120,
1116         .st_min_limits[1] = 120,
1117         .st_min_limits[2] = 140,
1118         .st_max_limits[0] = 550,
1119         .st_max_limits[1] = 550,
1120         .st_max_limits[2] = 750,
1121 };
1123 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1124         {
1125                 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1126         },
1127         {
1128                 I2C_BOARD_INFO("lis331dlh", 0x18),
1129                 .platform_data = &lis331dlh_pdata,
1130         },
1131         {
1132                 I2C_BOARD_INFO("tsl2550", 0x39),
1133         },
1134         {
1135                 I2C_BOARD_INFO("tmp275", 0x48),
1136         },
1137 };
1139 static void i2c1_init(int evm_id, int profile)
1141         setup_pin_mux(i2c1_pin_mux);
1142         omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1143                         ARRAY_SIZE(am335x_i2c_boardinfo1));
1144         return;
1147 /* Setup McASP 1 */
1148 static void mcasp1_init(int evm_id, int profile)
1150         /* Configure McASP */
1151         setup_pin_mux(mcasp1_pin_mux);
1152         am335x_register_mcasp1(&am335x_evm_snd_data1);
1153         return;
1156 static void mmc1_init(int evm_id, int profile)
1158         setup_pin_mux(mmc1_pin_mux);
1160         am335x_mmc[1].mmc = 2;
1161         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1162         am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1163         am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1164         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1166         /* mmc will be initialized when mmc0_init is called */
1167         return;
1170 static void mmc2_wl12xx_init(int evm_id, int profile)
1172         setup_pin_mux(mmc2_wl12xx_pin_mux);
1174         am335x_mmc[1].mmc = 3;
1175         am335x_mmc[1].name = "wl1271";
1176         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1177                                 | MMC_PM_KEEP_POWER;
1178         am335x_mmc[1].nonremovable = true;
1179         am335x_mmc[1].gpio_cd = -EINVAL;
1180         am335x_mmc[1].gpio_wp = -EINVAL;
1181         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1183         /* mmc will be initialized when mmc0_init is called */
1184         return;
1187 static void uart1_wl12xx_init(int evm_id, int profile)
1189         setup_pin_mux(uart1_wl12xx_pin_mux);
1192 static void wl12xx_bluetooth_enable(void)
1194         int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1195                 "bt_en\n");
1196         if (status < 0)
1197                 pr_err("Failed to request gpio for bt_enable");
1199         pr_info("Configure Bluetooth Enable pin...\n");
1200         gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1203 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1205         if (on) {
1206                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1207                 mdelay(70);
1208         }
1209         else
1210                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1212         return 0;
1215 static void wl12xx_init(int evm_id, int profile)
1217         struct device *dev;
1218         struct omap_mmc_platform_data *pdata;
1219         int ret;
1221         /* Register WLAN and BT enable pins based on the evm board revision */
1222         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1223                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1224                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1225         }
1226         else {
1227                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1228                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1229         }
1231         wl12xx_bluetooth_enable();
1233         if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1234                 pr_err("error setting wl12xx data\n");
1236         dev = am335x_mmc[1].dev;
1237         if (!dev) {
1238                 pr_err("wl12xx mmc device initialization failed\n");
1239                 goto out;
1240         }
1242         pdata = dev->platform_data;
1243         if (!pdata) {
1244                 pr_err("Platfrom data of wl12xx device not set\n");
1245                 goto out;
1246         }
1248         ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1249                 GPIOF_OUT_INIT_LOW, "wlan_en");
1250         if (ret) {
1251                 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1252                 goto out;
1253         }
1255         if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1256                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1257         else
1258                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1260         pdata->slots[0].set_power = wl12xx_set_power;
1261 out:
1262         return;
1265 static void d_can_init(int evm_id, int profile)
1267         switch (evm_id) {
1268         case IND_AUT_MTR_EVM:
1269                 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1270                         setup_pin_mux(d_can_ia_pin_mux);
1271                         /* Instance Zero */
1272                         am33xx_d_can_init(0);
1273                 }
1274                 break;
1275         case GEN_PURP_EVM:
1276                 if (profile == PROFILE_1) {
1277                         setup_pin_mux(d_can_gp_pin_mux);
1278                         /* Instance One */
1279                         am33xx_d_can_init(1);
1280                 }
1281                 break;
1282         default:
1283                 break;
1284         }
1287 static void mmc0_init(int evm_id, int profile)
1289         setup_pin_mux(mmc0_pin_mux);
1291         omap2_hsmmc_init(am335x_mmc);
1292         return;
1295 static void mmc0_no_cd_init(int evm_id, int profile)
1297         setup_pin_mux(mmc0_no_cd_pin_mux);
1299         omap2_hsmmc_init(am335x_mmc);
1300         return;
1304 /* setup spi0 */
1305 static void spi0_init(int evm_id, int profile)
1307         setup_pin_mux(spi0_pin_mux);
1308         spi_register_board_info(am335x_spi0_slave_info,
1309                         ARRAY_SIZE(am335x_spi0_slave_info));
1310         return;
1313 /* setup spi1 */
1314 static void spi1_init(int evm_id, int profile)
1316         setup_pin_mux(spi1_pin_mux);
1317         spi_register_board_info(am335x_spi1_slave_info,
1318                         ARRAY_SIZE(am335x_spi1_slave_info));
1319         return;
1323 static int beaglebone_phy_fixup(struct phy_device *phydev)
1325         phydev->supported &= ~(SUPPORTED_100baseT_Half |
1326                                 SUPPORTED_100baseT_Full);
1328         return 0;
1331 #if defined(CONFIG_TLK110_WORKAROUND) || \
1332                         defined(CONFIG_TLK110_WORKAROUND_MODULE)
1333 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1335         unsigned int val;
1337         /* This is done as a workaround to support TLK110 rev1.0 phy */
1338         val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1339         phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1341         val = phy_read(phydev, TLK110_LPFHPF_REG);
1342         phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1344         val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1345         phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1347         val = phy_read(phydev, TLK110_VRCR_REG);
1348         phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1350         val = phy_read(phydev, TLK110_SETFFE_REG);
1351         phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1353         val = phy_read(phydev, TLK110_FTSP_REG);
1354         phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1356         val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1357         phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1359         val = phy_read(phydev, TLK110_PSCOEF21_REG);
1360         phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1362         val = phy_read(phydev, TLK110_PSCOEF3_REG);
1363         phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1365         val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1366         phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1368         val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1369         phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1371         val = phy_read(phydev, TLK110_CFGPS_REG);
1372         phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1374         val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1375         phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1377         val = phy_read(phydev, TLK110_SWSCR3_REG);
1378         phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1380         val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1381         phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1383         val = phy_read(phydev, TLK110_PHYRCR_REG);
1384         phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1386         return 0;
1388 #endif
1390 static void profibus_init(int evm_id, int profile)
1392         setup_pin_mux(profibus_pin_mux);
1393         return;
1396 /* Low-Cost EVM */
1397 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1398         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1399         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1400         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1401         {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1402         {NULL, 0, 0},
1403 };
1405 /* General Purpose EVM */
1406 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1407         {enable_ecap0,  DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1408                                                 PROFILE_2 | PROFILE_7) },
1409         {lcdc_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1410                                                 PROFILE_2 | PROFILE_7) },
1411         {tsc_init,      DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1412                                                 PROFILE_2 | PROFILE_7) },
1413         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
1414         {rgmii2_init,   DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1415                                                 PROFILE_4 | PROFILE_6) },
1416         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1417         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1418         {evm_nand_init, DEV_ON_DGHTR_BRD,
1419                 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1420         {i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1421         {mcasp1_init,   DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1422         {mmc1_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1423         {mmc2_wl12xx_init,      DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1424                                                                 PROFILE_5)},
1425         {mmc0_init,     DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1426         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_5},
1427         {spi0_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1428         {uart1_wl12xx_init,     DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1429                                                                 PROFILE_5)},
1430         {wl12xx_init,   DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1431         {d_can_init,    DEV_ON_DGHTR_BRD, PROFILE_1},
1432         {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1433         {volume_keys_init,  DEV_ON_DGHTR_BRD, PROFILE_0},
1434         {uart2_init,    DEV_ON_DGHTR_BRD, PROFILE_3},
1435         {NULL, 0, 0},
1436 };
1438 /* Industrial Auto Motor Control EVM */
1439 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1440         {mii1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1441         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1442         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1443         {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1444         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1445         {spi1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1446         {uart3_init,    DEV_ON_DGHTR_BRD, PROFILE_ALL},
1447         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1448         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_ALL},
1449         {NULL, 0, 0},
1450 };
1452 /* IP-Phone EVM */
1453 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1454         {enable_ecap0,  DEV_ON_DGHTR_BRD, PROFILE_NONE},
1455         {lcdc_init,     DEV_ON_DGHTR_BRD, PROFILE_NONE},
1456         {tsc_init,      DEV_ON_DGHTR_BRD, PROFILE_NONE},
1457         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1458         {rgmii2_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1459         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1460         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1461         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1462         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1463         {mcasp1_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1464         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1465         {NULL, 0, 0},
1466 };
1468 /* Beaglebone < Rev A3 */
1469 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1470         {rmii1_init,    DEV_ON_BASEBOARD, PROFILE_NONE},
1471         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1472         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1473         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1474         {NULL, 0, 0},
1475 };
1477 /* Beaglebone Rev A3 and after */
1478 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1479         {mii1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1480         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1481         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1482         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1483         {NULL, 0, 0},
1484 };
1486 static void setup_low_cost_evm(void)
1488         pr_info("The board is a AM335x Low Cost EVM.\n");
1490         _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1493 static void setup_general_purpose_evm(void)
1495         u32 prof_sel = am335x_get_profile_selection();
1496         pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1498         if (!strncmp("1.1A", config.version, 4)) {
1499                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1500         } else if (!strncmp("1.0", config.version, 3)) {
1501                 gp_evm_revision = GP_EVM_REV_IS_1_0;
1502         } else {
1503                 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1504                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1505         }
1507         if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1508                 gigabit_enable = 0;
1509         else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1510                 gigabit_enable = 1;
1512         _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1515 static void setup_ind_auto_motor_ctrl_evm(void)
1517         u32 prof_sel = am335x_get_profile_selection();
1519         pr_info("The board is an industrial automation EVM in profile %d\n",
1520                 prof_sel);
1522         /* Only Profile 0 is supported */
1523         if ((1L << prof_sel) != PROFILE_0) {
1524                 pr_err("AM335X: Only Profile 0 is supported\n");
1525                 pr_err("Assuming profile 0 & continuing\n");
1526                 prof_sel = PROFILE_0;
1527         }
1529         _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1530                 PROFILE_0);
1532         /* Fillup global evmid */
1533         am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1535         /* Initialize TLK110 PHY registers for phy version 1.0 */
1536         am335x_tlk110_phy_init();
1541 static void setup_ip_phone_evm(void)
1543         pr_info("The board is an IP phone EVM\n");
1545         _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1548 /* BeagleBone < Rev A3 */
1549 static void setup_beaglebone_old(void)
1551         pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1553         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1554         am335x_mmc[0].gpio_wp = -EINVAL;
1556         _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1558         phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1559                                         beaglebone_phy_fixup);
1561         /* Fill up global evmid */
1562         am33xx_evmid_fillup(BEAGLE_BONE_OLD);
1565 /* BeagleBone after Rev A3 */
1566 static void setup_beaglebone(void)
1568         pr_info("The board is a AM335x Beaglebone.\n");
1570         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1571         am335x_mmc[0].gpio_wp = -EINVAL;
1573         _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1575         /* Fill up global evmid */
1576         am33xx_evmid_fillup(BEAGLE_BONE_A3);
1580 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1582         u8 tmp;
1583         int ret;
1585         /*
1586          * try reading a byte from the EEPROM to see if it is
1587          * present. We could read a lot more, but that would
1588          * just slow the boot process and we have all the information
1589          * we need from the EEPROM on the base board anyway.
1590          */
1591         ret = m->read(m, &tmp, 0, sizeof(u8));
1592         if (ret == sizeof(u8)) {
1593                 pr_info("Detected a daughter card on AM335x EVM..");
1594                 daughter_brd_detected = true;
1595         } else {
1596                 pr_info("No daughter card found\n");
1597                 daughter_brd_detected = false;
1598         }
1601 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1603         int ret;
1604         char tmp[10];
1606         /* 1st get the MAC address from EEPROM */
1607         ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1608                 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1610         if (ret != sizeof(am335x_mac_addr)) {
1611                 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1612                 return;
1613         }
1615         /* Fillup global mac id */
1616         am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1617                                 &am335x_mac_addr[1][0]);
1619         /* get board specific data */
1620         ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1621         if (ret != sizeof(config)) {
1622                 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1623                 return;
1624         }
1626         if (config.header != AM335X_EEPROM_HEADER) {
1627                 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1628                         config.header, AM335X_EEPROM_HEADER);
1629                 goto out;
1630         }
1632         if (strncmp("A335", config.name, 4)) {
1633                 pr_err("Board %s doesn't look like an AM335x board\n",
1634                         config.name);
1635                 goto out;
1636         }
1638         snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1639         pr_info("Board name: %s\n", tmp);
1640         snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1641         pr_info("Board version: %s\n", tmp);
1643         if (!strncmp("A335BONE", config.name, 8)) {
1644                 daughter_brd_detected = false;
1645                 if(!strncmp("00A1", config.version, 4) ||
1646                    !strncmp("00A2", config.version, 4))
1647                         setup_beaglebone_old();
1648                 else
1649                         setup_beaglebone();
1650         } else {
1651                 /* only 6 characters of options string used for now */
1652                 snprintf(tmp, 7, "%s", config.opt);
1653                 pr_info("SKU: %s\n", tmp);
1655                 if (!strncmp("SKU#00", config.opt, 6))
1656                         setup_low_cost_evm();
1657                 else if (!strncmp("SKU#01", config.opt, 6))
1658                         setup_general_purpose_evm();
1659                 else if (!strncmp("SKU#02", config.opt, 6))
1660                         setup_ind_auto_motor_ctrl_evm();
1661                 else if (!strncmp("SKU#03", config.opt, 6))
1662                         setup_ip_phone_evm();
1663                 else
1664                         goto out;
1665         }
1666         /* Initialize cpsw after board detection is completed as board
1667          * information is required for configuring phy address and hence
1668          * should be call only after board detection
1669          */
1670         am33xx_cpsw_init(gigabit_enable);
1672         return;
1673 out:
1674         /*
1675          * If the EEPROM hasn't been programed or an incorrect header
1676          * or board name are read, assume this is an old beaglebone board
1677          * (< Rev A3)
1678          */
1679         pr_err("Could not detect any board, falling back to: "
1680                 "Beaglebone (< Rev A3) with no daughter card connected\n");
1681         daughter_brd_detected = false;
1682         setup_beaglebone_old();
1684         /* Initialize cpsw after board detection is completed as board
1685          * information is required for configuring phy address and hence
1686          * should be call only after board detection
1687          */
1689         am33xx_cpsw_init(gigabit_enable);
1692 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1693         .byte_len       = (256*1024) / 8,
1694         .page_size      = 64,
1695         .flags          = AT24_FLAG_ADDR16,
1696         .setup          = am335x_setup_daughter_board,
1697         .context        = (void *)NULL,
1698 };
1700 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1701         .byte_len       = (256*1024) / 8,
1702         .page_size      = 64,
1703         .flags          = AT24_FLAG_ADDR16,
1704         .setup          = am335x_evm_setup,
1705         .context        = (void *)NULL,
1706 };
1708 static struct regulator_init_data am335x_dummy = {
1709         .constraints.always_on  = true,
1710 };
1712 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
1713         REGULATOR_SUPPLY("vdd_mpu", NULL),
1714 };
1716 static struct regulator_init_data am335x_vdd1 = {
1717         .constraints = {
1718                 .min_uV                 = 600000,
1719                 .max_uV                 = 1500000,
1720                 .valid_modes_mask       = REGULATOR_MODE_NORMAL,
1721                 .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
1722                 .always_on              = 1,
1723         },
1724         .num_consumer_supplies  = ARRAY_SIZE(am335x_vdd1_supply),
1725         .consumer_supplies      = am335x_vdd1_supply,
1726 };
1728 static struct tps65910_board am335x_tps65910_info = {
1729         .tps65910_pmic_init_data[TPS65910_REG_VRTC]     = &am335x_dummy,
1730         .tps65910_pmic_init_data[TPS65910_REG_VIO]      = &am335x_dummy,
1731         .tps65910_pmic_init_data[TPS65910_REG_VDD1]     = &am335x_vdd1,
1732         .tps65910_pmic_init_data[TPS65910_REG_VDD2]     = &am335x_dummy,
1733         .tps65910_pmic_init_data[TPS65910_REG_VDD3]     = &am335x_dummy,
1734         .tps65910_pmic_init_data[TPS65910_REG_VDIG1]    = &am335x_dummy,
1735         .tps65910_pmic_init_data[TPS65910_REG_VDIG2]    = &am335x_dummy,
1736         .tps65910_pmic_init_data[TPS65910_REG_VPLL]     = &am335x_dummy,
1737         .tps65910_pmic_init_data[TPS65910_REG_VDAC]     = &am335x_dummy,
1738         .tps65910_pmic_init_data[TPS65910_REG_VAUX1]    = &am335x_dummy,
1739         .tps65910_pmic_init_data[TPS65910_REG_VAUX2]    = &am335x_dummy,
1740         .tps65910_pmic_init_data[TPS65910_REG_VAUX33]   = &am335x_dummy,
1741         .tps65910_pmic_init_data[TPS65910_REG_VMMC]     = &am335x_dummy,
1742 };
1744 /*
1745 * Daughter board Detection.
1746 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1747 * machine init, starting from daughter board and ending with baseboard.
1748 * Assumptions :
1749 *       1. probe for i2c devices are called in the order they are included in
1750 *          the below struct. Daughter boards eeprom are probed 1st. Baseboard
1751 *          eeprom probe is called last.
1752 */
1753 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1754         {
1755                 /* Daughter Board EEPROM */
1756                 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1757                 .platform_data  = &am335x_daughter_board_eeprom_info,
1758         },
1759         {
1760                 /* Baseboard board EEPROM */
1761                 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1762                 .platform_data  = &am335x_baseboard_eeprom_info,
1763         },
1764         {
1765                 I2C_BOARD_INFO("cpld_reg", 0x35),
1766         },
1767         {
1768                 I2C_BOARD_INFO("tlc59108", 0x40),
1769         },
1770         {
1771                 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
1772                 .platform_data  = &am335x_tps65910_info,
1773         },
1775 };
1777 static struct omap_musb_board_data musb_board_data = {
1778         .interface_type = MUSB_INTERFACE_ULPI,
1779         /*
1780          * mode[0:3] = USB0PORT's mode
1781          * mode[4:7] = USB1PORT's mode
1782          * AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
1783          */
1784         .mode           = (MUSB_HOST << 4) | MUSB_OTG,
1785         .power          = 500,
1786         .instances      = 1,
1787 };
1789 static int cpld_reg_probe(struct i2c_client *client,
1790             const struct i2c_device_id *id)
1792         cpld_client = client;
1793         return 0;
1796 static int __devexit cpld_reg_remove(struct i2c_client *client)
1798         cpld_client = NULL;
1799         return 0;
1802 static const struct i2c_device_id cpld_reg_id[] = {
1803         { "cpld_reg", 0 },
1804         { }
1805 };
1807 static struct i2c_driver cpld_reg_driver = {
1808         .driver = {
1809                 .name   = "cpld_reg",
1810         },
1811         .probe          = cpld_reg_probe,
1812         .remove         = cpld_reg_remove,
1813         .id_table       = cpld_reg_id,
1814 };
1816 static void evm_init_cpld(void)
1818         i2c_add_driver(&cpld_reg_driver);
1821 static void __init am335x_evm_i2c_init(void)
1823         /* Initially assume Low Cost EVM Config */
1824         am335x_evm_id = LOW_COST_EVM;
1826         evm_init_cpld();
1828         omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1829                                 ARRAY_SIZE(am335x_i2c_boardinfo));
1832 static struct resource am335x_rtc_resources[] = {
1833         {
1834                 .start          = AM33XX_RTC_BASE,
1835                 .end            = AM33XX_RTC_BASE + SZ_4K - 1,
1836                 .flags          = IORESOURCE_MEM,
1837         },
1838         { /* timer irq */
1839                 .start          = AM33XX_IRQ_RTC_TIMER,
1840                 .end            = AM33XX_IRQ_RTC_TIMER,
1841                 .flags          = IORESOURCE_IRQ,
1842         },
1843         { /* alarm irq */
1844                 .start          = AM33XX_IRQ_RTC_ALARM,
1845                 .end            = AM33XX_IRQ_RTC_ALARM,
1846                 .flags          = IORESOURCE_IRQ,
1847         },
1848 };
1850 static struct platform_device am335x_rtc_device = {
1851         .name           = "omap_rtc",
1852         .id             = -1,
1853         .num_resources  = ARRAY_SIZE(am335x_rtc_resources),
1854         .resource       = am335x_rtc_resources,
1855 };
1857 static int am335x_rtc_init(void)
1859         void __iomem *base;
1860         struct clk *clk;
1862         clk = clk_get(NULL, "rtc_fck");
1863         if (IS_ERR(clk)) {
1864                 pr_err("rtc : Failed to get RTC clock\n");
1865                 return -1;
1866         }
1868         if (clk_enable(clk)) {
1869                 pr_err("rtc: Clock Enable Failed\n");
1870                 return -1;
1871         }
1873         base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1875         if (WARN_ON(!base))
1876                 return -ENOMEM;
1878         /* Unlock the rtc's registers */
1879         __raw_writel(0x83e70b13, base + 0x6c);
1880         __raw_writel(0x95a4f1e0, base + 0x70);
1882         /*
1883          * Enable the 32K OSc
1884          * TODO: Need a better way to handle this
1885          * Since we want the clock to be running before mmc init
1886          * we need to do it before the rtc probe happens
1887          */
1888         __raw_writel(0x48, base + 0x54);
1890         iounmap(base);
1892         return  platform_device_register(&am335x_rtc_device);
1895 /* Enable clkout2 */
1896 static struct pinmux_config clkout2_pin_mux[] = {
1897         {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1898         {NULL, 0},
1899 };
1901 static void __init clkout2_enable(void)
1903         struct clk *ck_32;
1905         ck_32 = clk_get(NULL, "clkout2_ck");
1906         if (IS_ERR(ck_32)) {
1907                 pr_err("Cannot clk_get ck_32\n");
1908                 return;
1909         }
1911         clk_enable(ck_32);
1913         setup_pin_mux(clkout2_pin_mux);
1916 void __iomem * __init am33xx_get_mem_ctlr(void)
1918         void __iomem *am33xx_emif_base;
1920         am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1922         if (!am33xx_emif_base)
1923                 pr_warning("%s: Unable to map DDR2 controller", __func__);
1925         return am33xx_emif_base;
1928 static struct resource am33xx_cpuidle_resources[] = {
1929         {
1930                 .start          = AM33XX_EMIF0_BASE,
1931                 .end            = AM33XX_EMIF0_BASE + SZ_32K - 1,
1932                 .flags          = IORESOURCE_MEM,
1933         },
1934 };
1936 /* AM33XX devices support DDR2 power down */
1937 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1938         .ddr2_pdown     = 1,
1939 };
1941 static struct platform_device am33xx_cpuidle_device = {
1942         .name                   = "cpuidle-am33xx",
1943         .num_resources          = ARRAY_SIZE(am33xx_cpuidle_resources),
1944         .resource               = am33xx_cpuidle_resources,
1945         .dev = {
1946                 .platform_data  = &am33xx_cpuidle_pdata,
1947         },
1948 };
1950 static void __init am33xx_cpuidle_init(void)
1952         int ret;
1954         am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1956         ret = platform_device_register(&am33xx_cpuidle_device);
1958         if (ret)
1959                 pr_warning("AM33XX cpuidle registration failed\n");
1963 static void __init am335x_evm_init(void)
1965         am33xx_cpuidle_init();
1966         am33xx_mux_init(board_mux);
1967         omap_serial_init();
1968         am335x_rtc_init();
1969         clkout2_enable();
1970         am335x_evm_i2c_init();
1971         omap_sdrc_init(NULL, NULL);
1972         usb_musb_init(&musb_board_data);
1973         omap_board_config = am335x_evm_config;
1974         omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1975         /* Create an alias for icss clock */
1976         if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1977                 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1978         /* Create an alias for gfx/sgx clock */
1979         if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1980                 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1983 static void __init am335x_evm_map_io(void)
1985         omap2_set_globals_am33xx();
1986         omapam33xx_map_common_io();
1989 MACHINE_START(AM335XEVM, "am335xevm")
1990         /* Maintainer: Texas Instruments */
1991         .atag_offset    = 0x100,
1992         .map_io         = am335x_evm_map_io,
1993         .init_early     = am33xx_init_early,
1994         .init_irq       = ti81xx_init_irq,
1995         .handle_irq     = omap3_intc_handle_irq,
1996         .timer          = &omap3_am33xx_timer,
1997         .init_machine   = am335x_evm_init,
1998 MACHINE_END
2000 MACHINE_START(AM335XIAEVM, "am335xiaevm")
2001         /* Maintainer: Texas Instruments */
2002         .atag_offset    = 0x100,
2003         .map_io         = am335x_evm_map_io,
2004         .init_irq       = ti81xx_init_irq,
2005         .init_early     = am33xx_init_early,
2006         .timer          = &omap3_am33xx_timer,
2007         .init_machine   = am335x_evm_init,
2008 MACHINE_END