arch/arm/mach-omap2/board-am335xevm.c

   1 /*
   2  * Code for AM335X EVM.
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/i2c.h>
  18 #include <linux/module.h>
  19 #include <linux/i2c/at24.h>
  20 #include <linux/phy.h>
  21 #include <linux/gpio.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/flash.h>
  24 #include <linux/gpio_keys.h>
  25 #include <linux/input.h>
  26 #include <linux/input/matrix_keypad.h>
  27 #include <linux/mtd/mtd.h>
  28 #include <linux/mtd/nand.h>
  29 #include <linux/mtd/partitions.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/clk.h>
  32 #include <linux/err.h>
  33 #include <linux/wl12xx.h>
  34 #include <linux/ethtool.h>
  35
  36 /* LCD controller is similar to DA850 */
  37 #include <video/da8xx-fb.h>
  38
  39 #include <mach/hardware.h>
  40 #include <mach/board-am335xevm.h>
  41
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/map.h>
  45 #include <asm/hardware/asp.h>
  46
  47 #include <plat/irqs.h>
  48 #include <plat/board.h>
  49 #include <plat/common.h>
  50 #include <plat/lcdc.h>
  51 #include <plat/usb.h>
  52 #include <plat/mmc.h>
  53
  54 #include "board-flash.h"
  55 #include "cpuidle33xx.h"
  56 #include "mux.h"
  57 #include "devices.h"
  58 #include "hsmmc.h"
  59
  60 /* Convert GPIO signal to GPIO pin number */
  61 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  62
  63 /* TLK PHY IDs */
  64 #define TLK110_PHY_ID           0x2000A201
  65 #define TLK110_PHY_MASK         0xfffffff0
  66
  67 /* BBB PHY IDs */
  68 #define BBB_PHY_ID              0x7c0f1
  69 #define BBB_PHY_MASK            0xfffffffe
  70
  71 /* TLK110 PHY register offsets */
  72 #define TLK110_COARSEGAIN_REG   0x00A3
  73 #define TLK110_LPFHPF_REG       0x00AC
  74 #define TLK110_SPAREANALOG_REG  0x00B9
  75 #define TLK110_VRCR_REG         0x00D0
  76 #define TLK110_SETFFE_REG       0x0107
  77 #define TLK110_FTSP_REG         0x0154
  78 #define TLK110_ALFATPIDL_REG    0x002A
  79 #define TLK110_PSCOEF21_REG     0x0096
  80 #define TLK110_PSCOEF3_REG      0x0097
  81 #define TLK110_ALFAFACTOR1_REG  0x002C
  82 #define TLK110_ALFAFACTOR2_REG  0x0023
  83 #define TLK110_CFGPS_REG        0x0095
  84 #define TLK110_FTSPTXGAIN_REG   0x0150
  85 #define TLK110_SWSCR3_REG       0x000B
  86 #define TLK110_SCFALLBACK_REG   0x0040
  87 #define TLK110_PHYRCR_REG       0x001F
  88
  89 /* TLK110 register writes values */
  90 #define TLK110_COARSEGAIN_VAL   0x0000
  91 #define TLK110_LPFHPF_VAL       0x8000
  92 #define TLK110_SPANALOG_VAL     0x0000
  93 #define TLK110_VRCR_VAL         0x0008
  94 #define TLK110_SETFFE_VAL       0x0605
  95 #define TLK110_FTSP_VAL         0x0255
  96 #define TLK110_ALFATPIDL_VAL    0x7998
  97 #define TLK110_PSCOEF21_VAL     0x3A20
  98 #define TLK110_PSCOEF3_VAL      0x003F
  99 #define TLK110_ALFACTOR1_VAL    0xFF80
 100 #define TLK110_ALFACTOR2_VAL    0x021C
 101 #define TLK110_CFGPS_VAL        0x0000
 102 #define TLK110_FTSPTXGAIN_VAL   0x6A88
 103 #define TLK110_SWSCR3_VAL       0x0000
 104 #define TLK110_SCFALLBACK_VAL   0xC11D
 105 #define TLK110_PHYRCR_VAL       0x4000
 106
 107 #if defined(CONFIG_TLK110_WORKAROUND) || \
 108                 defined(CONFIG_TLK110_WORKAROUND_MODULE)
 109 #define am335x_tlk110_phy_init()\
 110         do {    \
 111                 phy_register_fixup_for_uid(TLK110_PHY_ID,\
 112                                         TLK110_PHY_MASK,\
 113                                         am335x_tlk110_phy_fixup);\
 114         } while (0);
 115 #else
 116 #define am335x_tlk110_phy_init() do { } while (0);
 117 #endif
 118
 119 static const struct display_panel disp_panel = {
 120         WVGA,
 121         32,
 122         32,
 123         COLOR_ACTIVE,
 124 };
 125
 126 static struct lcd_ctrl_config lcd_cfg = {
 127         &disp_panel,
 128         .ac_bias                = 255,
 129         .ac_bias_intrpt         = 0,
 130         .dma_burst_sz           = 16,
 131         .bpp                    = 32,
 132         .fdd                    = 0x80,
 133         .tft_alt_mode           = 0,
 134         .stn_565_mode           = 0,
 135         .mono_8bit_mode         = 0,
 136         .invert_line_clock      = 1,
 137         .invert_frm_clock       = 1,
 138         .sync_edge              = 0,
 139         .sync_ctrl              = 1,
 140         .raster_order           = 0,
 141 };
 142
 143 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
 144         .manu_name              = "ThreeFive",
 145         .controller_data        = &lcd_cfg,
 146         .type                   = "TFC_S9700RTWV35TR_01B",
 147 };
 148
 149 #include "common.h"
 150
 151 /* TSc controller */
 152 #include <linux/input/ti_tscadc.h>
 153 #include <linux/lis3lv02d.h>
 154
 155 static struct resource tsc_resources[]  = {
 156         [0] = {
 157                 .start  = AM33XX_TSC_BASE,
 158                 .end    = AM33XX_TSC_BASE + SZ_8K - 1,
 159                 .flags  = IORESOURCE_MEM,
 160         },
 161         [1] = {
 162                 .start  = AM33XX_IRQ_ADC_GEN,
 163                 .end    = AM33XX_IRQ_ADC_GEN,
 164                 .flags  = IORESOURCE_IRQ,
 165         },
 166 };
 167
 168 static struct tsc_data am335x_touchscreen_data  = {
 169         .wires  = 4,
 170         .x_plate_resistance = 200,
 171 };
 172
 173 static struct platform_device tsc_device = {
 174         .name   = "tsc",
 175         .id     = -1,
 176         .dev    = {
 177                         .platform_data  = &am335x_touchscreen_data,
 178         },
 179         .num_resources  = ARRAY_SIZE(tsc_resources),
 180         .resource       = tsc_resources,
 181 };
 182
 183 static u8 am335x_iis_serializer_direction1[] = {
 184         INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,        RX_MODE,
 185         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
 186         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
 187         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
 188 };
 189
 190 static struct snd_platform_data am335x_evm_snd_data1 = {
 191         .tx_dma_offset  = 0x46400000,   /* McASP1 */
 192         .rx_dma_offset  = 0x46400000,
 193         .op_mode        = DAVINCI_MCASP_IIS_MODE,
 194         .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
 195         .tdm_slots      = 2,
 196         .serial_dir     = am335x_iis_serializer_direction1,
 197         .asp_chan_q     = EVENTQ_2,
 198         .version        = MCASP_VERSION_3,
 199         .txnumevt       = 1,
 200         .rxnumevt       = 1,
 201 };
 202
 203 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
 204         {
 205                 .mmc            = 1,
 206                 .caps           = MMC_CAP_4_BIT_DATA,
 207                 .gpio_cd        = GPIO_TO_PIN(0, 6),
 208                 .gpio_wp        = GPIO_TO_PIN(3, 18),
 209                 .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
 210         },
 211         {
 212                 .mmc            = 0,    /* will be set at runtime */
 213         },
 214         {
 215                 .mmc            = 0,    /* will be set at runtime */
 216         },
 217         {}      /* Terminator */
 218 };
 219
 220
 221 #ifdef CONFIG_OMAP_MUX
 222 static struct omap_board_mux board_mux[] __initdata = {
 223         AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
 224                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
 225         AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
 226                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
 227         { .reg_offset = OMAP_MUX_TERMINATOR },
 228 };
 229 #else
 230 #define board_mux       NULL
 231 #endif
 232
 233 /* module pin mux structure */
 234 struct pinmux_config {
 235         const char *string_name; /* signal name format */
 236         int val; /* Options for the mux register value */
 237 };
 238
 239 struct evm_dev_cfg {
 240         void (*device_init)(int evm_id, int profile);
 241
 242 /*
 243 * If the device is required on both baseboard & daughter board (ex i2c),
 244 * specify DEV_ON_BASEBOARD
 245 */
 246 #define DEV_ON_BASEBOARD        0
 247 #define DEV_ON_DGHTR_BRD        1
 248         u32 device_on;
 249
 250         u32 profile;    /* Profiles (0-7) in which the module is present */
 251 };
 252
 253 /* AM335X - CPLD Register Offsets */
 254 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
 255 #define CPLD_DEVICE_ID  0x04 /* CPLD identification */
 256 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
 257 #define CPLD_CFG_REG    0x10 /* Configuration Register */
 258
 259 static struct i2c_client *cpld_client;
 260 static u32 am335x_evm_id;
 261 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
 262 };
 263
 264 /*
 265 * EVM Config held in On-Board eeprom device.
 266 *
 267 * Header Format
 268 *
 269 *  Name                 Size    Contents
 270 *                       (Bytes)
 271 *-------------------------------------------------------------
 272 *  Header               4       0xAA, 0x55, 0x33, 0xEE
 273 *
 274 *  Board Name           8       Name for board in ASCII.
 275 *                               example "A33515BB" = "AM335X
 276                                 Low Cost EVM board"
 277 *
 278 *  Version              4       Hardware version code for board in
 279 *                               in ASCII. "1.0A" = rev.01.0A
 280 *
 281 *  Serial Number        12      Serial number of the board. This is a 12
 282 *                               character string which is WWYY4P16nnnn, where
 283 *                               WW = 2 digit week of the year of production
 284 *                               YY = 2 digit year of production
 285 *                               nnnn = incrementing board number
 286 *
 287 *  Configuration option 32      Codes(TBD) to show the configuration
 288 *                               setup on this board.
 289 *
 290 *  Available            32720   Available space for other non-volatile
 291 *                               data.
 292 */
 293 struct am335x_evm_eeprom_config {
 294         u32     header;
 295         u8      name[8];
 296         char    version[4];
 297         u8      serial[12];
 298         u8      opt[32];
 299 };
 300
 301 static struct am335x_evm_eeprom_config config;
 302 static bool daughter_brd_detected;
 303
 304 #define GP_EVM_REV_IS_1_0               0x1
 305 #define GP_EVM_REV_IS_1_1A              0x2
 306 #define GP_EVM_REV_IS_UNKNOWN           0xFF
 307 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
 308 unsigned int gigabit_enable = 1;
 309
 310 #define EEPROM_MAC_ADDRESS_OFFSET       60 /* 4+8+4+12+32 */
 311 #define EEPROM_NO_OF_MAC_ADDR           3
 312 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
 313
 314 #define AM335X_EEPROM_HEADER            0xEE3355AA
 315
 316 /* current profile if exists else PROFILE_0 on error */
 317 static u32 am335x_get_profile_selection(void)
 318 {
 319         int val = 0;
 320
 321         if (!cpld_client)
 322                 /* error checking is not done in func's calling this routine.
 323                 so return profile 0 on error */
 324                 return 0;
 325
 326         val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
 327         if (val < 0)
 328                 return 0;       /* default to Profile 0 on Error */
 329         else
 330                 return val & 0x7;
 331 }
 332
 333 /* Module pin mux for LCDC */
 334 static struct pinmux_config lcdc_pin_mux[] = {
 335         {"lcd_data0.lcd_data0",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 336                                                        | AM33XX_PULL_DISA},
 337         {"lcd_data1.lcd_data1",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 338                                                        | AM33XX_PULL_DISA},
 339         {"lcd_data2.lcd_data2",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 340                                                        | AM33XX_PULL_DISA},
 341         {"lcd_data3.lcd_data3",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 342                                                        | AM33XX_PULL_DISA},
 343         {"lcd_data4.lcd_data4",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 344                                                        | AM33XX_PULL_DISA},
 345         {"lcd_data5.lcd_data5",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 346                                                        | AM33XX_PULL_DISA},
 347         {"lcd_data6.lcd_data6",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 348                                                        | AM33XX_PULL_DISA},
 349         {"lcd_data7.lcd_data7",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 350                                                        | AM33XX_PULL_DISA},
 351         {"lcd_data8.lcd_data8",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 352                                                        | AM33XX_PULL_DISA},
 353         {"lcd_data9.lcd_data9",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 354                                                        | AM33XX_PULL_DISA},
 355         {"lcd_data10.lcd_data10",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 356                                                        | AM33XX_PULL_DISA},
 357         {"lcd_data11.lcd_data11",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 358                                                        | AM33XX_PULL_DISA},
 359         {"lcd_data12.lcd_data12",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 360                                                        | AM33XX_PULL_DISA},
 361         {"lcd_data13.lcd_data13",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 362                                                        | AM33XX_PULL_DISA},
 363         {"lcd_data14.lcd_data14",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 364                                                        | AM33XX_PULL_DISA},
 365         {"lcd_data15.lcd_data15",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 366                                                        | AM33XX_PULL_DISA},
 367         {"gpmc_ad8.lcd_data16",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 368         {"gpmc_ad9.lcd_data17",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 369         {"gpmc_ad10.lcd_data18",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 370         {"gpmc_ad11.lcd_data19",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 371         {"gpmc_ad12.lcd_data20",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 372         {"gpmc_ad13.lcd_data21",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 373         {"gpmc_ad14.lcd_data22",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 374         {"gpmc_ad15.lcd_data23",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 375         {"lcd_vsync.lcd_vsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 376         {"lcd_hsync.lcd_hsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 377         {"lcd_pclk.lcd_pclk",           OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 378         {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 379         {NULL, 0},
 380 };
 381
 382 static struct pinmux_config tsc_pin_mux[] = {
 383         {"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 384         {"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 385         {"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 386         {"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 387         {"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 388         {"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 389         {NULL, 0},
 390 };
 391
 392 /* Pin mux for nand flash module */
 393 static struct pinmux_config nand_pin_mux[] = {
 394         {"gpmc_ad0.gpmc_ad0",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 395         {"gpmc_ad1.gpmc_ad1",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 396         {"gpmc_ad2.gpmc_ad2",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 397         {"gpmc_ad3.gpmc_ad3",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 398         {"gpmc_ad4.gpmc_ad4",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 399         {"gpmc_ad5.gpmc_ad5",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 400         {"gpmc_ad6.gpmc_ad6",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 401         {"gpmc_ad7.gpmc_ad7",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 402         {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 403         {"gpmc_wpn.gpmc_wpn",     OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 404         {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 405         {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 406         {"gpmc_oen_ren.gpmc_oen_ren",    OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 407         {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 408         {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 409         {NULL, 0},
 410 };
 411
 412 /* Module pin mux for SPI fash */
 413 static struct pinmux_config spi0_pin_mux[] = {
 414         {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
 415                                                         | AM33XX_INPUT_EN},
 416         {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
 417                                                         | AM33XX_INPUT_EN},
 418         {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
 419                                                         | AM33XX_INPUT_EN},
 420         {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
 421                                                         | AM33XX_INPUT_EN},
 422         {NULL, 0},
 423 };
 424
 425 /* Module pin mux for SPI flash */
 426 static struct pinmux_config spi1_pin_mux[] = {
 427         {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 428                 | AM33XX_INPUT_EN},
 429         {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 430                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
 431         {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 432                 | AM33XX_INPUT_EN},
 433         {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 434                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
 435         {NULL, 0},
 436 };
 437
 438 /* Module pin mux for rgmii1 */
 439 static struct pinmux_config rgmii1_pin_mux[] = {
 440         {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 441         {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 442         {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 443         {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 444         {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 445         {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 446         {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 447         {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 448         {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 449         {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 450         {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 451         {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 452         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 453         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 454         {NULL, 0},
 455 };
 456
 457 /* Module pin mux for rgmii2 */
 458 static struct pinmux_config rgmii2_pin_mux[] = {
 459         {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 460         {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 461         {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 462         {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 463         {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 464         {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 465         {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 466         {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 467         {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 468         {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 469         {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 470         {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 471         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 472         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 473         {NULL, 0},
 474 };
 475
 476 /* Module pin mux for mii1 */
 477 static struct pinmux_config mii1_pin_mux[] = {
 478         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 479         {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 480         {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 481         {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 482         {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 483         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 484         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 485         {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 486         {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 487         {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 488         {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 489         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 490         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 491         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 492         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 493         {NULL, 0},
 494 };
 495
 496 /* Module pin mux for rmii1 */
 497 static struct pinmux_config rmii1_pin_mux[] = {
 498         {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 499         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 500         {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 501         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 502         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 503         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 504         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 505         {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 506         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 507         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 508         {NULL, 0},
 509 };
 510
 511 static struct pinmux_config i2c1_pin_mux[] = {
 512         {"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
 513                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
 514         {"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
 515                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
 516         {NULL, 0},
 517 };
 518
 519 /* Module pin mux for mcasp1 */
 520 static struct pinmux_config mcasp1_pin_mux[] = {
 521         {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 522         {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 523         {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 524         {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
 525                                                 AM33XX_PIN_INPUT_PULLDOWN},
 526         {NULL, 0},
 527 };
 528
 529
 530 /* Module pin mux for mmc0 */
 531 static struct pinmux_config mmc0_pin_mux[] = {
 532         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 533         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 534         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 535         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 536         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 537         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 538         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 539         {"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 540         {NULL, 0},
 541 };
 542
 543 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
 544         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 545         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 546         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 547         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 548         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 549         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 550         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 551         {NULL, 0},
 552 };
 553
 554 /* Module pin mux for mmc1 */
 555 static struct pinmux_config mmc1_pin_mux[] = {
 556         {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 557         {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 558         {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 559         {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 560         {"gpmc_ad3.mmc1_dat3",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 561         {"gpmc_ad2.mmc1_dat2",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 562         {"gpmc_ad1.mmc1_dat1",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 563         {"gpmc_ad0.mmc1_dat0",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
 564         {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 565         {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 566         {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 567         {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 568         {NULL, 0},
 569 };
 570
 571 /* Module pin mux for uart3 */
 572 static struct pinmux_config uart3_pin_mux[] = {
 573         {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
 574         {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
 575         {NULL, 0},
 576 };
 577
 578 static struct pinmux_config d_can_gp_pin_mux[] = {
 579         {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
 580         {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 581         {NULL, 0},
 582 };
 583
 584 static struct pinmux_config d_can_ia_pin_mux[] = {
 585         {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
 586         {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 587         {NULL, 0},
 588 };
 589
 590 /* Module pin mux for uart2 */
 591 static struct pinmux_config uart2_pin_mux[] = {
 592         {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
 593                                                 AM33XX_PIN_INPUT_PULLUP},
 594         {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
 595                                                 AM33XX_PULL_DISA |
 596                                                 AM33XX_SLEWCTRL_SLOW},
 597         {NULL, 0},
 598 };
 599
 600
 601 /*
 602 * @pin_mux - single module pin-mux structure which defines pin-mux
 603 *                       details for all its pins.
 604 */
 605 static void setup_pin_mux(struct pinmux_config *pin_mux)
 606 {
 607         int i;
 608
 609         for (i = 0; pin_mux->string_name != NULL; pin_mux++)
 610                 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
 611
 612 }
 613
 614 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
 615
 616 /* pinmux for keypad device */
 617 static struct pinmux_config matrix_keypad_pin_mux[] = {
 618         {"gpmc_a5.gpio1_21",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 619         {"gpmc_a6.gpio1_22",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 620         {"gpmc_a9.gpio1_25",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 621         {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 622         {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 623         {NULL, 0},
 624 };
 625
 626 /* Keys mapping */
 627 static const uint32_t am335x_evm_matrix_keys[] = {
 628         KEY(0, 0, KEY_MENU),
 629         KEY(1, 0, KEY_BACK),
 630         KEY(2, 0, KEY_LEFT),
 631
 632         KEY(0, 1, KEY_RIGHT),
 633         KEY(1, 1, KEY_ENTER),
 634         KEY(2, 1, KEY_DOWN),
 635 };
 636
 637 const struct matrix_keymap_data am335x_evm_keymap_data = {
 638         .keymap      = am335x_evm_matrix_keys,
 639         .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
 640 };
 641
 642 static const unsigned int am335x_evm_keypad_row_gpios[] = {
 643         GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
 644 };
 645
 646 static const unsigned int am335x_evm_keypad_col_gpios[] = {
 647         GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
 648 };
 649
 650 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
 651         .keymap_data       = &am335x_evm_keymap_data,
 652         .row_gpios         = am335x_evm_keypad_row_gpios,
 653         .num_row_gpios     = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
 654         .col_gpios         = am335x_evm_keypad_col_gpios,
 655         .num_col_gpios     = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
 656         .active_low        = false,
 657         .debounce_ms       = 5,
 658         .col_scan_delay_us = 2,
 659 };
 660
 661 static struct platform_device am335x_evm_keyboard = {
 662         .name  = "matrix-keypad",
 663         .id    = -1,
 664         .dev   = {
 665                 .platform_data = &am335x_evm_keypad_platform_data,
 666         },
 667 };
 668
 669 static void matrix_keypad_init(int evm_id, int profile)
 670 {
 671         int err;
 672
 673         setup_pin_mux(matrix_keypad_pin_mux);
 674         err = platform_device_register(&am335x_evm_keyboard);
 675         if (err) {
 676                 pr_err("failed to register matrix keypad (2x3) device\n");
 677         }
 678 }
 679
 680
 681 /* pinmux for keypad device */
 682 static struct pinmux_config volume_keys_pin_mux[] = {
 683         {"spi0_sclk.gpio0_2",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 684         {"spi0_d0.gpio0_3",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 685         {NULL, 0},
 686 };
 687
 688 /* Configure GPIOs for Volume Keys */
 689 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
 690         {
 691                 .code                   = KEY_VOLUMEUP,
 692                 .gpio                   = GPIO_TO_PIN(0, 2),
 693                 .active_low             = true,
 694                 .desc                   = "volume-up",
 695                 .type                   = EV_KEY,
 696                 .wakeup                 = 1,
 697         },
 698         {
 699                 .code                   = KEY_VOLUMEDOWN,
 700                 .gpio                   = GPIO_TO_PIN(0, 3),
 701                 .active_low             = true,
 702                 .desc                   = "volume-down",
 703                 .type                   = EV_KEY,
 704                 .wakeup                 = 1,
 705         },
 706 };
 707
 708 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
 709         .buttons        = am335x_evm_volume_gpio_buttons,
 710         .nbuttons       = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
 711 };
 712
 713 static struct platform_device am335x_evm_volume_keys = {
 714         .name   = "gpio-keys",
 715         .id     = -1,
 716         .dev    = {
 717                 .platform_data  = &am335x_evm_volume_gpio_key_info,
 718         },
 719 };
 720
 721 static void volume_keys_init(int evm_id, int profile)
 722 {
 723         int err;
 724
 725         setup_pin_mux(volume_keys_pin_mux);
 726         err = platform_device_register(&am335x_evm_volume_keys);
 727         if (err)
 728                 pr_err("failed to register matrix keypad (2x3) device\n");
 729 }
 730
 731 /*
 732 * @evm_id - evm id which needs to be configured
 733 * @dev_cfg - single evm structure which includes
 734 *                               all module inits, pin-mux defines
 735 * @profile - if present, else PROFILE_NONE
 736 * @dghtr_brd_flg - Whether Daughter board is present or not
 737 */
 738 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
 739         int profile)
 740 {
 741         int i;
 742
 743         /*
 744         * Only General Purpose & Industrial Auto Motro Control
 745         * EVM has profiles. So check if this evm has profile.
 746         * If not, ignore the profile comparison
 747         */
 748
 749         /*
 750         * If the device is on baseboard, directly configure it. Else (device on
 751         * Daughter board), check if the daughter card is detected.
 752         */
 753         if (profile == PROFILE_NONE) {
 754                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
 755                         if (dev_cfg->device_on == DEV_ON_BASEBOARD)
 756                                 dev_cfg->device_init(evm_id, profile);
 757                         else if (daughter_brd_detected == true)
 758                                 dev_cfg->device_init(evm_id, profile);
 759                 }
 760         } else {
 761                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
 762                         if (dev_cfg->profile & profile) {
 763                                 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
 764                                         dev_cfg->device_init(evm_id, profile);
 765                                 else if (daughter_brd_detected == true)
 766                                         dev_cfg->device_init(evm_id, profile);
 767                         }
 768                 }
 769         }
 770 }
 771
 772 #define AM335X_LCD_BL_PIN       GPIO_TO_PIN(0, 7)
 773
 774 /* pinmux for usb0 drvvbus */
 775 static struct pinmux_config usb0_pin_mux[] = {
 776         {"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 777         {NULL, 0},
 778 };
 779
 780 /* pinmux for usb1 drvvbus */
 781 static struct pinmux_config usb1_pin_mux[] = {
 782         {"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 783         {NULL, 0},
 784 };
 785
 786 /* pinmux for profibus */
 787 static struct pinmux_config profibus_pin_mux[] = {
 788         {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
 789         {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
 790         {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
 791         {NULL, 0},
 792 };
 793
 794 /* Module pin mux for eCAP0 */
 795 static struct pinmux_config ecap0_pin_mux[] = {
 796         {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
 797         {NULL, 0},
 798 };
 799
 800 static int backlight_enable;
 801
 802 #define AM335XEVM_WLAN_PMENA_GPIO       GPIO_TO_PIN(1, 30)
 803 #define AM335XEVM_WLAN_IRQ_GPIO         GPIO_TO_PIN(3, 17)
 804
 805 struct wl12xx_platform_data am335xevm_wlan_data = {
 806         .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
 807         .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
 808 };
 809
 810 /* Module pin mux for wlan and bluetooth */
 811 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
 812         {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 813         {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 814         {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 815         {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 816         {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 817         {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 818         {NULL, 0},
 819 };
 820
 821 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
 822         {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 823         {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
 824         {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 825         {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
 826         {NULL, 0},
 827 };
 828
 829 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
 830         {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 831         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 832         {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 833         {NULL, 0},
 834  };
 835
 836 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
 837         {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 838         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 839         {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 840         {NULL, 0},
 841  };
 842
 843 static void enable_ecap0(int evm_id, int profile)
 844 {
 845         backlight_enable = true;
 846 }
 847
 848 static int __init ecap0_init(void)
 849 {
 850         int status = 0;
 851
 852         if (backlight_enable) {
 853                 setup_pin_mux(ecap0_pin_mux);
 854
 855                 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
 856                 if (status < 0)
 857                         pr_warn("Failed to request gpio for LCD backlight\n");
 858
 859                 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
 860         }
 861         return status;
 862 }
 863 late_initcall(ecap0_init);
 864
 865 static int __init conf_disp_pll(int rate)
 866 {
 867         struct clk *disp_pll;
 868         int ret = -EINVAL;
 869
 870         disp_pll = clk_get(NULL, "dpll_disp_ck");
 871         if (IS_ERR(disp_pll)) {
 872                 pr_err("Cannot clk_get disp_pll\n");
 873                 goto out;
 874         }
 875
 876         ret = clk_set_rate(disp_pll, rate);
 877         clk_put(disp_pll);
 878 out:
 879         return ret;
 880 }
 881
 882 static void lcdc_init(int evm_id, int profile)
 883 {
 884
 885         setup_pin_mux(lcdc_pin_mux);
 886
 887         if (conf_disp_pll(300000000)) {
 888                 pr_info("Failed configure display PLL, not attempting to"
 889                                 "register LCDC\n");
 890                 return;
 891         }
 892
 893         if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
 894                 pr_info("Failed to register LCDC device\n");
 895         return;
 896 }
 897
 898 static void tsc_init(int evm_id, int profile)
 899 {
 900         int err;
 901
 902         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
 903                 am335x_touchscreen_data.analog_input = 1;
 904                 pr_info("TSC connected to beta GP EVM\n");
 905         } else {
 906                 am335x_touchscreen_data.analog_input = 0;
 907                 pr_info("TSC connected to alpha GP EVM\n");
 908         }
 909         setup_pin_mux(tsc_pin_mux);
 910         err = platform_device_register(&tsc_device);
 911         if (err)
 912                 pr_err("failed to register touchscreen device\n");
 913 }
 914
 915 static void rgmii1_init(int evm_id, int profile)
 916 {
 917         setup_pin_mux(rgmii1_pin_mux);
 918         return;
 919 }
 920
 921 static void rgmii2_init(int evm_id, int profile)
 922 {
 923         setup_pin_mux(rgmii2_pin_mux);
 924         return;
 925 }
 926
 927 static void mii1_init(int evm_id, int profile)
 928 {
 929         setup_pin_mux(mii1_pin_mux);
 930         return;
 931 }
 932
 933 static void rmii1_init(int evm_id, int profile)
 934 {
 935         setup_pin_mux(rmii1_pin_mux);
 936         return;
 937 }
 938
 939 static void usb0_init(int evm_id, int profile)
 940 {
 941         setup_pin_mux(usb0_pin_mux);
 942         return;
 943 }
 944
 945 static void usb1_init(int evm_id, int profile)
 946 {
 947         setup_pin_mux(usb1_pin_mux);
 948         return;
 949 }
 950
 951 /* setup uart3 */
 952 static void uart3_init(int evm_id, int profile)
 953 {
 954         setup_pin_mux(uart3_pin_mux);
 955         return;
 956 }
 957
 958 /* setup uart2 */
 959 static void uart2_init(int evm_id, int profile)
 960 {
 961         setup_pin_mux(uart2_pin_mux);
 962         return;
 963 }
 964
 965 /* NAND partition information */
 966 static struct mtd_partition am335x_nand_partitions[] = {
 967 /* All the partition sizes are listed in terms of NAND block size */
 968         {
 969                 .name           = "SPL",
 970                 .offset         = 0,                    /* Offset = 0x0 */
 971                 .size           = SZ_128K,
 972         },
 973         {
 974                 .name           = "SPL.backup1",
 975                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x20000 */
 976                 .size           = SZ_128K,
 977         },
 978         {
 979                 .name           = "SPL.backup2",
 980                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x40000 */
 981                 .size           = SZ_128K,
 982         },
 983         {
 984                 .name           = "SPL.backup3",
 985                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x60000 */
 986                 .size           = SZ_128K,
 987         },
 988         {
 989                 .name           = "U-Boot",
 990                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
 991                 .size           = 15 * SZ_128K,
 992         },
 993         {
 994                 .name           = "U-Boot Env",
 995                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
 996                 .size           = 1 * SZ_128K,
 997         },
 998         {
 999                 .name           = "Kernel",
1000                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
1001                 .size           = 40 * SZ_128K,
1002         },
1003         {
1004                 .name           = "File System",
1005                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
1006                 .size           = MTDPART_SIZ_FULL,
1007         },
1008 };
1009
1010 /* SPI 0/1 Platform Data */
1011 /* SPI flash information */
1012 static struct mtd_partition am335x_spi_partitions[] = {
1013         /* All the partition sizes are listed in terms of erase size */
1014         {
1015                 .name       = "SPL",
1016                 .offset     = 0,                        /* Offset = 0x0 */
1017                 .size       = SZ_128K,
1018         },
1019         {
1020                 .name       = "U-Boot",
1021                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x20000 */
1022                 .size       = 2 * SZ_128K,
1023         },
1024         {
1025                 .name       = "U-Boot Env",
1026                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x60000 */
1027                 .size       = 2 * SZ_4K,
1028         },
1029         {
1030                 .name       = "Kernel",
1031                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x62000 */
1032                 .size       = 28 * SZ_128K,
1033         },
1034         {
1035                 .name       = "File System",
1036                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x3E2000 */
1037                 .size       = MTDPART_SIZ_FULL,         /* size ~= 4.1 MiB */
1038         }
1039 };
1040
1041 static const struct flash_platform_data am335x_spi_flash = {
1042         .type      = "w25q64",
1043         .name      = "spi_flash",
1044         .parts     = am335x_spi_partitions,
1045         .nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
1046 };
1047
1048 /*
1049  * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1050  * So setup Max speed to be less than that of Controller speed
1051  */
1052 static struct spi_board_info am335x_spi0_slave_info[] = {
1053         {
1054                 .modalias      = "m25p80",
1055                 .platform_data = &am335x_spi_flash,
1056                 .irq           = -1,
1057                 .max_speed_hz  = 24000000,
1058                 .bus_num       = 1,
1059                 .chip_select   = 0,
1060         },
1061 };
1062
1063 static struct spi_board_info am335x_spi1_slave_info[] = {
1064         {
1065                 .modalias      = "m25p80",
1066                 .platform_data = &am335x_spi_flash,
1067                 .irq           = -1,
1068                 .max_speed_hz  = 12000000,
1069                 .bus_num       = 2,
1070                 .chip_select   = 0,
1071         },
1072 };
1073
1074 static void evm_nand_init(int evm_id, int profile)
1075 {
1076         setup_pin_mux(nand_pin_mux);
1077         board_nand_init(am335x_nand_partitions,
1078                 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1079 }
1080
1081 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1082         .click_flags = LIS3_CLICK_SINGLE_X |
1083                         LIS3_CLICK_SINGLE_Y |
1084                         LIS3_CLICK_SINGLE_Z,
1085         .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1086                         LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1087                         LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1088         .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1089         .wakeup_thresh  = 10,
1090         .click_thresh_x = 10,
1091         .click_thresh_y = 10,
1092         .click_thresh_z = 10,
1093         .g_range        = 2,
1094         .st_min_limits[0] = 120,
1095         .st_min_limits[1] = 120,
1096         .st_min_limits[2] = 140,
1097         .st_max_limits[0] = 550,
1098         .st_max_limits[1] = 550,
1099         .st_max_limits[2] = 750,
1100 };
1101
1102 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1103         {
1104                 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1105         },
1106         {
1107                 I2C_BOARD_INFO("lis331dlh", 0x18),
1108                 .platform_data = &lis331dlh_pdata,
1109         },
1110         {
1111                 I2C_BOARD_INFO("tsl2550", 0x39),
1112         },
1113         {
1114                 I2C_BOARD_INFO("tmp275", 0x48),
1115         },
1116 };
1117
1118 static void i2c1_init(int evm_id, int profile)
1119 {
1120         setup_pin_mux(i2c1_pin_mux);
1121         omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1122                         ARRAY_SIZE(am335x_i2c_boardinfo1));
1123         return;
1124 }
1125
1126 /* Setup McASP 1 */
1127 static void mcasp1_init(int evm_id, int profile)
1128 {
1129         /* Configure McASP */
1130         setup_pin_mux(mcasp1_pin_mux);
1131         am335x_register_mcasp1(&am335x_evm_snd_data1);
1132         return;
1133 }
1134
1135 static void mmc1_init(int evm_id, int profile)
1136 {
1137         setup_pin_mux(mmc1_pin_mux);
1138
1139         am335x_mmc[1].mmc = 2;
1140         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1141         am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1142         am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1143         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1144
1145         /* mmc will be initialized when mmc0_init is called */
1146         return;
1147 }
1148
1149 static void mmc2_wl12xx_init(int evm_id, int profile)
1150 {
1151         setup_pin_mux(mmc2_wl12xx_pin_mux);
1152
1153         am335x_mmc[1].mmc = 3;
1154         am335x_mmc[1].name = "wl1271";
1155         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1156                                 | MMC_PM_KEEP_POWER;
1157         am335x_mmc[1].nonremovable = true;
1158         am335x_mmc[1].gpio_cd = -EINVAL;
1159         am335x_mmc[1].gpio_wp = -EINVAL;
1160         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1161
1162         /* mmc will be initialized when mmc0_init is called */
1163         return;
1164 }
1165
1166 static void uart1_wl12xx_init(int evm_id, int profile)
1167 {
1168         setup_pin_mux(uart1_wl12xx_pin_mux);
1169 }
1170
1171 static void wl12xx_bluetooth_enable(void)
1172 {
1173         int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1174                 "bt_en\n");
1175         if (status < 0)
1176                 pr_err("Failed to request gpio for bt_enable");
1177
1178         pr_info("Configure Bluetooth Enable pin...\n");
1179         gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1180 }
1181
1182 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1183 {
1184         if (on) {
1185                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1186                 mdelay(70);
1187         }
1188         else
1189                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1190
1191         return 0;
1192 }
1193
1194 static void wl12xx_init(int evm_id, int profile)
1195 {
1196         struct device *dev;
1197         struct omap_mmc_platform_data *pdata;
1198         int ret;
1199
1200         /* Register WLAN and BT enable pins based on the evm board revision */
1201         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1202                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1203                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1204         }
1205         else {
1206                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1207                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1208         }
1209
1210         wl12xx_bluetooth_enable();
1211
1212         if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1213                 pr_err("error setting wl12xx data\n");
1214
1215         dev = am335x_mmc[1].dev;
1216         if (!dev) {
1217                 pr_err("wl12xx mmc device initialization failed\n");
1218                 goto out;
1219         }
1220
1221         pdata = dev->platform_data;
1222         if (!pdata) {
1223                 pr_err("Platfrom data of wl12xx device not set\n");
1224                 goto out;
1225         }
1226
1227         ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1228                 GPIOF_OUT_INIT_LOW, "wlan_en");
1229         if (ret) {
1230                 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1231                 goto out;
1232         }
1233
1234         if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1235                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1236         else
1237                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1238
1239         pdata->slots[0].set_power = wl12xx_set_power;
1240 out:
1241         return;
1242 }
1243
1244 static void d_can_init(int evm_id, int profile)
1245 {
1246         switch (evm_id) {
1247         case IND_AUT_MTR_EVM:
1248                 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1249                         setup_pin_mux(d_can_ia_pin_mux);
1250                         /* Instance Zero */
1251                         am33xx_d_can_init(0);
1252                 }
1253                 break;
1254         case GEN_PURP_EVM:
1255                 if (profile == PROFILE_1) {
1256                         setup_pin_mux(d_can_gp_pin_mux);
1257                         /* Instance One */
1258                         am33xx_d_can_init(1);
1259                 }
1260                 break;
1261         default:
1262                 break;
1263         }
1264 }
1265
1266 static void mmc0_init(int evm_id, int profile)
1267 {
1268         setup_pin_mux(mmc0_pin_mux);
1269
1270         omap2_hsmmc_init(am335x_mmc);
1271         return;
1272 }
1273
1274 static void mmc0_no_cd_init(int evm_id, int profile)
1275 {
1276         setup_pin_mux(mmc0_no_cd_pin_mux);
1277
1278         omap2_hsmmc_init(am335x_mmc);
1279         return;
1280 }
1281
1282
1283 /* setup spi0 */
1284 static void spi0_init(int evm_id, int profile)
1285 {
1286         setup_pin_mux(spi0_pin_mux);
1287         spi_register_board_info(am335x_spi0_slave_info,
1288                         ARRAY_SIZE(am335x_spi0_slave_info));
1289         return;
1290 }
1291
1292 /* setup spi1 */
1293 static void spi1_init(int evm_id, int profile)
1294 {
1295         setup_pin_mux(spi1_pin_mux);
1296         spi_register_board_info(am335x_spi1_slave_info,
1297                         ARRAY_SIZE(am335x_spi1_slave_info));
1298         return;
1299 }
1300
1301
1302 static int beaglebone_phy_fixup(struct phy_device *phydev)
1303 {
1304         phydev->supported &= ~(SUPPORTED_100baseT_Half |
1305                                 SUPPORTED_100baseT_Full);
1306
1307         return 0;
1308 }
1309
1310 #if defined(CONFIG_TLK110_WORKAROUND) || \
1311                         defined(CONFIG_TLK110_WORKAROUND_MODULE)
1312 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1313 {
1314         unsigned int val;
1315
1316         /* This is done as a workaround to support TLK110 rev1.0 phy */
1317         val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1318         phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1319
1320         val = phy_read(phydev, TLK110_LPFHPF_REG);
1321         phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1322
1323         val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1324         phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1325
1326         val = phy_read(phydev, TLK110_VRCR_REG);
1327         phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1328
1329         val = phy_read(phydev, TLK110_SETFFE_REG);
1330         phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1331
1332         val = phy_read(phydev, TLK110_FTSP_REG);
1333         phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1334
1335         val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1336         phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1337
1338         val = phy_read(phydev, TLK110_PSCOEF21_REG);
1339         phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1340
1341         val = phy_read(phydev, TLK110_PSCOEF3_REG);
1342         phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1343
1344         val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1345         phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1346
1347         val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1348         phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1349
1350         val = phy_read(phydev, TLK110_CFGPS_REG);
1351         phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1352
1353         val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1354         phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1355
1356         val = phy_read(phydev, TLK110_SWSCR3_REG);
1357         phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1358
1359         val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1360         phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1361
1362         val = phy_read(phydev, TLK110_PHYRCR_REG);
1363         phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1364
1365         return 0;
1366 }
1367 #endif
1368
1369 static void profibus_init(int evm_id, int profile)
1370 {
1371         setup_pin_mux(profibus_pin_mux);
1372         return;
1373 }
1374
1375 /* Low-Cost EVM */
1376 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1377         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1378         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1379         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1380         {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1381         {NULL, 0, 0},
1382 };
1383
1384 /* General Purpose EVM */
1385 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1386         {enable_ecap0,  DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1387                                                 PROFILE_2 | PROFILE_7) },
1388         {lcdc_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1389                                                 PROFILE_2 | PROFILE_7) },
1390         {tsc_init,      DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1391                                                 PROFILE_2 | PROFILE_7) },
1392         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
1393         {rgmii2_init,   DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1394                                                 PROFILE_4 | PROFILE_6) },
1395         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1396         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1397         {evm_nand_init, DEV_ON_DGHTR_BRD,
1398                 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1399         {i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1400         {mcasp1_init,   DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1401         {mmc1_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1402         {mmc2_wl12xx_init,      DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1403                                                                 PROFILE_5)},
1404         {mmc0_init,     DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1405         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_5},
1406         {spi0_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1407         {uart1_wl12xx_init,     DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1408                                                                 PROFILE_5)},
1409         {wl12xx_init,   DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1410         {d_can_init,    DEV_ON_DGHTR_BRD, PROFILE_1},
1411         {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1412         {volume_keys_init,  DEV_ON_DGHTR_BRD, PROFILE_0},
1413         {uart2_init,    DEV_ON_DGHTR_BRD, PROFILE_3},
1414         {NULL, 0, 0},
1415 };
1416
1417 /* Industrial Auto Motor Control EVM */
1418 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1419         {mii1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1420         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1421         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1422         {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1423         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1424         {spi1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1425         {uart3_init,    DEV_ON_DGHTR_BRD, PROFILE_ALL},
1426         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1427         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_ALL},
1428         {NULL, 0, 0},
1429 };
1430
1431 /* IP-Phone EVM */
1432 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1433         {enable_ecap0,  DEV_ON_DGHTR_BRD, PROFILE_NONE},
1434         {lcdc_init,     DEV_ON_DGHTR_BRD, PROFILE_NONE},
1435         {tsc_init,      DEV_ON_DGHTR_BRD, PROFILE_NONE},
1436         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1437         {rgmii2_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1438         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1439         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1440         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1441         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1442         {mcasp1_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1443         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1444         {NULL, 0, 0},
1445 };
1446
1447 /* Beaglebone < Rev A3 */
1448 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1449         {rmii1_init,    DEV_ON_BASEBOARD, PROFILE_NONE},
1450         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1451         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1452         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1453         {NULL, 0, 0},
1454 };
1455
1456 /* Beaglebone Rev A3 and after */
1457 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1458         {mii1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1459         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1460         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1461         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1462         {NULL, 0, 0},
1463 };
1464
1465 static void setup_low_cost_evm(void)
1466 {
1467         pr_info("The board is a AM335x Low Cost EVM.\n");
1468
1469         _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1470 }
1471
1472 static void setup_general_purpose_evm(void)
1473 {
1474         u32 prof_sel = am335x_get_profile_selection();
1475         pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1476
1477         if (!strncmp("1.1A", config.version, 4)) {
1478                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1479         } else if (!strncmp("1.0", config.version, 3)) {
1480                 gp_evm_revision = GP_EVM_REV_IS_1_0;
1481         } else {
1482                 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1483                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1484         }
1485
1486         if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1487                 gigabit_enable = 0;
1488         else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1489                 gigabit_enable = 1;
1490
1491         _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1492 }
1493
1494 static void setup_ind_auto_motor_ctrl_evm(void)
1495 {
1496         u32 prof_sel = am335x_get_profile_selection();
1497
1498         pr_info("The board is an industrial automation EVM in profile %d\n",
1499                 prof_sel);
1500
1501         /* Only Profile 0 is supported */
1502         if ((1L << prof_sel) != PROFILE_0) {
1503                 pr_err("AM335X: Only Profile 0 is supported\n");
1504                 pr_err("Assuming profile 0 & continuing\n");
1505                 prof_sel = PROFILE_0;
1506         }
1507
1508         _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1509                 PROFILE_0);
1510
1511         /* Fillup global evmid */
1512         am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1513
1514         /* Initialize TLK110 PHY registers for phy version 1.0 */
1515         am335x_tlk110_phy_init();
1516
1517
1518 }
1519
1520 static void setup_ip_phone_evm(void)
1521 {
1522         pr_info("The board is an IP phone EVM\n");
1523
1524         _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1525 }
1526
1527 /* BeagleBone < Rev A3 */
1528 static void setup_beaglebone_old(void)
1529 {
1530         pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1531
1532         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1533         am335x_mmc[0].gpio_wp = -EINVAL;
1534
1535         _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1536
1537         phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1538                                         beaglebone_phy_fixup);
1539 }
1540
1541 /* BeagleBone after Rev A3 */
1542 static void setup_beaglebone(void)
1543 {
1544         pr_info("The board is a AM335x Beaglebone.\n");
1545
1546         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1547         am335x_mmc[0].gpio_wp = -EINVAL;
1548
1549         _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1550 }
1551
1552
1553 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1554 {
1555         u8 tmp;
1556         int ret;
1557
1558         /*
1559          * try reading a byte from the EEPROM to see if it is
1560          * present. We could read a lot more, but that would
1561          * just slow the boot process and we have all the information
1562          * we need from the EEPROM on the base board anyway.
1563          */
1564         ret = m->read(m, &tmp, 0, sizeof(u8));
1565         if (ret == sizeof(u8)) {
1566                 pr_info("Detected a daughter card on AM335x EVM..");
1567                 daughter_brd_detected = true;
1568         } else {
1569                 pr_info("No daughter card found\n");
1570                 daughter_brd_detected = false;
1571         }
1572 }
1573
1574 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1575 {
1576         int ret;
1577         char tmp[10];
1578
1579         /* 1st get the MAC address from EEPROM */
1580         ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1581                 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1582
1583         if (ret != sizeof(am335x_mac_addr)) {
1584                 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1585                 return;
1586         }
1587
1588         /* Fillup global mac id */
1589         am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1590                                 &am335x_mac_addr[1][0]);
1591
1592         /* get board specific data */
1593         ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1594         if (ret != sizeof(config)) {
1595                 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1596                 return;
1597         }
1598
1599         if (config.header != AM335X_EEPROM_HEADER) {
1600                 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1601                         config.header, AM335X_EEPROM_HEADER);
1602                 goto out;
1603         }
1604
1605         if (strncmp("A335", config.name, 4)) {
1606                 pr_err("Board %s doesn't look like an AM335x board\n",
1607                         config.name);
1608                 goto out;
1609         }
1610
1611         snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1612         pr_info("Board name: %s\n", tmp);
1613         snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1614         pr_info("Board version: %s\n", tmp);
1615
1616         if (!strncmp("A335BONE", config.name, 8)) {
1617                 daughter_brd_detected = false;
1618                 if(!strncmp("00A1", config.version, 4) ||
1619                    !strncmp("00A2", config.version, 4))
1620                         setup_beaglebone_old();
1621                 else
1622                         setup_beaglebone();
1623         } else {
1624                 /* only 6 characters of options string used for now */
1625                 snprintf(tmp, 7, "%s", config.opt);
1626                 pr_info("SKU: %s\n", tmp);
1627
1628                 if (!strncmp("SKU#00", config.opt, 6))
1629                         setup_low_cost_evm();
1630                 else if (!strncmp("SKU#01", config.opt, 6))
1631                         setup_general_purpose_evm();
1632                 else if (!strncmp("SKU#02", config.opt, 6))
1633                         setup_ind_auto_motor_ctrl_evm();
1634                 else if (!strncmp("SKU#03", config.opt, 6))
1635                         setup_ip_phone_evm();
1636                 else
1637                         goto out;
1638         }
1639         /* Initialize cpsw after board detection is completed as board
1640          * information is required for configuring phy address and hence
1641          * should be call only after board detection
1642          */
1643         am33xx_cpsw_init(gigabit_enable);
1644
1645         return;
1646 out:
1647         /*
1648          * If the EEPROM hasn't been programed or an incorrect header
1649          * or board name are read, assume this is an old beaglebone board
1650          * (< Rev A3)
1651          */
1652         pr_err("Could not detect any board, falling back to: "
1653                 "Beaglebone (< Rev A3) with no daughter card connected\n");
1654         daughter_brd_detected = false;
1655         setup_beaglebone_old();
1656
1657         /* Initialize cpsw after board detection is completed as board
1658          * information is required for configuring phy address and hence
1659          * should be call only after board detection
1660          */
1661
1662         am33xx_cpsw_init(gigabit_enable);
1663 }
1664
1665 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1666         .byte_len       = (256*1024) / 8,
1667         .page_size      = 64,
1668         .flags          = AT24_FLAG_ADDR16,
1669         .setup          = am335x_setup_daughter_board,
1670         .context        = (void *)NULL,
1671 };
1672
1673 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1674         .byte_len       = (256*1024) / 8,
1675         .page_size      = 64,
1676         .flags          = AT24_FLAG_ADDR16,
1677         .setup          = am335x_evm_setup,
1678         .context        = (void *)NULL,
1679 };
1680
1681 /*
1682 * Daughter board Detection.
1683 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1684 * machine init, starting from daughter board and ending with baseboard.
1685 * Assumptions :
1686 *       1. probe for i2c devices are called in the order they are included in
1687 *          the below struct. Daughter boards eeprom are probed 1st. Baseboard
1688 *          eeprom probe is called last.
1689 */
1690 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1691         {
1692                 /* Daughter Board EEPROM */
1693                 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1694                 .platform_data  = &am335x_daughter_board_eeprom_info,
1695         },
1696         {
1697                 /* Baseboard board EEPROM */
1698                 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1699                 .platform_data  = &am335x_baseboard_eeprom_info,
1700         },
1701         {
1702                 I2C_BOARD_INFO("cpld_reg", 0x35),
1703         },
1704         {
1705                 I2C_BOARD_INFO("tlc59108", 0x40),
1706         },
1707
1708 };
1709
1710 static struct omap_musb_board_data musb_board_data = {
1711         .interface_type = MUSB_INTERFACE_ULPI,
1712         .mode           = MUSB_OTG,
1713         .power          = 500,
1714         .instances      = 1,
1715 };
1716
1717 static int cpld_reg_probe(struct i2c_client *client,
1718             const struct i2c_device_id *id)
1719 {
1720         cpld_client = client;
1721         return 0;
1722 }
1723
1724 static int __devexit cpld_reg_remove(struct i2c_client *client)
1725 {
1726         cpld_client = NULL;
1727         return 0;
1728 }
1729
1730 static const struct i2c_device_id cpld_reg_id[] = {
1731         { "cpld_reg", 0 },
1732         { }
1733 };
1734
1735 static struct i2c_driver cpld_reg_driver = {
1736         .driver = {
1737                 .name   = "cpld_reg",
1738         },
1739         .probe          = cpld_reg_probe,
1740         .remove         = cpld_reg_remove,
1741         .id_table       = cpld_reg_id,
1742 };
1743
1744 static void evm_init_cpld(void)
1745 {
1746         i2c_add_driver(&cpld_reg_driver);
1747 }
1748
1749 static void __init am335x_evm_i2c_init(void)
1750 {
1751         /* Initially assume Low Cost EVM Config */
1752         am335x_evm_id = LOW_COST_EVM;
1753
1754         evm_init_cpld();
1755
1756         omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1757                                 ARRAY_SIZE(am335x_i2c_boardinfo));
1758 }
1759
1760 static struct resource am335x_rtc_resources[] = {
1761         {
1762                 .start          = AM33XX_RTC_BASE,
1763                 .end            = AM33XX_RTC_BASE + SZ_4K - 1,
1764                 .flags          = IORESOURCE_MEM,
1765         },
1766         { /* timer irq */
1767                 .start          = AM33XX_IRQ_RTC_TIMER,
1768                 .end            = AM33XX_IRQ_RTC_TIMER,
1769                 .flags          = IORESOURCE_IRQ,
1770         },
1771         { /* alarm irq */
1772                 .start          = AM33XX_IRQ_RTC_ALARM,
1773                 .end            = AM33XX_IRQ_RTC_ALARM,
1774                 .flags          = IORESOURCE_IRQ,
1775         },
1776 };
1777
1778 static struct platform_device am335x_rtc_device = {
1779         .name           = "omap_rtc",
1780         .id             = -1,
1781         .num_resources  = ARRAY_SIZE(am335x_rtc_resources),
1782         .resource       = am335x_rtc_resources,
1783 };
1784
1785 static int am335x_rtc_init(void)
1786 {
1787         void __iomem *base;
1788         struct clk *clk;
1789
1790         clk = clk_get(NULL, "rtc_fck");
1791         if (IS_ERR(clk)) {
1792                 pr_err("rtc : Failed to get RTC clock\n");
1793                 return -1;
1794         }
1795
1796         if (clk_enable(clk)) {
1797                 pr_err("rtc: Clock Enable Failed\n");
1798                 return -1;
1799         }
1800
1801         base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1802
1803         if (WARN_ON(!base))
1804                 return -ENOMEM;
1805
1806         /* Unlock the rtc's registers */
1807         __raw_writel(0x83e70b13, base + 0x6c);
1808         __raw_writel(0x95a4f1e0, base + 0x70);
1809
1810         /*
1811          * Enable the 32K OSc
1812          * TODO: Need a better way to handle this
1813          * Since we want the clock to be running before mmc init
1814          * we need to do it before the rtc probe happens
1815          */
1816         __raw_writel(0x48, base + 0x54);
1817
1818         iounmap(base);
1819
1820         return  platform_device_register(&am335x_rtc_device);
1821 }
1822
1823 /* Enable clkout2 */
1824 static struct pinmux_config clkout2_pin_mux[] = {
1825         {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1826         {NULL, 0},
1827 };
1828
1829 static void __init clkout2_enable(void)
1830 {
1831         struct clk *ck_32;
1832
1833         ck_32 = clk_get(NULL, "clkout2_ck");
1834         if (IS_ERR(ck_32)) {
1835                 pr_err("Cannot clk_get ck_32\n");
1836                 return;
1837         }
1838
1839         clk_enable(ck_32);
1840
1841         setup_pin_mux(clkout2_pin_mux);
1842 }
1843
1844 void __iomem * __init am33xx_get_mem_ctlr(void)
1845 {
1846         void __iomem *am33xx_emif_base;
1847
1848         am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1849
1850         if (!am33xx_emif_base)
1851                 pr_warning("%s: Unable to map DDR2 controller", __func__);
1852
1853         return am33xx_emif_base;
1854 }
1855
1856 static struct resource am33xx_cpuidle_resources[] = {
1857         {
1858                 .start          = AM33XX_EMIF0_BASE,
1859                 .end            = AM33XX_EMIF0_BASE + SZ_32K - 1,
1860                 .flags          = IORESOURCE_MEM,
1861         },
1862 };
1863
1864 /* AM33XX devices support DDR2 power down */
1865 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1866         .ddr2_pdown     = 1,
1867 };
1868
1869 static struct platform_device am33xx_cpuidle_device = {
1870         .name                   = "cpuidle-am33xx",
1871         .num_resources          = ARRAY_SIZE(am33xx_cpuidle_resources),
1872         .resource               = am33xx_cpuidle_resources,
1873         .dev = {
1874                 .platform_data  = &am33xx_cpuidle_pdata,
1875         },
1876 };
1877
1878 static void __init am33xx_cpuidle_init(void)
1879 {
1880         int ret;
1881
1882         am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1883
1884         ret = platform_device_register(&am33xx_cpuidle_device);
1885
1886         if (ret)
1887                 pr_warning("AM33XX cpuidle registration failed\n");
1888
1889 }
1890
1891 static void __init am335x_evm_init(void)
1892 {
1893         am33xx_cpuidle_init();
1894         am33xx_mux_init(board_mux);
1895         omap_serial_init();
1896         am335x_rtc_init();
1897         clkout2_enable();
1898         am335x_evm_i2c_init();
1899         omap_sdrc_init(NULL, NULL);
1900         usb_musb_init(&musb_board_data);
1901         omap_board_config = am335x_evm_config;
1902         omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1903         /* Create an alias for icss clock */
1904         if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1905                 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1906         /* Create an alias for gfx/sgx clock */
1907         if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1908                 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1909 }
1910
1911 static void __init am335x_evm_map_io(void)
1912 {
1913         omap2_set_globals_am33xx();
1914         omapam33xx_map_common_io();
1915 }
1916
1917 MACHINE_START(AM335XEVM, "am335xevm")
1918         /* Maintainer: Texas Instruments */
1919         .atag_offset    = 0x100,
1920         .map_io         = am335x_evm_map_io,
1921         .init_early     = am33xx_init_early,
1922         .init_irq       = ti81xx_init_irq,
1923         .handle_irq     = omap3_intc_handle_irq,
1924         .timer          = &omap3_am33xx_timer,
1925         .init_machine   = am335x_evm_init,
1926 MACHINE_END
1927
1928 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1929         /* Maintainer: Texas Instruments */
1930         .atag_offset    = 0x100,
1931         .map_io         = am335x_evm_map_io,
1932         .init_irq       = ti81xx_init_irq,
1933         .init_early     = am33xx_init_early,
1934         .timer          = &omap3_am33xx_timer,
1935         .init_machine   = am335x_evm_init,
1936 MACHINE_END