d2618b6dcb010417889f4d7e51227f0efc7bf68a
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / board-am335xevm.c
1 /*
2  * Code for AM335X EVM.
3  *
4  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/err.h>
30 #include <linux/wl12xx.h>
31 #include <linux/ethtool.h>
33 /* LCD controller is similar to DA850 */
34 #include <video/da8xx-fb.h>
36 #include <mach/hardware.h>
37 #include <mach/board-am335xevm.h>
39 #include <asm/mach-types.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/map.h>
42 #include <asm/hardware/asp.h>
44 #include <plat/irqs.h>
45 #include <plat/board.h>
46 #include <plat/common.h>
47 #include <plat/lcdc.h>
48 #include <plat/usb.h>
49 #include <plat/mmc.h>
51 #include "board-flash.h"
52 #include "mux.h"
53 #include "devices.h"
54 #include "hsmmc.h"
56 /* Convert GPIO signal to GPIO pin number */
57 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
59 /* TLK PHY IDs */
60 #define TLK110_PHY_ID           0x2000A201
61 #define TLK110_PHY_MASK         0xfffffff0
63 /* BBB PHY IDs */
64 #define BBB_PHY_ID              0x7c0f1
65 #define BBB_PHY_MASK            0xfffffffe
67 /* TLK110 PHY register offsets */
68 #define TLK110_COARSEGAIN_REG   0x00A3
69 #define TLK110_LPFHPF_REG       0x00AC
70 #define TLK110_SPAREANALOG_REG  0x00B9
71 #define TLK110_VRCR_REG         0x00D0
72 #define TLK110_SETFFE_REG       0x0107
73 #define TLK110_FTSP_REG         0x0154
74 #define TLK110_ALFATPIDL_REG    0x002A
75 #define TLK110_PSCOEF21_REG     0x0096
76 #define TLK110_PSCOEF3_REG      0x0097
77 #define TLK110_ALFAFACTOR1_REG  0x002C
78 #define TLK110_ALFAFACTOR2_REG  0x0023
79 #define TLK110_CFGPS_REG        0x0095
80 #define TLK110_FTSPTXGAIN_REG   0x0150
81 #define TLK110_SWSCR3_REG       0x000B
82 #define TLK110_SCFALLBACK_REG   0x0040
83 #define TLK110_PHYRCR_REG       0x001F
85 /* TLK110 register writes values */
86 #define TLK110_COARSEGAIN_VAL   0x0000
87 #define TLK110_LPFHPF_VAL       0x8000
88 #define TLK110_SPANALOG_VAL     0x0000
89 #define TLK110_VRCR_VAL         0x0008
90 #define TLK110_SETFFE_VAL       0x0605
91 #define TLK110_FTSP_VAL         0x0255
92 #define TLK110_ALFATPIDL_VAL    0x7998
93 #define TLK110_PSCOEF21_VAL     0x3A20
94 #define TLK110_PSCOEF3_VAL      0x003F
95 #define TLK110_ALFACTOR1_VAL    0xFF80
96 #define TLK110_ALFACTOR2_VAL    0x021C
97 #define TLK110_CFGPS_VAL        0x0000
98 #define TLK110_FTSPTXGAIN_VAL   0x6A88
99 #define TLK110_SWSCR3_VAL       0x0000
100 #define TLK110_SCFALLBACK_VAL   0xC11D
101 #define TLK110_PHYRCR_VAL       0x4000
103 #ifdef CONFIG_TLK110_WORKAROUND
104 #define am335x_tlk110_phy_init()\
105         do {    \
106                 phy_register_fixup_for_uid(TLK110_PHY_ID,\
107                                         TLK110_PHY_MASK,\
108                                         am335x_tlk110_phy_fixup);\
109         } while (0);
110 #else
111 #define am335x_tlk110_phy_init() do { } while (0);
112 #endif
114 static const struct display_panel disp_panel = {
115         WVGA,
116         32,
117         32,
118         COLOR_ACTIVE,
119 };
121 static struct lcd_ctrl_config lcd_cfg = {
122         &disp_panel,
123         .ac_bias                = 255,
124         .ac_bias_intrpt         = 0,
125         .dma_burst_sz           = 16,
126         .bpp                    = 32,
127         .fdd                    = 0x80,
128         .tft_alt_mode           = 0,
129         .stn_565_mode           = 0,
130         .mono_8bit_mode         = 0,
131         .invert_line_clock      = 1,
132         .invert_frm_clock       = 1,
133         .sync_edge              = 0,
134         .sync_ctrl              = 1,
135         .raster_order           = 0,
136 };
138 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
139         .manu_name              = "ThreeFive",
140         .controller_data        = &lcd_cfg,
141         .type                   = "TFC_S9700RTWV35TR_01B",
142 };
144 #include "common.h"
146 /* TSc controller */
147 #include <linux/input/ti_tscadc.h>
149 static struct resource tsc_resources[]  = {
150         [0] = {
151                 .start  = AM33XX_TSC_BASE,
152                 .end    = AM33XX_TSC_BASE + SZ_8K - 1,
153                 .flags  = IORESOURCE_MEM,
154         },
155         [1] = {
156                 .start  = AM33XX_IRQ_ADC_GEN,
157                 .end    = AM33XX_IRQ_ADC_GEN,
158                 .flags  = IORESOURCE_IRQ,
159         },
160 };
162 static struct tsc_data am335x_touchscreen_data  = {
163         .wires  = 4,
164         .x_plate_resistance = 200,
165 };
167 static struct platform_device tsc_device = {
168         .name   = "tsc",
169         .id     = -1,
170         .dev    = {
171                         .platform_data  = &am335x_touchscreen_data,
172         },
173         .num_resources  = ARRAY_SIZE(tsc_resources),
174         .resource       = tsc_resources,
175 };
177 static u8 am335x_iis_serializer_direction1[] = {
178         INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,        RX_MODE,
179         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
180         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
181         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
182 };
184 static struct snd_platform_data am335x_evm_snd_data1 = {
185         .tx_dma_offset  = 0x46400000,   /* McASP1 */
186         .rx_dma_offset  = 0x46400000,
187         .op_mode        = DAVINCI_MCASP_IIS_MODE,
188         .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
189         .tdm_slots      = 2,
190         .serial_dir     = am335x_iis_serializer_direction1,
191         .asp_chan_q     = EVENTQ_2,
192         .version        = MCASP_VERSION_3,
193         .txnumevt       = 1,
194         .rxnumevt       = 1,
195 };
197 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
198         {
199                 .mmc            = 1,
200                 .caps           = MMC_CAP_4_BIT_DATA,
201                 .gpio_cd        = GPIO_TO_PIN(0, 6),
202                 .gpio_wp        = GPIO_TO_PIN(3, 18),
203                 .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
204         },
205         {
206                 .mmc            = 0,    /* will be set at runtime */
207         },
208         {
209                 .mmc            = 0,    /* will be set at runtime */
210         },
211         {}      /* Terminator */
212 };
215 #ifdef CONFIG_OMAP_MUX
216 static struct omap_board_mux board_mux[] __initdata = {
217         AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
218                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
219         AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
220                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
221         { .reg_offset = OMAP_MUX_TERMINATOR },
222 };
223 #else
224 #define board_mux       NULL
225 #endif
227 /* module pin mux structure */
228 struct pinmux_config {
229         const char *string_name; /* signal name format */
230         int val; /* Options for the mux register value */
231 };
233 struct evm_dev_cfg {
234         void (*device_init)(int evm_id, int profile);
236 /*
237 * If the device is required on both baseboard & daughter board (ex i2c),
238 * specify DEV_ON_BASEBOARD
239 */
240 #define DEV_ON_BASEBOARD        0
241 #define DEV_ON_DGHTR_BRD        1
242         u32 device_on;
244         u32 profile;    /* Profiles (0-7) in which the module is present */
245 };
247 /* AM335X - CPLD Register Offsets */
248 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
249 #define CPLD_DEVICE_ID  0x04 /* CPLD identification */
250 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
251 #define CPLD_CFG_REG    0x10 /* Configuration Register */
253 static struct i2c_client *cpld_client;
254 static u32 am335x_evm_id;
255 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
256 };
258 /*
259 * EVM Config held in On-Board eeprom device.
261 * Header Format
263 *  Name                 Size    Contents
264 *                       (Bytes)
265 *-------------------------------------------------------------
266 *  Header               4       0xAA, 0x55, 0x33, 0xEE
268 *  Board Name           8       Name for board in ASCII.
269 *                               example "A33515BB" = "AM335X
270                                 Low Cost EVM board"
272 *  Version              4       Hardware version code for board in
273 *                               in ASCII. "1.0A" = rev.01.0A
275 *  Serial Number        12      Serial number of the board. This is a 12
276 *                               character string which is WWYY4P16nnnn, where
277 *                               WW = 2 digit week of the year of production
278 *                               YY = 2 digit year of production
279 *                               nnnn = incrementing board number
281 *  Configuration option 32      Codes(TBD) to show the configuration
282 *                               setup on this board.
284 *  Available            32720   Available space for other non-volatile
285 *                               data.
286 */
287 struct am335x_evm_eeprom_config {
288         u32     header;
289         u8      name[8];
290         char    version[4];
291         u8      serial[12];
292         u8      opt[32];
293 };
295 static struct am335x_evm_eeprom_config config;
296 static bool daughter_brd_detected;
298 #define GP_EVM_REV_IS_1_0               0x1
299 #define GP_EVM_REV_IS_1_1A              0x2
300 #define GP_EVM_REV_IS_UNKNOWN           0xFF
301 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
303 #define EEPROM_MAC_ADDRESS_OFFSET       60 /* 4+8+4+12+32 */
304 #define EEPROM_NO_OF_MAC_ADDR           3
305 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
307 #define AM335X_EEPROM_HEADER            0xEE3355AA
309 /* current profile if exists else PROFILE_0 on error */
310 static u32 am335x_get_profile_selection(void)
312         int val = 0;
314         if (!cpld_client)
315                 /* error checking is not done in func's calling this routine.
316                 so return profile 0 on error */
317                 return 0;
319         val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
320         if (val < 0)
321                 return 0;       /* default to Profile 0 on Error */
322         else
323                 return val & 0x7;
326 /* Module pin mux for LCDC */
327 static struct pinmux_config lcdc_pin_mux[] = {
328         {"lcd_data0.lcd_data0",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
329                                                        | AM33XX_PULL_DISA},
330         {"lcd_data1.lcd_data1",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
331                                                        | AM33XX_PULL_DISA},
332         {"lcd_data2.lcd_data2",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
333                                                        | AM33XX_PULL_DISA},
334         {"lcd_data3.lcd_data3",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
335                                                        | AM33XX_PULL_DISA},
336         {"lcd_data4.lcd_data4",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
337                                                        | AM33XX_PULL_DISA},
338         {"lcd_data5.lcd_data5",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
339                                                        | AM33XX_PULL_DISA},
340         {"lcd_data6.lcd_data6",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
341                                                        | AM33XX_PULL_DISA},
342         {"lcd_data7.lcd_data7",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
343                                                        | AM33XX_PULL_DISA},
344         {"lcd_data8.lcd_data8",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
345                                                        | AM33XX_PULL_DISA},
346         {"lcd_data9.lcd_data9",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
347                                                        | AM33XX_PULL_DISA},
348         {"lcd_data10.lcd_data10",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
349                                                        | AM33XX_PULL_DISA},
350         {"lcd_data11.lcd_data11",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
351                                                        | AM33XX_PULL_DISA},
352         {"lcd_data12.lcd_data12",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
353                                                        | AM33XX_PULL_DISA},
354         {"lcd_data13.lcd_data13",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
355                                                        | AM33XX_PULL_DISA},
356         {"lcd_data14.lcd_data14",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
357                                                        | AM33XX_PULL_DISA},
358         {"lcd_data15.lcd_data15",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
359                                                        | AM33XX_PULL_DISA},
360         {"gpmc_ad8.lcd_data16",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
361         {"gpmc_ad9.lcd_data17",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
362         {"gpmc_ad10.lcd_data18",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
363         {"gpmc_ad11.lcd_data19",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
364         {"gpmc_ad12.lcd_data20",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
365         {"gpmc_ad13.lcd_data21",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
366         {"gpmc_ad14.lcd_data22",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
367         {"gpmc_ad15.lcd_data23",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
368         {"lcd_vsync.lcd_vsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
369         {"lcd_hsync.lcd_hsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
370         {"lcd_pclk.lcd_pclk",           OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
371         {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
372         {NULL, 0},
373 };
375 static struct pinmux_config tsc_pin_mux[] = {
376         {"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
377         {"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
378         {"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
379         {"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
380         {"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
381         {"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
382         {NULL, 0},
383 };
385 /* Pin mux for nand flash module */
386 static struct pinmux_config nand_pin_mux[] = {
387         {"gpmc_ad0.gpmc_ad0",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
388         {"gpmc_ad1.gpmc_ad1",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
389         {"gpmc_ad2.gpmc_ad2",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
390         {"gpmc_ad3.gpmc_ad3",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
391         {"gpmc_ad4.gpmc_ad4",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
392         {"gpmc_ad5.gpmc_ad5",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
393         {"gpmc_ad6.gpmc_ad6",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
394         {"gpmc_ad7.gpmc_ad7",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
395         {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
396         {"gpmc_wpn.gpmc_wpn",     OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
397         {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
398         {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
399         {"gpmc_oen_ren.gpmc_oen_ren",    OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
400         {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
401         {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
402         {NULL, 0},
403 };
405 /* Module pin mux for SPI fash */
406 static struct pinmux_config spi0_pin_mux[] = {
407         {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
408                                                         | AM33XX_INPUT_EN},
409         {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
410                                                         | AM33XX_INPUT_EN},
411         {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
412                                                         | AM33XX_INPUT_EN},
413         {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
414                                                         | AM33XX_INPUT_EN},
415         {NULL, 0},
416 };
418 /* Module pin mux for SPI flash */
419 static struct pinmux_config spi1_pin_mux[] = {
420         {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
421                 | AM33XX_INPUT_EN},
422         {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
423                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
424         {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
425                 | AM33XX_INPUT_EN},
426         {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
427                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
428         {NULL, 0},
429 };
431 /* Module pin mux for rgmii1 */
432 static struct pinmux_config rgmii1_pin_mux[] = {
433         {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
434         {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
435         {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
436         {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
437         {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
438         {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
439         {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
440         {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
441         {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
442         {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
443         {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
444         {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
445         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
446         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
447         {NULL, 0},
448 };
450 /* Module pin mux for rgmii2 */
451 static struct pinmux_config rgmii2_pin_mux[] = {
452         {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
453         {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
454         {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
455         {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
456         {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
457         {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
458         {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
459         {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
460         {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
461         {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
462         {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
463         {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
464         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
465         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
466         {NULL, 0},
467 };
469 /* Module pin mux for mii1 */
470 static struct pinmux_config mii1_pin_mux[] = {
471         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
472         {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
473         {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
474         {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
475         {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
476         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
477         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
478         {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
479         {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
480         {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
481         {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
482         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
483         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
484         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
485         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
486         {NULL, 0},
487 };
489 /* Module pin mux for rmii1 */
490 static struct pinmux_config rmii1_pin_mux[] = {
491         {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
492         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
493         {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
494         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
495         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
496         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
497         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
498         {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
499         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
500         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
501         {NULL, 0},
502 };
504 static struct pinmux_config i2c1_pin_mux[] = {
505         {"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
506                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
507         {"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
508                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
509         {NULL, 0},
510 };
512 /* Module pin mux for mcasp1 */
513 static struct pinmux_config mcasp1_pin_mux[] = {
514         {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
515         {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
516         {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
517         {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
518                                                 AM33XX_PIN_INPUT_PULLDOWN},
519         {NULL, 0},
520 };
523 /* Module pin mux for mmc0 */
524 static struct pinmux_config mmc0_pin_mux[] = {
525         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
526         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
527         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
528         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
529         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
530         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
531         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
532         {"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
533         {NULL, 0},
534 };
536 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
537         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
538         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
539         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
540         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
541         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
542         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
543         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
544         {NULL, 0},
545 };
547 /* Module pin mux for mmc1 */
548 static struct pinmux_config mmc1_pin_mux[] = {
549         {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
550         {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
551         {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
552         {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
553         {"gpmc_ad3.mmc1_dat3",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
554         {"gpmc_ad2.mmc1_dat2",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
555         {"gpmc_ad1.mmc1_dat1",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
556         {"gpmc_ad0.mmc1_dat0",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
557         {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
558         {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
559         {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
560         {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
561         {NULL, 0},
562 };
564 /* Module pin mux for uart3 */
565 static struct pinmux_config uart3_pin_mux[] = {
566         {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
567         {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
568         {NULL, 0},
569 };
571 /*
572 * @pin_mux - single module pin-mux structure which defines pin-mux
573 *                       details for all its pins.
574 */
575 static void setup_pin_mux(struct pinmux_config *pin_mux)
577         int i;
579         for (i = 0; pin_mux->string_name != NULL; pin_mux++)
580                 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
584 /*
585 * @evm_id - evm id which needs to be configured
586 * @dev_cfg - single evm structure which includes
587 *                               all module inits, pin-mux defines
588 * @profile - if present, else PROFILE_NONE
589 * @dghtr_brd_flg - Whether Daughter board is present or not
590 */
591 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
592         int profile)
594         int i;
596         /*
597         * Only General Purpose & Industrial Auto Motro Control
598         * EVM has profiles. So check if this evm has profile.
599         * If not, ignore the profile comparison
600         */
602         /*
603         * If the device is on baseboard, directly configure it. Else (device on
604         * Daughter board), check if the daughter card is detected.
605         */
606         if (profile == PROFILE_NONE) {
607                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
608                         if (dev_cfg->device_on == DEV_ON_BASEBOARD)
609                                 dev_cfg->device_init(evm_id, profile);
610                         else if (daughter_brd_detected == true)
611                                 dev_cfg->device_init(evm_id, profile);
612                 }
613         } else {
614                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
615                         if (dev_cfg->profile & profile) {
616                                 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
617                                         dev_cfg->device_init(evm_id, profile);
618                                 else if (daughter_brd_detected == true)
619                                         dev_cfg->device_init(evm_id, profile);
620                         }
621                 }
622         }
625 #define AM335X_LCD_BL_PIN       GPIO_TO_PIN(0, 7)
627 /* pinmux for usb0 drvvbus */
628 static struct pinmux_config usb0_pin_mux[] = {
629         {"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
630         {NULL, 0},
631 };
633 /* pinmux for usb1 drvvbus */
634 static struct pinmux_config usb1_pin_mux[] = {
635         {"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
636         {NULL, 0},
637 };
639 /* Module pin mux for eCAP0 */
640 static struct pinmux_config ecap0_pin_mux[] = {
641         {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
642         {NULL, 0},
643 };
645 static int backlight_enable;
647 #define AM335XEVM_WLAN_PMENA_GPIO       GPIO_TO_PIN(1, 30)
648 #define AM335XEVM_WLAN_IRQ_GPIO         GPIO_TO_PIN(3, 17)
649 #define AM335XEVM_BT_ENABLE_GPIO        GPIO_TO_PIN(1, 31)
651 struct wl12xx_platform_data am335xevm_wlan_data = {
652         .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
653         .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
654         .board_tcxo_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
655 };
657 /* Module pin mux for wlan and bluetooth */
658 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
659         {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
660         {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
661         {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
662         {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
663         {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
664         {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
665         {NULL, 0},
666 };
668 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
669         {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
670         {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
671         {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
672         {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
673         {NULL, 0},
674 };
676 static struct pinmux_config wl12xx_pin_mux[] = {
677         {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
678         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
679         {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
680         {NULL, 0},
681  };
683 static void enable_ecap0(int evm_id, int profile)
685         backlight_enable = true;
688 static int __init ecap0_init(void)
690         int status = 0;
692         if (backlight_enable) {
693                 setup_pin_mux(ecap0_pin_mux);
695                 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
696                 if (status < 0)
697                         pr_warn("Failed to request gpio for LCD backlight\n");
699                 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
700         }
701         return status;
703 late_initcall(ecap0_init);
705 static int __init conf_disp_pll(int rate)
707         struct clk *disp_pll;
708         int ret = -EINVAL;
710         disp_pll = clk_get(NULL, "dpll_disp_ck");
711         if (IS_ERR(disp_pll)) {
712                 pr_err("Cannot clk_get disp_pll\n");
713                 goto out;
714         }
716         ret = clk_set_rate(disp_pll, rate);
717         clk_put(disp_pll);
718 out:
719         return ret;
722 static void lcdc_init(int evm_id, int profile)
725         setup_pin_mux(lcdc_pin_mux);
727         if (conf_disp_pll(300000000)) {
728                 pr_info("Failed configure display PLL, not attempting to"
729                                 "register LCDC\n");
730                 return;
731         }
733         if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
734                 pr_info("Failed to register LCDC device\n");
735         return;
738 static void tsc_init(int evm_id, int profile)
740         int err;
742         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
743                 am335x_touchscreen_data.analog_input = 1;
744                 pr_info("TSC connected to beta GP EVM\n");
745         } else {
746                 am335x_touchscreen_data.analog_input = 0;
747                 pr_info("TSC connected to alpha GP EVM\n");
748         }
749         setup_pin_mux(tsc_pin_mux);
750         err = platform_device_register(&tsc_device);
751         if (err)
752                 pr_err("failed to register touchscreen device\n");
755 static void rgmii1_init(int evm_id, int profile)
757         setup_pin_mux(rgmii1_pin_mux);
758         return;
761 static void rgmii2_init(int evm_id, int profile)
763         setup_pin_mux(rgmii2_pin_mux);
764         return;
767 static void mii1_init(int evm_id, int profile)
769         setup_pin_mux(mii1_pin_mux);
770         return;
773 static void rmii1_init(int evm_id, int profile)
775         setup_pin_mux(rmii1_pin_mux);
776         return;
779 static void usb0_init(int evm_id, int profile)
781         setup_pin_mux(usb0_pin_mux);
782         return;
785 static void usb1_init(int evm_id, int profile)
787         setup_pin_mux(usb1_pin_mux);
788         return;
791 /* setup uart3 */
792 static void uart3_init(int evm_id, int profile)
794         setup_pin_mux(uart3_pin_mux);
795         return;
798 /* NAND partition information */
799 static struct mtd_partition am335x_nand_partitions[] = {
800 /* All the partition sizes are listed in terms of NAND block size */
801         {
802                 .name           = "SPL",
803                 .offset         = 0,                    /* Offset = 0x0 */
804                 .size           = SZ_128K,
805         },
806         {
807                 .name           = "SPL.backup1",
808                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x20000 */
809                 .size           = SZ_128K,
810         },
811         {
812                 .name           = "SPL.backup2",
813                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x40000 */
814                 .size           = SZ_128K,
815         },
816         {
817                 .name           = "SPL.backup3",
818                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x60000 */
819                 .size           = SZ_128K,
820         },
821         {
822                 .name           = "U-Boot",
823                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
824                 .size           = 15 * SZ_128K,
825         },
826         {
827                 .name           = "U-Boot Env",
828                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
829                 .size           = 1 * SZ_128K,
830         },
831         {
832                 .name           = "Kernel",
833                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
834                 .size           = 40 * SZ_128K,
835         },
836         {
837                 .name           = "File System",
838                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
839                 .size           = MTDPART_SIZ_FULL,
840         },
841 };
843 /* SPI 0/1 Platform Data */
844 /* SPI flash information */
845 static struct mtd_partition am335x_spi_partitions[] = {
846         /* All the partition sizes are listed in terms of erase size */
847         {
848                 .name       = "SPL",
849                 .offset     = 0,                        /* Offset = 0x0 */
850                 .size       = SZ_128K,
851         },
852         {
853                 .name       = "U-Boot",
854                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x20000 */
855                 .size       = 2 * SZ_128K,
856         },
857         {
858                 .name       = "U-Boot Env",
859                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x60000 */
860                 .size       = 2 * SZ_4K,
861         },
862         {
863                 .name       = "Kernel",
864                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x62000 */
865                 .size       = 28 * SZ_128K,
866         },
867         {
868                 .name       = "File System",
869                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x3E2000 */
870                 .size       = MTDPART_SIZ_FULL,         /* size ~= 4.1 MiB */
871         }
872 };
874 static const struct flash_platform_data am335x_spi_flash = {
875         .type      = "w25q64",
876         .name      = "spi_flash",
877         .parts     = am335x_spi_partitions,
878         .nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
879 };
881 /*
882  * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
883  * So setup Max speed to be less than that of Controller speed
884  */
885 static struct spi_board_info am335x_spi0_slave_info[] = {
886         {
887                 .modalias      = "m25p80",
888                 .platform_data = &am335x_spi_flash,
889                 .irq           = -1,
890                 .max_speed_hz  = 24000000,
891                 .bus_num       = 1,
892                 .chip_select   = 0,
893         },
894 };
896 static struct spi_board_info am335x_spi1_slave_info[] = {
897         {
898                 .modalias      = "m25p80",
899                 .platform_data = &am335x_spi_flash,
900                 .irq           = -1,
901                 .max_speed_hz  = 12000000,
902                 .bus_num       = 2,
903                 .chip_select   = 0,
904         },
905 };
907 static void evm_nand_init(int evm_id, int profile)
909         setup_pin_mux(nand_pin_mux);
910         board_nand_init(am335x_nand_partitions,
911                 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
914 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
915         {
916                 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
917         },
918 };
920 static void i2c1_init(int evm_id, int profile)
922         setup_pin_mux(i2c1_pin_mux);
923         omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
924                         ARRAY_SIZE(am335x_i2c_boardinfo1));
925         return;
928 /* Setup McASP 1 */
929 static void mcasp1_init(int evm_id, int profile)
931         /* Configure McASP */
932         setup_pin_mux(mcasp1_pin_mux);
933         am335x_register_mcasp1(&am335x_evm_snd_data1);
934         return;
937 static void mmc1_init(int evm_id, int profile)
939         setup_pin_mux(mmc1_pin_mux);
941         am335x_mmc[1].mmc = 2;
942         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
943         am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
944         am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
945         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
947         /* mmc will be initialized when mmc0_init is called */
948         return;
951 static void mmc2_wl12xx_init(int evm_id, int profile)
953         setup_pin_mux(mmc2_wl12xx_pin_mux);
955         am335x_mmc[1].mmc = 3;
956         am335x_mmc[1].name = "wl1271";
957         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
958                                 | MMC_PM_KEEP_POWER;
959         am335x_mmc[1].nonremovable = true;
960         am335x_mmc[1].gpio_cd = -EINVAL;
961         am335x_mmc[1].gpio_wp = -EINVAL;
962         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
964         /* mmc will be initialized when mmc0_init is called */
965         return;
968 static void uart1_wl12xx_init(int evm_id, int profile)
970         setup_pin_mux(uart1_wl12xx_pin_mux);
973 static void wl12xx_bluetooth_enable(void)
975         int status = gpio_request(AM335XEVM_BT_ENABLE_GPIO, "bt_en\n");
976         if (status < 0)
977                 pr_err("Failed to request gpio for bt_enable");
979         pr_info("Enable bluetooth...\n");
980         gpio_direction_output(AM335XEVM_BT_ENABLE_GPIO, 0);
981         msleep(1);
982         gpio_set_value(AM335XEVM_BT_ENABLE_GPIO, 1);
985 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
987         if (on)
988                 gpio_set_value(AM335XEVM_WLAN_PMENA_GPIO, 1);
989         else
990                 gpio_set_value(AM335XEVM_WLAN_PMENA_GPIO, 0);
992         return 0;
995 static void wl12xx_init(int evm_id, int profile)
997         struct device *dev;
998         struct omap_mmc_platform_data *pdata;
999         int ret;
1001         wl12xx_bluetooth_enable();
1003         if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1004                 pr_err("error setting wl12xx data\n");
1006         dev = am335x_mmc[1].dev;
1007         if (!dev) {
1008                 pr_err("wl12xx mmc device initialization failed\n");
1009                 goto out;
1010         }
1012         pdata = dev->platform_data;
1013         if (!pdata) {
1014                 pr_err("Platfrom data of wl12xx device not set\n");
1015                 goto out;
1016         }
1018         ret = gpio_request_one(AM335XEVM_WLAN_PMENA_GPIO, GPIOF_OUT_INIT_LOW,
1019                                "wlan_en");
1020         if (ret) {
1021                 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1022                 goto out;
1023         }
1025         setup_pin_mux(wl12xx_pin_mux);
1027         pdata->slots[0].set_power = wl12xx_set_power;
1028 out:
1029         return;
1032 static void mmc0_init(int evm_id, int profile)
1034         setup_pin_mux(mmc0_pin_mux);
1036         omap2_hsmmc_init(am335x_mmc);
1037         return;
1040 static void mmc0_no_cd_init(int evm_id, int profile)
1042         setup_pin_mux(mmc0_no_cd_pin_mux);
1044         omap2_hsmmc_init(am335x_mmc);
1045         return;
1049 /* setup spi0 */
1050 static void spi0_init(int evm_id, int profile)
1052         setup_pin_mux(spi0_pin_mux);
1053         spi_register_board_info(am335x_spi0_slave_info,
1054                         ARRAY_SIZE(am335x_spi0_slave_info));
1055         return;
1058 /* setup spi1 */
1059 static void spi1_init(int evm_id, int profile)
1061         setup_pin_mux(spi1_pin_mux);
1062         spi_register_board_info(am335x_spi1_slave_info,
1063                         ARRAY_SIZE(am335x_spi1_slave_info));
1064         return;
1068 static int beaglebone_phy_fixup(struct phy_device *phydev)
1070         phydev->supported &= ~(SUPPORTED_100baseT_Half |
1071                                 SUPPORTED_100baseT_Full);
1073         return 0;
1076 #ifdef CONFIG_TLK110_WORKAROUND
1077 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1079         unsigned int val;
1081         /* This is done as a workaround to support TLK110 rev1.0 phy */
1082         val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1083         phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1085         val = phy_read(phydev, TLK110_LPFHPF_REG);
1086         phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1088         val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1089         phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1091         val = phy_read(phydev, TLK110_VRCR_REG);
1092         phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1094         val = phy_read(phydev, TLK110_SETFFE_REG);
1095         phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1097         val = phy_read(phydev, TLK110_FTSP_REG);
1098         phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1100         val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1101         phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1103         val = phy_read(phydev, TLK110_PSCOEF21_REG);
1104         phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1106         val = phy_read(phydev, TLK110_PSCOEF3_REG);
1107         phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1109         val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1110         phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1112         val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1113         phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1115         val = phy_read(phydev, TLK110_CFGPS_REG);
1116         phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1118         val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1119         phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1121         val = phy_read(phydev, TLK110_SWSCR3_REG);
1122         phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1124         val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1125         phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1127         val = phy_read(phydev, TLK110_PHYRCR_REG);
1128         phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1130         return 0;
1132 #endif
1135 /* Low-Cost EVM */
1136 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1137         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1138         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1139         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1140         {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1141         {NULL, 0, 0},
1142 };
1144 /* General Purpose EVM */
1145 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1146         {enable_ecap0,  DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1147                                                 PROFILE_2 | PROFILE_7) },
1148         {lcdc_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1149                                                 PROFILE_2 | PROFILE_7) },
1150         {tsc_init,      DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1151                                                 PROFILE_2 | PROFILE_7) },
1152         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
1153         {rgmii2_init,   DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1154                                                 PROFILE_4 | PROFILE_6) },
1155         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1156         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1157         {evm_nand_init, DEV_ON_DGHTR_BRD,
1158                 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1159         {i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1160         {mcasp1_init,   DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1161         {mmc1_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1162         {mmc2_wl12xx_init,      DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1163                                                                 PROFILE_5)},
1164         {mmc0_init,     DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1165         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_5},
1166         {spi0_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1167         {uart1_wl12xx_init,     DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1168                                                                 PROFILE_5)},
1169         {wl12xx_init,   DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1170         {NULL, 0, 0},
1171 };
1173 /* Industrial Auto Motor Control EVM */
1174 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1175         {mii1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1176         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1177         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1178         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1179         {spi1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1180         {uart3_init,    DEV_ON_DGHTR_BRD, PROFILE_ALL},
1181         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1182         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_ALL},
1183         {NULL, 0, 0},
1184 };
1186 /* IP-Phone EVM */
1187 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1188         {enable_ecap0,  DEV_ON_DGHTR_BRD, PROFILE_NONE},
1189         {lcdc_init,     DEV_ON_DGHTR_BRD, PROFILE_NONE},
1190         {tsc_init,      DEV_ON_DGHTR_BRD, PROFILE_NONE},
1191         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1192         {rgmii2_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1193         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1194         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1195         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1196         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1197         {mcasp1_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1198         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1199         {NULL, 0, 0},
1200 };
1202 /* Beaglebone < Rev A3 */
1203 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1204         {rmii1_init,    DEV_ON_BASEBOARD, PROFILE_NONE},
1205         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1206         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1207         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1208         {NULL, 0, 0},
1209 };
1211 /* Beaglebone Rev A3 and after */
1212 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1213         {mii1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1214         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1215         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1216         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1217         {NULL, 0, 0},
1218 };
1220 static void setup_low_cost_evm(void)
1222         pr_info("The board is a AM335x Low Cost EVM.\n");
1224         _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1227 static void setup_general_purpose_evm(void)
1229         u32 prof_sel = am335x_get_profile_selection();
1230         pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1232         if (!strncmp("1.1A", config.version, 4)) {
1233                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1234         } else if (!strncmp("1.0", config.version, 3)) {
1235                 gp_evm_revision = GP_EVM_REV_IS_1_0;
1236         } else {
1237                 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1238                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1239         }
1241         if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1242                 gigabit_enable = 0;
1243         else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1244                 gigabit_enable = 1;
1246         _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1249 static void setup_ind_auto_motor_ctrl_evm(void)
1251         u32 prof_sel = am335x_get_profile_selection();
1253         pr_info("The board is an industrial automation EVM in profile %d\n",
1254                 prof_sel);
1256         /* Only Profile 0 is supported */
1257         if ((1L << prof_sel) != PROFILE_0) {
1258                 pr_err("AM335X: Only Profile 0 is supported\n");
1259                 pr_err("Assuming profile 0 & continuing\n");
1260                 prof_sel = PROFILE_0;
1261         }
1263         _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1264                 PROFILE_0);
1266         /* Fillup global evmid */
1267         am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1269         /* Initialize TLK110 PHY registers for phy version 1.0 */
1270         am335x_tlk110_phy_init();
1275 static void setup_ip_phone_evm(void)
1277         pr_info("The board is an IP phone EVM\n");
1279         _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1282 /* BeagleBone < Rev A3 */
1283 static void setup_beaglebone_old(void)
1285         pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1287         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1288         am335x_mmc[0].gpio_wp = -EINVAL;
1290         _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1292         phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1293                                         beaglebone_phy_fixup);
1296 /* BeagleBone after Rev A3 */
1297 static void setup_beaglebone(void)
1299         pr_info("The board is a AM335x Beaglebone.\n");
1301         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1302         am335x_mmc[0].gpio_wp = -EINVAL;
1304         _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1308 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1310         u8 tmp;
1311         int ret;
1313         /*
1314          * try reading a byte from the EEPROM to see if it is
1315          * present. We could read a lot more, but that would
1316          * just slow the boot process and we have all the information
1317          * we need from the EEPROM on the base board anyway.
1318          */
1319         ret = m->read(m, &tmp, 0, sizeof(u8));
1320         if (ret == sizeof(u8)) {
1321                 pr_info("Detected a daughter card on AM335x EVM..");
1322                 daughter_brd_detected = true;
1323         } else {
1324                 pr_info("No daughter card found\n");
1325                 daughter_brd_detected = false;
1326         }
1329 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1331         int ret;
1332         char tmp[10];
1334         /* 1st get the MAC address from EEPROM */
1335         ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1336                 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1338         if (ret != sizeof(am335x_mac_addr)) {
1339                 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1340                 return;
1341         }
1343         /* Fillup global mac id */
1344         am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1345                                 &am335x_mac_addr[1][0]);
1347         /* get board specific data */
1348         ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1349         if (ret != sizeof(config)) {
1350                 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1351                 return;
1352         }
1354         if (config.header != AM335X_EEPROM_HEADER) {
1355                 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1356                         config.header, AM335X_EEPROM_HEADER);
1357                 goto out;
1358         }
1360         if (strncmp("A335", config.name, 4)) {
1361                 pr_err("Board %s doesn't look like an AM335x board\n",
1362                         config.name);
1363                 goto out;
1364         }
1366         snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1367         pr_info("Board name: %s\n", tmp);
1368         snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1369         pr_info("Board version: %s\n", tmp);
1371         if (!strncmp("A335BONE", config.name, 8)) {
1372                 daughter_brd_detected = false;
1373                 if(!strncmp("00A1", config.version, 4) ||
1374                    !strncmp("00A2", config.version, 4))
1375                         setup_beaglebone_old();
1376                 else
1377                         setup_beaglebone();
1378         } else {
1379                 /* only 6 characters of options string used for now */
1380                 snprintf(tmp, 7, "%s", config.opt);
1381                 pr_info("SKU: %s\n", tmp);
1383                 if (!strncmp("SKU#00", config.opt, 6))
1384                         setup_low_cost_evm();
1385                 else if (!strncmp("SKU#01", config.opt, 6))
1386                         setup_general_purpose_evm();
1387                 else if (!strncmp("SKU#02", config.opt, 6))
1388                         setup_ind_auto_motor_ctrl_evm();
1389                 else if (!strncmp("SKU#03", config.opt, 6))
1390                         setup_ip_phone_evm();
1391                 else
1392                         goto out;
1393         }
1394         /* Initialize cpsw after board detection is completed as board
1395          * information is required for configuring phy address and hence
1396          * should be call only after board detection
1397          */
1398         am33xx_cpsw_init();
1400         return;
1401 out:
1402         /*
1403          * If the EEPROM hasn't been programed or an incorrect header
1404          * or board name are read, assume this is an old beaglebone board
1405          * (< Rev A3)
1406          */
1407         pr_err("Could not detect any board, falling back to: "
1408                 "Beaglebone (< Rev A3) with no daughter card connected\n");
1409         daughter_brd_detected = false;
1410         setup_beaglebone_old();
1412         /* Initialize cpsw after board detection is completed as board
1413          * information is required for configuring phy address and hence
1414          * should be call only after board detection
1415          */
1416         am33xx_cpsw_init();
1419 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1420         .byte_len       = (256*1024) / 8,
1421         .page_size      = 64,
1422         .flags          = AT24_FLAG_ADDR16,
1423         .setup          = am335x_setup_daughter_board,
1424         .context        = (void *)NULL,
1425 };
1427 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1428         .byte_len       = (256*1024) / 8,
1429         .page_size      = 64,
1430         .flags          = AT24_FLAG_ADDR16,
1431         .setup          = am335x_evm_setup,
1432         .context        = (void *)NULL,
1433 };
1435 /*
1436 * Daughter board Detection.
1437 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1438 * machine init, starting from daughter board and ending with baseboard.
1439 * Assumptions :
1440 *       1. probe for i2c devices are called in the order they are included in
1441 *          the below struct. Daughter boards eeprom are probed 1st. Baseboard
1442 *          eeprom probe is called last.
1443 */
1444 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1445         {
1446                 /* Daughter Board EEPROM */
1447                 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1448                 .platform_data  = &am335x_daughter_board_eeprom_info,
1449         },
1450         {
1451                 /* Baseboard board EEPROM */
1452                 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1453                 .platform_data  = &am335x_baseboard_eeprom_info,
1454         },
1455         {
1456                 I2C_BOARD_INFO("cpld_reg", 0x35),
1457         },
1458         {
1459                 I2C_BOARD_INFO("tlc59108", 0x40),
1460         },
1462 };
1464 static struct omap_musb_board_data musb_board_data = {
1465         .interface_type = MUSB_INTERFACE_ULPI,
1466         .mode           = MUSB_OTG,
1467         .power          = 500,
1468         .instances      = 1,
1469 };
1471 static int cpld_reg_probe(struct i2c_client *client,
1472             const struct i2c_device_id *id)
1474         cpld_client = client;
1475         return 0;
1478 static int __devexit cpld_reg_remove(struct i2c_client *client)
1480         cpld_client = NULL;
1481         return 0;
1484 static const struct i2c_device_id cpld_reg_id[] = {
1485         { "cpld_reg", 0 },
1486         { }
1487 };
1489 static struct i2c_driver cpld_reg_driver = {
1490         .driver = {
1491                 .name   = "cpld_reg",
1492         },
1493         .probe          = cpld_reg_probe,
1494         .remove         = cpld_reg_remove,
1495         .id_table       = cpld_reg_id,
1496 };
1498 static void evm_init_cpld(void)
1500         i2c_add_driver(&cpld_reg_driver);
1503 static void __init am335x_evm_i2c_init(void)
1505         /* Initially assume Low Cost EVM Config */
1506         am335x_evm_id = LOW_COST_EVM;
1508         evm_init_cpld();
1510         omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1511                                 ARRAY_SIZE(am335x_i2c_boardinfo));
1514 static struct resource am335x_rtc_resources[] = {
1515         {
1516                 .start          = AM33XX_RTC_BASE,
1517                 .end            = AM33XX_RTC_BASE + SZ_4K - 1,
1518                 .flags          = IORESOURCE_MEM,
1519         },
1520         { /* timer irq */
1521                 .start          = AM33XX_IRQ_RTC_TIMER,
1522                 .end            = AM33XX_IRQ_RTC_TIMER,
1523                 .flags          = IORESOURCE_IRQ,
1524         },
1525         { /* alarm irq */
1526                 .start          = AM33XX_IRQ_RTC_ALARM,
1527                 .end            = AM33XX_IRQ_RTC_ALARM,
1528                 .flags          = IORESOURCE_IRQ,
1529         },
1530 };
1532 static struct platform_device am335x_rtc_device = {
1533         .name           = "omap_rtc",
1534         .id             = -1,
1535         .num_resources  = ARRAY_SIZE(am335x_rtc_resources),
1536         .resource       = am335x_rtc_resources,
1537 };
1539 static int am335x_rtc_init(void)
1541         void __iomem *base;
1542         struct clk *clk;
1544         clk = clk_get(NULL, "rtc_fck");
1545         if (IS_ERR(clk)) {
1546                 pr_err("rtc : Failed to get RTC clock\n");
1547                 return -1;
1548         }
1550         if (clk_enable(clk)) {
1551                 pr_err("rtc: Clock Enable Failed\n");
1552                 return -1;
1553         }
1555         base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1557         if (WARN_ON(!base))
1558                 return -ENOMEM;
1560         /* Unlock the rtc's registers */
1561         __raw_writel(0x83e70b13, base + 0x6c);
1562         __raw_writel(0x95a4f1e0, base + 0x70);
1564         /*
1565          * Enable the 32K OSc
1566          * TODO: Need a better way to handle this
1567          * Since we want the clock to be running before mmc init
1568          * we need to do it before the rtc probe happens
1569          */
1570         __raw_writel(0x48, base + 0x54);
1572         iounmap(base);
1574         return  platform_device_register(&am335x_rtc_device);
1577 /* Enable clkout2 */
1578 static struct pinmux_config clkout2_pin_mux[] = {
1579         {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1580         {NULL, 0},
1581 };
1583 static void __init clkout2_enable(void)
1585         struct clk *ck_32;
1587         ck_32 = clk_get(NULL, "clkout2_ck");
1588         if (IS_ERR(ck_32)) {
1589                 pr_err("Cannot clk_get ck_32\n");
1590                 return;
1591         }
1593         clk_enable(ck_32);
1595         setup_pin_mux(clkout2_pin_mux);
1598 static void __init am335x_evm_init(void)
1600         am33xx_mux_init(board_mux);
1601         omap_serial_init();
1602         am335x_rtc_init();
1603         clkout2_enable();
1604         am335x_evm_i2c_init();
1605         omap_sdrc_init(NULL, NULL);
1606         usb_musb_init(&musb_board_data);
1607         omap_board_config = am335x_evm_config;
1608         omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1611 static void __init am335x_evm_map_io(void)
1613         omap2_set_globals_am33xx();
1614         omapam33xx_map_common_io();
1617 MACHINE_START(AM335XEVM, "am335xevm")
1618         /* Maintainer: Texas Instruments */
1619         .atag_offset    = 0x100,
1620         .map_io         = am335x_evm_map_io,
1621         .init_early     = am33xx_init_early,
1622         .init_irq       = ti81xx_init_irq,
1623         .handle_irq     = omap3_intc_handle_irq,
1624         .timer          = &omap3_am33xx_timer,
1625         .init_machine   = am335x_evm_init,
1626 MACHINE_END
1628 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1629         /* Maintainer: Texas Instruments */
1630         .atag_offset    = 0x100,
1631         .map_io         = am335x_evm_map_io,
1632         .init_irq       = ti81xx_init_irq,
1633         .init_early     = am33xx_init_early,
1634         .timer          = &omap3_am33xx_timer,
1635         .init_machine   = am335x_evm_init,
1636 MACHINE_END