arm:omap:pwm - LCD backlight enabled through PWM.
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / board-am335xevm.c
1 /*
2  * Code for AM335X EVM.
3  *
4  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
35 #include <linux/mfd/tps65910.h>
36 #include <linux/pwm_backlight.h>
38 /* LCD controller is similar to DA850 */
39 #include <video/da8xx-fb.h>
41 #include <mach/hardware.h>
42 #include <mach/board-am335xevm.h>
44 #include <asm/mach-types.h>
45 #include <asm/mach/arch.h>
46 #include <asm/mach/map.h>
47 #include <asm/hardware/asp.h>
49 #include <plat/irqs.h>
50 #include <plat/board.h>
51 #include <plat/common.h>
52 #include <plat/lcdc.h>
53 #include <plat/usb.h>
54 #include <plat/mmc.h>
56 #include "board-flash.h"
57 #include "cpuidle33xx.h"
58 #include "mux.h"
59 #include "devices.h"
60 #include "hsmmc.h"
62 /* Convert GPIO signal to GPIO pin number */
63 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
65 /* TLK PHY IDs */
66 #define TLK110_PHY_ID           0x2000A201
67 #define TLK110_PHY_MASK         0xfffffff0
69 /* BBB PHY IDs */
70 #define BBB_PHY_ID              0x7c0f1
71 #define BBB_PHY_MASK            0xfffffffe
73 /* TLK110 PHY register offsets */
74 #define TLK110_COARSEGAIN_REG   0x00A3
75 #define TLK110_LPFHPF_REG       0x00AC
76 #define TLK110_SPAREANALOG_REG  0x00B9
77 #define TLK110_VRCR_REG         0x00D0
78 #define TLK110_SETFFE_REG       0x0107
79 #define TLK110_FTSP_REG         0x0154
80 #define TLK110_ALFATPIDL_REG    0x002A
81 #define TLK110_PSCOEF21_REG     0x0096
82 #define TLK110_PSCOEF3_REG      0x0097
83 #define TLK110_ALFAFACTOR1_REG  0x002C
84 #define TLK110_ALFAFACTOR2_REG  0x0023
85 #define TLK110_CFGPS_REG        0x0095
86 #define TLK110_FTSPTXGAIN_REG   0x0150
87 #define TLK110_SWSCR3_REG       0x000B
88 #define TLK110_SCFALLBACK_REG   0x0040
89 #define TLK110_PHYRCR_REG       0x001F
91 /* TLK110 register writes values */
92 #define TLK110_COARSEGAIN_VAL   0x0000
93 #define TLK110_LPFHPF_VAL       0x8000
94 #define TLK110_SPANALOG_VAL     0x0000
95 #define TLK110_VRCR_VAL         0x0008
96 #define TLK110_SETFFE_VAL       0x0605
97 #define TLK110_FTSP_VAL         0x0255
98 #define TLK110_ALFATPIDL_VAL    0x7998
99 #define TLK110_PSCOEF21_VAL     0x3A20
100 #define TLK110_PSCOEF3_VAL      0x003F
101 #define TLK110_ALFACTOR1_VAL    0xFF80
102 #define TLK110_ALFACTOR2_VAL    0x021C
103 #define TLK110_CFGPS_VAL        0x0000
104 #define TLK110_FTSPTXGAIN_VAL   0x6A88
105 #define TLK110_SWSCR3_VAL       0x0000
106 #define TLK110_SCFALLBACK_VAL   0xC11D
107 #define TLK110_PHYRCR_VAL       0x4000
109 #if defined(CONFIG_TLK110_WORKAROUND) || \
110                 defined(CONFIG_TLK110_WORKAROUND_MODULE)
111 #define am335x_tlk110_phy_init()\
112         do {    \
113                 phy_register_fixup_for_uid(TLK110_PHY_ID,\
114                                         TLK110_PHY_MASK,\
115                                         am335x_tlk110_phy_fixup);\
116         } while (0);
117 #else
118 #define am335x_tlk110_phy_init() do { } while (0);
119 #endif
121 static const struct display_panel disp_panel = {
122         WVGA,
123         32,
124         32,
125         COLOR_ACTIVE,
126 };
128 #define AM335X_LCD_BL_PIN       GPIO_TO_PIN(0, 7)
129 /* LCD backlight platform Data */
130 #define AM335X_BACKLIGHT_MAX_BRIGHTNESS        250
131 #define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS    250
132 #define AM335X_PWM_PERIOD_NANO_SECONDS        (10000 * 10)
134 #define PWM_DEVICE_ID   "ecap.0"
136 static struct platform_pwm_backlight_data am335x_backlight_data = {
137         .pwm_id         = PWM_DEVICE_ID,
138         .ch             = -1,
139         .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
140         .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
141         .pwm_period_ns  = AM335X_PWM_PERIOD_NANO_SECONDS,
142 };
144 static struct lcd_ctrl_config lcd_cfg = {
145         &disp_panel,
146         .ac_bias                = 255,
147         .ac_bias_intrpt         = 0,
148         .dma_burst_sz           = 16,
149         .bpp                    = 32,
150         .fdd                    = 0x80,
151         .tft_alt_mode           = 0,
152         .stn_565_mode           = 0,
153         .mono_8bit_mode         = 0,
154         .invert_line_clock      = 1,
155         .invert_frm_clock       = 1,
156         .sync_edge              = 0,
157         .sync_ctrl              = 1,
158         .raster_order           = 0,
159 };
161 static void am335x_gpio_bl_ctrl(int val);
163 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
164         .manu_name              = "ThreeFive",
165         .controller_data        = &lcd_cfg,
166         .type                   = "TFC_S9700RTWV35TR_01B",
167         .panel_power_ctrl       = am335x_gpio_bl_ctrl,
168 };
170 #include "common.h"
172 /* TSc controller */
173 #include <linux/input/ti_tscadc.h>
174 #include <linux/lis3lv02d.h>
176 static struct resource tsc_resources[]  = {
177         [0] = {
178                 .start  = AM33XX_TSC_BASE,
179                 .end    = AM33XX_TSC_BASE + SZ_8K - 1,
180                 .flags  = IORESOURCE_MEM,
181         },
182         [1] = {
183                 .start  = AM33XX_IRQ_ADC_GEN,
184                 .end    = AM33XX_IRQ_ADC_GEN,
185                 .flags  = IORESOURCE_IRQ,
186         },
187 };
189 static struct tsc_data am335x_touchscreen_data  = {
190         .wires  = 4,
191         .x_plate_resistance = 200,
192 };
194 static struct platform_device tsc_device = {
195         .name   = "tsc",
196         .id     = -1,
197         .dev    = {
198                         .platform_data  = &am335x_touchscreen_data,
199         },
200         .num_resources  = ARRAY_SIZE(tsc_resources),
201         .resource       = tsc_resources,
202 };
204 static u8 am335x_iis_serializer_direction1[] = {
205         INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,        RX_MODE,
206         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
207         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
208         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
209 };
211 static struct snd_platform_data am335x_evm_snd_data1 = {
212         .tx_dma_offset  = 0x46400000,   /* McASP1 */
213         .rx_dma_offset  = 0x46400000,
214         .op_mode        = DAVINCI_MCASP_IIS_MODE,
215         .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
216         .tdm_slots      = 2,
217         .serial_dir     = am335x_iis_serializer_direction1,
218         .asp_chan_q     = EVENTQ_2,
219         .version        = MCASP_VERSION_3,
220         .txnumevt       = 1,
221         .rxnumevt       = 1,
222 };
224 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
225         {
226                 .mmc            = 1,
227                 .caps           = MMC_CAP_4_BIT_DATA,
228                 .gpio_cd        = GPIO_TO_PIN(0, 6),
229                 .gpio_wp        = GPIO_TO_PIN(3, 18),
230                 .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
231         },
232         {
233                 .mmc            = 0,    /* will be set at runtime */
234         },
235         {
236                 .mmc            = 0,    /* will be set at runtime */
237         },
238         {}      /* Terminator */
239 };
242 #ifdef CONFIG_OMAP_MUX
243 static struct omap_board_mux board_mux[] __initdata = {
244         AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
245                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
246         AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
247                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
248         { .reg_offset = OMAP_MUX_TERMINATOR },
249 };
250 #else
251 #define board_mux       NULL
252 #endif
254 /* module pin mux structure */
255 struct pinmux_config {
256         const char *string_name; /* signal name format */
257         int val; /* Options for the mux register value */
258 };
260 struct evm_dev_cfg {
261         void (*device_init)(int evm_id, int profile);
263 /*
264 * If the device is required on both baseboard & daughter board (ex i2c),
265 * specify DEV_ON_BASEBOARD
266 */
267 #define DEV_ON_BASEBOARD        0
268 #define DEV_ON_DGHTR_BRD        1
269         u32 device_on;
271         u32 profile;    /* Profiles (0-7) in which the module is present */
272 };
274 /* AM335X - CPLD Register Offsets */
275 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
276 #define CPLD_DEVICE_ID  0x04 /* CPLD identification */
277 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
278 #define CPLD_CFG_REG    0x10 /* Configuration Register */
280 static struct i2c_client *cpld_client;
281 static u32 am335x_evm_id;
282 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
283 };
285 /*
286 * EVM Config held in On-Board eeprom device.
288 * Header Format
290 *  Name                 Size    Contents
291 *                       (Bytes)
292 *-------------------------------------------------------------
293 *  Header               4       0xAA, 0x55, 0x33, 0xEE
295 *  Board Name           8       Name for board in ASCII.
296 *                               example "A33515BB" = "AM335X
297                                 Low Cost EVM board"
299 *  Version              4       Hardware version code for board in
300 *                               in ASCII. "1.0A" = rev.01.0A
302 *  Serial Number        12      Serial number of the board. This is a 12
303 *                               character string which is WWYY4P16nnnn, where
304 *                               WW = 2 digit week of the year of production
305 *                               YY = 2 digit year of production
306 *                               nnnn = incrementing board number
308 *  Configuration option 32      Codes(TBD) to show the configuration
309 *                               setup on this board.
311 *  Available            32720   Available space for other non-volatile
312 *                               data.
313 */
314 struct am335x_evm_eeprom_config {
315         u32     header;
316         u8      name[8];
317         char    version[4];
318         u8      serial[12];
319         u8      opt[32];
320 };
322 static struct am335x_evm_eeprom_config config;
323 static bool daughter_brd_detected;
325 #define GP_EVM_REV_IS_1_0               0x1
326 #define GP_EVM_REV_IS_1_1A              0x2
327 #define GP_EVM_REV_IS_UNKNOWN           0xFF
328 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
329 unsigned int gigabit_enable = 1;
331 #define EEPROM_MAC_ADDRESS_OFFSET       60 /* 4+8+4+12+32 */
332 #define EEPROM_NO_OF_MAC_ADDR           3
333 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
335 #define AM335X_EEPROM_HEADER            0xEE3355AA
337 /* current profile if exists else PROFILE_0 on error */
338 static u32 am335x_get_profile_selection(void)
340         int val = 0;
342         if (!cpld_client)
343                 /* error checking is not done in func's calling this routine.
344                 so return profile 0 on error */
345                 return 0;
347         val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
348         if (val < 0)
349                 return 0;       /* default to Profile 0 on Error */
350         else
351                 return val & 0x7;
354 /* Module pin mux for LCDC */
355 static struct pinmux_config lcdc_pin_mux[] = {
356         {"lcd_data0.lcd_data0",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
357                                                        | AM33XX_PULL_DISA},
358         {"lcd_data1.lcd_data1",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
359                                                        | AM33XX_PULL_DISA},
360         {"lcd_data2.lcd_data2",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
361                                                        | AM33XX_PULL_DISA},
362         {"lcd_data3.lcd_data3",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
363                                                        | AM33XX_PULL_DISA},
364         {"lcd_data4.lcd_data4",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
365                                                        | AM33XX_PULL_DISA},
366         {"lcd_data5.lcd_data5",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
367                                                        | AM33XX_PULL_DISA},
368         {"lcd_data6.lcd_data6",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
369                                                        | AM33XX_PULL_DISA},
370         {"lcd_data7.lcd_data7",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
371                                                        | AM33XX_PULL_DISA},
372         {"lcd_data8.lcd_data8",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
373                                                        | AM33XX_PULL_DISA},
374         {"lcd_data9.lcd_data9",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
375                                                        | AM33XX_PULL_DISA},
376         {"lcd_data10.lcd_data10",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
377                                                        | AM33XX_PULL_DISA},
378         {"lcd_data11.lcd_data11",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
379                                                        | AM33XX_PULL_DISA},
380         {"lcd_data12.lcd_data12",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
381                                                        | AM33XX_PULL_DISA},
382         {"lcd_data13.lcd_data13",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
383                                                        | AM33XX_PULL_DISA},
384         {"lcd_data14.lcd_data14",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
385                                                        | AM33XX_PULL_DISA},
386         {"lcd_data15.lcd_data15",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
387                                                        | AM33XX_PULL_DISA},
388         {"gpmc_ad8.lcd_data16",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
389         {"gpmc_ad9.lcd_data17",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
390         {"gpmc_ad10.lcd_data18",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
391         {"gpmc_ad11.lcd_data19",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
392         {"gpmc_ad12.lcd_data20",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
393         {"gpmc_ad13.lcd_data21",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
394         {"gpmc_ad14.lcd_data22",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
395         {"gpmc_ad15.lcd_data23",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
396         {"lcd_vsync.lcd_vsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
397         {"lcd_hsync.lcd_hsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
398         {"lcd_pclk.lcd_pclk",           OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
399         {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
400         {NULL, 0},
401 };
403 static struct pinmux_config tsc_pin_mux[] = {
404         {"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
405         {"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
406         {"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
407         {"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
408         {"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
409         {"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
410         {NULL, 0},
411 };
413 /* Pin mux for nand flash module */
414 static struct pinmux_config nand_pin_mux[] = {
415         {"gpmc_ad0.gpmc_ad0",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
416         {"gpmc_ad1.gpmc_ad1",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
417         {"gpmc_ad2.gpmc_ad2",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
418         {"gpmc_ad3.gpmc_ad3",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
419         {"gpmc_ad4.gpmc_ad4",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
420         {"gpmc_ad5.gpmc_ad5",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
421         {"gpmc_ad6.gpmc_ad6",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
422         {"gpmc_ad7.gpmc_ad7",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
423         {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
424         {"gpmc_wpn.gpmc_wpn",     OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
425         {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
426         {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
427         {"gpmc_oen_ren.gpmc_oen_ren",    OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
428         {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
429         {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
430         {NULL, 0},
431 };
433 /* Module pin mux for SPI fash */
434 static struct pinmux_config spi0_pin_mux[] = {
435         {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
436                                                         | AM33XX_INPUT_EN},
437         {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
438                                                         | AM33XX_INPUT_EN},
439         {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
440                                                         | AM33XX_INPUT_EN},
441         {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
442                                                         | AM33XX_INPUT_EN},
443         {NULL, 0},
444 };
446 /* Module pin mux for SPI flash */
447 static struct pinmux_config spi1_pin_mux[] = {
448         {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
449                 | AM33XX_INPUT_EN},
450         {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
451                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
452         {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
453                 | AM33XX_INPUT_EN},
454         {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
455                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
456         {NULL, 0},
457 };
459 /* Module pin mux for rgmii1 */
460 static struct pinmux_config rgmii1_pin_mux[] = {
461         {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
462         {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
463         {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
464         {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
465         {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
466         {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
467         {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
468         {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
469         {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
470         {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
471         {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
472         {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
473         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
474         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
475         {NULL, 0},
476 };
478 /* Module pin mux for rgmii2 */
479 static struct pinmux_config rgmii2_pin_mux[] = {
480         {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
481         {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
482         {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
483         {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
484         {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
485         {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
486         {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
487         {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
488         {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
489         {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
490         {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
491         {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
492         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
493         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
494         {NULL, 0},
495 };
497 /* Module pin mux for mii1 */
498 static struct pinmux_config mii1_pin_mux[] = {
499         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
500         {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
501         {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
502         {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
503         {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
504         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
505         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
506         {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
507         {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
508         {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
509         {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
510         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
511         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
512         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
513         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
514         {NULL, 0},
515 };
517 /* Module pin mux for rmii1 */
518 static struct pinmux_config rmii1_pin_mux[] = {
519         {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
520         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
521         {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
522         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
523         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
524         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
525         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
526         {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
527         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
528         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
529         {NULL, 0},
530 };
532 static struct pinmux_config i2c1_pin_mux[] = {
533         {"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
534                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
535         {"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
536                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
537         {NULL, 0},
538 };
540 /* Module pin mux for mcasp1 */
541 static struct pinmux_config mcasp1_pin_mux[] = {
542         {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
543         {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
544         {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
545         {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
546                                                 AM33XX_PIN_INPUT_PULLDOWN},
547         {NULL, 0},
548 };
551 /* Module pin mux for mmc0 */
552 static struct pinmux_config mmc0_pin_mux[] = {
553         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
554         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
555         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
556         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
557         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
558         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
559         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
560         {"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
561         {NULL, 0},
562 };
564 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
565         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
566         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
567         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
568         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
569         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
570         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
571         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
572         {NULL, 0},
573 };
575 /* Module pin mux for mmc1 */
576 static struct pinmux_config mmc1_pin_mux[] = {
577         {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
578         {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
579         {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
580         {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
581         {"gpmc_ad3.mmc1_dat3",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
582         {"gpmc_ad2.mmc1_dat2",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
583         {"gpmc_ad1.mmc1_dat1",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
584         {"gpmc_ad0.mmc1_dat0",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
585         {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
586         {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
587         {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
588         {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
589         {NULL, 0},
590 };
592 /* Module pin mux for uart3 */
593 static struct pinmux_config uart3_pin_mux[] = {
594         {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
595         {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
596         {NULL, 0},
597 };
599 static struct pinmux_config d_can_gp_pin_mux[] = {
600         {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
601         {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
602         {NULL, 0},
603 };
605 static struct pinmux_config d_can_ia_pin_mux[] = {
606         {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
607         {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
608         {NULL, 0},
609 };
611 /* Module pin mux for uart2 */
612 static struct pinmux_config uart2_pin_mux[] = {
613         {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
614                                                 AM33XX_PIN_INPUT_PULLUP},
615         {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
616                                                 AM33XX_PULL_DISA |
617                                                 AM33XX_SLEWCTRL_SLOW},
618         {NULL, 0},
619 };
622 /*
623 * @pin_mux - single module pin-mux structure which defines pin-mux
624 *                       details for all its pins.
625 */
626 static void setup_pin_mux(struct pinmux_config *pin_mux)
628         int i;
630         for (i = 0; pin_mux->string_name != NULL; pin_mux++)
631                 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
635 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
637 /* pinmux for keypad device */
638 static struct pinmux_config matrix_keypad_pin_mux[] = {
639         {"gpmc_a5.gpio1_21",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
640         {"gpmc_a6.gpio1_22",  OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
641         {"gpmc_a9.gpio1_25",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
642         {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
643         {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
644         {NULL, 0},
645 };
647 /* Keys mapping */
648 static const uint32_t am335x_evm_matrix_keys[] = {
649         KEY(0, 0, KEY_MENU),
650         KEY(1, 0, KEY_BACK),
651         KEY(2, 0, KEY_LEFT),
653         KEY(0, 1, KEY_RIGHT),
654         KEY(1, 1, KEY_ENTER),
655         KEY(2, 1, KEY_DOWN),
656 };
658 const struct matrix_keymap_data am335x_evm_keymap_data = {
659         .keymap      = am335x_evm_matrix_keys,
660         .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
661 };
663 static const unsigned int am335x_evm_keypad_row_gpios[] = {
664         GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
665 };
667 static const unsigned int am335x_evm_keypad_col_gpios[] = {
668         GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
669 };
671 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
672         .keymap_data       = &am335x_evm_keymap_data,
673         .row_gpios         = am335x_evm_keypad_row_gpios,
674         .num_row_gpios     = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
675         .col_gpios         = am335x_evm_keypad_col_gpios,
676         .num_col_gpios     = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
677         .active_low        = false,
678         .debounce_ms       = 5,
679         .col_scan_delay_us = 2,
680 };
682 static struct platform_device am335x_evm_keyboard = {
683         .name  = "matrix-keypad",
684         .id    = -1,
685         .dev   = {
686                 .platform_data = &am335x_evm_keypad_platform_data,
687         },
688 };
690 static void matrix_keypad_init(int evm_id, int profile)
692         int err;
694         setup_pin_mux(matrix_keypad_pin_mux);
695         err = platform_device_register(&am335x_evm_keyboard);
696         if (err) {
697                 pr_err("failed to register matrix keypad (2x3) device\n");
698         }
702 /* pinmux for keypad device */
703 static struct pinmux_config volume_keys_pin_mux[] = {
704         {"spi0_sclk.gpio0_2",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
705         {"spi0_d0.gpio0_3",    OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
706         {NULL, 0},
707 };
709 /* Configure GPIOs for Volume Keys */
710 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
711         {
712                 .code                   = KEY_VOLUMEUP,
713                 .gpio                   = GPIO_TO_PIN(0, 2),
714                 .active_low             = true,
715                 .desc                   = "volume-up",
716                 .type                   = EV_KEY,
717                 .wakeup                 = 1,
718         },
719         {
720                 .code                   = KEY_VOLUMEDOWN,
721                 .gpio                   = GPIO_TO_PIN(0, 3),
722                 .active_low             = true,
723                 .desc                   = "volume-down",
724                 .type                   = EV_KEY,
725                 .wakeup                 = 1,
726         },
727 };
729 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
730         .buttons        = am335x_evm_volume_gpio_buttons,
731         .nbuttons       = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
732 };
734 static struct platform_device am335x_evm_volume_keys = {
735         .name   = "gpio-keys",
736         .id     = -1,
737         .dev    = {
738                 .platform_data  = &am335x_evm_volume_gpio_key_info,
739         },
740 };
742 static void volume_keys_init(int evm_id, int profile)
744         int err;
746         setup_pin_mux(volume_keys_pin_mux);
747         err = platform_device_register(&am335x_evm_volume_keys);
748         if (err)
749                 pr_err("failed to register matrix keypad (2x3) device\n");
752 /*
753 * @evm_id - evm id which needs to be configured
754 * @dev_cfg - single evm structure which includes
755 *                               all module inits, pin-mux defines
756 * @profile - if present, else PROFILE_NONE
757 * @dghtr_brd_flg - Whether Daughter board is present or not
758 */
759 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
760         int profile)
762         int i;
764         /*
765         * Only General Purpose & Industrial Auto Motro Control
766         * EVM has profiles. So check if this evm has profile.
767         * If not, ignore the profile comparison
768         */
770         /*
771         * If the device is on baseboard, directly configure it. Else (device on
772         * Daughter board), check if the daughter card is detected.
773         */
774         if (profile == PROFILE_NONE) {
775                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
776                         if (dev_cfg->device_on == DEV_ON_BASEBOARD)
777                                 dev_cfg->device_init(evm_id, profile);
778                         else if (daughter_brd_detected == true)
779                                 dev_cfg->device_init(evm_id, profile);
780                 }
781         } else {
782                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
783                         if (dev_cfg->profile & profile) {
784                                 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
785                                         dev_cfg->device_init(evm_id, profile);
786                                 else if (daughter_brd_detected == true)
787                                         dev_cfg->device_init(evm_id, profile);
788                         }
789                 }
790         }
794 /* pinmux for usb0 drvvbus */
795 static struct pinmux_config usb0_pin_mux[] = {
796         {"usb0_drvvbus.usb0_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
797         {NULL, 0},
798 };
800 /* pinmux for usb1 drvvbus */
801 static struct pinmux_config usb1_pin_mux[] = {
802         {"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
803         {NULL, 0},
804 };
806 /* pinmux for profibus */
807 static struct pinmux_config profibus_pin_mux[] = {
808         {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
809         {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
810         {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
811         {NULL, 0},
812 };
814 /* Module pin mux for eCAP0 */
815 static struct pinmux_config ecap0_pin_mux[] = {
816         {"ecap0_in_pwm0_out.ecap0_in_pwm0_out",
817                 OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
818         {NULL, 0},
819 };
821 static int backlight_enable;
823 #define AM335XEVM_WLAN_PMENA_GPIO       GPIO_TO_PIN(1, 30)
824 #define AM335XEVM_WLAN_IRQ_GPIO         GPIO_TO_PIN(3, 17)
826 struct wl12xx_platform_data am335xevm_wlan_data = {
827         .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
828         .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
829 };
831 /* Module pin mux for wlan and bluetooth */
832 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
833         {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
834         {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
835         {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
836         {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
837         {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
838         {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
839         {NULL, 0},
840 };
842 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
843         {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
844         {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
845         {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
846         {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
847         {NULL, 0},
848 };
850 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
851         {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
852         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
853         {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
854         {NULL, 0},
855  };
857 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
858         {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
859         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
860         {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
861         {NULL, 0},
862  };
864 static void enable_ecap0(int evm_id, int profile)
866         backlight_enable = true;
869 static void am335x_gpio_bl_ctrl(int val)
871         /* lcd backlight */
872         gpio_set_value(AM335X_LCD_BL_PIN, val);
874 /* Setup pwm-backlight */
875 static struct platform_device am335x_backlight = {
876         .name           = "pwm-backlight",
877         .id             = -1,
878         .dev            = {
879                 .platform_data  = &am335x_backlight_data,
880         }
881 };
883 static int __init ecap0_init(void)
885         int status = 0;
887         if (backlight_enable) {
888                 setup_pin_mux(ecap0_pin_mux);
889                 platform_device_register(&am335x_backlight);
890         }
891         return status;
893 late_initcall(ecap0_init);
895 static int __init conf_disp_pll(int rate)
897         struct clk *disp_pll;
898         int ret = -EINVAL;
900         disp_pll = clk_get(NULL, "dpll_disp_ck");
901         if (IS_ERR(disp_pll)) {
902                 pr_err("Cannot clk_get disp_pll\n");
903                 goto out;
904         }
906         ret = clk_set_rate(disp_pll, rate);
907         clk_put(disp_pll);
908 out:
909         return ret;
912 static void lcdc_init(int evm_id, int profile)
915         setup_pin_mux(lcdc_pin_mux);
917         if (conf_disp_pll(300000000)) {
918                 pr_info("Failed configure display PLL, not attempting to"
919                                 "register LCDC\n");
920                 return;
921         }
923         if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
924                 pr_info("Failed to register LCDC device\n");
925         return;
928 static void tsc_init(int evm_id, int profile)
930         int err;
932         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
933                 am335x_touchscreen_data.analog_input = 1;
934                 pr_info("TSC connected to beta GP EVM\n");
935         } else {
936                 am335x_touchscreen_data.analog_input = 0;
937                 pr_info("TSC connected to alpha GP EVM\n");
938         }
939         setup_pin_mux(tsc_pin_mux);
940         err = platform_device_register(&tsc_device);
941         if (err)
942                 pr_err("failed to register touchscreen device\n");
945 static void rgmii1_init(int evm_id, int profile)
947         setup_pin_mux(rgmii1_pin_mux);
948         return;
951 static void rgmii2_init(int evm_id, int profile)
953         setup_pin_mux(rgmii2_pin_mux);
954         return;
957 static void mii1_init(int evm_id, int profile)
959         setup_pin_mux(mii1_pin_mux);
960         return;
963 static void rmii1_init(int evm_id, int profile)
965         setup_pin_mux(rmii1_pin_mux);
966         return;
969 static void usb0_init(int evm_id, int profile)
971         setup_pin_mux(usb0_pin_mux);
972         return;
975 static void usb1_init(int evm_id, int profile)
977         setup_pin_mux(usb1_pin_mux);
978         return;
981 /* setup uart3 */
982 static void uart3_init(int evm_id, int profile)
984         setup_pin_mux(uart3_pin_mux);
985         return;
988 /* setup uart2 */
989 static void uart2_init(int evm_id, int profile)
991         setup_pin_mux(uart2_pin_mux);
992         return;
995 /* NAND partition information */
996 static struct mtd_partition am335x_nand_partitions[] = {
997 /* All the partition sizes are listed in terms of NAND block size */
998         {
999                 .name           = "SPL",
1000                 .offset         = 0,                    /* Offset = 0x0 */
1001                 .size           = SZ_128K,
1002         },
1003         {
1004                 .name           = "SPL.backup1",
1005                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x20000 */
1006                 .size           = SZ_128K,
1007         },
1008         {
1009                 .name           = "SPL.backup2",
1010                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x40000 */
1011                 .size           = SZ_128K,
1012         },
1013         {
1014                 .name           = "SPL.backup3",
1015                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x60000 */
1016                 .size           = SZ_128K,
1017         },
1018         {
1019                 .name           = "U-Boot",
1020                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
1021                 .size           = 15 * SZ_128K,
1022         },
1023         {
1024                 .name           = "U-Boot Env",
1025                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
1026                 .size           = 1 * SZ_128K,
1027         },
1028         {
1029                 .name           = "Kernel",
1030                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
1031                 .size           = 40 * SZ_128K,
1032         },
1033         {
1034                 .name           = "File System",
1035                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
1036                 .size           = MTDPART_SIZ_FULL,
1037         },
1038 };
1040 /* SPI 0/1 Platform Data */
1041 /* SPI flash information */
1042 static struct mtd_partition am335x_spi_partitions[] = {
1043         /* All the partition sizes are listed in terms of erase size */
1044         {
1045                 .name       = "SPL",
1046                 .offset     = 0,                        /* Offset = 0x0 */
1047                 .size       = SZ_128K,
1048         },
1049         {
1050                 .name       = "U-Boot",
1051                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x20000 */
1052                 .size       = 2 * SZ_128K,
1053         },
1054         {
1055                 .name       = "U-Boot Env",
1056                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x60000 */
1057                 .size       = 2 * SZ_4K,
1058         },
1059         {
1060                 .name       = "Kernel",
1061                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x62000 */
1062                 .size       = 28 * SZ_128K,
1063         },
1064         {
1065                 .name       = "File System",
1066                 .offset     = MTDPART_OFS_APPEND,       /* Offset = 0x3E2000 */
1067                 .size       = MTDPART_SIZ_FULL,         /* size ~= 4.1 MiB */
1068         }
1069 };
1071 static const struct flash_platform_data am335x_spi_flash = {
1072         .type      = "w25q64",
1073         .name      = "spi_flash",
1074         .parts     = am335x_spi_partitions,
1075         .nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
1076 };
1078 /*
1079  * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1080  * So setup Max speed to be less than that of Controller speed
1081  */
1082 static struct spi_board_info am335x_spi0_slave_info[] = {
1083         {
1084                 .modalias      = "m25p80",
1085                 .platform_data = &am335x_spi_flash,
1086                 .irq           = -1,
1087                 .max_speed_hz  = 24000000,
1088                 .bus_num       = 1,
1089                 .chip_select   = 0,
1090         },
1091 };
1093 static struct spi_board_info am335x_spi1_slave_info[] = {
1094         {
1095                 .modalias      = "m25p80",
1096                 .platform_data = &am335x_spi_flash,
1097                 .irq           = -1,
1098                 .max_speed_hz  = 12000000,
1099                 .bus_num       = 2,
1100                 .chip_select   = 0,
1101         },
1102 };
1104 static void evm_nand_init(int evm_id, int profile)
1106         setup_pin_mux(nand_pin_mux);
1107         board_nand_init(am335x_nand_partitions,
1108                 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1111 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1112         .click_flags = LIS3_CLICK_SINGLE_X |
1113                         LIS3_CLICK_SINGLE_Y |
1114                         LIS3_CLICK_SINGLE_Z,
1115         .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1116                         LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1117                         LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1118         .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1119         .wakeup_thresh  = 10,
1120         .click_thresh_x = 10,
1121         .click_thresh_y = 10,
1122         .click_thresh_z = 10,
1123         .g_range        = 2,
1124         .st_min_limits[0] = 120,
1125         .st_min_limits[1] = 120,
1126         .st_min_limits[2] = 140,
1127         .st_max_limits[0] = 550,
1128         .st_max_limits[1] = 550,
1129         .st_max_limits[2] = 750,
1130 };
1132 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1133         {
1134                 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1135         },
1136         {
1137                 I2C_BOARD_INFO("lis331dlh", 0x18),
1138                 .platform_data = &lis331dlh_pdata,
1139         },
1140         {
1141                 I2C_BOARD_INFO("tsl2550", 0x39),
1142         },
1143         {
1144                 I2C_BOARD_INFO("tmp275", 0x48),
1145         },
1146 };
1148 static void i2c1_init(int evm_id, int profile)
1150         setup_pin_mux(i2c1_pin_mux);
1151         omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1152                         ARRAY_SIZE(am335x_i2c_boardinfo1));
1153         return;
1156 /* Setup McASP 1 */
1157 static void mcasp1_init(int evm_id, int profile)
1159         /* Configure McASP */
1160         setup_pin_mux(mcasp1_pin_mux);
1161         am335x_register_mcasp1(&am335x_evm_snd_data1);
1162         return;
1165 static void mmc1_init(int evm_id, int profile)
1167         setup_pin_mux(mmc1_pin_mux);
1169         am335x_mmc[1].mmc = 2;
1170         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1171         am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1172         am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1173         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1175         /* mmc will be initialized when mmc0_init is called */
1176         return;
1179 static void mmc2_wl12xx_init(int evm_id, int profile)
1181         setup_pin_mux(mmc2_wl12xx_pin_mux);
1183         am335x_mmc[1].mmc = 3;
1184         am335x_mmc[1].name = "wl1271";
1185         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1186                                 | MMC_PM_KEEP_POWER;
1187         am335x_mmc[1].nonremovable = true;
1188         am335x_mmc[1].gpio_cd = -EINVAL;
1189         am335x_mmc[1].gpio_wp = -EINVAL;
1190         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1192         /* mmc will be initialized when mmc0_init is called */
1193         return;
1196 static void uart1_wl12xx_init(int evm_id, int profile)
1198         setup_pin_mux(uart1_wl12xx_pin_mux);
1201 static void wl12xx_bluetooth_enable(void)
1203         int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1204                 "bt_en\n");
1205         if (status < 0)
1206                 pr_err("Failed to request gpio for bt_enable");
1208         pr_info("Configure Bluetooth Enable pin...\n");
1209         gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1212 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1214         if (on) {
1215                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1216                 mdelay(70);
1217         }
1218         else
1219                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1221         return 0;
1224 static void wl12xx_init(int evm_id, int profile)
1226         struct device *dev;
1227         struct omap_mmc_platform_data *pdata;
1228         int ret;
1230         /* Register WLAN and BT enable pins based on the evm board revision */
1231         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1232                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1233                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1234         }
1235         else {
1236                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1237                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1238         }
1240         wl12xx_bluetooth_enable();
1242         if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1243                 pr_err("error setting wl12xx data\n");
1245         dev = am335x_mmc[1].dev;
1246         if (!dev) {
1247                 pr_err("wl12xx mmc device initialization failed\n");
1248                 goto out;
1249         }
1251         pdata = dev->platform_data;
1252         if (!pdata) {
1253                 pr_err("Platfrom data of wl12xx device not set\n");
1254                 goto out;
1255         }
1257         ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1258                 GPIOF_OUT_INIT_LOW, "wlan_en");
1259         if (ret) {
1260                 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1261                 goto out;
1262         }
1264         if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1265                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1266         else
1267                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1269         pdata->slots[0].set_power = wl12xx_set_power;
1270 out:
1271         return;
1274 static void d_can_init(int evm_id, int profile)
1276         switch (evm_id) {
1277         case IND_AUT_MTR_EVM:
1278                 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1279                         setup_pin_mux(d_can_ia_pin_mux);
1280                         /* Instance Zero */
1281                         am33xx_d_can_init(0);
1282                 }
1283                 break;
1284         case GEN_PURP_EVM:
1285                 if (profile == PROFILE_1) {
1286                         setup_pin_mux(d_can_gp_pin_mux);
1287                         /* Instance One */
1288                         am33xx_d_can_init(1);
1289                 }
1290                 break;
1291         default:
1292                 break;
1293         }
1296 static void mmc0_init(int evm_id, int profile)
1298         setup_pin_mux(mmc0_pin_mux);
1300         omap2_hsmmc_init(am335x_mmc);
1301         return;
1304 static void mmc0_no_cd_init(int evm_id, int profile)
1306         setup_pin_mux(mmc0_no_cd_pin_mux);
1308         omap2_hsmmc_init(am335x_mmc);
1309         return;
1313 /* setup spi0 */
1314 static void spi0_init(int evm_id, int profile)
1316         setup_pin_mux(spi0_pin_mux);
1317         spi_register_board_info(am335x_spi0_slave_info,
1318                         ARRAY_SIZE(am335x_spi0_slave_info));
1319         return;
1322 /* setup spi1 */
1323 static void spi1_init(int evm_id, int profile)
1325         setup_pin_mux(spi1_pin_mux);
1326         spi_register_board_info(am335x_spi1_slave_info,
1327                         ARRAY_SIZE(am335x_spi1_slave_info));
1328         return;
1332 static int beaglebone_phy_fixup(struct phy_device *phydev)
1334         phydev->supported &= ~(SUPPORTED_100baseT_Half |
1335                                 SUPPORTED_100baseT_Full);
1337         return 0;
1340 #if defined(CONFIG_TLK110_WORKAROUND) || \
1341                         defined(CONFIG_TLK110_WORKAROUND_MODULE)
1342 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1344         unsigned int val;
1346         /* This is done as a workaround to support TLK110 rev1.0 phy */
1347         val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1348         phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1350         val = phy_read(phydev, TLK110_LPFHPF_REG);
1351         phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1353         val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1354         phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1356         val = phy_read(phydev, TLK110_VRCR_REG);
1357         phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1359         val = phy_read(phydev, TLK110_SETFFE_REG);
1360         phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1362         val = phy_read(phydev, TLK110_FTSP_REG);
1363         phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1365         val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1366         phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1368         val = phy_read(phydev, TLK110_PSCOEF21_REG);
1369         phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1371         val = phy_read(phydev, TLK110_PSCOEF3_REG);
1372         phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1374         val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1375         phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1377         val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1378         phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1380         val = phy_read(phydev, TLK110_CFGPS_REG);
1381         phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1383         val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1384         phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1386         val = phy_read(phydev, TLK110_SWSCR3_REG);
1387         phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1389         val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1390         phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1392         val = phy_read(phydev, TLK110_PHYRCR_REG);
1393         phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1395         return 0;
1397 #endif
1399 static void profibus_init(int evm_id, int profile)
1401         setup_pin_mux(profibus_pin_mux);
1402         return;
1405 /* Low-Cost EVM */
1406 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1407         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1408         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1409         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1410         {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1411         {NULL, 0, 0},
1412 };
1414 /* General Purpose EVM */
1415 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1416         {enable_ecap0,  DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1417                                                 PROFILE_2 | PROFILE_7) },
1418         {lcdc_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1419                                                 PROFILE_2 | PROFILE_7) },
1420         {tsc_init,      DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1421                                                 PROFILE_2 | PROFILE_7) },
1422         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
1423         {rgmii2_init,   DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1424                                                 PROFILE_4 | PROFILE_6) },
1425         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1426         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1427         {evm_nand_init, DEV_ON_DGHTR_BRD,
1428                 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1429         {i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1430         {mcasp1_init,   DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1431         {mmc1_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1432         {mmc2_wl12xx_init,      DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1433                                                                 PROFILE_5)},
1434         {mmc0_init,     DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1435         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_5},
1436         {spi0_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
1437         {uart1_wl12xx_init,     DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1438                                                                 PROFILE_5)},
1439         {wl12xx_init,   DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1440         {d_can_init,    DEV_ON_DGHTR_BRD, PROFILE_1},
1441         {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1442         {volume_keys_init,  DEV_ON_DGHTR_BRD, PROFILE_0},
1443         {uart2_init,    DEV_ON_DGHTR_BRD, PROFILE_3},
1444         {NULL, 0, 0},
1445 };
1447 /* Industrial Auto Motor Control EVM */
1448 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1449         {mii1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1450         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1451         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1452         {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1453         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1454         {spi1_init,     DEV_ON_DGHTR_BRD, PROFILE_ALL},
1455         {uart3_init,    DEV_ON_DGHTR_BRD, PROFILE_ALL},
1456         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1457         {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_ALL},
1458         {NULL, 0, 0},
1459 };
1461 /* IP-Phone EVM */
1462 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1463         {enable_ecap0,  DEV_ON_DGHTR_BRD, PROFILE_NONE},
1464         {lcdc_init,     DEV_ON_DGHTR_BRD, PROFILE_NONE},
1465         {tsc_init,      DEV_ON_DGHTR_BRD, PROFILE_NONE},
1466         {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
1467         {rgmii2_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1468         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1469         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1470         {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1471         {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1472         {mcasp1_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
1473         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1474         {NULL, 0, 0},
1475 };
1477 /* Beaglebone < Rev A3 */
1478 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1479         {rmii1_init,    DEV_ON_BASEBOARD, PROFILE_NONE},
1480         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1481         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1482         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1483         {NULL, 0, 0},
1484 };
1486 /* Beaglebone Rev A3 and after */
1487 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1488         {mii1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1489         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1490         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1491         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
1492         {NULL, 0, 0},
1493 };
1495 static void setup_low_cost_evm(void)
1497         pr_info("The board is a AM335x Low Cost EVM.\n");
1499         _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1502 static void setup_general_purpose_evm(void)
1504         u32 prof_sel = am335x_get_profile_selection();
1505         pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1507         if (!strncmp("1.1A", config.version, 4)) {
1508                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1509         } else if (!strncmp("1.0", config.version, 3)) {
1510                 gp_evm_revision = GP_EVM_REV_IS_1_0;
1511         } else {
1512                 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1513                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1514         }
1516         if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1517                 gigabit_enable = 0;
1518         else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1519                 gigabit_enable = 1;
1521         _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1524 static void setup_ind_auto_motor_ctrl_evm(void)
1526         u32 prof_sel = am335x_get_profile_selection();
1528         pr_info("The board is an industrial automation EVM in profile %d\n",
1529                 prof_sel);
1531         /* Only Profile 0 is supported */
1532         if ((1L << prof_sel) != PROFILE_0) {
1533                 pr_err("AM335X: Only Profile 0 is supported\n");
1534                 pr_err("Assuming profile 0 & continuing\n");
1535                 prof_sel = PROFILE_0;
1536         }
1538         _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1539                 PROFILE_0);
1541         /* Fillup global evmid */
1542         am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1544         /* Initialize TLK110 PHY registers for phy version 1.0 */
1545         am335x_tlk110_phy_init();
1550 static void setup_ip_phone_evm(void)
1552         pr_info("The board is an IP phone EVM\n");
1554         _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1557 /* BeagleBone < Rev A3 */
1558 static void setup_beaglebone_old(void)
1560         pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1562         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1563         am335x_mmc[0].gpio_wp = -EINVAL;
1565         _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1567         phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1568                                         beaglebone_phy_fixup);
1570         /* Fill up global evmid */
1571         am33xx_evmid_fillup(BEAGLE_BONE_OLD);
1574 /* BeagleBone after Rev A3 */
1575 static void setup_beaglebone(void)
1577         pr_info("The board is a AM335x Beaglebone.\n");
1579         /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1580         am335x_mmc[0].gpio_wp = -EINVAL;
1582         _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1584         /* Fill up global evmid */
1585         am33xx_evmid_fillup(BEAGLE_BONE_A3);
1589 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1591         u8 tmp;
1592         int ret;
1594         /*
1595          * try reading a byte from the EEPROM to see if it is
1596          * present. We could read a lot more, but that would
1597          * just slow the boot process and we have all the information
1598          * we need from the EEPROM on the base board anyway.
1599          */
1600         ret = m->read(m, &tmp, 0, sizeof(u8));
1601         if (ret == sizeof(u8)) {
1602                 pr_info("Detected a daughter card on AM335x EVM..");
1603                 daughter_brd_detected = true;
1604         } else {
1605                 pr_info("No daughter card found\n");
1606                 daughter_brd_detected = false;
1607         }
1610 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1612         int ret;
1613         char tmp[10];
1615         /* 1st get the MAC address from EEPROM */
1616         ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1617                 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1619         if (ret != sizeof(am335x_mac_addr)) {
1620                 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1621                 return;
1622         }
1624         /* Fillup global mac id */
1625         am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1626                                 &am335x_mac_addr[1][0]);
1628         /* get board specific data */
1629         ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1630         if (ret != sizeof(config)) {
1631                 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1632                 return;
1633         }
1635         if (config.header != AM335X_EEPROM_HEADER) {
1636                 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1637                         config.header, AM335X_EEPROM_HEADER);
1638                 goto out;
1639         }
1641         if (strncmp("A335", config.name, 4)) {
1642                 pr_err("Board %s doesn't look like an AM335x board\n",
1643                         config.name);
1644                 goto out;
1645         }
1647         snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1648         pr_info("Board name: %s\n", tmp);
1649         snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1650         pr_info("Board version: %s\n", tmp);
1652         if (!strncmp("A335BONE", config.name, 8)) {
1653                 daughter_brd_detected = false;
1654                 if(!strncmp("00A1", config.version, 4) ||
1655                    !strncmp("00A2", config.version, 4))
1656                         setup_beaglebone_old();
1657                 else
1658                         setup_beaglebone();
1659         } else {
1660                 /* only 6 characters of options string used for now */
1661                 snprintf(tmp, 7, "%s", config.opt);
1662                 pr_info("SKU: %s\n", tmp);
1664                 if (!strncmp("SKU#00", config.opt, 6))
1665                         setup_low_cost_evm();
1666                 else if (!strncmp("SKU#01", config.opt, 6))
1667                         setup_general_purpose_evm();
1668                 else if (!strncmp("SKU#02", config.opt, 6))
1669                         setup_ind_auto_motor_ctrl_evm();
1670                 else if (!strncmp("SKU#03", config.opt, 6))
1671                         setup_ip_phone_evm();
1672                 else
1673                         goto out;
1674         }
1675         /* Initialize cpsw after board detection is completed as board
1676          * information is required for configuring phy address and hence
1677          * should be call only after board detection
1678          */
1679         am33xx_cpsw_init(gigabit_enable);
1681         return;
1682 out:
1683         /*
1684          * If the EEPROM hasn't been programed or an incorrect header
1685          * or board name are read, assume this is an old beaglebone board
1686          * (< Rev A3)
1687          */
1688         pr_err("Could not detect any board, falling back to: "
1689                 "Beaglebone (< Rev A3) with no daughter card connected\n");
1690         daughter_brd_detected = false;
1691         setup_beaglebone_old();
1693         /* Initialize cpsw after board detection is completed as board
1694          * information is required for configuring phy address and hence
1695          * should be call only after board detection
1696          */
1698         am33xx_cpsw_init(gigabit_enable);
1701 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1702         .byte_len       = (256*1024) / 8,
1703         .page_size      = 64,
1704         .flags          = AT24_FLAG_ADDR16,
1705         .setup          = am335x_setup_daughter_board,
1706         .context        = (void *)NULL,
1707 };
1709 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1710         .byte_len       = (256*1024) / 8,
1711         .page_size      = 64,
1712         .flags          = AT24_FLAG_ADDR16,
1713         .setup          = am335x_evm_setup,
1714         .context        = (void *)NULL,
1715 };
1717 static struct regulator_init_data am335x_dummy = {
1718         .constraints.always_on  = true,
1719 };
1721 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
1722         REGULATOR_SUPPLY("vdd_mpu", NULL),
1723 };
1725 static struct regulator_init_data am335x_vdd1 = {
1726         .constraints = {
1727                 .min_uV                 = 600000,
1728                 .max_uV                 = 1500000,
1729                 .valid_modes_mask       = REGULATOR_MODE_NORMAL,
1730                 .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
1731                 .always_on              = 1,
1732         },
1733         .num_consumer_supplies  = ARRAY_SIZE(am335x_vdd1_supply),
1734         .consumer_supplies      = am335x_vdd1_supply,
1735 };
1737 static struct tps65910_board am335x_tps65910_info = {
1738         .tps65910_pmic_init_data[TPS65910_REG_VRTC]     = &am335x_dummy,
1739         .tps65910_pmic_init_data[TPS65910_REG_VIO]      = &am335x_dummy,
1740         .tps65910_pmic_init_data[TPS65910_REG_VDD1]     = &am335x_vdd1,
1741         .tps65910_pmic_init_data[TPS65910_REG_VDD2]     = &am335x_dummy,
1742         .tps65910_pmic_init_data[TPS65910_REG_VDD3]     = &am335x_dummy,
1743         .tps65910_pmic_init_data[TPS65910_REG_VDIG1]    = &am335x_dummy,
1744         .tps65910_pmic_init_data[TPS65910_REG_VDIG2]    = &am335x_dummy,
1745         .tps65910_pmic_init_data[TPS65910_REG_VPLL]     = &am335x_dummy,
1746         .tps65910_pmic_init_data[TPS65910_REG_VDAC]     = &am335x_dummy,
1747         .tps65910_pmic_init_data[TPS65910_REG_VAUX1]    = &am335x_dummy,
1748         .tps65910_pmic_init_data[TPS65910_REG_VAUX2]    = &am335x_dummy,
1749         .tps65910_pmic_init_data[TPS65910_REG_VAUX33]   = &am335x_dummy,
1750         .tps65910_pmic_init_data[TPS65910_REG_VMMC]     = &am335x_dummy,
1751 };
1753 /*
1754 * Daughter board Detection.
1755 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1756 * machine init, starting from daughter board and ending with baseboard.
1757 * Assumptions :
1758 *       1. probe for i2c devices are called in the order they are included in
1759 *          the below struct. Daughter boards eeprom are probed 1st. Baseboard
1760 *          eeprom probe is called last.
1761 */
1762 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1763         {
1764                 /* Daughter Board EEPROM */
1765                 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1766                 .platform_data  = &am335x_daughter_board_eeprom_info,
1767         },
1768         {
1769                 /* Baseboard board EEPROM */
1770                 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1771                 .platform_data  = &am335x_baseboard_eeprom_info,
1772         },
1773         {
1774                 I2C_BOARD_INFO("cpld_reg", 0x35),
1775         },
1776         {
1777                 I2C_BOARD_INFO("tlc59108", 0x40),
1778         },
1779         {
1780                 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
1781                 .platform_data  = &am335x_tps65910_info,
1782         },
1784 };
1786 static struct omap_musb_board_data musb_board_data = {
1787         .interface_type = MUSB_INTERFACE_ULPI,
1788         /*
1789          * mode[0:3] = USB0PORT's mode
1790          * mode[4:7] = USB1PORT's mode
1791          * AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
1792          */
1793         .mode           = (MUSB_HOST << 4) | MUSB_OTG,
1794         .power          = 500,
1795         .instances      = 1,
1796 };
1798 static int cpld_reg_probe(struct i2c_client *client,
1799             const struct i2c_device_id *id)
1801         cpld_client = client;
1802         return 0;
1805 static int __devexit cpld_reg_remove(struct i2c_client *client)
1807         cpld_client = NULL;
1808         return 0;
1811 static const struct i2c_device_id cpld_reg_id[] = {
1812         { "cpld_reg", 0 },
1813         { }
1814 };
1816 static struct i2c_driver cpld_reg_driver = {
1817         .driver = {
1818                 .name   = "cpld_reg",
1819         },
1820         .probe          = cpld_reg_probe,
1821         .remove         = cpld_reg_remove,
1822         .id_table       = cpld_reg_id,
1823 };
1825 static void evm_init_cpld(void)
1827         i2c_add_driver(&cpld_reg_driver);
1830 static void __init am335x_evm_i2c_init(void)
1832         /* Initially assume Low Cost EVM Config */
1833         am335x_evm_id = LOW_COST_EVM;
1835         evm_init_cpld();
1837         omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1838                                 ARRAY_SIZE(am335x_i2c_boardinfo));
1841 static struct resource am335x_rtc_resources[] = {
1842         {
1843                 .start          = AM33XX_RTC_BASE,
1844                 .end            = AM33XX_RTC_BASE + SZ_4K - 1,
1845                 .flags          = IORESOURCE_MEM,
1846         },
1847         { /* timer irq */
1848                 .start          = AM33XX_IRQ_RTC_TIMER,
1849                 .end            = AM33XX_IRQ_RTC_TIMER,
1850                 .flags          = IORESOURCE_IRQ,
1851         },
1852         { /* alarm irq */
1853                 .start          = AM33XX_IRQ_RTC_ALARM,
1854                 .end            = AM33XX_IRQ_RTC_ALARM,
1855                 .flags          = IORESOURCE_IRQ,
1856         },
1857 };
1859 static struct platform_device am335x_rtc_device = {
1860         .name           = "omap_rtc",
1861         .id             = -1,
1862         .num_resources  = ARRAY_SIZE(am335x_rtc_resources),
1863         .resource       = am335x_rtc_resources,
1864 };
1866 static int am335x_rtc_init(void)
1868         void __iomem *base;
1869         struct clk *clk;
1871         clk = clk_get(NULL, "rtc_fck");
1872         if (IS_ERR(clk)) {
1873                 pr_err("rtc : Failed to get RTC clock\n");
1874                 return -1;
1875         }
1877         if (clk_enable(clk)) {
1878                 pr_err("rtc: Clock Enable Failed\n");
1879                 return -1;
1880         }
1882         base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1884         if (WARN_ON(!base))
1885                 return -ENOMEM;
1887         /* Unlock the rtc's registers */
1888         __raw_writel(0x83e70b13, base + 0x6c);
1889         __raw_writel(0x95a4f1e0, base + 0x70);
1891         /*
1892          * Enable the 32K OSc
1893          * TODO: Need a better way to handle this
1894          * Since we want the clock to be running before mmc init
1895          * we need to do it before the rtc probe happens
1896          */
1897         __raw_writel(0x48, base + 0x54);
1899         iounmap(base);
1901         return  platform_device_register(&am335x_rtc_device);
1904 /* Enable clkout2 */
1905 static struct pinmux_config clkout2_pin_mux[] = {
1906         {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1907         {NULL, 0},
1908 };
1910 static void __init clkout2_enable(void)
1912         struct clk *ck_32;
1914         ck_32 = clk_get(NULL, "clkout2_ck");
1915         if (IS_ERR(ck_32)) {
1916                 pr_err("Cannot clk_get ck_32\n");
1917                 return;
1918         }
1920         clk_enable(ck_32);
1922         setup_pin_mux(clkout2_pin_mux);
1925 void __iomem * __init am33xx_get_mem_ctlr(void)
1927         void __iomem *am33xx_emif_base;
1929         am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1931         if (!am33xx_emif_base)
1932                 pr_warning("%s: Unable to map DDR2 controller", __func__);
1934         return am33xx_emif_base;
1937 static struct resource am33xx_cpuidle_resources[] = {
1938         {
1939                 .start          = AM33XX_EMIF0_BASE,
1940                 .end            = AM33XX_EMIF0_BASE + SZ_32K - 1,
1941                 .flags          = IORESOURCE_MEM,
1942         },
1943 };
1945 /* AM33XX devices support DDR2 power down */
1946 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1947         .ddr2_pdown     = 1,
1948 };
1950 static struct platform_device am33xx_cpuidle_device = {
1951         .name                   = "cpuidle-am33xx",
1952         .num_resources          = ARRAY_SIZE(am33xx_cpuidle_resources),
1953         .resource               = am33xx_cpuidle_resources,
1954         .dev = {
1955                 .platform_data  = &am33xx_cpuidle_pdata,
1956         },
1957 };
1959 static void __init am33xx_cpuidle_init(void)
1961         int ret;
1963         am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1965         ret = platform_device_register(&am33xx_cpuidle_device);
1967         if (ret)
1968                 pr_warning("AM33XX cpuidle registration failed\n");
1972 static void __init am335x_evm_init(void)
1974         am33xx_cpuidle_init();
1975         am33xx_mux_init(board_mux);
1976         omap_serial_init();
1977         am335x_rtc_init();
1978         clkout2_enable();
1979         am335x_evm_i2c_init();
1980         omap_sdrc_init(NULL, NULL);
1981         usb_musb_init(&musb_board_data);
1982         omap_board_config = am335x_evm_config;
1983         omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1984         /* Create an alias for icss clock */
1985         if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1986                 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1987         /* Create an alias for gfx/sgx clock */
1988         if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1989                 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1992 static void __init am335x_evm_map_io(void)
1994         omap2_set_globals_am33xx();
1995         omapam33xx_map_common_io();
1998 MACHINE_START(AM335XEVM, "am335xevm")
1999         /* Maintainer: Texas Instruments */
2000         .atag_offset    = 0x100,
2001         .map_io         = am335x_evm_map_io,
2002         .init_early     = am33xx_init_early,
2003         .init_irq       = ti81xx_init_irq,
2004         .handle_irq     = omap3_intc_handle_irq,
2005         .timer          = &omap3_am33xx_timer,
2006         .init_machine   = am335x_evm_init,
2007 MACHINE_END
2009 MACHINE_START(AM335XIAEVM, "am335xiaevm")
2010         /* Maintainer: Texas Instruments */
2011         .atag_offset    = 0x100,
2012         .map_io         = am335x_evm_map_io,
2013         .init_irq       = ti81xx_init_irq,
2014         .init_early     = am33xx_init_early,
2015         .timer          = &omap3_am33xx_timer,
2016         .init_machine   = am335x_evm_init,
2017 MACHINE_END