f8b93e0d2387fa0003342efde4f01497466b91d1
1 /*
2 * Code for AM335X EVM.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
36 /* LCD controller is similar to DA850 */
37 #include <video/da8xx-fb.h>
39 #include <mach/hardware.h>
40 #include <mach/board-am335xevm.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/map.h>
45 #include <asm/hardware/asp.h>
47 #include <plat/irqs.h>
48 #include <plat/board.h>
49 #include <plat/common.h>
50 #include <plat/lcdc.h>
51 #include <plat/usb.h>
52 #include <plat/mmc.h>
54 #include "board-flash.h"
55 #include "cpuidle33xx.h"
56 #include "mux.h"
57 #include "devices.h"
58 #include "hsmmc.h"
60 /* Convert GPIO signal to GPIO pin number */
61 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
63 /* TLK PHY IDs */
64 #define TLK110_PHY_ID 0x2000A201
65 #define TLK110_PHY_MASK 0xfffffff0
67 /* BBB PHY IDs */
68 #define BBB_PHY_ID 0x7c0f1
69 #define BBB_PHY_MASK 0xfffffffe
71 /* TLK110 PHY register offsets */
72 #define TLK110_COARSEGAIN_REG 0x00A3
73 #define TLK110_LPFHPF_REG 0x00AC
74 #define TLK110_SPAREANALOG_REG 0x00B9
75 #define TLK110_VRCR_REG 0x00D0
76 #define TLK110_SETFFE_REG 0x0107
77 #define TLK110_FTSP_REG 0x0154
78 #define TLK110_ALFATPIDL_REG 0x002A
79 #define TLK110_PSCOEF21_REG 0x0096
80 #define TLK110_PSCOEF3_REG 0x0097
81 #define TLK110_ALFAFACTOR1_REG 0x002C
82 #define TLK110_ALFAFACTOR2_REG 0x0023
83 #define TLK110_CFGPS_REG 0x0095
84 #define TLK110_FTSPTXGAIN_REG 0x0150
85 #define TLK110_SWSCR3_REG 0x000B
86 #define TLK110_SCFALLBACK_REG 0x0040
87 #define TLK110_PHYRCR_REG 0x001F
89 /* TLK110 register writes values */
90 #define TLK110_COARSEGAIN_VAL 0x0000
91 #define TLK110_LPFHPF_VAL 0x8000
92 #define TLK110_SPANALOG_VAL 0x0000
93 #define TLK110_VRCR_VAL 0x0008
94 #define TLK110_SETFFE_VAL 0x0605
95 #define TLK110_FTSP_VAL 0x0255
96 #define TLK110_ALFATPIDL_VAL 0x7998
97 #define TLK110_PSCOEF21_VAL 0x3A20
98 #define TLK110_PSCOEF3_VAL 0x003F
99 #define TLK110_ALFACTOR1_VAL 0xFF80
100 #define TLK110_ALFACTOR2_VAL 0x021C
101 #define TLK110_CFGPS_VAL 0x0000
102 #define TLK110_FTSPTXGAIN_VAL 0x6A88
103 #define TLK110_SWSCR3_VAL 0x0000
104 #define TLK110_SCFALLBACK_VAL 0xC11D
105 #define TLK110_PHYRCR_VAL 0x4000
107 #if defined(CONFIG_TLK110_WORKAROUND) || \
108 defined(CONFIG_TLK110_WORKAROUND_MODULE)
109 #define am335x_tlk110_phy_init()\
110 do { \
111 phy_register_fixup_for_uid(TLK110_PHY_ID,\
112 TLK110_PHY_MASK,\
113 am335x_tlk110_phy_fixup);\
114 } while (0);
115 #else
116 #define am335x_tlk110_phy_init() do { } while (0);
117 #endif
119 static const struct display_panel disp_panel = {
120 WVGA,
121 32,
122 32,
123 COLOR_ACTIVE,
124 };
126 static struct lcd_ctrl_config lcd_cfg = {
127 &disp_panel,
128 .ac_bias = 255,
129 .ac_bias_intrpt = 0,
130 .dma_burst_sz = 16,
131 .bpp = 32,
132 .fdd = 0x80,
133 .tft_alt_mode = 0,
134 .stn_565_mode = 0,
135 .mono_8bit_mode = 0,
136 .invert_line_clock = 1,
137 .invert_frm_clock = 1,
138 .sync_edge = 0,
139 .sync_ctrl = 1,
140 .raster_order = 0,
141 };
143 static void am335x_gpio_bl_ctrl(int val);
145 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
146 .manu_name = "ThreeFive",
147 .controller_data = &lcd_cfg,
148 .type = "TFC_S9700RTWV35TR_01B",
149 .panel_power_ctrl = am335x_gpio_bl_ctrl,
150 };
152 #include "common.h"
154 /* TSc controller */
155 #include <linux/input/ti_tscadc.h>
156 #include <linux/lis3lv02d.h>
158 static struct resource tsc_resources[] = {
159 [0] = {
160 .start = AM33XX_TSC_BASE,
161 .end = AM33XX_TSC_BASE + SZ_8K - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 [1] = {
165 .start = AM33XX_IRQ_ADC_GEN,
166 .end = AM33XX_IRQ_ADC_GEN,
167 .flags = IORESOURCE_IRQ,
168 },
169 };
171 static struct tsc_data am335x_touchscreen_data = {
172 .wires = 4,
173 .x_plate_resistance = 200,
174 };
176 static struct platform_device tsc_device = {
177 .name = "tsc",
178 .id = -1,
179 .dev = {
180 .platform_data = &am335x_touchscreen_data,
181 },
182 .num_resources = ARRAY_SIZE(tsc_resources),
183 .resource = tsc_resources,
184 };
186 static u8 am335x_iis_serializer_direction1[] = {
187 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
188 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
189 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
190 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
191 };
193 static struct snd_platform_data am335x_evm_snd_data1 = {
194 .tx_dma_offset = 0x46400000, /* McASP1 */
195 .rx_dma_offset = 0x46400000,
196 .op_mode = DAVINCI_MCASP_IIS_MODE,
197 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
198 .tdm_slots = 2,
199 .serial_dir = am335x_iis_serializer_direction1,
200 .asp_chan_q = EVENTQ_2,
201 .version = MCASP_VERSION_3,
202 .txnumevt = 1,
203 .rxnumevt = 1,
204 };
206 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
207 {
208 .mmc = 1,
209 .caps = MMC_CAP_4_BIT_DATA,
210 .gpio_cd = GPIO_TO_PIN(0, 6),
211 .gpio_wp = GPIO_TO_PIN(3, 18),
212 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
213 },
214 {
215 .mmc = 0, /* will be set at runtime */
216 },
217 {
218 .mmc = 0, /* will be set at runtime */
219 },
220 {} /* Terminator */
221 };
224 #ifdef CONFIG_OMAP_MUX
225 static struct omap_board_mux board_mux[] __initdata = {
226 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
227 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
228 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
229 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
230 { .reg_offset = OMAP_MUX_TERMINATOR },
231 };
232 #else
233 #define board_mux NULL
234 #endif
236 /* module pin mux structure */
237 struct pinmux_config {
238 const char *string_name; /* signal name format */
239 int val; /* Options for the mux register value */
240 };
242 struct evm_dev_cfg {
243 void (*device_init)(int evm_id, int profile);
245 /*
246 * If the device is required on both baseboard & daughter board (ex i2c),
247 * specify DEV_ON_BASEBOARD
248 */
249 #define DEV_ON_BASEBOARD 0
250 #define DEV_ON_DGHTR_BRD 1
251 u32 device_on;
253 u32 profile; /* Profiles (0-7) in which the module is present */
254 };
256 /* AM335X - CPLD Register Offsets */
257 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
258 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
259 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
260 #define CPLD_CFG_REG 0x10 /* Configuration Register */
262 static struct i2c_client *cpld_client;
263 static u32 am335x_evm_id;
264 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
265 };
267 /*
268 * EVM Config held in On-Board eeprom device.
269 *
270 * Header Format
271 *
272 * Name Size Contents
273 * (Bytes)
274 *-------------------------------------------------------------
275 * Header 4 0xAA, 0x55, 0x33, 0xEE
276 *
277 * Board Name 8 Name for board in ASCII.
278 * example "A33515BB" = "AM335X
279 Low Cost EVM board"
280 *
281 * Version 4 Hardware version code for board in
282 * in ASCII. "1.0A" = rev.01.0A
283 *
284 * Serial Number 12 Serial number of the board. This is a 12
285 * character string which is WWYY4P16nnnn, where
286 * WW = 2 digit week of the year of production
287 * YY = 2 digit year of production
288 * nnnn = incrementing board number
289 *
290 * Configuration option 32 Codes(TBD) to show the configuration
291 * setup on this board.
292 *
293 * Available 32720 Available space for other non-volatile
294 * data.
295 */
296 struct am335x_evm_eeprom_config {
297 u32 header;
298 u8 name[8];
299 char version[4];
300 u8 serial[12];
301 u8 opt[32];
302 };
304 static struct am335x_evm_eeprom_config config;
305 static bool daughter_brd_detected;
307 #define GP_EVM_REV_IS_1_0 0x1
308 #define GP_EVM_REV_IS_1_1A 0x2
309 #define GP_EVM_REV_IS_UNKNOWN 0xFF
310 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
311 unsigned int gigabit_enable = 1;
313 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
314 #define EEPROM_NO_OF_MAC_ADDR 3
315 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
317 #define AM335X_EEPROM_HEADER 0xEE3355AA
319 /* current profile if exists else PROFILE_0 on error */
320 static u32 am335x_get_profile_selection(void)
321 {
322 int val = 0;
324 if (!cpld_client)
325 /* error checking is not done in func's calling this routine.
326 so return profile 0 on error */
327 return 0;
329 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
330 if (val < 0)
331 return 0; /* default to Profile 0 on Error */
332 else
333 return val & 0x7;
334 }
336 /* Module pin mux for LCDC */
337 static struct pinmux_config lcdc_pin_mux[] = {
338 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
339 | AM33XX_PULL_DISA},
340 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
341 | AM33XX_PULL_DISA},
342 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
343 | AM33XX_PULL_DISA},
344 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
345 | AM33XX_PULL_DISA},
346 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
347 | AM33XX_PULL_DISA},
348 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
349 | AM33XX_PULL_DISA},
350 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
351 | AM33XX_PULL_DISA},
352 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
353 | AM33XX_PULL_DISA},
354 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
355 | AM33XX_PULL_DISA},
356 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
357 | AM33XX_PULL_DISA},
358 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
359 | AM33XX_PULL_DISA},
360 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
361 | AM33XX_PULL_DISA},
362 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
363 | AM33XX_PULL_DISA},
364 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
365 | AM33XX_PULL_DISA},
366 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
367 | AM33XX_PULL_DISA},
368 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
369 | AM33XX_PULL_DISA},
370 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
371 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
372 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
373 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
374 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
375 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
376 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
377 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
378 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
379 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
380 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
381 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
382 {NULL, 0},
383 };
385 static struct pinmux_config tsc_pin_mux[] = {
386 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
387 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
388 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
389 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
390 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
391 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
392 {NULL, 0},
393 };
395 /* Pin mux for nand flash module */
396 static struct pinmux_config nand_pin_mux[] = {
397 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
398 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
399 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
400 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
401 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
402 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
403 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
404 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
405 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
406 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
407 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
408 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
409 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
410 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
411 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
412 {NULL, 0},
413 };
415 /* Module pin mux for SPI fash */
416 static struct pinmux_config spi0_pin_mux[] = {
417 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
418 | AM33XX_INPUT_EN},
419 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
420 | AM33XX_INPUT_EN},
421 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
422 | AM33XX_INPUT_EN},
423 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
424 | AM33XX_INPUT_EN},
425 {NULL, 0},
426 };
428 /* Module pin mux for SPI flash */
429 static struct pinmux_config spi1_pin_mux[] = {
430 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
431 | AM33XX_INPUT_EN},
432 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
433 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
434 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
435 | AM33XX_INPUT_EN},
436 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
437 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
438 {NULL, 0},
439 };
441 /* Module pin mux for rgmii1 */
442 static struct pinmux_config rgmii1_pin_mux[] = {
443 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
444 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
445 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
446 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
447 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
448 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
449 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
450 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
451 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
452 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
453 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
454 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
455 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
456 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
457 {NULL, 0},
458 };
460 /* Module pin mux for rgmii2 */
461 static struct pinmux_config rgmii2_pin_mux[] = {
462 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
463 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
464 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
465 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
466 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
467 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
468 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
469 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
470 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
471 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
472 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
473 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
474 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
475 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
476 {NULL, 0},
477 };
479 /* Module pin mux for mii1 */
480 static struct pinmux_config mii1_pin_mux[] = {
481 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
482 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
483 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
484 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
485 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
486 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
487 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
488 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
489 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
490 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
491 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
492 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
493 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
494 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
495 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
496 {NULL, 0},
497 };
499 /* Module pin mux for rmii1 */
500 static struct pinmux_config rmii1_pin_mux[] = {
501 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
502 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
503 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
504 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
505 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
506 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
507 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
508 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
509 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
510 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
511 {NULL, 0},
512 };
514 static struct pinmux_config i2c1_pin_mux[] = {
515 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
516 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
517 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
518 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
519 {NULL, 0},
520 };
522 /* Module pin mux for mcasp1 */
523 static struct pinmux_config mcasp1_pin_mux[] = {
524 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
525 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
526 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
527 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
528 AM33XX_PIN_INPUT_PULLDOWN},
529 {NULL, 0},
530 };
533 /* Module pin mux for mmc0 */
534 static struct pinmux_config mmc0_pin_mux[] = {
535 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
536 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
537 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
538 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
539 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
540 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
541 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
542 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
543 {NULL, 0},
544 };
546 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
547 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
548 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
549 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
550 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
551 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
552 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
553 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
554 {NULL, 0},
555 };
557 /* Module pin mux for mmc1 */
558 static struct pinmux_config mmc1_pin_mux[] = {
559 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
560 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
561 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
562 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
563 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
564 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
565 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
566 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
567 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
568 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
569 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
570 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
571 {NULL, 0},
572 };
574 /* Module pin mux for uart3 */
575 static struct pinmux_config uart3_pin_mux[] = {
576 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
577 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
578 {NULL, 0},
579 };
581 static struct pinmux_config d_can_gp_pin_mux[] = {
582 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
583 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
584 {NULL, 0},
585 };
587 static struct pinmux_config d_can_ia_pin_mux[] = {
588 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
589 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
590 {NULL, 0},
591 };
593 /* Module pin mux for uart2 */
594 static struct pinmux_config uart2_pin_mux[] = {
595 {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
596 AM33XX_PIN_INPUT_PULLUP},
597 {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
598 AM33XX_PULL_DISA |
599 AM33XX_SLEWCTRL_SLOW},
600 {NULL, 0},
601 };
604 /*
605 * @pin_mux - single module pin-mux structure which defines pin-mux
606 * details for all its pins.
607 */
608 static void setup_pin_mux(struct pinmux_config *pin_mux)
609 {
610 int i;
612 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
613 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
615 }
617 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
619 /* pinmux for keypad device */
620 static struct pinmux_config matrix_keypad_pin_mux[] = {
621 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
622 {"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
623 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
624 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
625 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
626 {NULL, 0},
627 };
629 /* Keys mapping */
630 static const uint32_t am335x_evm_matrix_keys[] = {
631 KEY(0, 0, KEY_MENU),
632 KEY(1, 0, KEY_BACK),
633 KEY(2, 0, KEY_LEFT),
635 KEY(0, 1, KEY_RIGHT),
636 KEY(1, 1, KEY_ENTER),
637 KEY(2, 1, KEY_DOWN),
638 };
640 const struct matrix_keymap_data am335x_evm_keymap_data = {
641 .keymap = am335x_evm_matrix_keys,
642 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
643 };
645 static const unsigned int am335x_evm_keypad_row_gpios[] = {
646 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
647 };
649 static const unsigned int am335x_evm_keypad_col_gpios[] = {
650 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
651 };
653 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
654 .keymap_data = &am335x_evm_keymap_data,
655 .row_gpios = am335x_evm_keypad_row_gpios,
656 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
657 .col_gpios = am335x_evm_keypad_col_gpios,
658 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
659 .active_low = false,
660 .debounce_ms = 5,
661 .col_scan_delay_us = 2,
662 };
664 static struct platform_device am335x_evm_keyboard = {
665 .name = "matrix-keypad",
666 .id = -1,
667 .dev = {
668 .platform_data = &am335x_evm_keypad_platform_data,
669 },
670 };
672 static void matrix_keypad_init(int evm_id, int profile)
673 {
674 int err;
676 setup_pin_mux(matrix_keypad_pin_mux);
677 err = platform_device_register(&am335x_evm_keyboard);
678 if (err) {
679 pr_err("failed to register matrix keypad (2x3) device\n");
680 }
681 }
684 /* pinmux for keypad device */
685 static struct pinmux_config volume_keys_pin_mux[] = {
686 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
687 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
688 {NULL, 0},
689 };
691 /* Configure GPIOs for Volume Keys */
692 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
693 {
694 .code = KEY_VOLUMEUP,
695 .gpio = GPIO_TO_PIN(0, 2),
696 .active_low = true,
697 .desc = "volume-up",
698 .type = EV_KEY,
699 .wakeup = 1,
700 },
701 {
702 .code = KEY_VOLUMEDOWN,
703 .gpio = GPIO_TO_PIN(0, 3),
704 .active_low = true,
705 .desc = "volume-down",
706 .type = EV_KEY,
707 .wakeup = 1,
708 },
709 };
711 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
712 .buttons = am335x_evm_volume_gpio_buttons,
713 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
714 };
716 static struct platform_device am335x_evm_volume_keys = {
717 .name = "gpio-keys",
718 .id = -1,
719 .dev = {
720 .platform_data = &am335x_evm_volume_gpio_key_info,
721 },
722 };
724 static void volume_keys_init(int evm_id, int profile)
725 {
726 int err;
728 setup_pin_mux(volume_keys_pin_mux);
729 err = platform_device_register(&am335x_evm_volume_keys);
730 if (err)
731 pr_err("failed to register matrix keypad (2x3) device\n");
732 }
734 /*
735 * @evm_id - evm id which needs to be configured
736 * @dev_cfg - single evm structure which includes
737 * all module inits, pin-mux defines
738 * @profile - if present, else PROFILE_NONE
739 * @dghtr_brd_flg - Whether Daughter board is present or not
740 */
741 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
742 int profile)
743 {
744 int i;
746 /*
747 * Only General Purpose & Industrial Auto Motro Control
748 * EVM has profiles. So check if this evm has profile.
749 * If not, ignore the profile comparison
750 */
752 /*
753 * If the device is on baseboard, directly configure it. Else (device on
754 * Daughter board), check if the daughter card is detected.
755 */
756 if (profile == PROFILE_NONE) {
757 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
758 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
759 dev_cfg->device_init(evm_id, profile);
760 else if (daughter_brd_detected == true)
761 dev_cfg->device_init(evm_id, profile);
762 }
763 } else {
764 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
765 if (dev_cfg->profile & profile) {
766 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
767 dev_cfg->device_init(evm_id, profile);
768 else if (daughter_brd_detected == true)
769 dev_cfg->device_init(evm_id, profile);
770 }
771 }
772 }
773 }
775 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
777 /* pinmux for usb0 drvvbus */
778 static struct pinmux_config usb0_pin_mux[] = {
779 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
780 {NULL, 0},
781 };
783 /* pinmux for usb1 drvvbus */
784 static struct pinmux_config usb1_pin_mux[] = {
785 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
786 {NULL, 0},
787 };
789 /* pinmux for profibus */
790 static struct pinmux_config profibus_pin_mux[] = {
791 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
792 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
793 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
794 {NULL, 0},
795 };
797 /* Module pin mux for eCAP0 */
798 static struct pinmux_config ecap0_pin_mux[] = {
799 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
800 {NULL, 0},
801 };
803 static int backlight_enable;
805 #define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
806 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
808 struct wl12xx_platform_data am335xevm_wlan_data = {
809 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
810 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
811 };
813 /* Module pin mux for wlan and bluetooth */
814 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
815 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
816 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
817 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
818 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
819 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
820 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
821 {NULL, 0},
822 };
824 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
825 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
826 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
827 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
828 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
829 {NULL, 0},
830 };
832 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
833 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
834 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
835 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
836 {NULL, 0},
837 };
839 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
840 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
841 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
842 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
843 {NULL, 0},
844 };
846 static void enable_ecap0(int evm_id, int profile)
847 {
848 backlight_enable = true;
849 }
851 static void am335x_gpio_bl_ctrl(int val)
852 {
853 /* lcd backlight */
854 gpio_set_value(AM335X_LCD_BL_PIN, val);
855 }
857 static int __init ecap0_init(void)
858 {
859 int status = 0;
861 if (backlight_enable) {
862 setup_pin_mux(ecap0_pin_mux);
864 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
865 if (status < 0)
866 pr_warn("Failed to request gpio for LCD backlight\n");
868 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
869 }
870 return status;
871 }
872 late_initcall(ecap0_init);
874 static int __init conf_disp_pll(int rate)
875 {
876 struct clk *disp_pll;
877 int ret = -EINVAL;
879 disp_pll = clk_get(NULL, "dpll_disp_ck");
880 if (IS_ERR(disp_pll)) {
881 pr_err("Cannot clk_get disp_pll\n");
882 goto out;
883 }
885 ret = clk_set_rate(disp_pll, rate);
886 clk_put(disp_pll);
887 out:
888 return ret;
889 }
891 static void lcdc_init(int evm_id, int profile)
892 {
894 setup_pin_mux(lcdc_pin_mux);
896 if (conf_disp_pll(300000000)) {
897 pr_info("Failed configure display PLL, not attempting to"
898 "register LCDC\n");
899 return;
900 }
902 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
903 pr_info("Failed to register LCDC device\n");
904 return;
905 }
907 static void tsc_init(int evm_id, int profile)
908 {
909 int err;
911 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
912 am335x_touchscreen_data.analog_input = 1;
913 pr_info("TSC connected to beta GP EVM\n");
914 } else {
915 am335x_touchscreen_data.analog_input = 0;
916 pr_info("TSC connected to alpha GP EVM\n");
917 }
918 setup_pin_mux(tsc_pin_mux);
919 err = platform_device_register(&tsc_device);
920 if (err)
921 pr_err("failed to register touchscreen device\n");
922 }
924 static void rgmii1_init(int evm_id, int profile)
925 {
926 setup_pin_mux(rgmii1_pin_mux);
927 return;
928 }
930 static void rgmii2_init(int evm_id, int profile)
931 {
932 setup_pin_mux(rgmii2_pin_mux);
933 return;
934 }
936 static void mii1_init(int evm_id, int profile)
937 {
938 setup_pin_mux(mii1_pin_mux);
939 return;
940 }
942 static void rmii1_init(int evm_id, int profile)
943 {
944 setup_pin_mux(rmii1_pin_mux);
945 return;
946 }
948 static void usb0_init(int evm_id, int profile)
949 {
950 setup_pin_mux(usb0_pin_mux);
951 return;
952 }
954 static void usb1_init(int evm_id, int profile)
955 {
956 setup_pin_mux(usb1_pin_mux);
957 return;
958 }
960 /* setup uart3 */
961 static void uart3_init(int evm_id, int profile)
962 {
963 setup_pin_mux(uart3_pin_mux);
964 return;
965 }
967 /* setup uart2 */
968 static void uart2_init(int evm_id, int profile)
969 {
970 setup_pin_mux(uart2_pin_mux);
971 return;
972 }
974 /* NAND partition information */
975 static struct mtd_partition am335x_nand_partitions[] = {
976 /* All the partition sizes are listed in terms of NAND block size */
977 {
978 .name = "SPL",
979 .offset = 0, /* Offset = 0x0 */
980 .size = SZ_128K,
981 },
982 {
983 .name = "SPL.backup1",
984 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
985 .size = SZ_128K,
986 },
987 {
988 .name = "SPL.backup2",
989 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
990 .size = SZ_128K,
991 },
992 {
993 .name = "SPL.backup3",
994 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
995 .size = SZ_128K,
996 },
997 {
998 .name = "U-Boot",
999 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
1000 .size = 15 * SZ_128K,
1001 },
1002 {
1003 .name = "U-Boot Env",
1004 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
1005 .size = 1 * SZ_128K,
1006 },
1007 {
1008 .name = "Kernel",
1009 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
1010 .size = 40 * SZ_128K,
1011 },
1012 {
1013 .name = "File System",
1014 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
1015 .size = MTDPART_SIZ_FULL,
1016 },
1017 };
1019 /* SPI 0/1 Platform Data */
1020 /* SPI flash information */
1021 static struct mtd_partition am335x_spi_partitions[] = {
1022 /* All the partition sizes are listed in terms of erase size */
1023 {
1024 .name = "SPL",
1025 .offset = 0, /* Offset = 0x0 */
1026 .size = SZ_128K,
1027 },
1028 {
1029 .name = "U-Boot",
1030 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
1031 .size = 2 * SZ_128K,
1032 },
1033 {
1034 .name = "U-Boot Env",
1035 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
1036 .size = 2 * SZ_4K,
1037 },
1038 {
1039 .name = "Kernel",
1040 .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
1041 .size = 28 * SZ_128K,
1042 },
1043 {
1044 .name = "File System",
1045 .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
1046 .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
1047 }
1048 };
1050 static const struct flash_platform_data am335x_spi_flash = {
1051 .type = "w25q64",
1052 .name = "spi_flash",
1053 .parts = am335x_spi_partitions,
1054 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
1055 };
1057 /*
1058 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1059 * So setup Max speed to be less than that of Controller speed
1060 */
1061 static struct spi_board_info am335x_spi0_slave_info[] = {
1062 {
1063 .modalias = "m25p80",
1064 .platform_data = &am335x_spi_flash,
1065 .irq = -1,
1066 .max_speed_hz = 24000000,
1067 .bus_num = 1,
1068 .chip_select = 0,
1069 },
1070 };
1072 static struct spi_board_info am335x_spi1_slave_info[] = {
1073 {
1074 .modalias = "m25p80",
1075 .platform_data = &am335x_spi_flash,
1076 .irq = -1,
1077 .max_speed_hz = 12000000,
1078 .bus_num = 2,
1079 .chip_select = 0,
1080 },
1081 };
1083 static void evm_nand_init(int evm_id, int profile)
1084 {
1085 setup_pin_mux(nand_pin_mux);
1086 board_nand_init(am335x_nand_partitions,
1087 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1088 }
1090 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1091 .click_flags = LIS3_CLICK_SINGLE_X |
1092 LIS3_CLICK_SINGLE_Y |
1093 LIS3_CLICK_SINGLE_Z,
1094 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1095 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1096 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1097 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1098 .wakeup_thresh = 10,
1099 .click_thresh_x = 10,
1100 .click_thresh_y = 10,
1101 .click_thresh_z = 10,
1102 .g_range = 2,
1103 .st_min_limits[0] = 120,
1104 .st_min_limits[1] = 120,
1105 .st_min_limits[2] = 140,
1106 .st_max_limits[0] = 550,
1107 .st_max_limits[1] = 550,
1108 .st_max_limits[2] = 750,
1109 };
1111 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1112 {
1113 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1114 },
1115 {
1116 I2C_BOARD_INFO("lis331dlh", 0x18),
1117 .platform_data = &lis331dlh_pdata,
1118 },
1119 {
1120 I2C_BOARD_INFO("tsl2550", 0x39),
1121 },
1122 {
1123 I2C_BOARD_INFO("tmp275", 0x48),
1124 },
1125 };
1127 static void i2c1_init(int evm_id, int profile)
1128 {
1129 setup_pin_mux(i2c1_pin_mux);
1130 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1131 ARRAY_SIZE(am335x_i2c_boardinfo1));
1132 return;
1133 }
1135 /* Setup McASP 1 */
1136 static void mcasp1_init(int evm_id, int profile)
1137 {
1138 /* Configure McASP */
1139 setup_pin_mux(mcasp1_pin_mux);
1140 am335x_register_mcasp1(&am335x_evm_snd_data1);
1141 return;
1142 }
1144 static void mmc1_init(int evm_id, int profile)
1145 {
1146 setup_pin_mux(mmc1_pin_mux);
1148 am335x_mmc[1].mmc = 2;
1149 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1150 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1151 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1152 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1154 /* mmc will be initialized when mmc0_init is called */
1155 return;
1156 }
1158 static void mmc2_wl12xx_init(int evm_id, int profile)
1159 {
1160 setup_pin_mux(mmc2_wl12xx_pin_mux);
1162 am335x_mmc[1].mmc = 3;
1163 am335x_mmc[1].name = "wl1271";
1164 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1165 | MMC_PM_KEEP_POWER;
1166 am335x_mmc[1].nonremovable = true;
1167 am335x_mmc[1].gpio_cd = -EINVAL;
1168 am335x_mmc[1].gpio_wp = -EINVAL;
1169 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1171 /* mmc will be initialized when mmc0_init is called */
1172 return;
1173 }
1175 static void uart1_wl12xx_init(int evm_id, int profile)
1176 {
1177 setup_pin_mux(uart1_wl12xx_pin_mux);
1178 }
1180 static void wl12xx_bluetooth_enable(void)
1181 {
1182 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1183 "bt_en\n");
1184 if (status < 0)
1185 pr_err("Failed to request gpio for bt_enable");
1187 pr_info("Configure Bluetooth Enable pin...\n");
1188 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1189 }
1191 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1192 {
1193 if (on) {
1194 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1195 mdelay(70);
1196 }
1197 else
1198 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1200 return 0;
1201 }
1203 static void wl12xx_init(int evm_id, int profile)
1204 {
1205 struct device *dev;
1206 struct omap_mmc_platform_data *pdata;
1207 int ret;
1209 /* Register WLAN and BT enable pins based on the evm board revision */
1210 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1211 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1212 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1213 }
1214 else {
1215 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1216 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1217 }
1219 wl12xx_bluetooth_enable();
1221 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1222 pr_err("error setting wl12xx data\n");
1224 dev = am335x_mmc[1].dev;
1225 if (!dev) {
1226 pr_err("wl12xx mmc device initialization failed\n");
1227 goto out;
1228 }
1230 pdata = dev->platform_data;
1231 if (!pdata) {
1232 pr_err("Platfrom data of wl12xx device not set\n");
1233 goto out;
1234 }
1236 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1237 GPIOF_OUT_INIT_LOW, "wlan_en");
1238 if (ret) {
1239 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1240 goto out;
1241 }
1243 if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1244 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1245 else
1246 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1248 pdata->slots[0].set_power = wl12xx_set_power;
1249 out:
1250 return;
1251 }
1253 static void d_can_init(int evm_id, int profile)
1254 {
1255 switch (evm_id) {
1256 case IND_AUT_MTR_EVM:
1257 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1258 setup_pin_mux(d_can_ia_pin_mux);
1259 /* Instance Zero */
1260 am33xx_d_can_init(0);
1261 }
1262 break;
1263 case GEN_PURP_EVM:
1264 if (profile == PROFILE_1) {
1265 setup_pin_mux(d_can_gp_pin_mux);
1266 /* Instance One */
1267 am33xx_d_can_init(1);
1268 }
1269 break;
1270 default:
1271 break;
1272 }
1273 }
1275 static void mmc0_init(int evm_id, int profile)
1276 {
1277 setup_pin_mux(mmc0_pin_mux);
1279 omap2_hsmmc_init(am335x_mmc);
1280 return;
1281 }
1283 static void mmc0_no_cd_init(int evm_id, int profile)
1284 {
1285 setup_pin_mux(mmc0_no_cd_pin_mux);
1287 omap2_hsmmc_init(am335x_mmc);
1288 return;
1289 }
1292 /* setup spi0 */
1293 static void spi0_init(int evm_id, int profile)
1294 {
1295 setup_pin_mux(spi0_pin_mux);
1296 spi_register_board_info(am335x_spi0_slave_info,
1297 ARRAY_SIZE(am335x_spi0_slave_info));
1298 return;
1299 }
1301 /* setup spi1 */
1302 static void spi1_init(int evm_id, int profile)
1303 {
1304 setup_pin_mux(spi1_pin_mux);
1305 spi_register_board_info(am335x_spi1_slave_info,
1306 ARRAY_SIZE(am335x_spi1_slave_info));
1307 return;
1308 }
1311 static int beaglebone_phy_fixup(struct phy_device *phydev)
1312 {
1313 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1314 SUPPORTED_100baseT_Full);
1316 return 0;
1317 }
1319 #if defined(CONFIG_TLK110_WORKAROUND) || \
1320 defined(CONFIG_TLK110_WORKAROUND_MODULE)
1321 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1322 {
1323 unsigned int val;
1325 /* This is done as a workaround to support TLK110 rev1.0 phy */
1326 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1327 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1329 val = phy_read(phydev, TLK110_LPFHPF_REG);
1330 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1332 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1333 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1335 val = phy_read(phydev, TLK110_VRCR_REG);
1336 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1338 val = phy_read(phydev, TLK110_SETFFE_REG);
1339 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1341 val = phy_read(phydev, TLK110_FTSP_REG);
1342 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1344 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1345 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1347 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1348 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1350 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1351 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1353 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1354 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1356 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1357 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1359 val = phy_read(phydev, TLK110_CFGPS_REG);
1360 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1362 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1363 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1365 val = phy_read(phydev, TLK110_SWSCR3_REG);
1366 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1368 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1369 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1371 val = phy_read(phydev, TLK110_PHYRCR_REG);
1372 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1374 return 0;
1375 }
1376 #endif
1378 static void profibus_init(int evm_id, int profile)
1379 {
1380 setup_pin_mux(profibus_pin_mux);
1381 return;
1382 }
1384 /* Low-Cost EVM */
1385 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1386 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1387 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1388 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1389 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1390 {NULL, 0, 0},
1391 };
1393 /* General Purpose EVM */
1394 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1395 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1396 PROFILE_2 | PROFILE_7) },
1397 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1398 PROFILE_2 | PROFILE_7) },
1399 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1400 PROFILE_2 | PROFILE_7) },
1401 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1402 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1403 PROFILE_4 | PROFILE_6) },
1404 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1405 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1406 {evm_nand_init, DEV_ON_DGHTR_BRD,
1407 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1408 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1409 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1410 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1411 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1412 PROFILE_5)},
1413 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1414 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1415 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1416 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1417 PROFILE_5)},
1418 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1419 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
1420 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1421 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1422 {uart2_init, DEV_ON_DGHTR_BRD, PROFILE_3},
1423 {NULL, 0, 0},
1424 };
1426 /* Industrial Auto Motor Control EVM */
1427 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1428 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1429 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1430 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1431 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1432 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1433 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1434 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1435 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1436 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1437 {NULL, 0, 0},
1438 };
1440 /* IP-Phone EVM */
1441 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1442 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1443 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1444 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1445 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1446 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1447 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1448 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1449 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1450 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1451 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1452 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1453 {NULL, 0, 0},
1454 };
1456 /* Beaglebone < Rev A3 */
1457 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1458 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1459 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1460 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1461 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1462 {NULL, 0, 0},
1463 };
1465 /* Beaglebone Rev A3 and after */
1466 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1467 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1468 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1469 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1470 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1471 {NULL, 0, 0},
1472 };
1474 static void setup_low_cost_evm(void)
1475 {
1476 pr_info("The board is a AM335x Low Cost EVM.\n");
1478 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1479 }
1481 static void setup_general_purpose_evm(void)
1482 {
1483 u32 prof_sel = am335x_get_profile_selection();
1484 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1486 if (!strncmp("1.1A", config.version, 4)) {
1487 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1488 } else if (!strncmp("1.0", config.version, 3)) {
1489 gp_evm_revision = GP_EVM_REV_IS_1_0;
1490 } else {
1491 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1492 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1493 }
1495 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1496 gigabit_enable = 0;
1497 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1498 gigabit_enable = 1;
1500 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1501 }
1503 static void setup_ind_auto_motor_ctrl_evm(void)
1504 {
1505 u32 prof_sel = am335x_get_profile_selection();
1507 pr_info("The board is an industrial automation EVM in profile %d\n",
1508 prof_sel);
1510 /* Only Profile 0 is supported */
1511 if ((1L << prof_sel) != PROFILE_0) {
1512 pr_err("AM335X: Only Profile 0 is supported\n");
1513 pr_err("Assuming profile 0 & continuing\n");
1514 prof_sel = PROFILE_0;
1515 }
1517 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1518 PROFILE_0);
1520 /* Fillup global evmid */
1521 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1523 /* Initialize TLK110 PHY registers for phy version 1.0 */
1524 am335x_tlk110_phy_init();
1527 }
1529 static void setup_ip_phone_evm(void)
1530 {
1531 pr_info("The board is an IP phone EVM\n");
1533 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1534 }
1536 /* BeagleBone < Rev A3 */
1537 static void setup_beaglebone_old(void)
1538 {
1539 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1541 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1542 am335x_mmc[0].gpio_wp = -EINVAL;
1544 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1546 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1547 beaglebone_phy_fixup);
1548 }
1550 /* BeagleBone after Rev A3 */
1551 static void setup_beaglebone(void)
1552 {
1553 pr_info("The board is a AM335x Beaglebone.\n");
1555 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1556 am335x_mmc[0].gpio_wp = -EINVAL;
1558 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1559 }
1562 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1563 {
1564 u8 tmp;
1565 int ret;
1567 /*
1568 * try reading a byte from the EEPROM to see if it is
1569 * present. We could read a lot more, but that would
1570 * just slow the boot process and we have all the information
1571 * we need from the EEPROM on the base board anyway.
1572 */
1573 ret = m->read(m, &tmp, 0, sizeof(u8));
1574 if (ret == sizeof(u8)) {
1575 pr_info("Detected a daughter card on AM335x EVM..");
1576 daughter_brd_detected = true;
1577 } else {
1578 pr_info("No daughter card found\n");
1579 daughter_brd_detected = false;
1580 }
1581 }
1583 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1584 {
1585 int ret;
1586 char tmp[10];
1588 /* 1st get the MAC address from EEPROM */
1589 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1590 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1592 if (ret != sizeof(am335x_mac_addr)) {
1593 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1594 return;
1595 }
1597 /* Fillup global mac id */
1598 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1599 &am335x_mac_addr[1][0]);
1601 /* get board specific data */
1602 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1603 if (ret != sizeof(config)) {
1604 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1605 return;
1606 }
1608 if (config.header != AM335X_EEPROM_HEADER) {
1609 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1610 config.header, AM335X_EEPROM_HEADER);
1611 goto out;
1612 }
1614 if (strncmp("A335", config.name, 4)) {
1615 pr_err("Board %s doesn't look like an AM335x board\n",
1616 config.name);
1617 goto out;
1618 }
1620 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1621 pr_info("Board name: %s\n", tmp);
1622 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1623 pr_info("Board version: %s\n", tmp);
1625 if (!strncmp("A335BONE", config.name, 8)) {
1626 daughter_brd_detected = false;
1627 if(!strncmp("00A1", config.version, 4) ||
1628 !strncmp("00A2", config.version, 4))
1629 setup_beaglebone_old();
1630 else
1631 setup_beaglebone();
1632 } else {
1633 /* only 6 characters of options string used for now */
1634 snprintf(tmp, 7, "%s", config.opt);
1635 pr_info("SKU: %s\n", tmp);
1637 if (!strncmp("SKU#00", config.opt, 6))
1638 setup_low_cost_evm();
1639 else if (!strncmp("SKU#01", config.opt, 6))
1640 setup_general_purpose_evm();
1641 else if (!strncmp("SKU#02", config.opt, 6))
1642 setup_ind_auto_motor_ctrl_evm();
1643 else if (!strncmp("SKU#03", config.opt, 6))
1644 setup_ip_phone_evm();
1645 else
1646 goto out;
1647 }
1648 /* Initialize cpsw after board detection is completed as board
1649 * information is required for configuring phy address and hence
1650 * should be call only after board detection
1651 */
1652 am33xx_cpsw_init(gigabit_enable);
1654 return;
1655 out:
1656 /*
1657 * If the EEPROM hasn't been programed or an incorrect header
1658 * or board name are read, assume this is an old beaglebone board
1659 * (< Rev A3)
1660 */
1661 pr_err("Could not detect any board, falling back to: "
1662 "Beaglebone (< Rev A3) with no daughter card connected\n");
1663 daughter_brd_detected = false;
1664 setup_beaglebone_old();
1666 /* Initialize cpsw after board detection is completed as board
1667 * information is required for configuring phy address and hence
1668 * should be call only after board detection
1669 */
1671 am33xx_cpsw_init(gigabit_enable);
1672 }
1674 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1675 .byte_len = (256*1024) / 8,
1676 .page_size = 64,
1677 .flags = AT24_FLAG_ADDR16,
1678 .setup = am335x_setup_daughter_board,
1679 .context = (void *)NULL,
1680 };
1682 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1683 .byte_len = (256*1024) / 8,
1684 .page_size = 64,
1685 .flags = AT24_FLAG_ADDR16,
1686 .setup = am335x_evm_setup,
1687 .context = (void *)NULL,
1688 };
1690 /*
1691 * Daughter board Detection.
1692 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1693 * machine init, starting from daughter board and ending with baseboard.
1694 * Assumptions :
1695 * 1. probe for i2c devices are called in the order they are included in
1696 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
1697 * eeprom probe is called last.
1698 */
1699 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1700 {
1701 /* Daughter Board EEPROM */
1702 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1703 .platform_data = &am335x_daughter_board_eeprom_info,
1704 },
1705 {
1706 /* Baseboard board EEPROM */
1707 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1708 .platform_data = &am335x_baseboard_eeprom_info,
1709 },
1710 {
1711 I2C_BOARD_INFO("cpld_reg", 0x35),
1712 },
1713 {
1714 I2C_BOARD_INFO("tlc59108", 0x40),
1715 },
1717 };
1719 static struct omap_musb_board_data musb_board_data = {
1720 .interface_type = MUSB_INTERFACE_ULPI,
1721 /*
1722 * mode[0:3] = USB0PORT's mode
1723 * mode[4:7] = USB1PORT's mode
1724 * AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
1725 */
1726 .mode = (MUSB_HOST << 4) | MUSB_OTG,
1727 .power = 500,
1728 .instances = 1,
1729 };
1731 static int cpld_reg_probe(struct i2c_client *client,
1732 const struct i2c_device_id *id)
1733 {
1734 cpld_client = client;
1735 return 0;
1736 }
1738 static int __devexit cpld_reg_remove(struct i2c_client *client)
1739 {
1740 cpld_client = NULL;
1741 return 0;
1742 }
1744 static const struct i2c_device_id cpld_reg_id[] = {
1745 { "cpld_reg", 0 },
1746 { }
1747 };
1749 static struct i2c_driver cpld_reg_driver = {
1750 .driver = {
1751 .name = "cpld_reg",
1752 },
1753 .probe = cpld_reg_probe,
1754 .remove = cpld_reg_remove,
1755 .id_table = cpld_reg_id,
1756 };
1758 static void evm_init_cpld(void)
1759 {
1760 i2c_add_driver(&cpld_reg_driver);
1761 }
1763 static void __init am335x_evm_i2c_init(void)
1764 {
1765 /* Initially assume Low Cost EVM Config */
1766 am335x_evm_id = LOW_COST_EVM;
1768 evm_init_cpld();
1770 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1771 ARRAY_SIZE(am335x_i2c_boardinfo));
1772 }
1774 static struct resource am335x_rtc_resources[] = {
1775 {
1776 .start = AM33XX_RTC_BASE,
1777 .end = AM33XX_RTC_BASE + SZ_4K - 1,
1778 .flags = IORESOURCE_MEM,
1779 },
1780 { /* timer irq */
1781 .start = AM33XX_IRQ_RTC_TIMER,
1782 .end = AM33XX_IRQ_RTC_TIMER,
1783 .flags = IORESOURCE_IRQ,
1784 },
1785 { /* alarm irq */
1786 .start = AM33XX_IRQ_RTC_ALARM,
1787 .end = AM33XX_IRQ_RTC_ALARM,
1788 .flags = IORESOURCE_IRQ,
1789 },
1790 };
1792 static struct platform_device am335x_rtc_device = {
1793 .name = "omap_rtc",
1794 .id = -1,
1795 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
1796 .resource = am335x_rtc_resources,
1797 };
1799 static int am335x_rtc_init(void)
1800 {
1801 void __iomem *base;
1802 struct clk *clk;
1804 clk = clk_get(NULL, "rtc_fck");
1805 if (IS_ERR(clk)) {
1806 pr_err("rtc : Failed to get RTC clock\n");
1807 return -1;
1808 }
1810 if (clk_enable(clk)) {
1811 pr_err("rtc: Clock Enable Failed\n");
1812 return -1;
1813 }
1815 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1817 if (WARN_ON(!base))
1818 return -ENOMEM;
1820 /* Unlock the rtc's registers */
1821 __raw_writel(0x83e70b13, base + 0x6c);
1822 __raw_writel(0x95a4f1e0, base + 0x70);
1824 /*
1825 * Enable the 32K OSc
1826 * TODO: Need a better way to handle this
1827 * Since we want the clock to be running before mmc init
1828 * we need to do it before the rtc probe happens
1829 */
1830 __raw_writel(0x48, base + 0x54);
1832 iounmap(base);
1834 return platform_device_register(&am335x_rtc_device);
1835 }
1837 /* Enable clkout2 */
1838 static struct pinmux_config clkout2_pin_mux[] = {
1839 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1840 {NULL, 0},
1841 };
1843 static void __init clkout2_enable(void)
1844 {
1845 struct clk *ck_32;
1847 ck_32 = clk_get(NULL, "clkout2_ck");
1848 if (IS_ERR(ck_32)) {
1849 pr_err("Cannot clk_get ck_32\n");
1850 return;
1851 }
1853 clk_enable(ck_32);
1855 setup_pin_mux(clkout2_pin_mux);
1856 }
1858 void __iomem * __init am33xx_get_mem_ctlr(void)
1859 {
1860 void __iomem *am33xx_emif_base;
1862 am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1864 if (!am33xx_emif_base)
1865 pr_warning("%s: Unable to map DDR2 controller", __func__);
1867 return am33xx_emif_base;
1868 }
1870 static struct resource am33xx_cpuidle_resources[] = {
1871 {
1872 .start = AM33XX_EMIF0_BASE,
1873 .end = AM33XX_EMIF0_BASE + SZ_32K - 1,
1874 .flags = IORESOURCE_MEM,
1875 },
1876 };
1878 /* AM33XX devices support DDR2 power down */
1879 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1880 .ddr2_pdown = 1,
1881 };
1883 static struct platform_device am33xx_cpuidle_device = {
1884 .name = "cpuidle-am33xx",
1885 .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
1886 .resource = am33xx_cpuidle_resources,
1887 .dev = {
1888 .platform_data = &am33xx_cpuidle_pdata,
1889 },
1890 };
1892 static void __init am33xx_cpuidle_init(void)
1893 {
1894 int ret;
1896 am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1898 ret = platform_device_register(&am33xx_cpuidle_device);
1900 if (ret)
1901 pr_warning("AM33XX cpuidle registration failed\n");
1903 }
1905 static void __init am335x_evm_init(void)
1906 {
1907 am33xx_cpuidle_init();
1908 am33xx_mux_init(board_mux);
1909 omap_serial_init();
1910 am335x_rtc_init();
1911 clkout2_enable();
1912 am335x_evm_i2c_init();
1913 omap_sdrc_init(NULL, NULL);
1914 usb_musb_init(&musb_board_data);
1915 omap_board_config = am335x_evm_config;
1916 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1917 /* Create an alias for icss clock */
1918 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1919 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1920 /* Create an alias for gfx/sgx clock */
1921 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1922 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1923 }
1925 static void __init am335x_evm_map_io(void)
1926 {
1927 omap2_set_globals_am33xx();
1928 omapam33xx_map_common_io();
1929 }
1931 MACHINE_START(AM335XEVM, "am335xevm")
1932 /* Maintainer: Texas Instruments */
1933 .atag_offset = 0x100,
1934 .map_io = am335x_evm_map_io,
1935 .init_early = am33xx_init_early,
1936 .init_irq = ti81xx_init_irq,
1937 .handle_irq = omap3_intc_handle_irq,
1938 .timer = &omap3_am33xx_timer,
1939 .init_machine = am335x_evm_init,
1940 MACHINE_END
1942 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1943 /* Maintainer: Texas Instruments */
1944 .atag_offset = 0x100,
1945 .map_io = am335x_evm_map_io,
1946 .init_irq = ti81xx_init_irq,
1947 .init_early = am33xx_init_early,
1948 .timer = &omap3_am33xx_timer,
1949 .init_machine = am335x_evm_init,
1950 MACHINE_END