faeb35d6cae589ba2447d40c5f5f67b64040916d
1 /*
2 * Code for AM335X EVM.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
35 #include <linux/mfd/tps65910.h>
36 #include <linux/mfd/tps65217.h>
37 #include <linux/pwm_backlight.h>
38 #include <linux/input/ti_tscadc.h>
39 #include <linux/reboot.h>
41 /* LCD controller is similar to DA850 */
42 #include <video/da8xx-fb.h>
44 #include <mach/hardware.h>
45 #include <mach/board-am335xevm.h>
47 #include <asm/mach-types.h>
48 #include <asm/mach/arch.h>
49 #include <asm/mach/map.h>
50 #include <asm/hardware/asp.h>
52 #include <plat/irqs.h>
53 #include <plat/board.h>
54 #include <plat/common.h>
55 #include <plat/lcdc.h>
56 #include <plat/usb.h>
57 #include <plat/mmc.h>
58 #include <plat/emif.h>
59 #include <plat/nand.h>
61 #include "board-flash.h"
62 #include "cpuidle33xx.h"
63 #include "mux.h"
64 #include "devices.h"
65 #include "hsmmc.h"
67 /* Convert GPIO signal to GPIO pin number */
68 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
70 /* TLK PHY IDs */
71 #define TLK110_PHY_ID 0x2000A201
72 #define TLK110_PHY_MASK 0xfffffff0
74 /* BBB PHY IDs */
75 #define BBB_PHY_ID 0x7c0f1
76 #define BBB_PHY_MASK 0xfffffffe
78 /* TLK110 PHY register offsets */
79 #define TLK110_COARSEGAIN_REG 0x00A3
80 #define TLK110_LPFHPF_REG 0x00AC
81 #define TLK110_SPAREANALOG_REG 0x00B9
82 #define TLK110_VRCR_REG 0x00D0
83 #define TLK110_SETFFE_REG 0x0107
84 #define TLK110_FTSP_REG 0x0154
85 #define TLK110_ALFATPIDL_REG 0x002A
86 #define TLK110_PSCOEF21_REG 0x0096
87 #define TLK110_PSCOEF3_REG 0x0097
88 #define TLK110_ALFAFACTOR1_REG 0x002C
89 #define TLK110_ALFAFACTOR2_REG 0x0023
90 #define TLK110_CFGPS_REG 0x0095
91 #define TLK110_FTSPTXGAIN_REG 0x0150
92 #define TLK110_SWSCR3_REG 0x000B
93 #define TLK110_SCFALLBACK_REG 0x0040
94 #define TLK110_PHYRCR_REG 0x001F
96 /* TLK110 register writes values */
97 #define TLK110_COARSEGAIN_VAL 0x0000
98 #define TLK110_LPFHPF_VAL 0x8000
99 #define TLK110_SPANALOG_VAL 0x0000
100 #define TLK110_VRCR_VAL 0x0008
101 #define TLK110_SETFFE_VAL 0x0605
102 #define TLK110_FTSP_VAL 0x0255
103 #define TLK110_ALFATPIDL_VAL 0x7998
104 #define TLK110_PSCOEF21_VAL 0x3A20
105 #define TLK110_PSCOEF3_VAL 0x003F
106 #define TLK110_ALFACTOR1_VAL 0xFF80
107 #define TLK110_ALFACTOR2_VAL 0x021C
108 #define TLK110_CFGPS_VAL 0x0000
109 #define TLK110_FTSPTXGAIN_VAL 0x6A88
110 #define TLK110_SWSCR3_VAL 0x0000
111 #define TLK110_SCFALLBACK_VAL 0xC11D
112 #define TLK110_PHYRCR_VAL 0x4000
114 #if defined(CONFIG_TLK110_WORKAROUND) || \
115 defined(CONFIG_TLK110_WORKAROUND_MODULE)
116 #define am335x_tlk110_phy_init()\
117 do { \
118 phy_register_fixup_for_uid(TLK110_PHY_ID,\
119 TLK110_PHY_MASK,\
120 am335x_tlk110_phy_fixup);\
121 } while (0);
122 #else
123 #define am335x_tlk110_phy_init() do { } while (0);
124 #endif
126 static const struct display_panel disp_panel = {
127 WVGA,
128 32,
129 32,
130 COLOR_ACTIVE,
131 };
133 /* LCD backlight platform Data */
134 #define AM335X_BACKLIGHT_MAX_BRIGHTNESS 100
135 #define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS 100
136 #define AM335X_PWM_PERIOD_NANO_SECONDS (1000000 * 10)
138 #define PWM_DEVICE_ID "ecap.0"
140 static struct platform_pwm_backlight_data am335x_backlight_data = {
141 .pwm_id = PWM_DEVICE_ID,
142 .ch = -1,
143 .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
144 .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
145 .pwm_period_ns = AM335X_PWM_PERIOD_NANO_SECONDS,
146 };
148 static struct lcd_ctrl_config lcd_cfg = {
149 &disp_panel,
150 .ac_bias = 255,
151 .ac_bias_intrpt = 0,
152 .dma_burst_sz = 16,
153 .bpp = 32,
154 .fdd = 0x80,
155 .tft_alt_mode = 0,
156 .stn_565_mode = 0,
157 .mono_8bit_mode = 0,
158 .invert_line_clock = 1,
159 .invert_frm_clock = 1,
160 .sync_edge = 0,
161 .sync_ctrl = 1,
162 .raster_order = 0,
163 };
165 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
166 .manu_name = "ThreeFive",
167 .controller_data = &lcd_cfg,
168 .type = "TFC_S9700RTWV35TR_01B",
169 };
171 #include "common.h"
173 #include <linux/lis3lv02d.h>
175 /* TSc controller */
176 static struct tsc_data am335x_touchscreen_data = {
177 .wires = 4,
178 .x_plate_resistance = 200,
179 };
181 static u8 am335x_iis_serializer_direction1[] = {
182 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
183 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
184 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
185 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
186 };
188 static struct snd_platform_data am335x_evm_snd_data1 = {
189 .tx_dma_offset = 0x46400000, /* McASP1 */
190 .rx_dma_offset = 0x46400000,
191 .op_mode = DAVINCI_MCASP_IIS_MODE,
192 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
193 .tdm_slots = 2,
194 .serial_dir = am335x_iis_serializer_direction1,
195 .asp_chan_q = EVENTQ_2,
196 .version = MCASP_VERSION_3,
197 .txnumevt = 1,
198 .rxnumevt = 1,
199 };
201 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
202 {
203 .mmc = 1,
204 .caps = MMC_CAP_4_BIT_DATA,
205 .gpio_cd = GPIO_TO_PIN(0, 6),
206 .gpio_wp = GPIO_TO_PIN(3, 18),
207 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
208 },
209 {
210 .mmc = 0, /* will be set at runtime */
211 },
212 {
213 .mmc = 0, /* will be set at runtime */
214 },
215 {} /* Terminator */
216 };
219 #ifdef CONFIG_OMAP_MUX
220 static struct omap_board_mux board_mux[] __initdata = {
221 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
222 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
223 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
224 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
225 { .reg_offset = OMAP_MUX_TERMINATOR },
226 };
227 #else
228 #define board_mux NULL
229 #endif
231 /* module pin mux structure */
232 struct pinmux_config {
233 const char *string_name; /* signal name format */
234 int val; /* Options for the mux register value */
235 };
237 struct evm_dev_cfg {
238 void (*device_init)(int evm_id, int profile);
240 /*
241 * If the device is required on both baseboard & daughter board (ex i2c),
242 * specify DEV_ON_BASEBOARD
243 */
244 #define DEV_ON_BASEBOARD 0
245 #define DEV_ON_DGHTR_BRD 1
246 u32 device_on;
248 u32 profile; /* Profiles (0-7) in which the module is present */
249 };
251 /* AM335X - CPLD Register Offsets */
252 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
253 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
254 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
255 #define CPLD_CFG_REG 0x10 /* Configuration Register */
257 static struct i2c_client *cpld_client;
258 static u32 am335x_evm_id;
259 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
260 };
262 /*
263 * EVM Config held in On-Board eeprom device.
264 *
265 * Header Format
266 *
267 * Name Size Contents
268 * (Bytes)
269 *-------------------------------------------------------------
270 * Header 4 0xAA, 0x55, 0x33, 0xEE
271 *
272 * Board Name 8 Name for board in ASCII.
273 * example "A33515BB" = "AM335X
274 Low Cost EVM board"
275 *
276 * Version 4 Hardware version code for board in
277 * in ASCII. "1.0A" = rev.01.0A
278 *
279 * Serial Number 12 Serial number of the board. This is a 12
280 * character string which is WWYY4P16nnnn, where
281 * WW = 2 digit week of the year of production
282 * YY = 2 digit year of production
283 * nnnn = incrementing board number
284 *
285 * Configuration option 32 Codes(TBD) to show the configuration
286 * setup on this board.
287 *
288 * Available 32720 Available space for other non-volatile
289 * data.
290 */
291 struct am335x_evm_eeprom_config {
292 u32 header;
293 u8 name[8];
294 char version[4];
295 u8 serial[12];
296 u8 opt[32];
297 };
299 /*
300 * EVM Config held in daughter board eeprom device.
301 *
302 * Header Format
303 *
304 * Name Size Contents
305 * (Bytes)
306 *-------------------------------------------------------------
307 * Header 4 0xAA, 0x55, 0x33, 0xEE
308 *
309 * Board Name 8 Name for board in ASCII.
310 * example "A335GPBD" = "AM335x
311 * General Purpose Daughterboard"
312 *
313 * Version 4 Hardware version code for board in
314 * in ASCII. "1.0A" = rev.01.0A
315 * Serial Number 12 Serial number of the board. This is a 12
316 * character string which is: WWYY4P13nnnn, where
317 * WW = 2 digit week of the year of production
318 * YY = 2 digit year of production
319 * nnnn = incrementing board number
320 * Configuration Option 32 Codes to show the configuration
321 * setup on this board.
322 * CPLD Version 8 CPLD code version for board in ASCII
323 * "CPLD1.0A" = rev. 01.0A of the CPLD
324 * Available 32700 Available space for other non-volatile
325 * codes/data
326 */
328 struct am335x_eeprom_config1 {
329 u32 header;
330 u8 name[8];
331 char version[4];
332 u8 serial[12];
333 u8 opt[32];
334 u8 cpld_ver[8];
335 };
337 static struct am335x_evm_eeprom_config config;
338 static struct am335x_eeprom_config1 config1;
339 static bool daughter_brd_detected;
341 #define GP_EVM_REV_IS_1_0 0x1
342 #define GP_EVM_REV_IS_1_1A 0x2
343 #define GP_EVM_REV_IS_UNKNOWN 0xFF
344 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
346 #define CPLD_REV_1_0A 0x1
347 #define CPLD_REV_1_1A 0x2
348 #define CPLD_UNKNOWN 0xFF
349 static unsigned int cpld_version = CPLD_UNKNOWN;
351 unsigned int gigabit_enable = 1;
353 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
354 #define EEPROM_NO_OF_MAC_ADDR 3
355 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
357 #define AM335X_EEPROM_HEADER 0xEE3355AA
359 /* current profile if exists else PROFILE_0 on error */
360 static u32 am335x_get_profile_selection(void)
361 {
362 int val = 0;
364 if (!cpld_client)
365 /* error checking is not done in func's calling this routine.
366 so return profile 0 on error */
367 return 0;
369 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
370 if (val < 0)
371 return 0; /* default to Profile 0 on Error */
372 else
373 return val & 0x7;
374 }
376 static struct pinmux_config haptics_pin_mux[] = {
377 {"gpmc_ad9.ehrpwm2B", OMAP_MUX_MODE4 |
378 AM33XX_PIN_OUTPUT},
379 {NULL, 0},
380 };
382 /* Module pin mux for LCDC */
383 static struct pinmux_config lcdc_pin_mux[] = {
384 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
385 | AM33XX_PULL_DISA},
386 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
387 | AM33XX_PULL_DISA},
388 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
389 | AM33XX_PULL_DISA},
390 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
391 | AM33XX_PULL_DISA},
392 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
393 | AM33XX_PULL_DISA},
394 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
395 | AM33XX_PULL_DISA},
396 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
397 | AM33XX_PULL_DISA},
398 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
399 | AM33XX_PULL_DISA},
400 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
401 | AM33XX_PULL_DISA},
402 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
403 | AM33XX_PULL_DISA},
404 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
405 | AM33XX_PULL_DISA},
406 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
407 | AM33XX_PULL_DISA},
408 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
409 | AM33XX_PULL_DISA},
410 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
411 | AM33XX_PULL_DISA},
412 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
413 | AM33XX_PULL_DISA},
414 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
415 | AM33XX_PULL_DISA},
416 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
417 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
418 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
419 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
420 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
421 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
422 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
423 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
424 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
425 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
426 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
427 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
428 {NULL, 0},
429 };
431 static struct pinmux_config tsc_pin_mux[] = {
432 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
433 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
434 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
435 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
436 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
437 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
438 {NULL, 0},
439 };
441 /* Pin mux for nand flash module */
442 static struct pinmux_config nand_pin_mux[] = {
443 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
444 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
445 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
446 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
447 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
448 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
449 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
450 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
451 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
452 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
453 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
454 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
455 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
456 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
457 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
458 {NULL, 0},
459 };
461 /* Module pin mux for SPI fash */
462 static struct pinmux_config spi0_pin_mux[] = {
463 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
464 | AM33XX_INPUT_EN},
465 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
466 | AM33XX_INPUT_EN},
467 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
468 | AM33XX_INPUT_EN},
469 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
470 | AM33XX_INPUT_EN},
471 {NULL, 0},
472 };
474 /* Module pin mux for SPI flash */
475 static struct pinmux_config spi1_pin_mux[] = {
476 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
477 | AM33XX_INPUT_EN},
478 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
479 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
480 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
481 | AM33XX_INPUT_EN},
482 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
483 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
484 {NULL, 0},
485 };
487 /* Module pin mux for rgmii1 */
488 static struct pinmux_config rgmii1_pin_mux[] = {
489 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
490 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
491 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
492 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
493 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
494 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
495 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
496 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
497 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
498 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
499 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
500 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
501 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
502 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
503 {NULL, 0},
504 };
506 /* Module pin mux for rgmii2 */
507 static struct pinmux_config rgmii2_pin_mux[] = {
508 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
509 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
510 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
511 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
512 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
513 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
514 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
515 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
516 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
517 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
518 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
519 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
520 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
521 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
522 {NULL, 0},
523 };
525 /* Module pin mux for mii1 */
526 static struct pinmux_config mii1_pin_mux[] = {
527 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
528 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
529 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
530 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
531 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
532 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
533 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
534 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
535 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
536 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
537 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
538 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
539 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
540 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
541 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
542 {NULL, 0},
543 };
545 /* Module pin mux for rmii1 */
546 static struct pinmux_config rmii1_pin_mux[] = {
547 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
548 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
549 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
550 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
551 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
552 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
553 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
554 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
555 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
556 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
557 {NULL, 0},
558 };
560 static struct pinmux_config i2c1_pin_mux[] = {
561 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
562 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
563 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
564 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
565 {NULL, 0},
566 };
568 static struct pinmux_config i2c2_pin_mux[] = {
569 {"uart1_ctsn.i2c2_sda", OMAP_MUX_MODE3 | AM33XX_SLEWCTRL_SLOW |
570 AM33XX_PULL_UP | AM33XX_INPUT_EN},
571 {"uart1_rtsn.i2c2_scl", OMAP_MUX_MODE3 | AM33XX_SLEWCTRL_SLOW |
572 AM33XX_PULL_UP | AM33XX_INPUT_EN},
573 {NULL, 0},
574 };
576 /* Module pin mux for mcasp1 */
577 static struct pinmux_config mcasp1_pin_mux[] = {
578 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
579 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
580 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
581 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
582 AM33XX_PIN_INPUT_PULLDOWN},
583 {NULL, 0},
584 };
587 /* Module pin mux for mmc0 */
588 static struct pinmux_config mmc0_pin_mux[] = {
589 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
590 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
591 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
592 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
593 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
594 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
595 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
596 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
597 {NULL, 0},
598 };
600 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
601 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
602 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
603 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
604 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
605 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
606 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
607 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
608 {NULL, 0},
609 };
611 /* Module pin mux for mmc1 */
612 static struct pinmux_config mmc1_pin_mux[] = {
613 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
614 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
615 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
616 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
617 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
618 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
619 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
620 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
621 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
622 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
623 {"gpmc_csn0.gpio1_29", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
624 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
625 {NULL, 0},
626 };
628 /* Module pin mux for uart3 */
629 static struct pinmux_config uart3_pin_mux[] = {
630 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
631 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
632 {NULL, 0},
633 };
635 static struct pinmux_config d_can_gp_pin_mux[] = {
636 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
637 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
638 {NULL, 0},
639 };
641 static struct pinmux_config d_can_ia_pin_mux[] = {
642 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
643 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
644 {NULL, 0},
645 };
647 /* Module pin mux for uart2 */
648 static struct pinmux_config uart2_pin_mux[] = {
649 {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
650 AM33XX_PIN_INPUT_PULLUP},
651 {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
652 AM33XX_PULL_DISA |
653 AM33XX_SLEWCTRL_SLOW},
654 {NULL, 0},
655 };
658 /*
659 * @pin_mux - single module pin-mux structure which defines pin-mux
660 * details for all its pins.
661 */
662 static void setup_pin_mux(struct pinmux_config *pin_mux)
663 {
664 int i;
666 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
667 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
669 }
671 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
673 /* pinmux for keypad device */
674 static struct pinmux_config matrix_keypad_pin_mux[] = {
675 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
676 {"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
677 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
678 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
679 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
680 {NULL, 0},
681 };
683 /* Keys mapping */
684 static const uint32_t am335x_evm_matrix_keys[] = {
685 KEY(0, 0, KEY_MENU),
686 KEY(1, 0, KEY_BACK),
687 KEY(2, 0, KEY_LEFT),
689 KEY(0, 1, KEY_RIGHT),
690 KEY(1, 1, KEY_ENTER),
691 KEY(2, 1, KEY_DOWN),
692 };
694 const struct matrix_keymap_data am335x_evm_keymap_data = {
695 .keymap = am335x_evm_matrix_keys,
696 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
697 };
699 static const unsigned int am335x_evm_keypad_row_gpios[] = {
700 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
701 };
703 static const unsigned int am335x_evm_keypad_col_gpios[] = {
704 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
705 };
707 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
708 .keymap_data = &am335x_evm_keymap_data,
709 .row_gpios = am335x_evm_keypad_row_gpios,
710 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
711 .col_gpios = am335x_evm_keypad_col_gpios,
712 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
713 .active_low = false,
714 .debounce_ms = 5,
715 .col_scan_delay_us = 2,
716 };
718 static struct platform_device am335x_evm_keyboard = {
719 .name = "matrix-keypad",
720 .id = -1,
721 .dev = {
722 .platform_data = &am335x_evm_keypad_platform_data,
723 },
724 };
726 static void matrix_keypad_init(int evm_id, int profile)
727 {
728 int err;
730 setup_pin_mux(matrix_keypad_pin_mux);
731 err = platform_device_register(&am335x_evm_keyboard);
732 if (err) {
733 pr_err("failed to register matrix keypad (2x3) device\n");
734 }
735 }
738 /* pinmux for keypad device */
739 static struct pinmux_config volume_keys_pin_mux[] = {
740 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
741 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
742 {NULL, 0},
743 };
745 /* Configure GPIOs for Volume Keys */
746 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
747 {
748 .code = KEY_VOLUMEUP,
749 .gpio = GPIO_TO_PIN(0, 2),
750 .active_low = true,
751 .desc = "volume-up",
752 .type = EV_KEY,
753 .wakeup = 1,
754 },
755 {
756 .code = KEY_VOLUMEDOWN,
757 .gpio = GPIO_TO_PIN(0, 3),
758 .active_low = true,
759 .desc = "volume-down",
760 .type = EV_KEY,
761 .wakeup = 1,
762 },
763 };
765 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
766 .buttons = am335x_evm_volume_gpio_buttons,
767 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
768 };
770 static struct platform_device am335x_evm_volume_keys = {
771 .name = "gpio-keys",
772 .id = -1,
773 .dev = {
774 .platform_data = &am335x_evm_volume_gpio_key_info,
775 },
776 };
778 static void volume_keys_init(int evm_id, int profile)
779 {
780 int err;
782 setup_pin_mux(volume_keys_pin_mux);
783 err = platform_device_register(&am335x_evm_volume_keys);
784 if (err)
785 pr_err("failed to register matrix keypad (2x3) device\n");
786 }
788 /*
789 * @evm_id - evm id which needs to be configured
790 * @dev_cfg - single evm structure which includes
791 * all module inits, pin-mux defines
792 * @profile - if present, else PROFILE_NONE
793 * @dghtr_brd_flg - Whether Daughter board is present or not
794 */
795 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
796 int profile)
797 {
798 int i;
800 /*
801 * Only General Purpose & Industrial Auto Motro Control
802 * EVM has profiles. So check if this evm has profile.
803 * If not, ignore the profile comparison
804 */
806 /*
807 * If the device is on baseboard, directly configure it. Else (device on
808 * Daughter board), check if the daughter card is detected.
809 */
810 if (profile == PROFILE_NONE) {
811 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
812 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
813 dev_cfg->device_init(evm_id, profile);
814 else if (daughter_brd_detected == true)
815 dev_cfg->device_init(evm_id, profile);
816 }
817 } else {
818 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
819 if (dev_cfg->profile & profile) {
820 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
821 dev_cfg->device_init(evm_id, profile);
822 else if (daughter_brd_detected == true)
823 dev_cfg->device_init(evm_id, profile);
824 }
825 }
826 }
827 }
830 /* pinmux for usb0 drvvbus */
831 static struct pinmux_config usb0_pin_mux[] = {
832 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
833 {NULL, 0},
834 };
836 /* pinmux for usb1 drvvbus */
837 static struct pinmux_config usb1_pin_mux[] = {
838 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
839 {NULL, 0},
840 };
842 /* pinmux for profibus */
843 static struct pinmux_config profibus_pin_mux[] = {
844 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
845 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
846 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
847 {NULL, 0},
848 };
850 /* Module pin mux for eCAP0 */
851 static struct pinmux_config ecap0_pin_mux[] = {
852 {"ecap0_in_pwm0_out.ecap0_in_pwm0_out",
853 OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
854 {NULL, 0},
855 };
857 static int backlight_enable;
859 #define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
860 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
862 struct wl12xx_platform_data am335xevm_wlan_data = {
863 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
864 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
865 };
867 /* Module pin mux for wlan and bluetooth */
868 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
869 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
870 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
871 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
872 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
873 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
874 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
875 {NULL, 0},
876 };
878 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
879 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
880 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
881 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
882 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
883 {NULL, 0},
884 };
886 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
887 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
888 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
889 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
890 {NULL, 0},
891 };
893 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
894 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
895 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
896 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
897 {NULL, 0},
898 };
900 static void enable_ecap0(int evm_id, int profile)
901 {
902 backlight_enable = true;
903 }
905 /* Setup pwm-backlight */
906 static struct platform_device am335x_backlight = {
907 .name = "pwm-backlight",
908 .id = -1,
909 .dev = {
910 .platform_data = &am335x_backlight_data,
911 }
912 };
914 static int __init ecap0_init(void)
915 {
916 int status = 0;
918 if (backlight_enable) {
919 setup_pin_mux(ecap0_pin_mux);
920 platform_device_register(&am335x_backlight);
921 }
922 return status;
923 }
924 late_initcall(ecap0_init);
926 static int __init conf_disp_pll(int rate)
927 {
928 struct clk *disp_pll;
929 int ret = -EINVAL;
931 disp_pll = clk_get(NULL, "dpll_disp_ck");
932 if (IS_ERR(disp_pll)) {
933 pr_err("Cannot clk_get disp_pll\n");
934 goto out;
935 }
937 ret = clk_set_rate(disp_pll, rate);
938 clk_put(disp_pll);
939 out:
940 return ret;
941 }
943 static void lcdc_init(int evm_id, int profile)
944 {
946 setup_pin_mux(lcdc_pin_mux);
948 if (conf_disp_pll(300000000)) {
949 pr_info("Failed configure display PLL, not attempting to"
950 "register LCDC\n");
951 return;
952 }
954 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
955 pr_info("Failed to register LCDC device\n");
956 return;
957 }
959 static void tsc_init(int evm_id, int profile)
960 {
961 int err;
963 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
964 am335x_touchscreen_data.analog_input = 1;
965 pr_info("TSC connected to beta GP EVM\n");
966 } else {
967 am335x_touchscreen_data.analog_input = 0;
968 pr_info("TSC connected to alpha GP EVM\n");
969 }
970 setup_pin_mux(tsc_pin_mux);
972 err = am33xx_register_tsc(&am335x_touchscreen_data);
973 if (err)
974 pr_err("failed to register touchscreen device\n");
975 }
977 static void rgmii1_init(int evm_id, int profile)
978 {
979 setup_pin_mux(rgmii1_pin_mux);
980 return;
981 }
983 static void rgmii2_init(int evm_id, int profile)
984 {
985 setup_pin_mux(rgmii2_pin_mux);
986 return;
987 }
989 static void mii1_init(int evm_id, int profile)
990 {
991 setup_pin_mux(mii1_pin_mux);
992 return;
993 }
995 static void rmii1_init(int evm_id, int profile)
996 {
997 setup_pin_mux(rmii1_pin_mux);
998 return;
999 }
1001 static void usb0_init(int evm_id, int profile)
1002 {
1003 setup_pin_mux(usb0_pin_mux);
1004 return;
1005 }
1007 static void usb1_init(int evm_id, int profile)
1008 {
1009 setup_pin_mux(usb1_pin_mux);
1010 return;
1011 }
1013 /* setup uart3 */
1014 static void uart3_init(int evm_id, int profile)
1015 {
1016 setup_pin_mux(uart3_pin_mux);
1017 return;
1018 }
1020 /* setup uart2 */
1021 static void uart2_init(int evm_id, int profile)
1022 {
1023 setup_pin_mux(uart2_pin_mux);
1024 return;
1025 }
1027 /* setup haptics */
1028 #define HAPTICS_MAX_FREQ (250)
1030 static void haptics_init(int evm_id, int profile)
1031 {
1032 setup_pin_mux(haptics_pin_mux);
1033 register_ehrpwm(HAPTICS_MAX_FREQ);
1034 return;
1035 }
1037 /* NAND partition information */
1038 static struct mtd_partition am335x_nand_partitions[] = {
1039 /* All the partition sizes are listed in terms of NAND block size */
1040 {
1041 .name = "SPL",
1042 .offset = 0, /* Offset = 0x0 */
1043 .size = SZ_128K,
1044 .mask_flags = MTD_WRITEABLE, /* force read-only */
1045 },
1046 {
1047 .name = "SPL.backup1",
1048 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
1049 .size = SZ_128K,
1050 .mask_flags = MTD_WRITEABLE, /* force read-only */
1051 },
1052 {
1053 .name = "SPL.backup2",
1054 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
1055 .size = SZ_128K,
1056 .mask_flags = MTD_WRITEABLE, /* force read-only */
1057 },
1058 {
1059 .name = "SPL.backup3",
1060 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
1061 .size = SZ_128K,
1062 .mask_flags = MTD_WRITEABLE, /* force read-only */
1063 },
1064 {
1065 .name = "U-Boot",
1066 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
1067 .size = 15 * SZ_128K,
1068 .mask_flags = MTD_WRITEABLE, /* force read-only */
1069 },
1070 {
1071 .name = "U-Boot Env",
1072 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
1073 .size = 1 * SZ_128K,
1074 },
1075 {
1076 .name = "Kernel",
1077 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
1078 .size = 40 * SZ_128K,
1079 },
1080 {
1081 .name = "File System",
1082 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
1083 .size = MTDPART_SIZ_FULL,
1084 },
1085 };
1087 /* SPI 0/1 Platform Data */
1088 /* SPI flash information */
1089 static struct mtd_partition am335x_spi_partitions[] = {
1090 /* All the partition sizes are listed in terms of erase size */
1091 {
1092 .name = "SPL",
1093 .offset = 0, /* Offset = 0x0 */
1094 .size = SZ_128K,
1095 },
1096 {
1097 .name = "U-Boot",
1098 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
1099 .size = 2 * SZ_128K,
1100 },
1101 {
1102 .name = "U-Boot Env",
1103 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
1104 .size = 2 * SZ_4K,
1105 },
1106 {
1107 .name = "Kernel",
1108 .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
1109 .size = 28 * SZ_128K,
1110 },
1111 {
1112 .name = "File System",
1113 .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
1114 .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
1115 }
1116 };
1118 static const struct flash_platform_data am335x_spi_flash = {
1119 .type = "w25q64",
1120 .name = "spi_flash",
1121 .parts = am335x_spi_partitions,
1122 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
1123 };
1125 /*
1126 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1127 * So setup Max speed to be less than that of Controller speed
1128 */
1129 static struct spi_board_info am335x_spi0_slave_info[] = {
1130 {
1131 .modalias = "m25p80",
1132 .platform_data = &am335x_spi_flash,
1133 .irq = -1,
1134 .max_speed_hz = 24000000,
1135 .bus_num = 1,
1136 .chip_select = 0,
1137 },
1138 };
1140 static struct spi_board_info am335x_spi1_slave_info[] = {
1141 {
1142 .modalias = "m25p80",
1143 .platform_data = &am335x_spi_flash,
1144 .irq = -1,
1145 .max_speed_hz = 12000000,
1146 .bus_num = 2,
1147 .chip_select = 0,
1148 },
1149 };
1151 static struct gpmc_timings am335x_nand_timings = {
1152 .sync_clk = 0,
1154 .cs_on = 0,
1155 .cs_rd_off = 44,
1156 .cs_wr_off = 44,
1158 .adv_on = 6,
1159 .adv_rd_off = 34,
1160 .adv_wr_off = 44,
1161 .we_off = 40,
1162 .oe_off = 54,
1164 .access = 64,
1165 .rd_cycle = 82,
1166 .wr_cycle = 82,
1168 .wr_access = 40,
1169 .wr_data_mux_bus = 0,
1170 };
1172 static void evm_nand_init(int evm_id, int profile)
1173 {
1174 struct omap_nand_platform_data *pdata;
1175 struct gpmc_devices_info gpmc_device[2] = {
1176 { NULL, 0 },
1177 { NULL, 0 },
1178 };
1180 setup_pin_mux(nand_pin_mux);
1181 pdata = omap_nand_init(am335x_nand_partitions,
1182 ARRAY_SIZE(am335x_nand_partitions), 0, 0,
1183 &am335x_nand_timings);
1184 pdata->ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
1185 pdata->elm_used = true;
1186 gpmc_device[0].pdata = pdata;
1187 gpmc_device[0].flag = GPMC_DEVICE_NAND;
1189 omap_init_gpmc(gpmc_device, sizeof(gpmc_device));
1190 }
1192 /* TPS65217 voltage regulator support */
1194 /* 1.8V */
1195 static struct regulator_consumer_supply tps65217_dcdc1_consumers[] = {
1196 {
1197 .supply = "vdds_osc",
1198 },
1199 {
1200 .supply = "vdds_pll_ddr",
1201 },
1202 {
1203 .supply = "vdds_pll_mpu",
1204 },
1205 {
1206 .supply = "vdds_pll_core_lcd",
1207 },
1208 {
1209 .supply = "vdds_sram_mpu_bb",
1210 },
1211 {
1212 .supply = "vdds_sram_core_bg",
1213 },
1214 {
1215 .supply = "vdda_usb0_1p8v",
1216 },
1217 {
1218 .supply = "vdds_ddr",
1219 },
1220 {
1221 .supply = "vdds",
1222 },
1223 {
1224 .supply = "vdds_hvx_1p8v",
1225 },
1226 {
1227 .supply = "vdda_adc",
1228 },
1229 {
1230 .supply = "ddr2",
1231 },
1232 };
1234 /* 1.1V */
1235 static struct regulator_consumer_supply tps65217_dcdc2_consumers[] = {
1236 {
1237 .supply = "vdd_mpu",
1238 },
1239 };
1241 /* 1.1V */
1242 static struct regulator_consumer_supply tps65217_dcdc3_consumers[] = {
1243 {
1244 .supply = "vdd_core",
1245 },
1246 };
1248 /* 1.8V LDO */
1249 static struct regulator_consumer_supply tps65217_ldo1_consumers[] = {
1250 {
1251 .supply = "vdds_rtc",
1252 },
1253 };
1255 /* 3.3V LDO */
1256 static struct regulator_consumer_supply tps65217_ldo2_consumers[] = {
1257 {
1258 .supply = "vdds_any_pn",
1259 },
1260 };
1262 /* 3.3V LDO */
1263 static struct regulator_consumer_supply tps65217_ldo3_consumers[] = {
1264 {
1265 .supply = "vdds_hvx_ldo3_3p3v",
1266 },
1267 {
1268 .supply = "vdda_usb0_3p3v",
1269 },
1270 };
1272 /* 3.3V LDO */
1273 static struct regulator_consumer_supply tps65217_ldo4_consumers[] = {
1274 {
1275 .supply = "vdds_hvx_ldo4_3p3v",
1276 },
1277 };
1279 static struct regulator_init_data tps65217_regulator_data[] = {
1280 /* dcdc1 */
1281 {
1282 .constraints = {
1283 .min_uV = 900000,
1284 .max_uV = 1800000,
1285 .boot_on = 1,
1286 .always_on = 1,
1287 },
1288 .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc1_consumers),
1289 .consumer_supplies = tps65217_dcdc1_consumers,
1290 },
1292 /* dcdc2 */
1293 {
1294 .constraints = {
1295 .min_uV = 900000,
1296 .max_uV = 3300000,
1297 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1298 REGULATOR_CHANGE_STATUS),
1299 .boot_on = 1,
1300 .always_on = 1,
1301 },
1302 .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc2_consumers),
1303 .consumer_supplies = tps65217_dcdc2_consumers,
1304 },
1306 /* dcdc3 */
1307 {
1308 .constraints = {
1309 .min_uV = 900000,
1310 .max_uV = 1500000,
1311 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1312 REGULATOR_CHANGE_STATUS),
1313 .boot_on = 1,
1314 .always_on = 1,
1315 },
1316 .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc3_consumers),
1317 .consumer_supplies = tps65217_dcdc3_consumers,
1318 },
1320 /* ldo1 */
1321 {
1322 .constraints = {
1323 .min_uV = 1000000,
1324 .max_uV = 3300000,
1325 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1326 .boot_on = 1,
1327 .always_on = 1,
1328 },
1329 .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo1_consumers),
1330 .consumer_supplies = tps65217_ldo1_consumers,
1331 },
1333 /* ldo2 */
1334 {
1335 .constraints = {
1336 .min_uV = 900000,
1337 .max_uV = 3300000,
1338 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1339 REGULATOR_CHANGE_STATUS),
1340 .boot_on = 1,
1341 .always_on = 1,
1342 },
1343 .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo2_consumers),
1344 .consumer_supplies = tps65217_ldo2_consumers,
1345 },
1347 /* ldo3 */
1348 {
1349 .constraints = {
1350 .min_uV = 1800000,
1351 .max_uV = 3300000,
1352 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1353 REGULATOR_CHANGE_STATUS),
1354 .boot_on = 1,
1355 .always_on = 1,
1356 },
1357 .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo3_consumers),
1358 .consumer_supplies = tps65217_ldo3_consumers,
1359 },
1361 /* ldo4 */
1362 {
1363 .constraints = {
1364 .min_uV = 1800000,
1365 .max_uV = 3300000,
1366 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1367 REGULATOR_CHANGE_STATUS),
1368 .boot_on = 1,
1369 .always_on = 1,
1370 },
1371 .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo4_consumers),
1372 .consumer_supplies = tps65217_ldo4_consumers,
1373 },
1374 };
1376 static struct tps65217_board beaglebone_tps65217_info = {
1377 .tps65217_init_data = &tps65217_regulator_data[0],
1378 };
1380 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1381 .click_flags = LIS3_CLICK_SINGLE_X |
1382 LIS3_CLICK_SINGLE_Y |
1383 LIS3_CLICK_SINGLE_Z,
1384 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1385 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1386 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1387 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1388 .wakeup_thresh = 10,
1389 .click_thresh_x = 10,
1390 .click_thresh_y = 10,
1391 .click_thresh_z = 10,
1392 .g_range = 2,
1393 .st_min_limits[0] = 120,
1394 .st_min_limits[1] = 120,
1395 .st_min_limits[2] = 140,
1396 .st_max_limits[0] = 550,
1397 .st_max_limits[1] = 550,
1398 .st_max_limits[2] = 750,
1399 };
1401 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1402 {
1403 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1404 },
1405 {
1406 I2C_BOARD_INFO("lis331dlh", 0x18),
1407 .platform_data = &lis331dlh_pdata,
1408 },
1409 {
1410 I2C_BOARD_INFO("tsl2550", 0x39),
1411 },
1412 {
1413 I2C_BOARD_INFO("tmp275", 0x48),
1414 },
1415 };
1417 static void i2c1_init(int evm_id, int profile)
1418 {
1419 setup_pin_mux(i2c1_pin_mux);
1420 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1421 ARRAY_SIZE(am335x_i2c_boardinfo1));
1422 return;
1423 }
1426 static struct i2c_board_info am335x_i2c_boardinfo2[] = {
1427 };
1429 static void i2c2_init(int evm_id, int profile)
1430 {
1431 setup_pin_mux(i2c2_pin_mux);
1432 omap_register_i2c_bus(3, 100, am335x_i2c_boardinfo2,
1433 ARRAY_SIZE(am335x_i2c_boardinfo2));
1434 return;
1435 }
1437 /* Setup McASP 1 */
1438 static void mcasp1_init(int evm_id, int profile)
1439 {
1440 /* Configure McASP */
1441 setup_pin_mux(mcasp1_pin_mux);
1442 am335x_register_mcasp1(&am335x_evm_snd_data1);
1443 return;
1444 }
1446 static void mmc1_init(int evm_id, int profile)
1447 {
1448 setup_pin_mux(mmc1_pin_mux);
1450 am335x_mmc[1].mmc = 2;
1451 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1452 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1453 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1454 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1456 /* mmc will be initialized when mmc0_init is called */
1457 return;
1458 }
1460 static void mmc2_wl12xx_init(int evm_id, int profile)
1461 {
1462 setup_pin_mux(mmc2_wl12xx_pin_mux);
1464 am335x_mmc[1].mmc = 3;
1465 am335x_mmc[1].name = "wl1271";
1466 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1467 | MMC_PM_KEEP_POWER;
1468 am335x_mmc[1].nonremovable = true;
1469 am335x_mmc[1].gpio_cd = -EINVAL;
1470 am335x_mmc[1].gpio_wp = -EINVAL;
1471 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1473 /* mmc will be initialized when mmc0_init is called */
1474 return;
1475 }
1477 static void uart1_wl12xx_init(int evm_id, int profile)
1478 {
1479 setup_pin_mux(uart1_wl12xx_pin_mux);
1480 }
1482 static void wl12xx_bluetooth_enable(void)
1483 {
1484 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1485 "bt_en\n");
1486 if (status < 0)
1487 pr_err("Failed to request gpio for bt_enable");
1489 pr_info("Configure Bluetooth Enable pin...\n");
1490 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1491 }
1493 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1494 {
1495 if (on) {
1496 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1497 mdelay(70);
1498 }
1499 else
1500 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1502 return 0;
1503 }
1505 static void wl12xx_init(int evm_id, int profile)
1506 {
1507 struct device *dev;
1508 struct omap_mmc_platform_data *pdata;
1509 int ret;
1511 /* Register WLAN and BT enable pins based on the evm board revision */
1512 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1513 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1514 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1515 }
1516 else {
1517 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1518 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1519 }
1521 wl12xx_bluetooth_enable();
1523 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1524 pr_err("error setting wl12xx data\n");
1526 dev = am335x_mmc[1].dev;
1527 if (!dev) {
1528 pr_err("wl12xx mmc device initialization failed\n");
1529 goto out;
1530 }
1532 pdata = dev->platform_data;
1533 if (!pdata) {
1534 pr_err("Platfrom data of wl12xx device not set\n");
1535 goto out;
1536 }
1538 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1539 GPIOF_OUT_INIT_LOW, "wlan_en");
1540 if (ret) {
1541 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1542 goto out;
1543 }
1545 if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1546 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1547 else
1548 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1550 pdata->slots[0].set_power = wl12xx_set_power;
1551 out:
1552 return;
1553 }
1555 static void d_can_init(int evm_id, int profile)
1556 {
1557 switch (evm_id) {
1558 case IND_AUT_MTR_EVM:
1559 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1560 setup_pin_mux(d_can_ia_pin_mux);
1561 /* Instance Zero */
1562 am33xx_d_can_init(0);
1563 }
1564 break;
1565 case GEN_PURP_EVM:
1566 if (profile == PROFILE_1) {
1567 setup_pin_mux(d_can_gp_pin_mux);
1568 /* Instance One */
1569 am33xx_d_can_init(1);
1570 }
1571 break;
1572 default:
1573 break;
1574 }
1575 }
1577 static void mmc0_init(int evm_id, int profile)
1578 {
1579 setup_pin_mux(mmc0_pin_mux);
1581 omap2_hsmmc_init(am335x_mmc);
1582 return;
1583 }
1585 static struct i2c_board_info tps65217_i2c_boardinfo[] = {
1586 {
1587 I2C_BOARD_INFO("tps65217", TPS65217_I2C_ID),
1588 .platform_data = &beaglebone_tps65217_info,
1589 },
1590 };
1592 static void tps65217_init(int evm_id, int profile)
1593 {
1594 struct i2c_adapter *adapter;
1595 struct i2c_client *client;
1597 /* I2C1 adapter request */
1598 adapter = i2c_get_adapter(1);
1599 if (!adapter) {
1600 pr_err("failed to get adapter i2c1\n");
1601 return;
1602 }
1604 client = i2c_new_device(adapter, tps65217_i2c_boardinfo);
1605 if (!client)
1606 pr_err("failed to register tps65217 to i2c1\n");
1608 i2c_put_adapter(adapter);
1609 }
1611 static void mmc0_no_cd_init(int evm_id, int profile)
1612 {
1613 setup_pin_mux(mmc0_no_cd_pin_mux);
1615 omap2_hsmmc_init(am335x_mmc);
1616 return;
1617 }
1620 /* setup spi0 */
1621 static void spi0_init(int evm_id, int profile)
1622 {
1623 setup_pin_mux(spi0_pin_mux);
1624 spi_register_board_info(am335x_spi0_slave_info,
1625 ARRAY_SIZE(am335x_spi0_slave_info));
1626 return;
1627 }
1629 /* setup spi1 */
1630 static void spi1_init(int evm_id, int profile)
1631 {
1632 setup_pin_mux(spi1_pin_mux);
1633 spi_register_board_info(am335x_spi1_slave_info,
1634 ARRAY_SIZE(am335x_spi1_slave_info));
1635 return;
1636 }
1639 static int beaglebone_phy_fixup(struct phy_device *phydev)
1640 {
1641 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1642 SUPPORTED_100baseT_Full);
1644 return 0;
1645 }
1647 #if defined(CONFIG_TLK110_WORKAROUND) || \
1648 defined(CONFIG_TLK110_WORKAROUND_MODULE)
1649 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1650 {
1651 unsigned int val;
1653 /* This is done as a workaround to support TLK110 rev1.0 phy */
1654 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1655 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1657 val = phy_read(phydev, TLK110_LPFHPF_REG);
1658 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1660 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1661 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1663 val = phy_read(phydev, TLK110_VRCR_REG);
1664 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1666 val = phy_read(phydev, TLK110_SETFFE_REG);
1667 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1669 val = phy_read(phydev, TLK110_FTSP_REG);
1670 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1672 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1673 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1675 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1676 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1678 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1679 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1681 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1682 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1684 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1685 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1687 val = phy_read(phydev, TLK110_CFGPS_REG);
1688 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1690 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1691 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1693 val = phy_read(phydev, TLK110_SWSCR3_REG);
1694 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1696 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1697 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1699 val = phy_read(phydev, TLK110_PHYRCR_REG);
1700 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1702 return 0;
1703 }
1704 #endif
1706 static void profibus_init(int evm_id, int profile)
1707 {
1708 setup_pin_mux(profibus_pin_mux);
1709 return;
1710 }
1712 /* Low-Cost EVM */
1713 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1714 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1715 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1716 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1717 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1718 {NULL, 0, 0},
1719 };
1721 /* General Purpose EVM */
1722 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1723 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1724 PROFILE_2 | PROFILE_7) },
1725 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1726 PROFILE_2 | PROFILE_7) },
1727 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1728 PROFILE_2 | PROFILE_7) },
1729 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1730 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1731 PROFILE_4 | PROFILE_6) },
1732 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1733 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1734 {evm_nand_init, DEV_ON_DGHTR_BRD,
1735 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1736 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1737 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1738 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1739 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1740 PROFILE_5)},
1741 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1742 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1743 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1744 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1745 PROFILE_5)},
1746 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1747 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
1748 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1749 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1750 {uart2_init, DEV_ON_DGHTR_BRD, PROFILE_3},
1751 {haptics_init, DEV_ON_DGHTR_BRD, (PROFILE_4)},
1752 {NULL, 0, 0},
1753 };
1755 /* Industrial Auto Motor Control EVM */
1756 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1757 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1758 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1759 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1760 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1761 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1762 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1763 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1764 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1765 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1766 {NULL, 0, 0},
1767 };
1769 /* IP-Phone EVM */
1770 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1771 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1772 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1773 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1774 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1775 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1776 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1777 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1778 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1779 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1780 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1781 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1782 {NULL, 0, 0},
1783 };
1785 /* Beaglebone < Rev A3 */
1786 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1787 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1788 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1789 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1790 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1791 {i2c2_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1792 {NULL, 0, 0},
1793 };
1795 /* Beaglebone Rev A3 and after */
1796 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1797 {tps65217_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1798 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1799 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1800 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1801 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1802 {i2c2_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1803 {NULL, 0, 0},
1804 };
1806 static void setup_low_cost_evm(void)
1807 {
1808 pr_info("The board is a AM335x Low Cost EVM.\n");
1810 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1811 }
1813 static void setup_general_purpose_evm(void)
1814 {
1815 u32 prof_sel = am335x_get_profile_selection();
1816 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1818 if (!strncmp("1.1A", config.version, 4)) {
1819 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1820 } else if (!strncmp("1.0", config.version, 3)) {
1821 gp_evm_revision = GP_EVM_REV_IS_1_0;
1822 } else {
1823 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1824 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1825 }
1827 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1828 gigabit_enable = 0;
1829 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1830 gigabit_enable = 1;
1832 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1833 }
1835 static void setup_ind_auto_motor_ctrl_evm(void)
1836 {
1837 u32 prof_sel = am335x_get_profile_selection();
1839 pr_info("The board is an industrial automation EVM in profile %d\n",
1840 prof_sel);
1842 /* Only Profile 0 is supported */
1843 if ((1L << prof_sel) != PROFILE_0) {
1844 pr_err("AM335X: Only Profile 0 is supported\n");
1845 pr_err("Assuming profile 0 & continuing\n");
1846 prof_sel = PROFILE_0;
1847 }
1849 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1850 PROFILE_0);
1852 /* Fillup global evmid */
1853 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1855 /* Initialize TLK110 PHY registers for phy version 1.0 */
1856 am335x_tlk110_phy_init();
1859 }
1861 static void setup_ip_phone_evm(void)
1862 {
1863 pr_info("The board is an IP phone EVM\n");
1865 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1866 }
1868 /* BeagleBone < Rev A3 */
1869 static void setup_beaglebone_old(void)
1870 {
1871 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1873 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1874 am335x_mmc[0].gpio_wp = -EINVAL;
1876 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1878 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1879 beaglebone_phy_fixup);
1881 /* Fill up global evmid */
1882 am33xx_evmid_fillup(BEAGLE_BONE_OLD);
1883 }
1885 /* BeagleBone after Rev A3 */
1886 static void setup_beaglebone(void)
1887 {
1888 pr_info("The board is a AM335x Beaglebone.\n");
1890 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1891 am335x_mmc[0].gpio_wp = -EINVAL;
1893 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1895 /* TPS65217 regulator has full constraints */
1896 regulator_has_full_constraints();
1898 /* Fill up global evmid */
1899 am33xx_evmid_fillup(BEAGLE_BONE_A3);
1900 }
1903 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1904 {
1905 int ret;
1907 /*
1908 * Read from the EEPROM to see the presence
1909 * of daughter board. If present, get daughter board
1910 * specific data.
1911 */
1913 ret = m->read(m, (char *)&config1, 0, sizeof(config1));
1914 if (ret == sizeof(config1)) {
1915 pr_info("Detected a daughter card on AM335x EVM..");
1916 daughter_brd_detected = true;
1917 }
1918 else {
1919 pr_info("No daughter card found\n");
1920 daughter_brd_detected = false;
1921 return;
1922 }
1924 if (!strncmp("CPLD1.0A", config1.cpld_ver, 8))
1925 cpld_version = CPLD_REV_1_0A;
1926 else if (!strncmp("CPLD1.1A", config1.cpld_ver, 8))
1927 cpld_version = CPLD_REV_1_1A;
1928 else {
1929 pr_err("Unknown CPLD version found, falling back to 1.0A\n");
1930 cpld_version = CPLD_REV_1_0A;
1931 }
1932 }
1934 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1935 {
1936 int ret;
1937 char tmp[10];
1939 /* 1st get the MAC address from EEPROM */
1940 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1941 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1943 if (ret != sizeof(am335x_mac_addr)) {
1944 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1945 return;
1946 }
1948 /* Fillup global mac id */
1949 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1950 &am335x_mac_addr[1][0]);
1952 /* get board specific data */
1953 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1954 if (ret != sizeof(config)) {
1955 pr_err("AM335X EVM config read fail, read %d bytes\n", ret);
1956 pr_err("This likely means that there either is no/or a failed EEPROM\n");
1957 goto out;
1958 }
1960 if (config.header != AM335X_EEPROM_HEADER) {
1961 pr_err("AM335X: wrong header 0x%x, expected 0x%x\n",
1962 config.header, AM335X_EEPROM_HEADER);
1963 goto out;
1964 }
1966 if (strncmp("A335", config.name, 4)) {
1967 pr_err("Board %s\ndoesn't look like an AM335x board\n",
1968 config.name);
1969 goto out;
1970 }
1972 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1973 pr_info("Board name: %s\n", tmp);
1974 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1975 pr_info("Board version: %s\n", tmp);
1977 if (!strncmp("A335BONE", config.name, 8)) {
1978 daughter_brd_detected = false;
1979 if(!strncmp("00A1", config.version, 4) ||
1980 !strncmp("00A2", config.version, 4))
1981 setup_beaglebone_old();
1982 else
1983 setup_beaglebone();
1984 } else {
1985 /* only 6 characters of options string used for now */
1986 snprintf(tmp, 7, "%s", config.opt);
1987 pr_info("SKU: %s\n", tmp);
1989 if (!strncmp("SKU#00", config.opt, 6))
1990 setup_low_cost_evm();
1991 else if (!strncmp("SKU#01", config.opt, 6))
1992 setup_general_purpose_evm();
1993 else if (!strncmp("SKU#02", config.opt, 6))
1994 setup_ind_auto_motor_ctrl_evm();
1995 else if (!strncmp("SKU#03", config.opt, 6))
1996 setup_ip_phone_evm();
1997 else
1998 goto out;
1999 }
2000 /* Initialize cpsw after board detection is completed as board
2001 * information is required for configuring phy address and hence
2002 * should be call only after board detection
2003 */
2004 am33xx_cpsw_init(gigabit_enable);
2006 return;
2008 out:
2009 /*
2010 * If the EEPROM hasn't been programed or an incorrect header
2011 * or board name are read then the hardware details are unknown.
2012 * Notify the user and call machine_halt to stop the boot process.
2013 */
2014 pr_err("The error message above indicates that there is an issue with\n"
2015 "the EEPROM or the EEPROM contents. After verifying the EEPROM\n"
2016 "contents, if any, refer to the %s function in the\n"
2017 "%s file to modify the board\n"
2018 "initialization code to match the hardware configuration\n",
2019 __func__ , __FILE__);
2020 machine_halt();
2021 }
2023 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
2024 .byte_len = (256*1024) / 8,
2025 .page_size = 64,
2026 .flags = AT24_FLAG_ADDR16,
2027 .setup = am335x_setup_daughter_board,
2028 .context = (void *)NULL,
2029 };
2031 static struct at24_platform_data am335x_baseboard_eeprom_info = {
2032 .byte_len = (256*1024) / 8,
2033 .page_size = 64,
2034 .flags = AT24_FLAG_ADDR16,
2035 .setup = am335x_evm_setup,
2036 .context = (void *)NULL,
2037 };
2039 static struct regulator_init_data am335x_dummy = {
2040 .constraints.always_on = true,
2041 };
2043 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
2044 REGULATOR_SUPPLY("vdd_mpu", NULL),
2045 };
2047 static struct regulator_init_data am335x_vdd1 = {
2048 .constraints = {
2049 .min_uV = 600000,
2050 .max_uV = 1500000,
2051 .valid_modes_mask = REGULATOR_MODE_NORMAL,
2052 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
2053 .always_on = 1,
2054 },
2055 .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply),
2056 .consumer_supplies = am335x_vdd1_supply,
2057 };
2059 static struct tps65910_board am335x_tps65910_info = {
2060 .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy,
2061 .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy,
2062 .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1,
2063 .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy,
2064 .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy,
2065 .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy,
2066 .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy,
2067 .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy,
2068 .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy,
2069 .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy,
2070 .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy,
2071 .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy,
2072 .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy,
2073 };
2075 /*
2076 * Daughter board Detection.
2077 * Every board has a ID memory (EEPROM) on board. We probe these devices at
2078 * machine init, starting from daughter board and ending with baseboard.
2079 * Assumptions :
2080 * 1. probe for i2c devices are called in the order they are included in
2081 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
2082 * eeprom probe is called last.
2083 */
2084 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
2085 {
2086 /* Daughter Board EEPROM */
2087 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
2088 .platform_data = &am335x_daughter_board_eeprom_info,
2089 },
2090 {
2091 /* Baseboard board EEPROM */
2092 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
2093 .platform_data = &am335x_baseboard_eeprom_info,
2094 },
2095 {
2096 I2C_BOARD_INFO("cpld_reg", 0x35),
2097 },
2098 {
2099 I2C_BOARD_INFO("tlc59108", 0x40),
2100 },
2101 {
2102 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
2103 .platform_data = &am335x_tps65910_info,
2104 },
2105 };
2107 static struct omap_musb_board_data musb_board_data = {
2108 .interface_type = MUSB_INTERFACE_ULPI,
2109 /*
2110 * mode[0:3] = USB0PORT's mode
2111 * mode[4:7] = USB1PORT's mode
2112 * AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
2113 */
2114 .mode = (MUSB_HOST << 4) | MUSB_OTG,
2115 .power = 500,
2116 .instances = 1,
2117 };
2119 static int cpld_reg_probe(struct i2c_client *client,
2120 const struct i2c_device_id *id)
2121 {
2122 cpld_client = client;
2123 return 0;
2124 }
2126 static int __devexit cpld_reg_remove(struct i2c_client *client)
2127 {
2128 cpld_client = NULL;
2129 return 0;
2130 }
2132 static const struct i2c_device_id cpld_reg_id[] = {
2133 { "cpld_reg", 0 },
2134 { }
2135 };
2137 static struct i2c_driver cpld_reg_driver = {
2138 .driver = {
2139 .name = "cpld_reg",
2140 },
2141 .probe = cpld_reg_probe,
2142 .remove = cpld_reg_remove,
2143 .id_table = cpld_reg_id,
2144 };
2146 static void evm_init_cpld(void)
2147 {
2148 i2c_add_driver(&cpld_reg_driver);
2149 }
2151 static void __init am335x_evm_i2c_init(void)
2152 {
2153 /* Initially assume Low Cost EVM Config */
2154 am335x_evm_id = LOW_COST_EVM;
2156 evm_init_cpld();
2158 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
2159 ARRAY_SIZE(am335x_i2c_boardinfo));
2160 }
2162 static struct resource am335x_rtc_resources[] = {
2163 {
2164 .start = AM33XX_RTC_BASE,
2165 .end = AM33XX_RTC_BASE + SZ_4K - 1,
2166 .flags = IORESOURCE_MEM,
2167 },
2168 { /* timer irq */
2169 .start = AM33XX_IRQ_RTC_TIMER,
2170 .end = AM33XX_IRQ_RTC_TIMER,
2171 .flags = IORESOURCE_IRQ,
2172 },
2173 { /* alarm irq */
2174 .start = AM33XX_IRQ_RTC_ALARM,
2175 .end = AM33XX_IRQ_RTC_ALARM,
2176 .flags = IORESOURCE_IRQ,
2177 },
2178 };
2180 static struct platform_device am335x_rtc_device = {
2181 .name = "omap_rtc",
2182 .id = -1,
2183 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
2184 .resource = am335x_rtc_resources,
2185 };
2187 static int am335x_rtc_init(void)
2188 {
2189 void __iomem *base;
2190 struct clk *clk;
2192 clk = clk_get(NULL, "rtc_fck");
2193 if (IS_ERR(clk)) {
2194 pr_err("rtc : Failed to get RTC clock\n");
2195 return -1;
2196 }
2198 if (clk_enable(clk)) {
2199 pr_err("rtc: Clock Enable Failed\n");
2200 return -1;
2201 }
2203 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
2205 if (WARN_ON(!base))
2206 return -ENOMEM;
2208 /* Unlock the rtc's registers */
2209 __raw_writel(0x83e70b13, base + 0x6c);
2210 __raw_writel(0x95a4f1e0, base + 0x70);
2212 /*
2213 * Enable the 32K OSc
2214 * TODO: Need a better way to handle this
2215 * Since we want the clock to be running before mmc init
2216 * we need to do it before the rtc probe happens
2217 */
2218 __raw_writel(0x48, base + 0x54);
2220 iounmap(base);
2222 return platform_device_register(&am335x_rtc_device);
2223 }
2225 /* Enable clkout2 */
2226 static struct pinmux_config clkout2_pin_mux[] = {
2227 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
2228 {NULL, 0},
2229 };
2231 static void __init clkout2_enable(void)
2232 {
2233 struct clk *ck_32;
2235 ck_32 = clk_get(NULL, "clkout2_ck");
2236 if (IS_ERR(ck_32)) {
2237 pr_err("Cannot clk_get ck_32\n");
2238 return;
2239 }
2241 clk_enable(ck_32);
2243 setup_pin_mux(clkout2_pin_mux);
2244 }
2246 void __iomem *am33xx_emif_base;
2248 void __iomem * __init am33xx_get_mem_ctlr(void)
2249 {
2251 am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
2253 if (!am33xx_emif_base)
2254 pr_warning("%s: Unable to map DDR2 controller", __func__);
2256 return am33xx_emif_base;
2257 }
2259 void __iomem *am33xx_get_ram_base(void)
2260 {
2261 return am33xx_emif_base;
2262 }
2264 static struct resource am33xx_cpuidle_resources[] = {
2265 {
2266 .start = AM33XX_EMIF0_BASE,
2267 .end = AM33XX_EMIF0_BASE + SZ_32K - 1,
2268 .flags = IORESOURCE_MEM,
2269 },
2270 };
2272 /* AM33XX devices support DDR2 power down */
2273 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
2274 .ddr2_pdown = 1,
2275 };
2277 static struct platform_device am33xx_cpuidle_device = {
2278 .name = "cpuidle-am33xx",
2279 .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
2280 .resource = am33xx_cpuidle_resources,
2281 .dev = {
2282 .platform_data = &am33xx_cpuidle_pdata,
2283 },
2284 };
2286 static void __init am33xx_cpuidle_init(void)
2287 {
2288 int ret;
2290 am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
2292 ret = platform_device_register(&am33xx_cpuidle_device);
2294 if (ret)
2295 pr_warning("AM33XX cpuidle registration failed\n");
2297 }
2299 static void __init am335x_evm_init(void)
2300 {
2301 am33xx_cpuidle_init();
2302 am33xx_mux_init(board_mux);
2303 omap_serial_init();
2304 am335x_rtc_init();
2305 clkout2_enable();
2306 am335x_evm_i2c_init();
2307 omap_sdrc_init(NULL, NULL);
2308 usb_musb_init(&musb_board_data);
2309 omap_board_config = am335x_evm_config;
2310 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
2311 /* Create an alias for icss clock */
2312 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
2313 pr_warn("failed to create an alias: icss_uart_gclk --> pruss\n");
2314 if (clk_add_alias("pruss", NULL, "icss_fck", NULL))
2315 pr_warn("failed to create an alias: icss_fck --> pruss\n");
2316 /* Create an alias for gfx/sgx clock */
2317 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
2318 pr_warn("failed to create an alias: gfx_fclk --> sgx_ck\n");
2319 }
2321 static void __init am335x_evm_map_io(void)
2322 {
2323 omap2_set_globals_am33xx();
2324 omapam33xx_map_common_io();
2325 }
2327 MACHINE_START(AM335XEVM, "am335xevm")
2328 /* Maintainer: Texas Instruments */
2329 .atag_offset = 0x100,
2330 .map_io = am335x_evm_map_io,
2331 .init_early = am33xx_init_early,
2332 .init_irq = ti81xx_init_irq,
2333 .handle_irq = omap3_intc_handle_irq,
2334 .timer = &omap3_am33xx_timer,
2335 .init_machine = am335x_evm_init,
2336 MACHINE_END
2338 MACHINE_START(AM335XIAEVM, "am335xiaevm")
2339 /* Maintainer: Texas Instruments */
2340 .atag_offset = 0x100,
2341 .map_io = am335x_evm_map_io,
2342 .init_irq = ti81xx_init_irq,
2343 .init_early = am33xx_init_early,
2344 .timer = &omap3_am33xx_timer,
2345 .init_machine = am335x_evm_init,
2346 MACHINE_END