1 /*
2 * Code for AM335X EVM.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/err.h>
30 #include <linux/wl12xx.h>
31 #include <linux/ethtool.h>
33 /* LCD controller is similar to DA850 */
34 #include <video/da8xx-fb.h>
36 #include <mach/hardware.h>
37 #include <mach/board-am335xevm.h>
39 #include <asm/mach-types.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/map.h>
42 #include <asm/hardware/asp.h>
44 #include <plat/irqs.h>
45 #include <plat/board.h>
46 #include <plat/common.h>
47 #include <plat/lcdc.h>
48 #include <plat/usb.h>
49 #include <plat/mmc.h>
51 #include "board-flash.h"
52 #include "mux.h"
53 #include "devices.h"
54 #include "hsmmc.h"
56 /* Convert GPIO signal to GPIO pin number */
57 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
59 /* TLK PHY IDs */
60 #define TLK110_PHY_ID 0x2000A201
61 #define TLK110_PHY_MASK 0xfffffff0
63 /* BBB PHY IDs */
64 #define BBB_PHY_ID 0x7c0f1
65 #define BBB_PHY_MASK 0xfffffffe
67 /* TLK110 PHY register offsets */
68 #define TLK110_COARSEGAIN_REG 0x00A3
69 #define TLK110_LPFHPF_REG 0x00AC
70 #define TLK110_SPAREANALOG_REG 0x00B9
71 #define TLK110_VRCR_REG 0x00D0
72 #define TLK110_SETFFE_REG 0x0107
73 #define TLK110_FTSP_REG 0x0154
74 #define TLK110_ALFATPIDL_REG 0x002A
75 #define TLK110_PSCOEF21_REG 0x0096
76 #define TLK110_PSCOEF3_REG 0x0097
77 #define TLK110_ALFAFACTOR1_REG 0x002C
78 #define TLK110_ALFAFACTOR2_REG 0x0023
79 #define TLK110_CFGPS_REG 0x0095
80 #define TLK110_FTSPTXGAIN_REG 0x0150
81 #define TLK110_SWSCR3_REG 0x000B
82 #define TLK110_SCFALLBACK_REG 0x0040
83 #define TLK110_PHYRCR_REG 0x001F
85 /* TLK110 register writes values */
86 #define TLK110_COARSEGAIN_VAL 0x0000
87 #define TLK110_LPFHPF_VAL 0x8000
88 #define TLK110_SPANALOG_VAL 0x0000
89 #define TLK110_VRCR_VAL 0x0008
90 #define TLK110_SETFFE_VAL 0x0605
91 #define TLK110_FTSP_VAL 0x0255
92 #define TLK110_ALFATPIDL_VAL 0x7998
93 #define TLK110_PSCOEF21_VAL 0x3A20
94 #define TLK110_PSCOEF3_VAL 0x003F
95 #define TLK110_ALFACTOR1_VAL 0xFF80
96 #define TLK110_ALFACTOR2_VAL 0x021C
97 #define TLK110_CFGPS_VAL 0x0000
98 #define TLK110_FTSPTXGAIN_VAL 0x6A88
99 #define TLK110_SWSCR3_VAL 0x0000
100 #define TLK110_SCFALLBACK_VAL 0xC11D
101 #define TLK110_PHYRCR_VAL 0x4000
103 #ifdef CONFIG_TLK110_WORKAROUND
104 #define am335x_tlk110_phy_init()\
105 do { \
106 phy_register_fixup_for_uid(TLK110_PHY_ID,\
107 TLK110_PHY_MASK,\
108 am335x_tlk110_phy_fixup);\
109 } while (0);
110 #else
111 #define am335x_tlk110_phy_init() do { } while (0);
112 #endif
114 static const struct display_panel disp_panel = {
115 WVGA,
116 32,
117 32,
118 COLOR_ACTIVE,
119 };
121 static struct lcd_ctrl_config lcd_cfg = {
122 &disp_panel,
123 .ac_bias = 255,
124 .ac_bias_intrpt = 0,
125 .dma_burst_sz = 16,
126 .bpp = 32,
127 .fdd = 0x80,
128 .tft_alt_mode = 0,
129 .stn_565_mode = 0,
130 .mono_8bit_mode = 0,
131 .invert_line_clock = 1,
132 .invert_frm_clock = 1,
133 .sync_edge = 0,
134 .sync_ctrl = 1,
135 .raster_order = 0,
136 };
138 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
139 .manu_name = "ThreeFive",
140 .controller_data = &lcd_cfg,
141 .type = "TFC_S9700RTWV35TR_01B",
142 };
144 #include "common.h"
146 /* TSc controller */
147 #include <linux/input/ti_tscadc.h>
149 static struct resource tsc_resources[] = {
150 [0] = {
151 .start = AM33XX_TSC_BASE,
152 .end = AM33XX_TSC_BASE + SZ_8K - 1,
153 .flags = IORESOURCE_MEM,
154 },
155 [1] = {
156 .start = AM33XX_IRQ_ADC_GEN,
157 .end = AM33XX_IRQ_ADC_GEN,
158 .flags = IORESOURCE_IRQ,
159 },
160 };
162 static struct tsc_data am335x_touchscreen_data = {
163 .wires = 4,
164 .x_plate_resistance = 200,
165 };
167 static struct platform_device tsc_device = {
168 .name = "tsc",
169 .id = -1,
170 .dev = {
171 .platform_data = &am335x_touchscreen_data,
172 },
173 .num_resources = ARRAY_SIZE(tsc_resources),
174 .resource = tsc_resources,
175 };
177 static u8 am335x_iis_serializer_direction1[] = {
178 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
179 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
180 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
181 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
182 };
184 static struct snd_platform_data am335x_evm_snd_data1 = {
185 .tx_dma_offset = 0x46400000, /* McASP1 */
186 .rx_dma_offset = 0x46400000,
187 .op_mode = DAVINCI_MCASP_IIS_MODE,
188 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
189 .tdm_slots = 2,
190 .serial_dir = am335x_iis_serializer_direction1,
191 .asp_chan_q = EVENTQ_2,
192 .version = MCASP_VERSION_3,
193 .txnumevt = 1,
194 .rxnumevt = 1,
195 };
197 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
198 {
199 .mmc = 1,
200 .caps = MMC_CAP_4_BIT_DATA,
201 .gpio_cd = GPIO_TO_PIN(0, 6),
202 .gpio_wp = GPIO_TO_PIN(3, 18),
203 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
204 },
205 {
206 .mmc = 0, /* will be set at runtime */
207 },
208 {
209 .mmc = 0, /* will be set at runtime */
210 },
211 {} /* Terminator */
212 };
215 #ifdef CONFIG_OMAP_MUX
216 static struct omap_board_mux board_mux[] __initdata = {
217 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
218 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
219 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
220 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
221 { .reg_offset = OMAP_MUX_TERMINATOR },
222 };
223 #else
224 #define board_mux NULL
225 #endif
227 /* module pin mux structure */
228 struct pinmux_config {
229 const char *string_name; /* signal name format */
230 int val; /* Options for the mux register value */
231 };
233 struct evm_dev_cfg {
234 void (*device_init)(int evm_id, int profile);
236 /*
237 * If the device is required on both baseboard & daughter board (ex i2c),
238 * specify DEV_ON_BASEBOARD
239 */
240 #define DEV_ON_BASEBOARD 0
241 #define DEV_ON_DGHTR_BRD 1
242 u32 device_on;
244 u32 profile; /* Profiles (0-7) in which the module is present */
245 };
247 /* AM335X - CPLD Register Offsets */
248 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
249 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
250 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
251 #define CPLD_CFG_REG 0x10 /* Configuration Register */
253 static struct i2c_client *cpld_client;
254 static u32 am335x_evm_id;
255 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
256 };
258 /*
259 * EVM Config held in On-Board eeprom device.
260 *
261 * Header Format
262 *
263 * Name Size Contents
264 * (Bytes)
265 *-------------------------------------------------------------
266 * Header 4 0xAA, 0x55, 0x33, 0xEE
267 *
268 * Board Name 8 Name for board in ASCII.
269 * example "A33515BB" = "AM335X
270 Low Cost EVM board"
271 *
272 * Version 4 Hardware version code for board in
273 * in ASCII. "1.0A" = rev.01.0A
274 *
275 * Serial Number 12 Serial number of the board. This is a 12
276 * character string which is WWYY4P16nnnn, where
277 * WW = 2 digit week of the year of production
278 * YY = 2 digit year of production
279 * nnnn = incrementing board number
280 *
281 * Configuration option 32 Codes(TBD) to show the configuration
282 * setup on this board.
283 *
284 * Available 32720 Available space for other non-volatile
285 * data.
286 */
287 struct am335x_evm_eeprom_config {
288 u32 header;
289 u8 name[8];
290 char version[4];
291 u8 serial[12];
292 u8 opt[32];
293 };
295 static struct am335x_evm_eeprom_config config;
296 static bool daughter_brd_detected;
298 #define GP_EVM_REV_IS_1_0 0x1
299 #define GP_EVM_REV_IS_1_1A 0x2
300 #define GP_EVM_REV_IS_UNKNOWN 0xFF
301 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
302 unsigned int gigabit_enable = 1;
304 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
305 #define EEPROM_NO_OF_MAC_ADDR 3
306 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
308 #define AM335X_EEPROM_HEADER 0xEE3355AA
310 /* current profile if exists else PROFILE_0 on error */
311 static u32 am335x_get_profile_selection(void)
312 {
313 int val = 0;
315 if (!cpld_client)
316 /* error checking is not done in func's calling this routine.
317 so return profile 0 on error */
318 return 0;
320 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
321 if (val < 0)
322 return 0; /* default to Profile 0 on Error */
323 else
324 return val & 0x7;
325 }
327 /* Module pin mux for LCDC */
328 static struct pinmux_config lcdc_pin_mux[] = {
329 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
330 | AM33XX_PULL_DISA},
331 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
332 | AM33XX_PULL_DISA},
333 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
334 | AM33XX_PULL_DISA},
335 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
336 | AM33XX_PULL_DISA},
337 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
338 | AM33XX_PULL_DISA},
339 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
340 | AM33XX_PULL_DISA},
341 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
342 | AM33XX_PULL_DISA},
343 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
344 | AM33XX_PULL_DISA},
345 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
346 | AM33XX_PULL_DISA},
347 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
348 | AM33XX_PULL_DISA},
349 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
350 | AM33XX_PULL_DISA},
351 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
352 | AM33XX_PULL_DISA},
353 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
354 | AM33XX_PULL_DISA},
355 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
356 | AM33XX_PULL_DISA},
357 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
358 | AM33XX_PULL_DISA},
359 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
360 | AM33XX_PULL_DISA},
361 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
362 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
363 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
364 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
365 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
366 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
367 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
368 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
369 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
370 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
371 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
372 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
373 {NULL, 0},
374 };
376 static struct pinmux_config tsc_pin_mux[] = {
377 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
378 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
379 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
380 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
381 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
382 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
383 {NULL, 0},
384 };
386 /* Pin mux for nand flash module */
387 static struct pinmux_config nand_pin_mux[] = {
388 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
389 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
390 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
391 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
392 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
393 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
394 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
395 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
396 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
397 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
398 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
399 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
400 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
401 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
402 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
403 {NULL, 0},
404 };
406 /* Module pin mux for SPI fash */
407 static struct pinmux_config spi0_pin_mux[] = {
408 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
409 | AM33XX_INPUT_EN},
410 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
411 | AM33XX_INPUT_EN},
412 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
413 | AM33XX_INPUT_EN},
414 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
415 | AM33XX_INPUT_EN},
416 {NULL, 0},
417 };
419 /* Module pin mux for SPI flash */
420 static struct pinmux_config spi1_pin_mux[] = {
421 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
422 | AM33XX_INPUT_EN},
423 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
424 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
425 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
426 | AM33XX_INPUT_EN},
427 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
428 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
429 {NULL, 0},
430 };
432 /* Module pin mux for rgmii1 */
433 static struct pinmux_config rgmii1_pin_mux[] = {
434 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
435 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
436 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
437 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
438 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
439 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
440 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
441 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
442 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
443 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
444 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
445 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
446 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
447 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
448 {NULL, 0},
449 };
451 /* Module pin mux for rgmii2 */
452 static struct pinmux_config rgmii2_pin_mux[] = {
453 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
454 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
455 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
456 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
457 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
458 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
459 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
460 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
461 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
462 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
463 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
464 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
465 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
466 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
467 {NULL, 0},
468 };
470 /* Module pin mux for mii1 */
471 static struct pinmux_config mii1_pin_mux[] = {
472 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
473 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
474 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
475 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
476 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
477 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
478 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
479 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
480 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
481 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
482 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
483 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
484 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
485 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
486 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
487 {NULL, 0},
488 };
490 /* Module pin mux for rmii1 */
491 static struct pinmux_config rmii1_pin_mux[] = {
492 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
493 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
494 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
495 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
496 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
497 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
498 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
499 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
500 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
501 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
502 {NULL, 0},
503 };
505 static struct pinmux_config i2c1_pin_mux[] = {
506 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
507 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
508 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
509 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
510 {NULL, 0},
511 };
513 /* Module pin mux for mcasp1 */
514 static struct pinmux_config mcasp1_pin_mux[] = {
515 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
516 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
517 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
518 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
519 AM33XX_PIN_INPUT_PULLDOWN},
520 {NULL, 0},
521 };
524 /* Module pin mux for mmc0 */
525 static struct pinmux_config mmc0_pin_mux[] = {
526 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
527 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
528 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
529 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
530 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
531 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
532 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
533 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
534 {NULL, 0},
535 };
537 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
538 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
539 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
540 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
541 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
542 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
543 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
544 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
545 {NULL, 0},
546 };
548 /* Module pin mux for mmc1 */
549 static struct pinmux_config mmc1_pin_mux[] = {
550 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
551 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
552 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
553 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
554 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
555 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
556 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
557 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
558 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
559 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
560 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
561 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
562 {NULL, 0},
563 };
565 /* Module pin mux for uart3 */
566 static struct pinmux_config uart3_pin_mux[] = {
567 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
568 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
569 {NULL, 0},
570 };
572 /*
573 * @pin_mux - single module pin-mux structure which defines pin-mux
574 * details for all its pins.
575 */
576 static void setup_pin_mux(struct pinmux_config *pin_mux)
577 {
578 int i;
580 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
581 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
583 }
585 /*
586 * @evm_id - evm id which needs to be configured
587 * @dev_cfg - single evm structure which includes
588 * all module inits, pin-mux defines
589 * @profile - if present, else PROFILE_NONE
590 * @dghtr_brd_flg - Whether Daughter board is present or not
591 */
592 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
593 int profile)
594 {
595 int i;
597 /*
598 * Only General Purpose & Industrial Auto Motro Control
599 * EVM has profiles. So check if this evm has profile.
600 * If not, ignore the profile comparison
601 */
603 /*
604 * If the device is on baseboard, directly configure it. Else (device on
605 * Daughter board), check if the daughter card is detected.
606 */
607 if (profile == PROFILE_NONE) {
608 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
609 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
610 dev_cfg->device_init(evm_id, profile);
611 else if (daughter_brd_detected == true)
612 dev_cfg->device_init(evm_id, profile);
613 }
614 } else {
615 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
616 if (dev_cfg->profile & profile) {
617 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
618 dev_cfg->device_init(evm_id, profile);
619 else if (daughter_brd_detected == true)
620 dev_cfg->device_init(evm_id, profile);
621 }
622 }
623 }
624 }
626 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
628 /* pinmux for usb0 drvvbus */
629 static struct pinmux_config usb0_pin_mux[] = {
630 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
631 {NULL, 0},
632 };
634 /* pinmux for usb1 drvvbus */
635 static struct pinmux_config usb1_pin_mux[] = {
636 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
637 {NULL, 0},
638 };
640 /* Module pin mux for eCAP0 */
641 static struct pinmux_config ecap0_pin_mux[] = {
642 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
643 {NULL, 0},
644 };
646 static int backlight_enable;
648 #define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
649 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
650 #define AM335XEVM_BT_ENABLE_GPIO GPIO_TO_PIN(1, 31)
652 struct wl12xx_platform_data am335xevm_wlan_data = {
653 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
654 .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
655 .board_tcxo_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
656 };
658 /* Module pin mux for wlan and bluetooth */
659 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
660 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
661 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
662 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
663 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
664 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
665 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
666 {NULL, 0},
667 };
669 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
670 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
671 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
672 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
673 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
674 {NULL, 0},
675 };
677 static struct pinmux_config wl12xx_pin_mux[] = {
678 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
679 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
680 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
681 {NULL, 0},
682 };
684 static void enable_ecap0(int evm_id, int profile)
685 {
686 backlight_enable = true;
687 }
689 static int __init ecap0_init(void)
690 {
691 int status = 0;
693 if (backlight_enable) {
694 setup_pin_mux(ecap0_pin_mux);
696 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
697 if (status < 0)
698 pr_warn("Failed to request gpio for LCD backlight\n");
700 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
701 }
702 return status;
703 }
704 late_initcall(ecap0_init);
706 static int __init conf_disp_pll(int rate)
707 {
708 struct clk *disp_pll;
709 int ret = -EINVAL;
711 disp_pll = clk_get(NULL, "dpll_disp_ck");
712 if (IS_ERR(disp_pll)) {
713 pr_err("Cannot clk_get disp_pll\n");
714 goto out;
715 }
717 ret = clk_set_rate(disp_pll, rate);
718 clk_put(disp_pll);
719 out:
720 return ret;
721 }
723 static void lcdc_init(int evm_id, int profile)
724 {
726 setup_pin_mux(lcdc_pin_mux);
728 if (conf_disp_pll(300000000)) {
729 pr_info("Failed configure display PLL, not attempting to"
730 "register LCDC\n");
731 return;
732 }
734 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
735 pr_info("Failed to register LCDC device\n");
736 return;
737 }
739 static void tsc_init(int evm_id, int profile)
740 {
741 int err;
743 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
744 am335x_touchscreen_data.analog_input = 1;
745 pr_info("TSC connected to beta GP EVM\n");
746 } else {
747 am335x_touchscreen_data.analog_input = 0;
748 pr_info("TSC connected to alpha GP EVM\n");
749 }
750 setup_pin_mux(tsc_pin_mux);
751 err = platform_device_register(&tsc_device);
752 if (err)
753 pr_err("failed to register touchscreen device\n");
754 }
756 static void rgmii1_init(int evm_id, int profile)
757 {
758 setup_pin_mux(rgmii1_pin_mux);
759 return;
760 }
762 static void rgmii2_init(int evm_id, int profile)
763 {
764 setup_pin_mux(rgmii2_pin_mux);
765 return;
766 }
768 static void mii1_init(int evm_id, int profile)
769 {
770 setup_pin_mux(mii1_pin_mux);
771 return;
772 }
774 static void rmii1_init(int evm_id, int profile)
775 {
776 setup_pin_mux(rmii1_pin_mux);
777 return;
778 }
780 static void usb0_init(int evm_id, int profile)
781 {
782 setup_pin_mux(usb0_pin_mux);
783 return;
784 }
786 static void usb1_init(int evm_id, int profile)
787 {
788 setup_pin_mux(usb1_pin_mux);
789 return;
790 }
792 /* setup uart3 */
793 static void uart3_init(int evm_id, int profile)
794 {
795 setup_pin_mux(uart3_pin_mux);
796 return;
797 }
799 /* NAND partition information */
800 static struct mtd_partition am335x_nand_partitions[] = {
801 /* All the partition sizes are listed in terms of NAND block size */
802 {
803 .name = "SPL",
804 .offset = 0, /* Offset = 0x0 */
805 .size = SZ_128K,
806 },
807 {
808 .name = "SPL.backup1",
809 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
810 .size = SZ_128K,
811 },
812 {
813 .name = "SPL.backup2",
814 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
815 .size = SZ_128K,
816 },
817 {
818 .name = "SPL.backup3",
819 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
820 .size = SZ_128K,
821 },
822 {
823 .name = "U-Boot",
824 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
825 .size = 15 * SZ_128K,
826 },
827 {
828 .name = "U-Boot Env",
829 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
830 .size = 1 * SZ_128K,
831 },
832 {
833 .name = "Kernel",
834 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
835 .size = 40 * SZ_128K,
836 },
837 {
838 .name = "File System",
839 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
840 .size = MTDPART_SIZ_FULL,
841 },
842 };
844 /* SPI 0/1 Platform Data */
845 /* SPI flash information */
846 static struct mtd_partition am335x_spi_partitions[] = {
847 /* All the partition sizes are listed in terms of erase size */
848 {
849 .name = "SPL",
850 .offset = 0, /* Offset = 0x0 */
851 .size = SZ_128K,
852 },
853 {
854 .name = "U-Boot",
855 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
856 .size = 2 * SZ_128K,
857 },
858 {
859 .name = "U-Boot Env",
860 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
861 .size = 2 * SZ_4K,
862 },
863 {
864 .name = "Kernel",
865 .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
866 .size = 28 * SZ_128K,
867 },
868 {
869 .name = "File System",
870 .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
871 .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
872 }
873 };
875 static const struct flash_platform_data am335x_spi_flash = {
876 .type = "w25q64",
877 .name = "spi_flash",
878 .parts = am335x_spi_partitions,
879 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
880 };
882 /*
883 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
884 * So setup Max speed to be less than that of Controller speed
885 */
886 static struct spi_board_info am335x_spi0_slave_info[] = {
887 {
888 .modalias = "m25p80",
889 .platform_data = &am335x_spi_flash,
890 .irq = -1,
891 .max_speed_hz = 24000000,
892 .bus_num = 1,
893 .chip_select = 0,
894 },
895 };
897 static struct spi_board_info am335x_spi1_slave_info[] = {
898 {
899 .modalias = "m25p80",
900 .platform_data = &am335x_spi_flash,
901 .irq = -1,
902 .max_speed_hz = 12000000,
903 .bus_num = 2,
904 .chip_select = 0,
905 },
906 };
908 static void evm_nand_init(int evm_id, int profile)
909 {
910 setup_pin_mux(nand_pin_mux);
911 board_nand_init(am335x_nand_partitions,
912 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
913 }
915 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
916 {
917 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
918 },
919 };
921 static void i2c1_init(int evm_id, int profile)
922 {
923 setup_pin_mux(i2c1_pin_mux);
924 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
925 ARRAY_SIZE(am335x_i2c_boardinfo1));
926 return;
927 }
929 /* Setup McASP 1 */
930 static void mcasp1_init(int evm_id, int profile)
931 {
932 /* Configure McASP */
933 setup_pin_mux(mcasp1_pin_mux);
934 am335x_register_mcasp1(&am335x_evm_snd_data1);
935 return;
936 }
938 static void mmc1_init(int evm_id, int profile)
939 {
940 setup_pin_mux(mmc1_pin_mux);
942 am335x_mmc[1].mmc = 2;
943 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
944 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
945 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
946 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
948 /* mmc will be initialized when mmc0_init is called */
949 return;
950 }
952 static void mmc2_wl12xx_init(int evm_id, int profile)
953 {
954 setup_pin_mux(mmc2_wl12xx_pin_mux);
956 am335x_mmc[1].mmc = 3;
957 am335x_mmc[1].name = "wl1271";
958 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
959 | MMC_PM_KEEP_POWER;
960 am335x_mmc[1].nonremovable = true;
961 am335x_mmc[1].gpio_cd = -EINVAL;
962 am335x_mmc[1].gpio_wp = -EINVAL;
963 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
965 /* mmc will be initialized when mmc0_init is called */
966 return;
967 }
969 static void uart1_wl12xx_init(int evm_id, int profile)
970 {
971 setup_pin_mux(uart1_wl12xx_pin_mux);
972 }
974 static void wl12xx_bluetooth_enable(void)
975 {
976 int status = gpio_request(AM335XEVM_BT_ENABLE_GPIO, "bt_en\n");
977 if (status < 0)
978 pr_err("Failed to request gpio for bt_enable");
980 pr_info("Enable bluetooth...\n");
981 gpio_direction_output(AM335XEVM_BT_ENABLE_GPIO, 0);
982 msleep(1);
983 gpio_set_value(AM335XEVM_BT_ENABLE_GPIO, 1);
984 }
986 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
987 {
988 if (on)
989 gpio_set_value(AM335XEVM_WLAN_PMENA_GPIO, 1);
990 else
991 gpio_set_value(AM335XEVM_WLAN_PMENA_GPIO, 0);
993 return 0;
994 }
996 static void wl12xx_init(int evm_id, int profile)
997 {
998 struct device *dev;
999 struct omap_mmc_platform_data *pdata;
1000 int ret;
1002 wl12xx_bluetooth_enable();
1004 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1005 pr_err("error setting wl12xx data\n");
1007 dev = am335x_mmc[1].dev;
1008 if (!dev) {
1009 pr_err("wl12xx mmc device initialization failed\n");
1010 goto out;
1011 }
1013 pdata = dev->platform_data;
1014 if (!pdata) {
1015 pr_err("Platfrom data of wl12xx device not set\n");
1016 goto out;
1017 }
1019 ret = gpio_request_one(AM335XEVM_WLAN_PMENA_GPIO, GPIOF_OUT_INIT_LOW,
1020 "wlan_en");
1021 if (ret) {
1022 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1023 goto out;
1024 }
1026 setup_pin_mux(wl12xx_pin_mux);
1028 pdata->slots[0].set_power = wl12xx_set_power;
1029 out:
1030 return;
1031 }
1033 static void mmc0_init(int evm_id, int profile)
1034 {
1035 setup_pin_mux(mmc0_pin_mux);
1037 omap2_hsmmc_init(am335x_mmc);
1038 return;
1039 }
1041 static void mmc0_no_cd_init(int evm_id, int profile)
1042 {
1043 setup_pin_mux(mmc0_no_cd_pin_mux);
1045 omap2_hsmmc_init(am335x_mmc);
1046 return;
1047 }
1050 /* setup spi0 */
1051 static void spi0_init(int evm_id, int profile)
1052 {
1053 setup_pin_mux(spi0_pin_mux);
1054 spi_register_board_info(am335x_spi0_slave_info,
1055 ARRAY_SIZE(am335x_spi0_slave_info));
1056 return;
1057 }
1059 /* setup spi1 */
1060 static void spi1_init(int evm_id, int profile)
1061 {
1062 setup_pin_mux(spi1_pin_mux);
1063 spi_register_board_info(am335x_spi1_slave_info,
1064 ARRAY_SIZE(am335x_spi1_slave_info));
1065 return;
1066 }
1069 static int beaglebone_phy_fixup(struct phy_device *phydev)
1070 {
1071 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1072 SUPPORTED_100baseT_Full);
1074 return 0;
1075 }
1077 #ifdef CONFIG_TLK110_WORKAROUND
1078 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1079 {
1080 unsigned int val;
1082 /* This is done as a workaround to support TLK110 rev1.0 phy */
1083 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1084 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1086 val = phy_read(phydev, TLK110_LPFHPF_REG);
1087 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1089 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1090 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1092 val = phy_read(phydev, TLK110_VRCR_REG);
1093 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1095 val = phy_read(phydev, TLK110_SETFFE_REG);
1096 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1098 val = phy_read(phydev, TLK110_FTSP_REG);
1099 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1101 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1102 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1104 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1105 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1107 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1108 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1110 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1111 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1113 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1114 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1116 val = phy_read(phydev, TLK110_CFGPS_REG);
1117 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1119 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1120 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1122 val = phy_read(phydev, TLK110_SWSCR3_REG);
1123 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1125 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1126 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1128 val = phy_read(phydev, TLK110_PHYRCR_REG);
1129 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1131 return 0;
1132 }
1133 #endif
1136 /* Low-Cost EVM */
1137 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1138 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1139 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1140 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1141 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1142 {NULL, 0, 0},
1143 };
1145 /* General Purpose EVM */
1146 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1147 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1148 PROFILE_2 | PROFILE_7) },
1149 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1150 PROFILE_2 | PROFILE_7) },
1151 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1152 PROFILE_2 | PROFILE_7) },
1153 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1154 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1155 PROFILE_4 | PROFILE_6) },
1156 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1157 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1158 {evm_nand_init, DEV_ON_DGHTR_BRD,
1159 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1160 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1161 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1162 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1163 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1164 PROFILE_5)},
1165 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1166 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1167 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1168 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1169 PROFILE_5)},
1170 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1171 {NULL, 0, 0},
1172 };
1174 /* Industrial Auto Motor Control EVM */
1175 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1176 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1177 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1178 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1179 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1180 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1181 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1182 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1183 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1184 {NULL, 0, 0},
1185 };
1187 /* IP-Phone EVM */
1188 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1189 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1190 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1191 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1192 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1193 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1194 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1195 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1196 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1197 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1198 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1199 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1200 {NULL, 0, 0},
1201 };
1203 /* Beaglebone < Rev A3 */
1204 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1205 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1206 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1207 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1208 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1209 {NULL, 0, 0},
1210 };
1212 /* Beaglebone Rev A3 and after */
1213 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1214 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1215 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1216 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1217 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1218 {NULL, 0, 0},
1219 };
1221 static void setup_low_cost_evm(void)
1222 {
1223 pr_info("The board is a AM335x Low Cost EVM.\n");
1225 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1226 }
1228 static void setup_general_purpose_evm(void)
1229 {
1230 u32 prof_sel = am335x_get_profile_selection();
1231 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1233 if (!strncmp("1.1A", config.version, 4)) {
1234 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1235 } else if (!strncmp("1.0", config.version, 3)) {
1236 gp_evm_revision = GP_EVM_REV_IS_1_0;
1237 } else {
1238 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1239 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1240 }
1242 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1243 gigabit_enable = 0;
1244 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1245 gigabit_enable = 1;
1247 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1248 }
1250 static void setup_ind_auto_motor_ctrl_evm(void)
1251 {
1252 u32 prof_sel = am335x_get_profile_selection();
1254 pr_info("The board is an industrial automation EVM in profile %d\n",
1255 prof_sel);
1257 /* Only Profile 0 is supported */
1258 if ((1L << prof_sel) != PROFILE_0) {
1259 pr_err("AM335X: Only Profile 0 is supported\n");
1260 pr_err("Assuming profile 0 & continuing\n");
1261 prof_sel = PROFILE_0;
1262 }
1264 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1265 PROFILE_0);
1267 /* Fillup global evmid */
1268 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1270 /* Initialize TLK110 PHY registers for phy version 1.0 */
1271 am335x_tlk110_phy_init();
1274 }
1276 static void setup_ip_phone_evm(void)
1277 {
1278 pr_info("The board is an IP phone EVM\n");
1280 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1281 }
1283 /* BeagleBone < Rev A3 */
1284 static void setup_beaglebone_old(void)
1285 {
1286 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1288 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1289 am335x_mmc[0].gpio_wp = -EINVAL;
1291 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1293 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1294 beaglebone_phy_fixup);
1295 }
1297 /* BeagleBone after Rev A3 */
1298 static void setup_beaglebone(void)
1299 {
1300 pr_info("The board is a AM335x Beaglebone.\n");
1302 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1303 am335x_mmc[0].gpio_wp = -EINVAL;
1305 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1306 }
1309 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1310 {
1311 u8 tmp;
1312 int ret;
1314 /*
1315 * try reading a byte from the EEPROM to see if it is
1316 * present. We could read a lot more, but that would
1317 * just slow the boot process and we have all the information
1318 * we need from the EEPROM on the base board anyway.
1319 */
1320 ret = m->read(m, &tmp, 0, sizeof(u8));
1321 if (ret == sizeof(u8)) {
1322 pr_info("Detected a daughter card on AM335x EVM..");
1323 daughter_brd_detected = true;
1324 } else {
1325 pr_info("No daughter card found\n");
1326 daughter_brd_detected = false;
1327 }
1328 }
1330 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1331 {
1332 int ret;
1333 char tmp[10];
1335 /* 1st get the MAC address from EEPROM */
1336 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1337 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1339 if (ret != sizeof(am335x_mac_addr)) {
1340 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1341 return;
1342 }
1344 /* Fillup global mac id */
1345 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1346 &am335x_mac_addr[1][0]);
1348 /* get board specific data */
1349 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1350 if (ret != sizeof(config)) {
1351 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1352 return;
1353 }
1355 if (config.header != AM335X_EEPROM_HEADER) {
1356 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1357 config.header, AM335X_EEPROM_HEADER);
1358 goto out;
1359 }
1361 if (strncmp("A335", config.name, 4)) {
1362 pr_err("Board %s doesn't look like an AM335x board\n",
1363 config.name);
1364 goto out;
1365 }
1367 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1368 pr_info("Board name: %s\n", tmp);
1369 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1370 pr_info("Board version: %s\n", tmp);
1372 if (!strncmp("A335BONE", config.name, 8)) {
1373 daughter_brd_detected = false;
1374 if(!strncmp("00A1", config.version, 4) ||
1375 !strncmp("00A2", config.version, 4))
1376 setup_beaglebone_old();
1377 else
1378 setup_beaglebone();
1379 } else {
1380 /* only 6 characters of options string used for now */
1381 snprintf(tmp, 7, "%s", config.opt);
1382 pr_info("SKU: %s\n", tmp);
1384 if (!strncmp("SKU#00", config.opt, 6))
1385 setup_low_cost_evm();
1386 else if (!strncmp("SKU#01", config.opt, 6))
1387 setup_general_purpose_evm();
1388 else if (!strncmp("SKU#02", config.opt, 6))
1389 setup_ind_auto_motor_ctrl_evm();
1390 else if (!strncmp("SKU#03", config.opt, 6))
1391 setup_ip_phone_evm();
1392 else
1393 goto out;
1394 }
1395 /* Initialize cpsw after board detection is completed as board
1396 * information is required for configuring phy address and hence
1397 * should be call only after board detection
1398 */
1399 am33xx_cpsw_init(gigabit_enable);
1401 return;
1402 out:
1403 /*
1404 * If the EEPROM hasn't been programed or an incorrect header
1405 * or board name are read, assume this is an old beaglebone board
1406 * (< Rev A3)
1407 */
1408 pr_err("Could not detect any board, falling back to: "
1409 "Beaglebone (< Rev A3) with no daughter card connected\n");
1410 daughter_brd_detected = false;
1411 setup_beaglebone_old();
1413 /* Initialize cpsw after board detection is completed as board
1414 * information is required for configuring phy address and hence
1415 * should be call only after board detection
1416 */
1418 am33xx_cpsw_init(gigabit_enable);
1419 }
1421 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1422 .byte_len = (256*1024) / 8,
1423 .page_size = 64,
1424 .flags = AT24_FLAG_ADDR16,
1425 .setup = am335x_setup_daughter_board,
1426 .context = (void *)NULL,
1427 };
1429 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1430 .byte_len = (256*1024) / 8,
1431 .page_size = 64,
1432 .flags = AT24_FLAG_ADDR16,
1433 .setup = am335x_evm_setup,
1434 .context = (void *)NULL,
1435 };
1437 /*
1438 * Daughter board Detection.
1439 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1440 * machine init, starting from daughter board and ending with baseboard.
1441 * Assumptions :
1442 * 1. probe for i2c devices are called in the order they are included in
1443 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
1444 * eeprom probe is called last.
1445 */
1446 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1447 {
1448 /* Daughter Board EEPROM */
1449 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1450 .platform_data = &am335x_daughter_board_eeprom_info,
1451 },
1452 {
1453 /* Baseboard board EEPROM */
1454 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1455 .platform_data = &am335x_baseboard_eeprom_info,
1456 },
1457 {
1458 I2C_BOARD_INFO("cpld_reg", 0x35),
1459 },
1460 {
1461 I2C_BOARD_INFO("tlc59108", 0x40),
1462 },
1464 };
1466 static struct omap_musb_board_data musb_board_data = {
1467 .interface_type = MUSB_INTERFACE_ULPI,
1468 .mode = MUSB_OTG,
1469 .power = 500,
1470 .instances = 1,
1471 };
1473 static int cpld_reg_probe(struct i2c_client *client,
1474 const struct i2c_device_id *id)
1475 {
1476 cpld_client = client;
1477 return 0;
1478 }
1480 static int __devexit cpld_reg_remove(struct i2c_client *client)
1481 {
1482 cpld_client = NULL;
1483 return 0;
1484 }
1486 static const struct i2c_device_id cpld_reg_id[] = {
1487 { "cpld_reg", 0 },
1488 { }
1489 };
1491 static struct i2c_driver cpld_reg_driver = {
1492 .driver = {
1493 .name = "cpld_reg",
1494 },
1495 .probe = cpld_reg_probe,
1496 .remove = cpld_reg_remove,
1497 .id_table = cpld_reg_id,
1498 };
1500 static void evm_init_cpld(void)
1501 {
1502 i2c_add_driver(&cpld_reg_driver);
1503 }
1505 static void __init am335x_evm_i2c_init(void)
1506 {
1507 /* Initially assume Low Cost EVM Config */
1508 am335x_evm_id = LOW_COST_EVM;
1510 evm_init_cpld();
1512 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1513 ARRAY_SIZE(am335x_i2c_boardinfo));
1514 }
1516 static struct resource am335x_rtc_resources[] = {
1517 {
1518 .start = AM33XX_RTC_BASE,
1519 .end = AM33XX_RTC_BASE + SZ_4K - 1,
1520 .flags = IORESOURCE_MEM,
1521 },
1522 { /* timer irq */
1523 .start = AM33XX_IRQ_RTC_TIMER,
1524 .end = AM33XX_IRQ_RTC_TIMER,
1525 .flags = IORESOURCE_IRQ,
1526 },
1527 { /* alarm irq */
1528 .start = AM33XX_IRQ_RTC_ALARM,
1529 .end = AM33XX_IRQ_RTC_ALARM,
1530 .flags = IORESOURCE_IRQ,
1531 },
1532 };
1534 static struct platform_device am335x_rtc_device = {
1535 .name = "omap_rtc",
1536 .id = -1,
1537 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
1538 .resource = am335x_rtc_resources,
1539 };
1541 static int am335x_rtc_init(void)
1542 {
1543 void __iomem *base;
1544 struct clk *clk;
1546 clk = clk_get(NULL, "rtc_fck");
1547 if (IS_ERR(clk)) {
1548 pr_err("rtc : Failed to get RTC clock\n");
1549 return -1;
1550 }
1552 if (clk_enable(clk)) {
1553 pr_err("rtc: Clock Enable Failed\n");
1554 return -1;
1555 }
1557 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1559 if (WARN_ON(!base))
1560 return -ENOMEM;
1562 /* Unlock the rtc's registers */
1563 __raw_writel(0x83e70b13, base + 0x6c);
1564 __raw_writel(0x95a4f1e0, base + 0x70);
1566 /*
1567 * Enable the 32K OSc
1568 * TODO: Need a better way to handle this
1569 * Since we want the clock to be running before mmc init
1570 * we need to do it before the rtc probe happens
1571 */
1572 __raw_writel(0x48, base + 0x54);
1574 iounmap(base);
1576 return platform_device_register(&am335x_rtc_device);
1577 }
1579 /* Enable clkout2 */
1580 static struct pinmux_config clkout2_pin_mux[] = {
1581 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1582 {NULL, 0},
1583 };
1585 static void __init clkout2_enable(void)
1586 {
1587 struct clk *ck_32;
1589 ck_32 = clk_get(NULL, "clkout2_ck");
1590 if (IS_ERR(ck_32)) {
1591 pr_err("Cannot clk_get ck_32\n");
1592 return;
1593 }
1595 clk_enable(ck_32);
1597 setup_pin_mux(clkout2_pin_mux);
1598 }
1600 static void __init am335x_evm_init(void)
1601 {
1602 am33xx_mux_init(board_mux);
1603 omap_serial_init();
1604 am335x_rtc_init();
1605 clkout2_enable();
1606 am335x_evm_i2c_init();
1607 omap_sdrc_init(NULL, NULL);
1608 usb_musb_init(&musb_board_data);
1609 omap_board_config = am335x_evm_config;
1610 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1611 }
1613 static void __init am335x_evm_map_io(void)
1614 {
1615 omap2_set_globals_am33xx();
1616 omapam33xx_map_common_io();
1617 }
1619 MACHINE_START(AM335XEVM, "am335xevm")
1620 /* Maintainer: Texas Instruments */
1621 .atag_offset = 0x100,
1622 .map_io = am335x_evm_map_io,
1623 .init_early = am33xx_init_early,
1624 .init_irq = ti81xx_init_irq,
1625 .handle_irq = omap3_intc_handle_irq,
1626 .timer = &omap3_am33xx_timer,
1627 .init_machine = am335x_evm_init,
1628 MACHINE_END
1630 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1631 /* Maintainer: Texas Instruments */
1632 .atag_offset = 0x100,
1633 .map_io = am335x_evm_map_io,
1634 .init_irq = ti81xx_init_irq,
1635 .init_early = am33xx_init_early,
1636 .timer = &omap3_am33xx_timer,
1637 .init_machine = am335x_evm_init,
1638 MACHINE_END