1 /*
2 * Code for AM335X EVM.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/i2c/at24.h>
20 #include <linux/phy.h>
21 #include <linux/gpio.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/input/matrix_keypad.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/wl12xx.h>
34 #include <linux/ethtool.h>
36 /* LCD controller is similar to DA850 */
37 #include <video/da8xx-fb.h>
39 #include <mach/hardware.h>
40 #include <mach/board-am335xevm.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/map.h>
45 #include <asm/hardware/asp.h>
47 #include <plat/irqs.h>
48 #include <plat/board.h>
49 #include <plat/common.h>
50 #include <plat/lcdc.h>
51 #include <plat/usb.h>
52 #include <plat/mmc.h>
54 #include "board-flash.h"
55 #include "mux.h"
56 #include "devices.h"
57 #include "hsmmc.h"
59 /* Convert GPIO signal to GPIO pin number */
60 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
62 /* TLK PHY IDs */
63 #define TLK110_PHY_ID 0x2000A201
64 #define TLK110_PHY_MASK 0xfffffff0
66 /* BBB PHY IDs */
67 #define BBB_PHY_ID 0x7c0f1
68 #define BBB_PHY_MASK 0xfffffffe
70 /* TLK110 PHY register offsets */
71 #define TLK110_COARSEGAIN_REG 0x00A3
72 #define TLK110_LPFHPF_REG 0x00AC
73 #define TLK110_SPAREANALOG_REG 0x00B9
74 #define TLK110_VRCR_REG 0x00D0
75 #define TLK110_SETFFE_REG 0x0107
76 #define TLK110_FTSP_REG 0x0154
77 #define TLK110_ALFATPIDL_REG 0x002A
78 #define TLK110_PSCOEF21_REG 0x0096
79 #define TLK110_PSCOEF3_REG 0x0097
80 #define TLK110_ALFAFACTOR1_REG 0x002C
81 #define TLK110_ALFAFACTOR2_REG 0x0023
82 #define TLK110_CFGPS_REG 0x0095
83 #define TLK110_FTSPTXGAIN_REG 0x0150
84 #define TLK110_SWSCR3_REG 0x000B
85 #define TLK110_SCFALLBACK_REG 0x0040
86 #define TLK110_PHYRCR_REG 0x001F
88 /* TLK110 register writes values */
89 #define TLK110_COARSEGAIN_VAL 0x0000
90 #define TLK110_LPFHPF_VAL 0x8000
91 #define TLK110_SPANALOG_VAL 0x0000
92 #define TLK110_VRCR_VAL 0x0008
93 #define TLK110_SETFFE_VAL 0x0605
94 #define TLK110_FTSP_VAL 0x0255
95 #define TLK110_ALFATPIDL_VAL 0x7998
96 #define TLK110_PSCOEF21_VAL 0x3A20
97 #define TLK110_PSCOEF3_VAL 0x003F
98 #define TLK110_ALFACTOR1_VAL 0xFF80
99 #define TLK110_ALFACTOR2_VAL 0x021C
100 #define TLK110_CFGPS_VAL 0x0000
101 #define TLK110_FTSPTXGAIN_VAL 0x6A88
102 #define TLK110_SWSCR3_VAL 0x0000
103 #define TLK110_SCFALLBACK_VAL 0xC11D
104 #define TLK110_PHYRCR_VAL 0x4000
106 #ifdef CONFIG_TLK110_WORKAROUND
107 #define am335x_tlk110_phy_init()\
108 do { \
109 phy_register_fixup_for_uid(TLK110_PHY_ID,\
110 TLK110_PHY_MASK,\
111 am335x_tlk110_phy_fixup);\
112 } while (0);
113 #else
114 #define am335x_tlk110_phy_init() do { } while (0);
115 #endif
117 static const struct display_panel disp_panel = {
118 WVGA,
119 32,
120 32,
121 COLOR_ACTIVE,
122 };
124 static struct lcd_ctrl_config lcd_cfg = {
125 &disp_panel,
126 .ac_bias = 255,
127 .ac_bias_intrpt = 0,
128 .dma_burst_sz = 16,
129 .bpp = 32,
130 .fdd = 0x80,
131 .tft_alt_mode = 0,
132 .stn_565_mode = 0,
133 .mono_8bit_mode = 0,
134 .invert_line_clock = 1,
135 .invert_frm_clock = 1,
136 .sync_edge = 0,
137 .sync_ctrl = 1,
138 .raster_order = 0,
139 };
141 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
142 .manu_name = "ThreeFive",
143 .controller_data = &lcd_cfg,
144 .type = "TFC_S9700RTWV35TR_01B",
145 };
147 #include "common.h"
149 /* TSc controller */
150 #include <linux/input/ti_tscadc.h>
151 #include <linux/lis3lv02d.h>
153 static struct resource tsc_resources[] = {
154 [0] = {
155 .start = AM33XX_TSC_BASE,
156 .end = AM33XX_TSC_BASE + SZ_8K - 1,
157 .flags = IORESOURCE_MEM,
158 },
159 [1] = {
160 .start = AM33XX_IRQ_ADC_GEN,
161 .end = AM33XX_IRQ_ADC_GEN,
162 .flags = IORESOURCE_IRQ,
163 },
164 };
166 static struct tsc_data am335x_touchscreen_data = {
167 .wires = 4,
168 .x_plate_resistance = 200,
169 };
171 static struct platform_device tsc_device = {
172 .name = "tsc",
173 .id = -1,
174 .dev = {
175 .platform_data = &am335x_touchscreen_data,
176 },
177 .num_resources = ARRAY_SIZE(tsc_resources),
178 .resource = tsc_resources,
179 };
181 static u8 am335x_iis_serializer_direction1[] = {
182 INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
183 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
184 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
185 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
186 };
188 static struct snd_platform_data am335x_evm_snd_data1 = {
189 .tx_dma_offset = 0x46400000, /* McASP1 */
190 .rx_dma_offset = 0x46400000,
191 .op_mode = DAVINCI_MCASP_IIS_MODE,
192 .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
193 .tdm_slots = 2,
194 .serial_dir = am335x_iis_serializer_direction1,
195 .asp_chan_q = EVENTQ_2,
196 .version = MCASP_VERSION_3,
197 .txnumevt = 1,
198 .rxnumevt = 1,
199 };
201 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
202 {
203 .mmc = 1,
204 .caps = MMC_CAP_4_BIT_DATA,
205 .gpio_cd = GPIO_TO_PIN(0, 6),
206 .gpio_wp = GPIO_TO_PIN(3, 18),
207 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
208 },
209 {
210 .mmc = 0, /* will be set at runtime */
211 },
212 {
213 .mmc = 0, /* will be set at runtime */
214 },
215 {} /* Terminator */
216 };
219 #ifdef CONFIG_OMAP_MUX
220 static struct omap_board_mux board_mux[] __initdata = {
221 AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
222 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
223 AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
224 AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
225 { .reg_offset = OMAP_MUX_TERMINATOR },
226 };
227 #else
228 #define board_mux NULL
229 #endif
231 /* module pin mux structure */
232 struct pinmux_config {
233 const char *string_name; /* signal name format */
234 int val; /* Options for the mux register value */
235 };
237 struct evm_dev_cfg {
238 void (*device_init)(int evm_id, int profile);
240 /*
241 * If the device is required on both baseboard & daughter board (ex i2c),
242 * specify DEV_ON_BASEBOARD
243 */
244 #define DEV_ON_BASEBOARD 0
245 #define DEV_ON_DGHTR_BRD 1
246 u32 device_on;
248 u32 profile; /* Profiles (0-7) in which the module is present */
249 };
251 /* AM335X - CPLD Register Offsets */
252 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
253 #define CPLD_DEVICE_ID 0x04 /* CPLD identification */
254 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
255 #define CPLD_CFG_REG 0x10 /* Configuration Register */
257 static struct i2c_client *cpld_client;
258 static u32 am335x_evm_id;
259 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
260 };
262 /*
263 * EVM Config held in On-Board eeprom device.
264 *
265 * Header Format
266 *
267 * Name Size Contents
268 * (Bytes)
269 *-------------------------------------------------------------
270 * Header 4 0xAA, 0x55, 0x33, 0xEE
271 *
272 * Board Name 8 Name for board in ASCII.
273 * example "A33515BB" = "AM335X
274 Low Cost EVM board"
275 *
276 * Version 4 Hardware version code for board in
277 * in ASCII. "1.0A" = rev.01.0A
278 *
279 * Serial Number 12 Serial number of the board. This is a 12
280 * character string which is WWYY4P16nnnn, where
281 * WW = 2 digit week of the year of production
282 * YY = 2 digit year of production
283 * nnnn = incrementing board number
284 *
285 * Configuration option 32 Codes(TBD) to show the configuration
286 * setup on this board.
287 *
288 * Available 32720 Available space for other non-volatile
289 * data.
290 */
291 struct am335x_evm_eeprom_config {
292 u32 header;
293 u8 name[8];
294 char version[4];
295 u8 serial[12];
296 u8 opt[32];
297 };
299 static struct am335x_evm_eeprom_config config;
300 static bool daughter_brd_detected;
302 #define GP_EVM_REV_IS_1_0 0x1
303 #define GP_EVM_REV_IS_1_1A 0x2
304 #define GP_EVM_REV_IS_UNKNOWN 0xFF
305 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
306 unsigned int gigabit_enable = 1;
308 #define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
309 #define EEPROM_NO_OF_MAC_ADDR 3
310 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
312 #define AM335X_EEPROM_HEADER 0xEE3355AA
314 /* current profile if exists else PROFILE_0 on error */
315 static u32 am335x_get_profile_selection(void)
316 {
317 int val = 0;
319 if (!cpld_client)
320 /* error checking is not done in func's calling this routine.
321 so return profile 0 on error */
322 return 0;
324 val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
325 if (val < 0)
326 return 0; /* default to Profile 0 on Error */
327 else
328 return val & 0x7;
329 }
331 /* Module pin mux for LCDC */
332 static struct pinmux_config lcdc_pin_mux[] = {
333 {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
334 | AM33XX_PULL_DISA},
335 {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
336 | AM33XX_PULL_DISA},
337 {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
338 | AM33XX_PULL_DISA},
339 {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
340 | AM33XX_PULL_DISA},
341 {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
342 | AM33XX_PULL_DISA},
343 {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
344 | AM33XX_PULL_DISA},
345 {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
346 | AM33XX_PULL_DISA},
347 {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
348 | AM33XX_PULL_DISA},
349 {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
350 | AM33XX_PULL_DISA},
351 {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
352 | AM33XX_PULL_DISA},
353 {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
354 | AM33XX_PULL_DISA},
355 {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
356 | AM33XX_PULL_DISA},
357 {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
358 | AM33XX_PULL_DISA},
359 {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
360 | AM33XX_PULL_DISA},
361 {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
362 | AM33XX_PULL_DISA},
363 {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
364 | AM33XX_PULL_DISA},
365 {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
366 {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
367 {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
368 {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
369 {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
370 {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
371 {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
372 {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
373 {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
374 {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
375 {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
376 {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
377 {NULL, 0},
378 };
380 static struct pinmux_config tsc_pin_mux[] = {
381 {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
382 {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
383 {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
384 {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
385 {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
386 {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
387 {NULL, 0},
388 };
390 /* Pin mux for nand flash module */
391 static struct pinmux_config nand_pin_mux[] = {
392 {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
393 {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
394 {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
395 {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
396 {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
397 {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
398 {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
399 {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
400 {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
401 {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
402 {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
403 {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
404 {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
405 {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
406 {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
407 {NULL, 0},
408 };
410 /* Module pin mux for SPI fash */
411 static struct pinmux_config spi0_pin_mux[] = {
412 {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
413 | AM33XX_INPUT_EN},
414 {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
415 | AM33XX_INPUT_EN},
416 {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
417 | AM33XX_INPUT_EN},
418 {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
419 | AM33XX_INPUT_EN},
420 {NULL, 0},
421 };
423 /* Module pin mux for SPI flash */
424 static struct pinmux_config spi1_pin_mux[] = {
425 {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
426 | AM33XX_INPUT_EN},
427 {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
428 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
429 {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
430 | AM33XX_INPUT_EN},
431 {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
432 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
433 {NULL, 0},
434 };
436 /* Module pin mux for rgmii1 */
437 static struct pinmux_config rgmii1_pin_mux[] = {
438 {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
439 {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
440 {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
441 {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
442 {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
443 {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
444 {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
445 {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
446 {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
447 {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
448 {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
449 {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
450 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
451 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
452 {NULL, 0},
453 };
455 /* Module pin mux for rgmii2 */
456 static struct pinmux_config rgmii2_pin_mux[] = {
457 {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
458 {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
459 {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
460 {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
461 {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
462 {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
463 {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
464 {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
465 {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
466 {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
467 {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
468 {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
469 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
470 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
471 {NULL, 0},
472 };
474 /* Module pin mux for mii1 */
475 static struct pinmux_config mii1_pin_mux[] = {
476 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
477 {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
478 {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
479 {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
480 {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
481 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
482 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
483 {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
484 {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
485 {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
486 {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
487 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
488 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
489 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
490 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
491 {NULL, 0},
492 };
494 /* Module pin mux for rmii1 */
495 static struct pinmux_config rmii1_pin_mux[] = {
496 {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
497 {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
498 {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
499 {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
500 {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
501 {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
502 {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
503 {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
504 {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
505 {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
506 {NULL, 0},
507 };
509 static struct pinmux_config i2c1_pin_mux[] = {
510 {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
511 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
512 {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
513 AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
514 {NULL, 0},
515 };
517 /* Module pin mux for mcasp1 */
518 static struct pinmux_config mcasp1_pin_mux[] = {
519 {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
520 {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
521 {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
522 {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
523 AM33XX_PIN_INPUT_PULLDOWN},
524 {NULL, 0},
525 };
528 /* Module pin mux for mmc0 */
529 static struct pinmux_config mmc0_pin_mux[] = {
530 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
531 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
532 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
533 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
534 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
535 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
536 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
537 {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
538 {NULL, 0},
539 };
541 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
542 {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
543 {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
544 {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
545 {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
546 {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
547 {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
548 {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
549 {NULL, 0},
550 };
552 /* Module pin mux for mmc1 */
553 static struct pinmux_config mmc1_pin_mux[] = {
554 {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
555 {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
556 {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
557 {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
558 {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
559 {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
560 {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
561 {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
562 {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
563 {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
564 {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
565 {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
566 {NULL, 0},
567 };
569 /* Module pin mux for uart3 */
570 static struct pinmux_config uart3_pin_mux[] = {
571 {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
572 {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
573 {NULL, 0},
574 };
576 static struct pinmux_config d_can_gp_pin_mux[] = {
577 {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
578 {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
579 {NULL, 0},
580 };
582 static struct pinmux_config d_can_ia_pin_mux[] = {
583 {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
584 {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
585 {NULL, 0},
586 };
588 /* Module pin mux for uart2 */
589 static struct pinmux_config uart2_pin_mux[] = {
590 {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
591 AM33XX_PIN_INPUT_PULLUP},
592 {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
593 AM33XX_PULL_DISA |
594 AM33XX_SLEWCTRL_SLOW},
595 {NULL, 0},
596 };
599 /*
600 * @pin_mux - single module pin-mux structure which defines pin-mux
601 * details for all its pins.
602 */
603 static void setup_pin_mux(struct pinmux_config *pin_mux)
604 {
605 int i;
607 for (i = 0; pin_mux->string_name != NULL; pin_mux++)
608 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
610 }
612 /* Matrix GPIO Keypad Support for profile-0 only: TODO */
614 /* pinmux for keypad device */
615 static struct pinmux_config matrix_keypad_pin_mux[] = {
616 {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
617 {"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
618 {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
619 {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
620 {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
621 {NULL, 0},
622 };
624 /* Keys mapping */
625 static const uint32_t am335x_evm_matrix_keys[] = {
626 KEY(0, 0, KEY_MENU),
627 KEY(1, 0, KEY_BACK),
628 KEY(2, 0, KEY_LEFT),
630 KEY(0, 1, KEY_RIGHT),
631 KEY(1, 1, KEY_ENTER),
632 KEY(2, 1, KEY_DOWN),
633 };
635 const struct matrix_keymap_data am335x_evm_keymap_data = {
636 .keymap = am335x_evm_matrix_keys,
637 .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
638 };
640 static const unsigned int am335x_evm_keypad_row_gpios[] = {
641 GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
642 };
644 static const unsigned int am335x_evm_keypad_col_gpios[] = {
645 GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
646 };
648 static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
649 .keymap_data = &am335x_evm_keymap_data,
650 .row_gpios = am335x_evm_keypad_row_gpios,
651 .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
652 .col_gpios = am335x_evm_keypad_col_gpios,
653 .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
654 .active_low = false,
655 .debounce_ms = 5,
656 .col_scan_delay_us = 2,
657 };
659 static struct platform_device am335x_evm_keyboard = {
660 .name = "matrix-keypad",
661 .id = -1,
662 .dev = {
663 .platform_data = &am335x_evm_keypad_platform_data,
664 },
665 };
667 static void matrix_keypad_init(int evm_id, int profile)
668 {
669 int err;
671 setup_pin_mux(matrix_keypad_pin_mux);
672 err = platform_device_register(&am335x_evm_keyboard);
673 if (err) {
674 pr_err("failed to register matrix keypad (2x3) device\n");
675 }
676 }
679 /* pinmux for keypad device */
680 static struct pinmux_config volume_keys_pin_mux[] = {
681 {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
682 {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
683 {NULL, 0},
684 };
686 /* Configure GPIOs for Volume Keys */
687 static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
688 {
689 .code = KEY_VOLUMEUP,
690 .gpio = GPIO_TO_PIN(0, 2),
691 .active_low = true,
692 .desc = "volume-up",
693 .type = EV_KEY,
694 .wakeup = 1,
695 },
696 {
697 .code = KEY_VOLUMEDOWN,
698 .gpio = GPIO_TO_PIN(0, 3),
699 .active_low = true,
700 .desc = "volume-down",
701 .type = EV_KEY,
702 .wakeup = 1,
703 },
704 };
706 static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
707 .buttons = am335x_evm_volume_gpio_buttons,
708 .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
709 };
711 static struct platform_device am335x_evm_volume_keys = {
712 .name = "gpio-keys",
713 .id = -1,
714 .dev = {
715 .platform_data = &am335x_evm_volume_gpio_key_info,
716 },
717 };
719 static void volume_keys_init(int evm_id, int profile)
720 {
721 int err;
723 setup_pin_mux(volume_keys_pin_mux);
724 err = platform_device_register(&am335x_evm_volume_keys);
725 if (err)
726 pr_err("failed to register matrix keypad (2x3) device\n");
727 }
729 /*
730 * @evm_id - evm id which needs to be configured
731 * @dev_cfg - single evm structure which includes
732 * all module inits, pin-mux defines
733 * @profile - if present, else PROFILE_NONE
734 * @dghtr_brd_flg - Whether Daughter board is present or not
735 */
736 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
737 int profile)
738 {
739 int i;
741 /*
742 * Only General Purpose & Industrial Auto Motro Control
743 * EVM has profiles. So check if this evm has profile.
744 * If not, ignore the profile comparison
745 */
747 /*
748 * If the device is on baseboard, directly configure it. Else (device on
749 * Daughter board), check if the daughter card is detected.
750 */
751 if (profile == PROFILE_NONE) {
752 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
753 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
754 dev_cfg->device_init(evm_id, profile);
755 else if (daughter_brd_detected == true)
756 dev_cfg->device_init(evm_id, profile);
757 }
758 } else {
759 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
760 if (dev_cfg->profile & profile) {
761 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
762 dev_cfg->device_init(evm_id, profile);
763 else if (daughter_brd_detected == true)
764 dev_cfg->device_init(evm_id, profile);
765 }
766 }
767 }
768 }
770 #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
772 /* pinmux for usb0 drvvbus */
773 static struct pinmux_config usb0_pin_mux[] = {
774 {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
775 {NULL, 0},
776 };
778 /* pinmux for usb1 drvvbus */
779 static struct pinmux_config usb1_pin_mux[] = {
780 {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
781 {NULL, 0},
782 };
784 /* pinmux for profibus */
785 static struct pinmux_config profibus_pin_mux[] = {
786 {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
787 {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
788 {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
789 {NULL, 0},
790 };
792 /* Module pin mux for eCAP0 */
793 static struct pinmux_config ecap0_pin_mux[] = {
794 {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
795 {NULL, 0},
796 };
798 static int backlight_enable;
800 #define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
801 #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
803 struct wl12xx_platform_data am335xevm_wlan_data = {
804 .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
805 .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
806 };
808 /* Module pin mux for wlan and bluetooth */
809 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
810 {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
811 {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
812 {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
813 {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
814 {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
815 {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
816 {NULL, 0},
817 };
819 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
820 {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
821 {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
822 {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
823 {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
824 {NULL, 0},
825 };
827 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
828 {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
829 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
830 {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
831 {NULL, 0},
832 };
834 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
835 {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
836 {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
837 {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
838 {NULL, 0},
839 };
841 static void enable_ecap0(int evm_id, int profile)
842 {
843 backlight_enable = true;
844 }
846 static int __init ecap0_init(void)
847 {
848 int status = 0;
850 if (backlight_enable) {
851 setup_pin_mux(ecap0_pin_mux);
853 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
854 if (status < 0)
855 pr_warn("Failed to request gpio for LCD backlight\n");
857 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
858 }
859 return status;
860 }
861 late_initcall(ecap0_init);
863 static int __init conf_disp_pll(int rate)
864 {
865 struct clk *disp_pll;
866 int ret = -EINVAL;
868 disp_pll = clk_get(NULL, "dpll_disp_ck");
869 if (IS_ERR(disp_pll)) {
870 pr_err("Cannot clk_get disp_pll\n");
871 goto out;
872 }
874 ret = clk_set_rate(disp_pll, rate);
875 clk_put(disp_pll);
876 out:
877 return ret;
878 }
880 static void lcdc_init(int evm_id, int profile)
881 {
883 setup_pin_mux(lcdc_pin_mux);
885 if (conf_disp_pll(300000000)) {
886 pr_info("Failed configure display PLL, not attempting to"
887 "register LCDC\n");
888 return;
889 }
891 if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
892 pr_info("Failed to register LCDC device\n");
893 return;
894 }
896 static void tsc_init(int evm_id, int profile)
897 {
898 int err;
900 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
901 am335x_touchscreen_data.analog_input = 1;
902 pr_info("TSC connected to beta GP EVM\n");
903 } else {
904 am335x_touchscreen_data.analog_input = 0;
905 pr_info("TSC connected to alpha GP EVM\n");
906 }
907 setup_pin_mux(tsc_pin_mux);
908 err = platform_device_register(&tsc_device);
909 if (err)
910 pr_err("failed to register touchscreen device\n");
911 }
913 static void rgmii1_init(int evm_id, int profile)
914 {
915 setup_pin_mux(rgmii1_pin_mux);
916 return;
917 }
919 static void rgmii2_init(int evm_id, int profile)
920 {
921 setup_pin_mux(rgmii2_pin_mux);
922 return;
923 }
925 static void mii1_init(int evm_id, int profile)
926 {
927 setup_pin_mux(mii1_pin_mux);
928 return;
929 }
931 static void rmii1_init(int evm_id, int profile)
932 {
933 setup_pin_mux(rmii1_pin_mux);
934 return;
935 }
937 static void usb0_init(int evm_id, int profile)
938 {
939 setup_pin_mux(usb0_pin_mux);
940 return;
941 }
943 static void usb1_init(int evm_id, int profile)
944 {
945 setup_pin_mux(usb1_pin_mux);
946 return;
947 }
949 /* setup uart3 */
950 static void uart3_init(int evm_id, int profile)
951 {
952 setup_pin_mux(uart3_pin_mux);
953 return;
954 }
956 /* setup uart2 */
957 static void uart2_init(int evm_id, int profile)
958 {
959 setup_pin_mux(uart2_pin_mux);
960 return;
961 }
963 /* NAND partition information */
964 static struct mtd_partition am335x_nand_partitions[] = {
965 /* All the partition sizes are listed in terms of NAND block size */
966 {
967 .name = "SPL",
968 .offset = 0, /* Offset = 0x0 */
969 .size = SZ_128K,
970 },
971 {
972 .name = "SPL.backup1",
973 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
974 .size = SZ_128K,
975 },
976 {
977 .name = "SPL.backup2",
978 .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
979 .size = SZ_128K,
980 },
981 {
982 .name = "SPL.backup3",
983 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
984 .size = SZ_128K,
985 },
986 {
987 .name = "U-Boot",
988 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
989 .size = 15 * SZ_128K,
990 },
991 {
992 .name = "U-Boot Env",
993 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
994 .size = 1 * SZ_128K,
995 },
996 {
997 .name = "Kernel",
998 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
999 .size = 40 * SZ_128K,
1000 },
1001 {
1002 .name = "File System",
1003 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
1004 .size = MTDPART_SIZ_FULL,
1005 },
1006 };
1008 /* SPI 0/1 Platform Data */
1009 /* SPI flash information */
1010 static struct mtd_partition am335x_spi_partitions[] = {
1011 /* All the partition sizes are listed in terms of erase size */
1012 {
1013 .name = "SPL",
1014 .offset = 0, /* Offset = 0x0 */
1015 .size = SZ_128K,
1016 },
1017 {
1018 .name = "U-Boot",
1019 .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
1020 .size = 2 * SZ_128K,
1021 },
1022 {
1023 .name = "U-Boot Env",
1024 .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
1025 .size = 2 * SZ_4K,
1026 },
1027 {
1028 .name = "Kernel",
1029 .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
1030 .size = 28 * SZ_128K,
1031 },
1032 {
1033 .name = "File System",
1034 .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
1035 .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
1036 }
1037 };
1039 static const struct flash_platform_data am335x_spi_flash = {
1040 .type = "w25q64",
1041 .name = "spi_flash",
1042 .parts = am335x_spi_partitions,
1043 .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
1044 };
1046 /*
1047 * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
1048 * So setup Max speed to be less than that of Controller speed
1049 */
1050 static struct spi_board_info am335x_spi0_slave_info[] = {
1051 {
1052 .modalias = "m25p80",
1053 .platform_data = &am335x_spi_flash,
1054 .irq = -1,
1055 .max_speed_hz = 24000000,
1056 .bus_num = 1,
1057 .chip_select = 0,
1058 },
1059 };
1061 static struct spi_board_info am335x_spi1_slave_info[] = {
1062 {
1063 .modalias = "m25p80",
1064 .platform_data = &am335x_spi_flash,
1065 .irq = -1,
1066 .max_speed_hz = 12000000,
1067 .bus_num = 2,
1068 .chip_select = 0,
1069 },
1070 };
1072 static void evm_nand_init(int evm_id, int profile)
1073 {
1074 setup_pin_mux(nand_pin_mux);
1075 board_nand_init(am335x_nand_partitions,
1076 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
1077 }
1079 static struct lis3lv02d_platform_data lis331dlh_pdata = {
1080 .click_flags = LIS3_CLICK_SINGLE_X |
1081 LIS3_CLICK_SINGLE_Y |
1082 LIS3_CLICK_SINGLE_Z,
1083 .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
1084 LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
1085 LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
1086 .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
1087 .wakeup_thresh = 10,
1088 .click_thresh_x = 10,
1089 .click_thresh_y = 10,
1090 .click_thresh_z = 10,
1091 .g_range = 2,
1092 .st_min_limits[0] = 120,
1093 .st_min_limits[1] = 120,
1094 .st_min_limits[2] = 140,
1095 .st_max_limits[0] = 550,
1096 .st_max_limits[1] = 550,
1097 .st_max_limits[2] = 750,
1098 };
1100 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
1101 {
1102 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
1103 },
1104 {
1105 I2C_BOARD_INFO("lis331dlh", 0x18),
1106 .platform_data = &lis331dlh_pdata,
1107 },
1108 {
1109 I2C_BOARD_INFO("tsl2550", 0x39),
1110 },
1111 {
1112 I2C_BOARD_INFO("tmp275", 0x48),
1113 },
1114 };
1116 static void i2c1_init(int evm_id, int profile)
1117 {
1118 setup_pin_mux(i2c1_pin_mux);
1119 omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
1120 ARRAY_SIZE(am335x_i2c_boardinfo1));
1121 return;
1122 }
1124 /* Setup McASP 1 */
1125 static void mcasp1_init(int evm_id, int profile)
1126 {
1127 /* Configure McASP */
1128 setup_pin_mux(mcasp1_pin_mux);
1129 am335x_register_mcasp1(&am335x_evm_snd_data1);
1130 return;
1131 }
1133 static void mmc1_init(int evm_id, int profile)
1134 {
1135 setup_pin_mux(mmc1_pin_mux);
1137 am335x_mmc[1].mmc = 2;
1138 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
1139 am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
1140 am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
1141 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1143 /* mmc will be initialized when mmc0_init is called */
1144 return;
1145 }
1147 static void mmc2_wl12xx_init(int evm_id, int profile)
1148 {
1149 setup_pin_mux(mmc2_wl12xx_pin_mux);
1151 am335x_mmc[1].mmc = 3;
1152 am335x_mmc[1].name = "wl1271";
1153 am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
1154 | MMC_PM_KEEP_POWER;
1155 am335x_mmc[1].nonremovable = true;
1156 am335x_mmc[1].gpio_cd = -EINVAL;
1157 am335x_mmc[1].gpio_wp = -EINVAL;
1158 am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
1160 /* mmc will be initialized when mmc0_init is called */
1161 return;
1162 }
1164 static void uart1_wl12xx_init(int evm_id, int profile)
1165 {
1166 setup_pin_mux(uart1_wl12xx_pin_mux);
1167 }
1169 static void wl12xx_bluetooth_enable(void)
1170 {
1171 int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
1172 "bt_en\n");
1173 if (status < 0)
1174 pr_err("Failed to request gpio for bt_enable");
1176 pr_info("Configure Bluetooth Enable pin...\n");
1177 gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
1178 }
1180 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
1181 {
1182 if (on) {
1183 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1184 mdelay(70);
1185 }
1186 else
1187 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1189 return 0;
1190 }
1192 static void wl12xx_init(int evm_id, int profile)
1193 {
1194 struct device *dev;
1195 struct omap_mmc_platform_data *pdata;
1196 int ret;
1198 /* Register WLAN and BT enable pins based on the evm board revision */
1199 if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1200 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1201 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1202 }
1203 else {
1204 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1205 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1206 }
1208 wl12xx_bluetooth_enable();
1210 if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1211 pr_err("error setting wl12xx data\n");
1213 dev = am335x_mmc[1].dev;
1214 if (!dev) {
1215 pr_err("wl12xx mmc device initialization failed\n");
1216 goto out;
1217 }
1219 pdata = dev->platform_data;
1220 if (!pdata) {
1221 pr_err("Platfrom data of wl12xx device not set\n");
1222 goto out;
1223 }
1225 ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1226 GPIOF_OUT_INIT_LOW, "wlan_en");
1227 if (ret) {
1228 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1229 goto out;
1230 }
1232 if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1233 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1234 else
1235 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1237 pdata->slots[0].set_power = wl12xx_set_power;
1238 out:
1239 return;
1240 }
1242 static void d_can_init(int evm_id, int profile)
1243 {
1244 switch (evm_id) {
1245 case IND_AUT_MTR_EVM:
1246 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1247 setup_pin_mux(d_can_ia_pin_mux);
1248 /* Instance Zero */
1249 am33xx_d_can_init(0);
1250 }
1251 break;
1252 case GEN_PURP_EVM:
1253 if (profile == PROFILE_1) {
1254 setup_pin_mux(d_can_gp_pin_mux);
1255 /* Instance One */
1256 am33xx_d_can_init(1);
1257 }
1258 break;
1259 default:
1260 break;
1261 }
1262 }
1264 static void mmc0_init(int evm_id, int profile)
1265 {
1266 setup_pin_mux(mmc0_pin_mux);
1268 omap2_hsmmc_init(am335x_mmc);
1269 return;
1270 }
1272 static void mmc0_no_cd_init(int evm_id, int profile)
1273 {
1274 setup_pin_mux(mmc0_no_cd_pin_mux);
1276 omap2_hsmmc_init(am335x_mmc);
1277 return;
1278 }
1281 /* setup spi0 */
1282 static void spi0_init(int evm_id, int profile)
1283 {
1284 setup_pin_mux(spi0_pin_mux);
1285 spi_register_board_info(am335x_spi0_slave_info,
1286 ARRAY_SIZE(am335x_spi0_slave_info));
1287 return;
1288 }
1290 /* setup spi1 */
1291 static void spi1_init(int evm_id, int profile)
1292 {
1293 setup_pin_mux(spi1_pin_mux);
1294 spi_register_board_info(am335x_spi1_slave_info,
1295 ARRAY_SIZE(am335x_spi1_slave_info));
1296 return;
1297 }
1300 static int beaglebone_phy_fixup(struct phy_device *phydev)
1301 {
1302 phydev->supported &= ~(SUPPORTED_100baseT_Half |
1303 SUPPORTED_100baseT_Full);
1305 return 0;
1306 }
1308 #ifdef CONFIG_TLK110_WORKAROUND
1309 static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
1310 {
1311 unsigned int val;
1313 /* This is done as a workaround to support TLK110 rev1.0 phy */
1314 val = phy_read(phydev, TLK110_COARSEGAIN_REG);
1315 phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
1317 val = phy_read(phydev, TLK110_LPFHPF_REG);
1318 phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
1320 val = phy_read(phydev, TLK110_SPAREANALOG_REG);
1321 phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
1323 val = phy_read(phydev, TLK110_VRCR_REG);
1324 phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
1326 val = phy_read(phydev, TLK110_SETFFE_REG);
1327 phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
1329 val = phy_read(phydev, TLK110_FTSP_REG);
1330 phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
1332 val = phy_read(phydev, TLK110_ALFATPIDL_REG);
1333 phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
1335 val = phy_read(phydev, TLK110_PSCOEF21_REG);
1336 phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
1338 val = phy_read(phydev, TLK110_PSCOEF3_REG);
1339 phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
1341 val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
1342 phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
1344 val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
1345 phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
1347 val = phy_read(phydev, TLK110_CFGPS_REG);
1348 phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
1350 val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
1351 phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
1353 val = phy_read(phydev, TLK110_SWSCR3_REG);
1354 phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
1356 val = phy_read(phydev, TLK110_SCFALLBACK_REG);
1357 phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
1359 val = phy_read(phydev, TLK110_PHYRCR_REG);
1360 phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
1362 return 0;
1363 }
1364 #endif
1366 static void profibus_init(int evm_id, int profile)
1367 {
1368 setup_pin_mux(profibus_pin_mux);
1369 return;
1370 }
1372 /* Low-Cost EVM */
1373 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
1374 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1375 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1376 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1377 {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1378 {NULL, 0, 0},
1379 };
1381 /* General Purpose EVM */
1382 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1383 {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1384 PROFILE_2 | PROFILE_7) },
1385 {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1386 PROFILE_2 | PROFILE_7) },
1387 {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
1388 PROFILE_2 | PROFILE_7) },
1389 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1390 {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
1391 PROFILE_4 | PROFILE_6) },
1392 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1393 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1394 {evm_nand_init, DEV_ON_DGHTR_BRD,
1395 (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
1396 {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
1397 {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
1398 {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1399 {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1400 PROFILE_5)},
1401 {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
1402 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
1403 {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
1404 {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
1405 PROFILE_5)},
1406 {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
1407 {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
1408 {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1409 {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
1410 {uart2_init, DEV_ON_DGHTR_BRD, PROFILE_3},
1411 {NULL, 0, 0},
1412 };
1414 /* Industrial Auto Motor Control EVM */
1415 static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
1416 {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1417 {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1418 {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1419 {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1420 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1421 {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1422 {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
1423 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1424 {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1425 {NULL, 0, 0},
1426 };
1428 /* IP-Phone EVM */
1429 static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
1430 {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1431 {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1432 {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1433 {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1434 {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1435 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1436 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1437 {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1438 {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1439 {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
1440 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1441 {NULL, 0, 0},
1442 };
1444 /* Beaglebone < Rev A3 */
1445 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
1446 {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1447 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1448 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1449 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1450 {NULL, 0, 0},
1451 };
1453 /* Beaglebone Rev A3 and after */
1454 static struct evm_dev_cfg beaglebone_dev_cfg[] = {
1455 {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1456 {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1457 {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1458 {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
1459 {NULL, 0, 0},
1460 };
1462 static void setup_low_cost_evm(void)
1463 {
1464 pr_info("The board is a AM335x Low Cost EVM.\n");
1466 _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
1467 }
1469 static void setup_general_purpose_evm(void)
1470 {
1471 u32 prof_sel = am335x_get_profile_selection();
1472 pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1474 if (!strncmp("1.1A", config.version, 4)) {
1475 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1476 } else if (!strncmp("1.0", config.version, 3)) {
1477 gp_evm_revision = GP_EVM_REV_IS_1_0;
1478 } else {
1479 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1480 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1481 }
1483 if (gp_evm_revision == GP_EVM_REV_IS_1_0)
1484 gigabit_enable = 0;
1485 else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1486 gigabit_enable = 1;
1488 _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1489 }
1491 static void setup_ind_auto_motor_ctrl_evm(void)
1492 {
1493 u32 prof_sel = am335x_get_profile_selection();
1495 pr_info("The board is an industrial automation EVM in profile %d\n",
1496 prof_sel);
1498 /* Only Profile 0 is supported */
1499 if ((1L << prof_sel) != PROFILE_0) {
1500 pr_err("AM335X: Only Profile 0 is supported\n");
1501 pr_err("Assuming profile 0 & continuing\n");
1502 prof_sel = PROFILE_0;
1503 }
1505 _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
1506 PROFILE_0);
1508 /* Fillup global evmid */
1509 am33xx_evmid_fillup(IND_AUT_MTR_EVM);
1511 /* Initialize TLK110 PHY registers for phy version 1.0 */
1512 am335x_tlk110_phy_init();
1515 }
1517 static void setup_ip_phone_evm(void)
1518 {
1519 pr_info("The board is an IP phone EVM\n");
1521 _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
1522 }
1524 /* BeagleBone < Rev A3 */
1525 static void setup_beaglebone_old(void)
1526 {
1527 pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
1529 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1530 am335x_mmc[0].gpio_wp = -EINVAL;
1532 _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
1534 phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
1535 beaglebone_phy_fixup);
1536 }
1538 /* BeagleBone after Rev A3 */
1539 static void setup_beaglebone(void)
1540 {
1541 pr_info("The board is a AM335x Beaglebone.\n");
1543 /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
1544 am335x_mmc[0].gpio_wp = -EINVAL;
1546 _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
1547 }
1550 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1551 {
1552 u8 tmp;
1553 int ret;
1555 /*
1556 * try reading a byte from the EEPROM to see if it is
1557 * present. We could read a lot more, but that would
1558 * just slow the boot process and we have all the information
1559 * we need from the EEPROM on the base board anyway.
1560 */
1561 ret = m->read(m, &tmp, 0, sizeof(u8));
1562 if (ret == sizeof(u8)) {
1563 pr_info("Detected a daughter card on AM335x EVM..");
1564 daughter_brd_detected = true;
1565 } else {
1566 pr_info("No daughter card found\n");
1567 daughter_brd_detected = false;
1568 }
1569 }
1571 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1572 {
1573 int ret;
1574 char tmp[10];
1576 /* 1st get the MAC address from EEPROM */
1577 ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1578 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1580 if (ret != sizeof(am335x_mac_addr)) {
1581 pr_warning("AM335X: EVM Config read fail: %d\n", ret);
1582 return;
1583 }
1585 /* Fillup global mac id */
1586 am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1587 &am335x_mac_addr[1][0]);
1589 /* get board specific data */
1590 ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
1591 if (ret != sizeof(config)) {
1592 pr_warning("AM335X EVM config read fail, read %d bytes\n", ret);
1593 return;
1594 }
1596 if (config.header != AM335X_EEPROM_HEADER) {
1597 pr_warning("AM335X: wrong header 0x%x, expected 0x%x\n",
1598 config.header, AM335X_EEPROM_HEADER);
1599 goto out;
1600 }
1602 if (strncmp("A335", config.name, 4)) {
1603 pr_err("Board %s doesn't look like an AM335x board\n",
1604 config.name);
1605 goto out;
1606 }
1608 snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
1609 pr_info("Board name: %s\n", tmp);
1610 snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
1611 pr_info("Board version: %s\n", tmp);
1613 if (!strncmp("A335BONE", config.name, 8)) {
1614 daughter_brd_detected = false;
1615 if(!strncmp("00A1", config.version, 4) ||
1616 !strncmp("00A2", config.version, 4))
1617 setup_beaglebone_old();
1618 else
1619 setup_beaglebone();
1620 } else {
1621 /* only 6 characters of options string used for now */
1622 snprintf(tmp, 7, "%s", config.opt);
1623 pr_info("SKU: %s\n", tmp);
1625 if (!strncmp("SKU#00", config.opt, 6))
1626 setup_low_cost_evm();
1627 else if (!strncmp("SKU#01", config.opt, 6))
1628 setup_general_purpose_evm();
1629 else if (!strncmp("SKU#02", config.opt, 6))
1630 setup_ind_auto_motor_ctrl_evm();
1631 else if (!strncmp("SKU#03", config.opt, 6))
1632 setup_ip_phone_evm();
1633 else
1634 goto out;
1635 }
1636 /* Initialize cpsw after board detection is completed as board
1637 * information is required for configuring phy address and hence
1638 * should be call only after board detection
1639 */
1640 am33xx_cpsw_init(gigabit_enable);
1642 return;
1643 out:
1644 /*
1645 * If the EEPROM hasn't been programed or an incorrect header
1646 * or board name are read, assume this is an old beaglebone board
1647 * (< Rev A3)
1648 */
1649 pr_err("Could not detect any board, falling back to: "
1650 "Beaglebone (< Rev A3) with no daughter card connected\n");
1651 daughter_brd_detected = false;
1652 setup_beaglebone_old();
1654 /* Initialize cpsw after board detection is completed as board
1655 * information is required for configuring phy address and hence
1656 * should be call only after board detection
1657 */
1659 am33xx_cpsw_init(gigabit_enable);
1660 }
1662 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1663 .byte_len = (256*1024) / 8,
1664 .page_size = 64,
1665 .flags = AT24_FLAG_ADDR16,
1666 .setup = am335x_setup_daughter_board,
1667 .context = (void *)NULL,
1668 };
1670 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1671 .byte_len = (256*1024) / 8,
1672 .page_size = 64,
1673 .flags = AT24_FLAG_ADDR16,
1674 .setup = am335x_evm_setup,
1675 .context = (void *)NULL,
1676 };
1678 /*
1679 * Daughter board Detection.
1680 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1681 * machine init, starting from daughter board and ending with baseboard.
1682 * Assumptions :
1683 * 1. probe for i2c devices are called in the order they are included in
1684 * the below struct. Daughter boards eeprom are probed 1st. Baseboard
1685 * eeprom probe is called last.
1686 */
1687 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1688 {
1689 /* Daughter Board EEPROM */
1690 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1691 .platform_data = &am335x_daughter_board_eeprom_info,
1692 },
1693 {
1694 /* Baseboard board EEPROM */
1695 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1696 .platform_data = &am335x_baseboard_eeprom_info,
1697 },
1698 {
1699 I2C_BOARD_INFO("cpld_reg", 0x35),
1700 },
1701 {
1702 I2C_BOARD_INFO("tlc59108", 0x40),
1703 },
1705 };
1707 static struct omap_musb_board_data musb_board_data = {
1708 .interface_type = MUSB_INTERFACE_ULPI,
1709 .mode = MUSB_OTG,
1710 .power = 500,
1711 .instances = 1,
1712 };
1714 static int cpld_reg_probe(struct i2c_client *client,
1715 const struct i2c_device_id *id)
1716 {
1717 cpld_client = client;
1718 return 0;
1719 }
1721 static int __devexit cpld_reg_remove(struct i2c_client *client)
1722 {
1723 cpld_client = NULL;
1724 return 0;
1725 }
1727 static const struct i2c_device_id cpld_reg_id[] = {
1728 { "cpld_reg", 0 },
1729 { }
1730 };
1732 static struct i2c_driver cpld_reg_driver = {
1733 .driver = {
1734 .name = "cpld_reg",
1735 },
1736 .probe = cpld_reg_probe,
1737 .remove = cpld_reg_remove,
1738 .id_table = cpld_reg_id,
1739 };
1741 static void evm_init_cpld(void)
1742 {
1743 i2c_add_driver(&cpld_reg_driver);
1744 }
1746 static void __init am335x_evm_i2c_init(void)
1747 {
1748 /* Initially assume Low Cost EVM Config */
1749 am335x_evm_id = LOW_COST_EVM;
1751 evm_init_cpld();
1753 omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1754 ARRAY_SIZE(am335x_i2c_boardinfo));
1755 }
1757 static struct resource am335x_rtc_resources[] = {
1758 {
1759 .start = AM33XX_RTC_BASE,
1760 .end = AM33XX_RTC_BASE + SZ_4K - 1,
1761 .flags = IORESOURCE_MEM,
1762 },
1763 { /* timer irq */
1764 .start = AM33XX_IRQ_RTC_TIMER,
1765 .end = AM33XX_IRQ_RTC_TIMER,
1766 .flags = IORESOURCE_IRQ,
1767 },
1768 { /* alarm irq */
1769 .start = AM33XX_IRQ_RTC_ALARM,
1770 .end = AM33XX_IRQ_RTC_ALARM,
1771 .flags = IORESOURCE_IRQ,
1772 },
1773 };
1775 static struct platform_device am335x_rtc_device = {
1776 .name = "omap_rtc",
1777 .id = -1,
1778 .num_resources = ARRAY_SIZE(am335x_rtc_resources),
1779 .resource = am335x_rtc_resources,
1780 };
1782 static int am335x_rtc_init(void)
1783 {
1784 void __iomem *base;
1785 struct clk *clk;
1787 clk = clk_get(NULL, "rtc_fck");
1788 if (IS_ERR(clk)) {
1789 pr_err("rtc : Failed to get RTC clock\n");
1790 return -1;
1791 }
1793 if (clk_enable(clk)) {
1794 pr_err("rtc: Clock Enable Failed\n");
1795 return -1;
1796 }
1798 base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1800 if (WARN_ON(!base))
1801 return -ENOMEM;
1803 /* Unlock the rtc's registers */
1804 __raw_writel(0x83e70b13, base + 0x6c);
1805 __raw_writel(0x95a4f1e0, base + 0x70);
1807 /*
1808 * Enable the 32K OSc
1809 * TODO: Need a better way to handle this
1810 * Since we want the clock to be running before mmc init
1811 * we need to do it before the rtc probe happens
1812 */
1813 __raw_writel(0x48, base + 0x54);
1815 iounmap(base);
1817 return platform_device_register(&am335x_rtc_device);
1818 }
1820 /* Enable clkout2 */
1821 static struct pinmux_config clkout2_pin_mux[] = {
1822 {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1823 {NULL, 0},
1824 };
1826 static void __init clkout2_enable(void)
1827 {
1828 struct clk *ck_32;
1830 ck_32 = clk_get(NULL, "clkout2_ck");
1831 if (IS_ERR(ck_32)) {
1832 pr_err("Cannot clk_get ck_32\n");
1833 return;
1834 }
1836 clk_enable(ck_32);
1838 setup_pin_mux(clkout2_pin_mux);
1839 }
1841 static void __init am335x_evm_init(void)
1842 {
1843 am33xx_mux_init(board_mux);
1844 omap_serial_init();
1845 am335x_rtc_init();
1846 clkout2_enable();
1847 am335x_evm_i2c_init();
1848 omap_sdrc_init(NULL, NULL);
1849 usb_musb_init(&musb_board_data);
1850 omap_board_config = am335x_evm_config;
1851 omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1852 /* Create an alias for icss clock */
1853 if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1854 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1855 /* Create an alias for gfx/sgx clock */
1856 if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1857 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1858 }
1860 static void __init am335x_evm_map_io(void)
1861 {
1862 omap2_set_globals_am33xx();
1863 omapam33xx_map_common_io();
1864 }
1866 MACHINE_START(AM335XEVM, "am335xevm")
1867 /* Maintainer: Texas Instruments */
1868 .atag_offset = 0x100,
1869 .map_io = am335x_evm_map_io,
1870 .init_early = am33xx_init_early,
1871 .init_irq = ti81xx_init_irq,
1872 .handle_irq = omap3_intc_handle_irq,
1873 .timer = &omap3_am33xx_timer,
1874 .init_machine = am335x_evm_init,
1875 MACHINE_END
1877 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1878 /* Maintainer: Texas Instruments */
1879 .atag_offset = 0x100,
1880 .map_io = am335x_evm_map_io,
1881 .init_irq = ti81xx_init_irq,
1882 .init_early = am33xx_init_early,
1883 .timer = &omap3_am33xx_timer,
1884 .init_machine = am335x_evm_init,
1885 MACHINE_END