43a6d2152373ed169ffda27ef8874b3521d7a5f3
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / clock33xx_data.c
1 /*
2  * AM33XX Clock data
3  *
4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  */
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/clk.h>
19 #include <plat/clkdev_omap.h>
21 #include "control.h"
22 #include "clock.h"
23 #include "clock33xx.h"
24 #include "cm.h"
25 #include "cm33xx.h"
26 #include "cm-regbits-33xx.h"
27 #include "prm.h"
29 /* Modulemode control */
30 #define AM33XX_MODULEMODE_HWCTRL        0
31 #define AM33XX_MODULEMODE_SWCTRL        1
33 /* Root clocks */
34 static struct clk clk_32768_ck = {
35         .name           = "clk_32768_ck",
36         .rate           = 32768,
37         .ops            = &clkops_null,
38 };
40 static struct clk clk_32khz_ck = {
41         .name           = "clk_32khz_ck",
42         .rate           = 32768,
43         .ops            = &clkops_null,
44 };
46 /* On-Chip 32KHz RC OSC */
47 static struct clk clk_rc32k_ck = {
48         .name           = "clk_rc32k_ck",
49         .rate           = 32000,
50         .ops            = &clkops_null,
51 };
53 static struct clk tclkin_ck = {
54         .name           = "tclkin_ck",
55         .rate           = 12000000,
56         .ops            = &clkops_null,
57 };
59 static const struct clksel_rate div_1_0_rates[] = {
60         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
61         { .div = 0 },
62 };
64 static const struct clksel_rate div_1_1_rates[] = {
65         { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
66         { .div = 0 },
67 };
69 static const struct clksel_rate div_1_2_rates[] = {
70         { .div = 1, .val = 2, .flags = RATE_IN_AM33XX },
71         { .div = 0 },
72 };
74 static const struct clksel_rate div_1_3_rates[] = {
75         { .div = 1, .val = 3, .flags = RATE_IN_AM33XX },
76         { .div = 0 },
77 };
79 static const struct clksel_rate div_1_4_rates[] = {
80         { .div = 1, .val = 4, .flags = RATE_IN_AM33XX },
81         { .div = 0 },
82 };
84 static struct clk sys_clkin_ck = {
85         .name           = "sys_clkin_ck",
86         .rate           = 24000000,
87         .ops            = &clkops_null,
88 };
90 /* DPLL_PER */
91 static struct dpll_data dpll_per_dd = {
92         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
93         .clk_bypass     = &sys_clkin_ck,
94         .clk_ref        = &sys_clkin_ck,
95         .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
96         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
97         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
98         .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
99         .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
100         .enable_mask    = AM33XX_DPLL_EN_MASK,
101         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
102         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
103         .max_multiplier = AM33XX_MAX_DPLL_MULT,
104         .max_divider    = AM33XX_MAX_DPLL_DIV,
105         .min_divider    = 1,
106 };
108 static struct clk dpll_per_ck = {
109         .name           = "dpll_per_ck",
110         .parent         = &sys_clkin_ck,
111         .dpll_data      = &dpll_per_dd,
112         .init           = &omap2_init_dpll_parent,
113         .ops            = &clkops_null,
114         .recalc         = &omap3_dpll_recalc,
115 };
117 static const struct clksel_rate div31_1to31_rates[] = {
118         { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
119         { .div = 2, .val = 2, .flags = RATE_IN_AM33XX },
120         { .div = 3, .val = 3, .flags = RATE_IN_AM33XX },
121         { .div = 4, .val = 4, .flags = RATE_IN_AM33XX },
122         { .div = 5, .val = 5, .flags = RATE_IN_AM33XX },
123         { .div = 6, .val = 6, .flags = RATE_IN_AM33XX },
124         { .div = 7, .val = 7, .flags = RATE_IN_AM33XX },
125         { .div = 8, .val = 8, .flags = RATE_IN_AM33XX },
126         { .div = 9, .val = 9, .flags = RATE_IN_AM33XX },
127         { .div = 10, .val = 10, .flags = RATE_IN_AM33XX },
128         { .div = 11, .val = 11, .flags = RATE_IN_AM33XX },
129         { .div = 12, .val = 12, .flags = RATE_IN_AM33XX },
130         { .div = 13, .val = 13, .flags = RATE_IN_AM33XX },
131         { .div = 14, .val = 14, .flags = RATE_IN_AM33XX },
132         { .div = 15, .val = 15, .flags = RATE_IN_AM33XX },
133         { .div = 16, .val = 16, .flags = RATE_IN_AM33XX },
134         { .div = 17, .val = 17, .flags = RATE_IN_AM33XX },
135         { .div = 18, .val = 18, .flags = RATE_IN_AM33XX },
136         { .div = 19, .val = 19, .flags = RATE_IN_AM33XX },
137         { .div = 20, .val = 20, .flags = RATE_IN_AM33XX },
138         { .div = 21, .val = 21, .flags = RATE_IN_AM33XX },
139         { .div = 22, .val = 22, .flags = RATE_IN_AM33XX },
140         { .div = 23, .val = 23, .flags = RATE_IN_AM33XX },
141         { .div = 24, .val = 24, .flags = RATE_IN_AM33XX },
142         { .div = 25, .val = 25, .flags = RATE_IN_AM33XX },
143         { .div = 26, .val = 26, .flags = RATE_IN_AM33XX },
144         { .div = 27, .val = 27, .flags = RATE_IN_AM33XX },
145         { .div = 28, .val = 28, .flags = RATE_IN_AM33XX },
146         { .div = 29, .val = 29, .flags = RATE_IN_AM33XX },
147         { .div = 30, .val = 30, .flags = RATE_IN_AM33XX },
148         { .div = 31, .val = 31, .flags = RATE_IN_AM33XX },
149         { .div = 0 },
150 };
152 static const struct clksel dpll_per_m2_div[] = {
153         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
154         { .parent = NULL },
155 };
157 static struct clk dpll_per_m2_ck = {
158         .name           = "dpll_per_m2_ck",
159         .parent         = &dpll_per_ck,
160         .clksel         = dpll_per_m2_div,
161         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_PER,
162         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
163         .ops            = &clkops_null,
164         .recalc         = &omap2_clksel_recalc,
165         .round_rate     = &omap2_clksel_round_rate,
166         .set_rate       = &omap2_clksel_set_rate,
167 };
169 static struct clk i2c_clk = {
170         .name           = "i2c_clk",
171         .parent         = &dpll_per_m2_ck,
172         .ops            = &clkops_null,
173         .recalc         = &followparent_recalc,
174 };
176 static struct clk clk_div_24_ck = {
177         .name           = "clk_div_24_ck",
178         .parent         = &i2c_clk,
179         .ops            = &clkops_null,
180         .recalc         = &followparent_recalc,
181 };
183 /* DPLL_CORE */
184 static struct dpll_data dpll_core_dd = {
185         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
186         .clk_bypass     = &sys_clkin_ck,
187         .clk_ref        = &sys_clkin_ck,
188         .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
189         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
190         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
191         .mult_mask      = AM33XX_DPLL_MULT_MASK,
192         .div1_mask      = AM33XX_DPLL_DIV_MASK,
193         .enable_mask    = AM33XX_DPLL_EN_MASK,
194         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
195         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
196         .max_multiplier = AM33XX_MAX_DPLL_MULT,
197         .max_divider    = AM33XX_MAX_DPLL_DIV,
198         .min_divider    = 1,
199 };
201 static struct clk dpll_core_ck = {
202         .name           = "dpll_core_ck",
203         .parent         = &sys_clkin_ck,
204         .dpll_data      = &dpll_core_dd,
205         .init           = &omap2_init_dpll_parent,
206         .ops            = &clkops_null,
207         .recalc         = &omap3_dpll_recalc,
208 };
210 static struct clk dpll_core_x2_ck = {
211         .name           = "dpll_core_x2_ck",
212         .parent         = &dpll_core_ck,
213         .ops            = &clkops_null,
214         .recalc         = &omap3_clkoutx2_recalc,
215 };
217 static const struct clksel dpll_core_m4_div[] = {
218         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
219         { .parent = NULL },
220 };
222 static struct clk dpll_core_m4_ck = {
223         .name           = "dpll_core_m4_ck",
224         .parent         = &dpll_core_x2_ck,
225         .clksel         = dpll_core_m4_div,
226         .clksel_reg     = AM33XX_CM_DIV_M4_DPLL_CORE,
227         .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
228         .ops            = &clkops_null,
229         .recalc         = &omap2_clksel_recalc,
230         .round_rate     = &omap2_clksel_round_rate,
231         .set_rate       = &omap2_clksel_set_rate,
232 };
234 static struct clk sysclk_div_ck = {
235         .name           = "sysclk_div_ck",
236         .parent         = &dpll_core_m4_ck,
237         .ops            = &clkops_null,
238         .recalc         = &followparent_recalc,
239 };
241 static struct clk div_l4_wkup_gclk_ck = {
242         .name           = "div_l4_wkup_gclk_ck",
243         .parent         = &dpll_core_m4_ck,
244         .ops            = &clkops_null,
245         .fixed_div      = 2,
246         .recalc         = &omap_fixed_divisor_recalc,
247 };
249 static struct clk core_100m_ck = {
250         .name           = "core_100m_ck",
251         .parent         = &sysclk_div_ck,
252         .ops            = &clkops_null,
253         .fixed_div      = 2,
254         .recalc         = &omap_fixed_divisor_recalc,
255 };
257 static struct clk l4ls_fck = {
258         .name           = "l4ls_fck",
259         .ops            = &clkops_omap2_dflt,
260         .enable_reg     = AM33XX_CM_PER_L4LS_CLKCTRL,
261         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
262         .clkdm_name     = "l4ls_clkdm",
263         .parent         = &core_100m_ck,
264         .recalc         = &followparent_recalc,
265         .flags          = ENABLE_ON_INIT,
266 };
268 static struct clk timer2_ick = {
269         .name           = "timer2_ick",
270         .parent         = &l4ls_fck,
271         .ops            = &clkops_null,
272         .recalc         = &followparent_recalc,
273 };
275 static struct clk timer3_ick = {
276         .name           = "timer3_ick",
277         .parent         = &l4ls_fck,
278         .ops            = &clkops_null,
279         .recalc         = &followparent_recalc,
280 };
282 static struct clk timer4_ick = {
283         .name           = "timer4_ick",
284         .parent         = &l4ls_fck,
285         .ops            = &clkops_null,
286         .recalc         = &followparent_recalc,
287 };
289 static struct clk timer5_ick = {
290         .name           = "timer5_ick",
291         .parent         = &l4ls_fck,
292         .ops            = &clkops_null,
293         .recalc         = &followparent_recalc,
294 };
296 static struct clk timer6_ick = {
297         .name           = "timer6_ick",
298         .parent         = &l4ls_fck,
299         .ops            = &clkops_null,
300         .recalc         = &followparent_recalc,
301 };
303 static struct clk timer7_ick = {
304         .name           = "timer7_ick",
305         .parent         = &l4ls_fck,
306         .ops            = &clkops_null,
307         .recalc         = &followparent_recalc,
308 };
310 static struct clk lcdc_l3ick = {
311         .name           = "lcdc_ick_l3_clk",
312         .enable_reg     = AM33XX_CM_PER_L3_CLKCTRL,
313         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
314         .parent         = &dpll_core_m4_ck,
315         .ops            = &clkops_null,
316         .clkdm_name     = "l3_clkdm",
317         .recalc         = &followparent_recalc,
318 };
320 static struct clk lcdc_l4ick = {
321         .name           = "lcdc_ick_l4_clk",
322         .enable_reg     = AM33XX_CM_PER_L4LS_CLKCTRL,
323         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
324         .parent         = &dpll_core_m4_ck,
325         .ops            = &clkops_null,
326         .clkdm_name     = "l4ls_clkdm",
327         .recalc         = &followparent_recalc,
328 };
330 /* Leaf clocks controlled by modules */
331 static struct clk adc_tsc_fck = {
332         .name           = "adc_tsc_fck",
333         .ops            = &clkops_null,
334         .parent         = &sys_clkin_ck,
335         .clkdm_name     = "l4_wkup_clkdm",
336         .recalc         = &followparent_recalc,
337 };
339 static struct clk adc_tsc_ick = {
340         .name           = "adc_tsc_ick",
341         .ops            = &clkops_omap2_dflt,
342         .enable_reg     = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL,
343         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
344         .parent         = &div_l4_wkup_gclk_ck,
345         .recalc         = &followparent_recalc,
346 };
348 static struct clk aes0_fck = {
349         .name           = "aes0_fck",
350         .ops            = &clkops_omap2_dflt,
351         .enable_reg     = AM33XX_CM_PER_AES0_CLKCTRL,
352         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
353         .clkdm_name     = "l3_clkdm",
354         .parent         = &sysclk_div_ck,
355         .recalc         = &followparent_recalc,
356 };
358 static struct clk cefuse_fck = {
359         .name           = "cefuse_fck",
360         .ops            = &clkops_omap2_dflt,
361         .enable_reg     = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
362         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
363         .clkdm_name     = "l4_cefuse_clkdm",
364         .parent         = &sys_clkin_ck,
365         .recalc         = &followparent_recalc,
366 };
368 static struct clk clkdiv32k_fck = {
369         .name           = "clkdiv32k_fck",
370         .ops            = &clkops_omap2_dflt,
371         .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
372         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
373         .clkdm_name     = "clk_24mhz_clkdm",
374         .parent         = &clk_div_24_ck,
375         .recalc         = &followparent_recalc,
376 };
378 static struct clk control_fck = {
379         .name           = "control_fck",
380         .ops            = &clkops_omap2_dflt,
381         .enable_reg     = AM33XX_CM_WKUP_CONTROL_CLKCTRL,
382         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
383         .clkdm_name     = "l4_wkup_clkdm",
384         .parent         = &div_l4_wkup_gclk_ck,
385         .recalc         = &followparent_recalc,
386         .flags          = ENABLE_ON_INIT,
387 };
389 static struct clk dcan0_fck = {
390         .name           = "dcan0_fck",
391         .ops            = &clkops_omap2_dflt,
392         .enable_reg     = AM33XX_CM_PER_DCAN0_CLKCTRL,
393         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
394         .clkdm_name     = "l4ls_clkdm",
395         .parent         = &sys_clkin_ck,
396         .recalc         = &followparent_recalc,
397 };
399 static struct clk dcan1_fck = {
400         .name           = "dcan1_fck",
401         .ops            = &clkops_omap2_dflt,
402         .enable_reg     = AM33XX_CM_PER_DCAN1_CLKCTRL,
403         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
404         .clkdm_name     = "l4ls_clkdm",
405         .parent         = &sys_clkin_ck,
406         .recalc         = &followparent_recalc,
407 };
409 static struct clk dcan0_ick = {
410         .name           = "dcan0_ick",
411         .parent         = &dpll_per_m2_ck ,
412         .ops            = &clkops_null,
413         .clkdm_name     = "l4ls_clkdm",
414         .recalc         = &followparent_recalc,
415 };
417 static struct clk dcan1_ick = {
418         .name           = "dcan1_ick",
419         .parent         = &dpll_per_m2_ck ,
420         .ops            = &clkops_null,
421         .clkdm_name     = "l4ls_clkdm",
422         .recalc         = &followparent_recalc,
423 };
425 static struct clk debugss_fck = {
426         .name           = "debugss_fck",
427         .ops            = &clkops_omap2_dflt,
428         .enable_reg     = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
429         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
430         .clkdm_name     = "l3_aon_clkdm",
431         .parent         = &dpll_core_m4_ck,
432         .recalc         = &followparent_recalc,
433 };
435 static struct clk elm_fck = {
436         .name           = "elm_fck",
437         .ops            = &clkops_omap2_dflt,
438         .enable_reg     = AM33XX_CM_PER_ELM_CLKCTRL,
439         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
440         .clkdm_name     = "l4ls_clkdm",
441         .parent         = &core_100m_ck,
442         .recalc         = &followparent_recalc,
443 };
445 static struct clk emif_fw_fck = {
446         .name           = "emif_fw_fck",
447         .ops            = &clkops_omap2_dflt,
448         .enable_reg     = AM33XX_CM_PER_EMIF_FW_CLKCTRL,
449         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
450         .clkdm_name     = "l4fw_clkdm",
451         .parent         = &core_100m_ck,
452         .recalc         = &followparent_recalc,
453         .flags          = ENABLE_ON_INIT,
454 };
456 static struct clk epwmss0_fck = {
457         .name           = "epwmss0_fck",
458         .ops            = &clkops_omap2_dflt,
459         .enable_reg     = AM33XX_CM_PER_EPWMSS0_CLKCTRL,
460         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
461         .clkdm_name     = "l4ls_clkdm",
462         .parent         = &core_100m_ck,
463         .recalc         = &followparent_recalc,
464 };
466 static struct clk epwmss1_fck = {
467         .name           = "epwmss1_fck",
468         .ops            = &clkops_omap2_dflt,
469         .enable_reg     = AM33XX_CM_PER_EPWMSS1_CLKCTRL,
470         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
471         .clkdm_name     = "l4ls_clkdm",
472         .parent         = &core_100m_ck,
473         .recalc         = &followparent_recalc,
474 };
476 static struct clk epwmss2_fck = {
477         .name           = "epwmss2_fck",
478         .ops            = &clkops_omap2_dflt,
479         .enable_reg     = AM33XX_CM_PER_EPWMSS2_CLKCTRL,
480         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
481         .clkdm_name     = "l4ls_clkdm",
482         .parent         = &core_100m_ck,
483         .recalc         = &followparent_recalc,
484 };
486 static struct clk gpio0_fck = {
487         .name           = "gpio0_fck",
488         .ops            = &clkops_omap2_dflt,
489         .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
490         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
491         .clkdm_name     = "l4_wkup_clkdm",
492         .parent         = &div_l4_wkup_gclk_ck,
493         .recalc         = &followparent_recalc,
494 };
496 static struct clk gpio1_fck = {
497         .name           = "gpio1_fck",
498         .ops            = &clkops_omap2_dflt,
499         .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
500         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
501         .clkdm_name     = "l4ls_clkdm",
502         .parent         = &core_100m_ck,
503         .recalc         = &followparent_recalc,
504 };
506 static struct clk gpio2_fck = {
507         .name           = "gpio2_fck",
508         .ops            = &clkops_omap2_dflt,
509         .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
510         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
511         .clkdm_name     = "l4ls_clkdm",
512         .parent         = &core_100m_ck,
513         .recalc         = &followparent_recalc,
514 };
516 static struct clk gpio3_fck = {
517         .name           = "gpio3_fck",
518         .ops            = &clkops_omap2_dflt,
519         .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
520         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
521         .clkdm_name     = "l4ls_clkdm",
522         .parent         = &core_100m_ck,
523         .recalc         = &followparent_recalc,
524 };
526 static struct clk gpmc_fck = {
527         .name           = "gpmc_fck",
528         .ops            = &clkops_omap2_dflt,
529         .enable_reg     = AM33XX_CM_PER_GPMC_CLKCTRL,
530         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
531         .clkdm_name     = "l3s_clkdm",
532         .parent         = &core_100m_ck,
533         .recalc         = &followparent_recalc,
534 };
536 static struct clk i2c1_fck = {
537         .name           = "i2c1_fck",
538         .ops            = &clkops_omap2_dflt,
539         .enable_reg     = AM33XX_CM_WKUP_I2C0_CLKCTRL,
540         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
541         .clkdm_name     = "l4_wkup_clkdm",
542         .parent         = &dpll_per_m2_ck,
543         .fixed_div      = 4,
544         .recalc         = &omap_fixed_divisor_recalc,
545 };
547 static struct clk i2c2_fck = {
548         .name           = "i2c2_fck",
549         .ops            = &clkops_omap2_dflt,
550         .enable_reg     = AM33XX_CM_PER_I2C1_CLKCTRL,
551         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
552         .clkdm_name     = "l4ls_clkdm",
553         .parent         = &i2c_clk,
554         .recalc         = &followparent_recalc,
555 };
557 static struct clk i2c3_fck = {
558         .name           = "i2c3_fck",
559         .ops            = &clkops_omap2_dflt,
560         .enable_reg     = AM33XX_CM_PER_I2C2_CLKCTRL,
561         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
562         .clkdm_name     = "l4ls_clkdm",
563         .parent         = &i2c_clk,
564         .recalc         = &followparent_recalc,
565 };
567 static struct clk icss_fck = {
568         .name           = "icss_fck",
569         .ops            = &clkops_omap2_dflt,
570         .enable_reg     = AM33XX_CM_PER_ICSS_CLKCTRL,
571         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
572         .clkdm_name     = "icss_ocp_clkdm",
573         .parent         = &dpll_per_m2_ck,
574         .recalc         = &followparent_recalc,
575 };
577 static struct clk ieee5000_fck = {
578         .name           = "ieee5000_fck",
579         .ops            = &clkops_omap2_dflt,
580         .enable_reg     = AM33XX_CM_PER_IEEE5000_CLKCTRL,
581         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
582         .clkdm_name     = "l3s_clkdm",
583         .parent         = &core_100m_ck,
584         .recalc         = &followparent_recalc,
585         .flags          = ENABLE_ON_INIT,
586 };
588 static struct clk l3_instr_fck = {
589         .name           = "l3_instr_fck",
590         .ops            = &clkops_omap2_dflt,
591         .enable_reg     = AM33XX_CM_PER_L3_INSTR_CLKCTRL,
592         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
593         .clkdm_name     = "l3_clkdm",
594         .parent         = &sysclk_div_ck,
595         .recalc         = &followparent_recalc,
596         .flags          = ENABLE_ON_INIT,
597 };
599 static struct clk l3_main_fck = {
600         .name           = "l3_main_fck",
601         .ops            = &clkops_omap2_dflt,
602         .enable_reg     = AM33XX_CM_PER_L3_CLKCTRL,
603         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
604         .clkdm_name     = "l3_clkdm",
605         .parent         = &sysclk_div_ck,
606         .recalc         = &followparent_recalc,
607         .flags          = ENABLE_ON_INIT,
608 };
610 static struct clk l4_hs_fck = {
611         .name           = "l4_hs_fck",
612         .ops            = &clkops_omap2_dflt,
613         .enable_reg     = AM33XX_CM_PER_L4HS_CLKCTRL,
614         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
615         .clkdm_name     = "l4hs_clkdm",
616         .parent         = &sysclk_div_ck,
617         .recalc         = &followparent_recalc,
618         .flags          = ENABLE_ON_INIT,
619 };
621 static struct clk l4fw_fck = {
622         .name           = "l4fw_fck",
623         .ops            = &clkops_omap2_dflt,
624         .enable_reg     = AM33XX_CM_PER_L4FW_CLKCTRL,
625         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
626         .clkdm_name     = "l4fw_clkdm",
627         .parent         = &core_100m_ck,
628         .recalc         = &followparent_recalc,
629         .flags          = ENABLE_ON_INIT,
630 };
632 static struct clk l4wkup_fck = {
633         .name           = "l4wkup_fck",
634         .ops            = &clkops_omap2_dflt,
635         .enable_reg     = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
636         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
637         .clkdm_name     = "l4_wkup_aon_clkdm",
638         .parent         = &div_l4_wkup_gclk_ck,
639         .recalc         = &followparent_recalc,
640         .flags          = ENABLE_ON_INIT,
641 };
643 static struct clk mailbox0_fck = {
644         .name           = "mailbox0_fck",
645         .ops            = &clkops_omap2_dflt,
646         .enable_reg     = AM33XX_CM_PER_MAILBOX0_CLKCTRL,
647         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
648         .clkdm_name     = "l4ls_clkdm",
649         .parent         = &core_100m_ck,
650         .recalc         = &followparent_recalc,
651 };
653 static struct clk mcasp0_ick = {
654         .name           = "mcasp0_ick",
655         .parent         = &l3_main_fck,
656         .ops            = &clkops_null,
657         .recalc         = &followparent_recalc,
658 };
660 static struct clk mcasp1_ick = {
661         .name           = "mcasp1_ick",
662         .parent         = &l3_main_fck,
663         .ops            = &clkops_null,
664         .recalc         = &followparent_recalc,
665 };
667 static struct clk mcasp0_fck = {
668         .name           = "mcasp0_fck",
669         .ops            = &clkops_omap2_dflt,
670         .enable_reg     = AM33XX_CM_PER_MCASP0_CLKCTRL,
671         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
672         .clkdm_name     = "l3s_clkdm",
673         .parent         = &sys_clkin_ck,
674         .recalc         = &followparent_recalc,
675 };
677 static struct clk mcasp1_fck = {
678         .name           = "mcasp1_fck",
679         .ops            = &clkops_omap2_dflt,
680         .enable_reg     = AM33XX_CM_PER_MCASP1_CLKCTRL,
681         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
682         .clkdm_name     = "l3s_clkdm",
683         .parent         = &sys_clkin_ck,
684         .recalc         = &followparent_recalc,
685 };
687 static struct clk mlb_fck = {
688         .name           = "mlb_fck",
689         .ops            = &clkops_omap2_dflt,
690         .enable_reg     = AM33XX_CM_PER_MLB_CLKCTRL,
691         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
692         .clkdm_name     = "l3_clkdm",
693         .parent         = &sysclk_div_ck,
694         .recalc         = &followparent_recalc,
695 };
697 static struct clk mmu_fck = {
698         .name           = "mmu_fck",
699         .ops            = &clkops_omap2_dflt,
700         .enable_reg     = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
701         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
702         .clkdm_name     = "gfx_l3_clkdm",
703         .parent         = &dpll_core_m4_ck,
704         .recalc         = &followparent_recalc,
705 };
708 static struct clk mstr_exps_fck = {
709         .name           = "mstr_exps_fck",
710         .ops            = &clkops_omap2_dflt,
711         .enable_reg     = AM33XX_CM_PER_MSTR_EXPS_CLKCTRL,
712         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
713         .clkdm_name     = "l3_clkdm",
714         .parent         = &sysclk_div_ck,
715         .recalc         = &followparent_recalc,
716 };
718 static struct clk ocmcram_fck = {
719         .name           = "ocmcram_fck",
720         .ops            = &clkops_omap2_dflt,
721         .enable_reg     = AM33XX_CM_PER_OCMCRAM_CLKCTRL,
722         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
723         .clkdm_name     = "l3_clkdm",
724         .parent         = &sysclk_div_ck,
725         .recalc         = &followparent_recalc,
726 };
728 static struct clk ocpwp_fck = {
729         .name           = "ocpwp_fck",
730         .ops            = &clkops_omap2_dflt,
731         .enable_reg     = AM33XX_CM_PER_OCPWP_CLKCTRL,
732         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
733         .clkdm_name     = "l4ls_clkdm",
734         .parent         = &core_100m_ck,
735         .recalc         = &followparent_recalc,
736 };
738 static struct clk pka_fck = {
739         .name           = "pka_fck",
740         .ops            = &clkops_omap2_dflt,
741         .enable_reg     = AM33XX_CM_PER_PKA_CLKCTRL,
742         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
743         .clkdm_name     = "l4ls_clkdm",
744         .parent         = &core_100m_ck,
745         .recalc         = &followparent_recalc,
746 };
748 static struct clk rng_fck = {
749         .name           = "rng_fck",
750         .ops            = &clkops_omap2_dflt,
751         .enable_reg     = AM33XX_CM_PER_RNG_CLKCTRL,
752         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
753         .clkdm_name     = "l4ls_clkdm",
754         .parent         = &core_100m_ck,
755         .recalc         = &followparent_recalc,
756 };
758 static struct clk rtc_fck = {
759         .name           = "rtc_fck",
760         .ops            = &clkops_omap2_dflt,
761         .enable_reg     = AM33XX_CM_RTC_RTC_CLKCTRL,
762         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
763         .clkdm_name     = "l4_rtc_clkdm",
764         .parent         = &clk_32khz_ck,
765         .recalc         = &followparent_recalc,
766 };
768 static struct clk sha0_fck = {
769         .name           = "sha0_fck",
770         .ops            = &clkops_omap2_dflt,
771         .enable_reg     = AM33XX_CM_PER_SHA0_CLKCTRL,
772         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
773         .clkdm_name     = "l3_clkdm",
774         .parent         = &sysclk_div_ck,
775         .recalc         = &followparent_recalc,
776 };
778 static struct clk slv_exps_fck = {
779         .name           = "slv_exps_fck",
780         .ops            = &clkops_omap2_dflt,
781         .enable_reg     = AM33XX_CM_PER_SLV_EXPS_CLKCTRL,
782         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
783         .clkdm_name     = "l3_clkdm",
784         .parent         = &sysclk_div_ck,
785         .recalc         = &followparent_recalc,
786 };
788 static struct clk smartreflex0_fck = {
789         .name           = "smartreflex0_fck",
790         .ops            = &clkops_omap2_dflt,
791         .enable_reg     = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL,
792         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
793         .clkdm_name     = "l4_wkup_clkdm",
794         .parent         = &sys_clkin_ck,
795         .recalc         = &followparent_recalc,
796 };
798 static struct clk smartreflex1_fck = {
799         .name           = "smartreflex1_fck",
800         .ops            = &clkops_omap2_dflt,
801         .enable_reg     = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL,
802         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
803         .clkdm_name     = "l4_wkup_clkdm",
804         .parent         = &sys_clkin_ck,
805         .recalc         = &followparent_recalc,
806 };
808 static struct clk spare0_fck = {
809         .name           = "spare0_fck",
810         .ops            = &clkops_omap2_dflt,
811         .enable_reg     = AM33XX_CM_PER_SPARE0_CLKCTRL,
812         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
813         .clkdm_name     = "l4ls_clkdm",
814         .parent         = &core_100m_ck,
815         .recalc         = &followparent_recalc,
816 };
818 static struct clk spare1_fck = {
819         .name           = "spare1_fck",
820         .ops            = &clkops_omap2_dflt,
821         .enable_reg     = AM33XX_CM_PER_SPARE1_CLKCTRL,
822         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
823         .clkdm_name     = "l4ls_clkdm",
824         .parent         = &core_100m_ck,
825         .recalc         = &followparent_recalc,
826 };
828 static struct clk spi0_fck = {
829         .name           = "spi0_fck",
830         .parent         = &dpll_per_m2_ck ,
831         .ops            = &clkops_omap2_dflt,
832         .enable_reg     = AM33XX_CM_PER_SPI0_CLKCTRL,
833         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
834         .clkdm_name     = "l4ls_clkdm",
835         .fixed_div      = 4,
836         .recalc         = &omap_fixed_divisor_recalc,
837 };
839 static struct clk spi1_fck = {
840         .name           = "spi1_fck",
841         .parent         = &dpll_per_m2_ck ,
842         .ops            = &clkops_omap2_dflt,
843         .enable_reg     = AM33XX_CM_PER_SPI1_CLKCTRL,
844         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
845         .clkdm_name     = "l4ls_clkdm",
846         .fixed_div      = 4,
847         .recalc         = &omap_fixed_divisor_recalc,
848 };
850 static struct clk spi0_ick = {
851         .name           = "spi0_ick",
852         .parent         = &l4ls_fck,
853         .ops            = &clkops_null,
854         .recalc         = &followparent_recalc,
855 };
857 static struct clk spi1_ick = {
858         .name           = "spi1_ick",
859         .parent         = &l4ls_fck,
860         .ops            = &clkops_null,
861         .recalc         = &followparent_recalc,
862 };
864 static struct clk spinlock_fck = {
865         .name           = "spinlock_fck",
866         .ops            = &clkops_omap2_dflt,
867         .enable_reg     = AM33XX_CM_PER_SPINLOCK_CLKCTRL,
868         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
869         .clkdm_name     = "l4ls_clkdm",
870         .parent         = &core_100m_ck,
871         .recalc         = &followparent_recalc,
872 };
874 static const struct clksel timer2_to_7_clk_sel[] = {
875         { .parent = &tclkin_ck, .rates = div_1_0_rates },
876         { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
877         { .parent = &clk_32khz_ck, .rates = div_1_2_rates },
878         { .parent = NULL },
879 };
881 static struct clk timer2_fck = {
882         .name           = "timer2_fck",
883         .parent         = &sys_clkin_ck,
884         .init           = &omap2_init_clksel_parent,
885         .clksel         = timer2_to_7_clk_sel,
886         .ops            = &clkops_omap2_dflt,
887         .enable_reg     = AM33XX_CM_PER_TIMER2_CLKCTRL,
888         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
889         .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
890         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
891         .clkdm_name     = "l4ls_clkdm",
892         .recalc         = &omap2_clksel_recalc,
893 };
895 static struct clk timer3_fck = {
896         .name           = "timer3_fck",
897         .parent         = &sys_clkin_ck,
898         .init           = &am33xx_init_timer_parent,
899         .clksel         = timer2_to_7_clk_sel,
900         .ops            = &clkops_omap2_dflt,
901         .enable_reg     = AM33XX_CM_PER_TIMER3_CLKCTRL,
902         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
903         .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
904         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
905         .clkdm_name     = "l4ls_clkdm",
906         .recalc         = &omap2_clksel_recalc,
907 };
909 static struct clk timer4_fck = {
910         .name           = "timer4_fck",
911         .parent         = &sys_clkin_ck,
912         .init           = &omap2_init_clksel_parent,
913         .clksel         = timer2_to_7_clk_sel,
914         .ops            = &clkops_omap2_dflt,
915         .enable_reg     = AM33XX_CM_PER_TIMER4_CLKCTRL,
916         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
917         .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
918         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
919         .clkdm_name     = "l4ls_clkdm",
920         .recalc         = &omap2_clksel_recalc,
921 };
923 static struct clk timer5_fck = {
924         .name           = "timer5_fck",
925         .parent         = &sys_clkin_ck,
926         .init           = &omap2_init_clksel_parent,
927         .clksel         = timer2_to_7_clk_sel,
928         .ops            = &clkops_omap2_dflt,
929         .enable_reg     = AM33XX_CM_PER_TIMER5_CLKCTRL,
930         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
931         .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
932         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
933         .clkdm_name     = "l4ls_clkdm",
934         .recalc         = &omap2_clksel_recalc,
935 };
937 static struct clk timer6_fck = {
938         .name           = "timer6_fck",
939         .parent         = &sys_clkin_ck,
940         .init           = &am33xx_init_timer_parent,
941         .clksel         = timer2_to_7_clk_sel,
942         .ops            = &clkops_omap2_dflt,
943         .enable_reg     = AM33XX_CM_PER_TIMER6_CLKCTRL,
944         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
945         .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
946         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
947         .clkdm_name     = "l4ls_clkdm",
948         .recalc         = &omap2_clksel_recalc,
949 };
951 static struct clk timer7_fck = {
952         .name           = "timer7_fck",
953         .parent         = &sys_clkin_ck,
954         .init           = &omap2_init_clksel_parent,
955         .clksel         = timer2_to_7_clk_sel,
956         .ops            = &clkops_omap2_dflt,
957         .enable_reg     = AM33XX_CM_PER_TIMER7_CLKCTRL,
958         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
959         .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
960         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
961         .clkdm_name     = "l4ls_clkdm",
962         .recalc         = &omap2_clksel_recalc,
963 };
965 static struct clk tpcc_ick = {
966         .name           = "tpcc_ick",
967         .ops            = &clkops_omap2_dflt,
968         .enable_reg     = AM33XX_CM_PER_TPCC_CLKCTRL,
969         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
970         .clkdm_name     = "l3_clkdm",
971         .parent         = &l3_main_fck,
972         .recalc         = &followparent_recalc,
973 };
975 static struct clk tptc0_ick = {
976         .name           = "tptc0_ick",
977         .ops            = &clkops_omap2_dflt,
978         .enable_reg     = AM33XX_CM_PER_TPTC0_CLKCTRL,
979         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
980         .clkdm_name     = "l3_clkdm",
981         .parent         = &l3_main_fck,
982         .recalc         = &followparent_recalc,
983 };
985 static struct clk tptc1_ick = {
986         .name           = "tptc1_ick",
987         .ops            = &clkops_omap2_dflt,
988         .enable_reg     = AM33XX_CM_PER_TPTC1_CLKCTRL,
989         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
990         .clkdm_name     = "l3_clkdm",
991         .parent         = &l3_main_fck,
992         .recalc         = &followparent_recalc,
993 };
995 static struct clk tptc2_ick = {
996         .name           = "tptc2_ick",
997         .ops            = &clkops_omap2_dflt,
998         .enable_reg     = AM33XX_CM_PER_TPTC2_CLKCTRL,
999         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1000         .clkdm_name     = "l3_clkdm",
1001         .parent         = &l3_main_fck,
1002         .recalc         = &followparent_recalc,
1003 };
1005 static struct clk uart1_fck = {
1006         .name           = "uart1_fck",
1007         .parent         = &dpll_per_m2_ck ,
1008         .ops            = &clkops_omap2_dflt,
1009         .enable_reg     = AM33XX_CM_WKUP_UART0_CLKCTRL,
1010         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1011         .clkdm_name     = "l4_wkup_clkdm",
1012         .fixed_div      = 4,
1013         .recalc         = &omap_fixed_divisor_recalc,
1014 };
1016 static struct clk uart2_fck = {
1017         .name           = "uart2_fck",
1018         .parent         = &dpll_per_m2_ck ,
1019         .ops            = &clkops_omap2_dflt,
1020         .enable_reg     = AM33XX_CM_PER_UART1_CLKCTRL,
1021         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1022         .clkdm_name     = "l4ls_clkdm",
1023         .fixed_div      = 4,
1024         .recalc         = &omap_fixed_divisor_recalc,
1025 };
1027 static struct clk uart3_fck = {
1028         .name           = "uart3_fck",
1029         .parent         = &dpll_per_m2_ck ,
1030         .ops            = &clkops_omap2_dflt,
1031         .enable_reg     = AM33XX_CM_PER_UART2_CLKCTRL,
1032         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1033         .clkdm_name     = "l4ls_clkdm",
1034         .fixed_div      = 4,
1035         .recalc         = &omap_fixed_divisor_recalc,
1036 };
1038 static struct clk uart4_fck = {
1039         .name           = "uart4_fck",
1040         .parent         = &dpll_per_m2_ck ,
1041         .ops            = &clkops_omap2_dflt,
1042         .enable_reg     = AM33XX_CM_PER_UART3_CLKCTRL,
1043         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1044         .clkdm_name     = "l4ls_clkdm",
1045         .fixed_div      = 4,
1046         .recalc         = &omap_fixed_divisor_recalc,
1047 };
1049 static struct clk uart5_fck = {
1050         .name           = "uart5_fck",
1051         .parent         = &dpll_per_m2_ck ,
1052         .ops            = &clkops_omap2_dflt,
1053         .enable_reg     = AM33XX_CM_PER_UART4_CLKCTRL,
1054         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1055         .clkdm_name     = "l4ls_clkdm",
1056         .fixed_div      = 4,
1057         .recalc         = &omap_fixed_divisor_recalc,
1058 };
1060 static struct clk uart6_fck = {
1061         .name           = "uart6_fck",
1062         .parent         = &dpll_per_m2_ck ,
1063         .ops            = &clkops_omap2_dflt,
1064         .enable_reg     = AM33XX_CM_PER_UART5_CLKCTRL,
1065         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1066         .clkdm_name     = "l4ls_clkdm",
1067         .fixed_div      = 4,
1068         .recalc         = &omap_fixed_divisor_recalc,
1069 };
1071 static struct clk uart1_ick = {
1072         .name           = "uart1_ick",
1073         .parent         = &div_l4_wkup_gclk_ck,
1074         .ops            = &clkops_null,
1075         .recalc         = &followparent_recalc,
1076 };
1078 static struct clk uart2_ick = {
1079         .name           = "uart2_ick",
1080         .parent         = &l4ls_fck,
1081         .ops            = &clkops_null,
1082         .recalc         = &followparent_recalc,
1083 };
1085 static struct clk uart3_ick = {
1086         .name           = "uart3_ick",
1087         .parent         = &l4ls_fck,
1088         .ops            = &clkops_null,
1089         .recalc         = &followparent_recalc,
1090 };
1092 static struct clk uart4_ick = {
1093         .name           = "uart4_ick",
1094         .parent         = &l4ls_fck,
1095         .ops            = &clkops_null,
1096         .recalc         = &followparent_recalc,
1097 };
1099 static struct clk uart5_ick = {
1100         .name           = "uart5_ick",
1101         .parent         = &l4ls_fck,
1102         .ops            = &clkops_null,
1103         .recalc         = &followparent_recalc,
1104 };
1106 static struct clk uart6_ick = {
1107         .name           = "uart6_ick",
1108         .parent         = &l4ls_fck,
1109         .ops            = &clkops_null,
1110         .recalc         = &followparent_recalc,
1111 };
1113 static struct clk wkup_m3_fck = {
1114         .name           = "wkup_m3_fck",
1115         .ops            = &clkops_omap2_dflt,
1116         .enable_reg     = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL,
1117         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1118         .clkdm_name     = "l4_wkup_aon_clkdm",
1119         .parent         = &div_l4_wkup_gclk_ck,
1120         .recalc         = &followparent_recalc,
1121 };
1123 static struct clk dpll_core_m5_ck = {
1124         .name           = "dpll_core_m5_ck",
1125         .parent         = &dpll_core_x2_ck,
1126         .clksel         = dpll_core_m4_div,
1127         .clksel_reg     = AM33XX_CM_DIV_M5_DPLL_CORE,
1128         .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
1129         .ops            = &clkops_null,
1130         .recalc         = &omap2_clksel_recalc,
1131         .round_rate     = &omap2_clksel_round_rate,
1132         .set_rate       = &omap2_clksel_set_rate,
1133 };
1135 static struct clk cpsw_250m_clkdiv_ck = {
1136         .name           = "cpsw_250m_clkdiv_ck",
1137         .parent         = &dpll_core_m5_ck,
1138         .ops            = &clkops_null,
1139         .recalc         = &followparent_recalc,
1140 };
1142 static struct clk cpsw_125mhz_ocp_ck = {
1143         .name           = "cpsw_125mhz_ocp_ck",
1144         .parent         = &dpll_core_m5_ck,
1145         .ops            = &clkops_null,
1146         .fixed_div      = 2,
1147         .recalc         = &omap_fixed_divisor_recalc,
1148 };
1150 static struct clk cpsw_50m_clkdiv_ck = {
1151         .name           = "cpsw_50m_clkdiv_ck",
1152         .parent         = &dpll_core_m5_ck,
1153         .ops            = &clkops_null,
1154         .fixed_div      = 5,
1155         .recalc         = &omap_fixed_divisor_recalc,
1156 };
1158 static struct clk cpgmac0_fck = {
1159         .name           = "cpgmac0_fck",
1160         .ops            = &clkops_omap2_dflt,
1161         .enable_reg     = AM33XX_CM_PER_CPGMAC0_CLKCTRL,
1162         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1163         .clkdm_name     = "cpsw_125mhz_clkdm",
1164         .parent         = &cpsw_125mhz_ocp_ck,
1165         .recalc         = &followparent_recalc,
1166 };
1168 static struct clk cpsw_5m_clkdiv_ck = {
1169         .name           = "cpsw_5m_clkdiv_ck",
1170         .parent         = &cpsw_50m_clkdiv_ck,
1171         .ops            = &clkops_null,
1172         .fixed_div      = 10,
1173         .recalc         = &omap_fixed_divisor_recalc,
1174 };
1177 static const struct clksel cpts_rft_clkmux_sel[] = {
1178         { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
1179         { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
1180         { .parent = NULL },
1181 };
1183 static struct clk cpts_rft_clkmux_ck = {
1184         .name           = "cpts_rft_clkmux_ck",
1185         .parent         = &dpll_core_m5_ck,
1186         .ops            = &clkops_null,
1187         .recalc         = &followparent_recalc,
1188 };
1192 /* DPLL_DDR */
1193 static struct dpll_data dpll_ddr_dd = {
1194         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
1195         .clk_bypass     = &sys_clkin_ck,
1196         .clk_ref        = &sys_clkin_ck,
1197         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
1198         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1199         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
1200         .mult_mask      = AM33XX_DPLL_MULT_MASK,
1201         .div1_mask      = AM33XX_DPLL_DIV_MASK,
1202         .enable_mask    = AM33XX_DPLL_EN_MASK,
1203         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
1204         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
1205         .max_multiplier = AM33XX_MAX_DPLL_MULT,
1206         .max_divider    = AM33XX_MAX_DPLL_DIV,
1207         .min_divider    = 1,
1208 };
1211 static struct clk dpll_ddr_ck = {
1212         .name           = "dpll_ddr_ck",
1213         .parent         = &sys_clkin_ck,
1214         .dpll_data      = &dpll_ddr_dd,
1215         .init           = &omap2_init_dpll_parent,
1216         .ops            = &clkops_null,
1217         .recalc         = &omap3_dpll_recalc,
1218 };
1220 static const struct clksel dpll_ddr_m2_div[] = {
1221         { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
1222         { .parent = NULL },
1223 };
1225 static struct clk dpll_ddr_m2_ck = {
1226         .name           = "dpll_ddr_m2_ck",
1227         .parent         = &dpll_ddr_ck,
1228         .clksel         = dpll_ddr_m2_div,
1229         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DDR,
1230         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1231         .ops            = &clkops_null,
1232         .recalc         = &omap2_clksel_recalc,
1233         .round_rate     = &omap2_clksel_round_rate,
1234         .set_rate       = &omap2_clksel_set_rate,
1235 };
1237 static struct clk ddr_pll_div_clk = {
1238         .name           = "ddr_pll_div_clk",
1239         .parent         = &dpll_ddr_m2_ck,
1240         .ops            = &clkops_null,
1241         .recalc         = &followparent_recalc,
1242 };
1244 static struct clk emif_fck = {
1245         .name           = "emif_fck",
1246         .ops            = &clkops_omap2_dflt,
1247         .enable_reg     = AM33XX_CM_PER_EMIF_CLKCTRL,
1248         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1249         .clkdm_name     = "l3_clkdm",
1250         .parent         = &ddr_pll_div_clk,
1251         .recalc         = &followparent_recalc,
1252         .flags          = ENABLE_ON_INIT,
1253 };
1255 static struct clk div_l4_rtc_gclk_ck = {
1256         .name           = "div_l4_rtc_gclk_ck",
1257         .parent         = &dpll_core_m4_ck,
1258         .ops            = &clkops_null,
1259         .recalc         = &followparent_recalc,
1260 };
1262 /* DPLL_DISP */
1263 static struct dpll_data dpll_disp_dd = {
1264         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
1265         .clk_bypass     = &sys_clkin_ck,
1266         .clk_ref        = &sys_clkin_ck,
1267         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
1268         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1269         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
1270         .mult_mask      = AM33XX_DPLL_MULT_MASK,
1271         .div1_mask      = AM33XX_DPLL_DIV_MASK,
1272         .enable_mask    = AM33XX_DPLL_EN_MASK,
1273         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
1274         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
1275         .max_multiplier = AM33XX_MAX_DPLL_MULT,
1276         .max_divider    = AM33XX_MAX_DPLL_DIV,
1277         .min_divider    = 1,
1278 };
1280 static struct clk dpll_disp_ck = {
1281         .name           = "dpll_disp_ck",
1282         .parent         = &sys_clkin_ck,
1283         .dpll_data      = &dpll_disp_dd,
1284         .init           = &omap2_init_dpll_parent,
1285         .ops            = &clkops_omap3_noncore_dpll_ops,
1286         .recalc         = &omap3_dpll_recalc,
1287         .round_rate     = &omap2_dpll_round_rate,
1288         .set_rate       = &omap3_noncore_dpll_set_rate,
1289 };
1291 static const struct clksel dpll_disp_m2_div[] = {
1292         { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
1293         { .parent = NULL },
1294 };
1296 static struct clk dpll_disp_m2_ck = {
1297         .name           = "dpll_disp_m2_ck",
1298         .parent         = &dpll_disp_ck,
1299         .clksel         = dpll_disp_m2_div,
1300         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DISP,
1301         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1302         .ops            = &clkops_null,
1303         .recalc         = &omap2_clksel_recalc,
1304         .round_rate     = &omap2_clksel_round_rate,
1305         .set_rate       = &omap2_clksel_set_rate,
1306 };
1308 /* DPLL_MPU */
1309 static struct dpll_data dpll_mpu_dd = {
1310         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
1311         .clk_bypass     = &sys_clkin_ck,
1312         .clk_ref        = &sys_clkin_ck,
1313         .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
1314         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1315         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
1316         .mult_mask      = AM33XX_DPLL_MULT_MASK,
1317         .div1_mask      = AM33XX_DPLL_DIV_MASK,
1318         .enable_mask    = AM33XX_DPLL_EN_MASK,
1319         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
1320         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
1321         .max_multiplier = AM33XX_MAX_DPLL_MULT,
1322         .max_divider    = AM33XX_MAX_DPLL_DIV,
1323         .min_divider    = 1,
1324 };
1326 static struct clk dpll_mpu_ck = {
1327         .name           = "dpll_mpu_ck",
1328         .parent         = &sys_clkin_ck,
1329         .dpll_data      = &dpll_mpu_dd,
1330         .init           = &omap2_init_dpll_parent,
1331         .ops            = &clkops_omap3_noncore_dpll_ops,
1332         .recalc         = &omap3_dpll_recalc,
1333         .round_rate     = &omap2_dpll_round_rate,
1334         .set_rate       = &omap3_noncore_dpll_set_rate,
1335 };
1338 static const struct clksel dpll_mpu_m2_div[] = {
1339         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
1340         { .parent = NULL },
1341 };
1343 static struct clk dpll_mpu_m2_ck = {
1344         .name           = "dpll_mpu_m2_ck",
1345         .parent         = &dpll_mpu_ck,
1346         .clksel         = dpll_mpu_m2_div,
1347         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_MPU,
1348         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1349         .ops            = &clkops_null,
1350         .recalc         = &omap2_clksel_recalc,
1351         .round_rate     = &omap2_clksel_round_rate,
1352         .set_rate       = &omap2_clksel_set_rate,
1353 };
1355 static struct clk mpu_fck = {
1356         .name           = "mpu_fck",
1357         .ops            = &clkops_omap2_dflt,
1358         .enable_reg     = AM33XX_CM_MPU_MPU_CLKCTRL,
1359         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1360         .clkdm_name     = "mpu_clkdm",
1361         .parent         = &dpll_mpu_m2_ck,
1362         .recalc         = &followparent_recalc,
1363 };
1365 static struct clk dpll_per_clkdcoldo_ck = {
1366         .name           = "dpll_per_clkdcoldo_ck",
1367         .parent         = &dpll_per_ck,
1368         .ops            = &clkops_null,
1369         .recalc         = &followparent_recalc,
1370 };
1373 static const struct clksel gpio_dbclk_mux_sel[] = {
1374         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1375         { .parent = &clk_32768_ck, .rates = div_1_1_rates },
1376         { .parent = &clk_32khz_ck, .rates = div_1_2_rates },
1377         { .parent = NULL },
1378 };
1380 static struct clk usbotg_ick = {
1381         .name           = "usbotg_ick",
1382         .parent         = &core_100m_ck,
1383         .ops            = &clkops_omap2_dflt,
1384         .clkdm_name     = "l3s_clkdm",
1385         .enable_reg     = AM33XX_CM_PER_USB0_CLKCTRL,
1386         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1387         .recalc         = &followparent_recalc,
1388 };
1390 static struct clk usbotg_fck = {
1391         .name           = "usbotg_fck",
1392         .ops            = &clkops_omap2_dflt,
1393         .clkdm_name     = "wkup_usb_clkdm",
1394         .enable_reg     = AM33XX_CM_CLKDCOLDO_DPLL_PER,
1395         .enable_bit     = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
1396         .parent         = &dpll_per_clkdcoldo_ck,
1397         .recalc         = &followparent_recalc,
1398 };
1400 static struct clk gpio_dbclk_mux_ck = {
1401         .name           = "gpio_dbclk_mux_ck",
1402         .parent         = &sys_clkin_ck,
1403         .init           = &omap2_init_clksel_parent,
1404         .clksel         = gpio_dbclk_mux_sel,
1405         .ops            = &clkops_null,
1406         .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
1407         .clksel_mask    = (3 << 0),
1408         .clkdm_name     = "l4_wkup_clkdm",
1409         .recalc         = &omap2_clksel_recalc,
1410 };
1412 static struct clk gpio0_dbclk = {
1413         .name           = "gpio0_dbclk",
1414         .parent         = &gpio_dbclk_mux_ck,
1415         .ops            = &clkops_omap2_dflt,
1416         .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
1417         .enable_bit     = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
1418         .clkdm_name     = "l4_wkup_clkdm",
1419         .recalc         = &followparent_recalc,
1420 };
1422 static struct clk gpio1_dbclk = {
1423         .name           = "gpio1_dbclk",
1424         .parent         = &clkdiv32k_fck,
1425         .ops            = &clkops_omap2_dflt,
1426         .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
1427         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
1428         .clkdm_name     = "l4ls_clkdm",
1429         .recalc         = &followparent_recalc,
1430 };
1432 static struct clk gpio2_dbclk = {
1433         .name           = "gpio2_dbclk",
1434         .parent         = &clkdiv32k_fck,
1435         .ops            = &clkops_omap2_dflt,
1436         .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
1437         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
1438         .clkdm_name     = "l4ls_clkdm",
1439         .recalc         = &followparent_recalc,
1440 };
1442 static struct clk gpio3_dbclk = {
1443         .name           = "gpio3_dbclk",
1444         .parent         = &clkdiv32k_fck,
1445         .ops            = &clkops_omap2_dflt,
1446         .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
1447         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
1448         .clkdm_name     = "l4ls_clkdm",
1449         .recalc         = &followparent_recalc,
1450 };
1452 static const struct clksel icss_ocp_clk_mux_sel[] = {
1453         { .parent = &sysclk_div_ck, .rates = div_1_0_rates },
1454         { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
1455         { .parent = NULL },
1456 };
1458 static struct clk icss_ocp_clk_mux_ck = {
1459         .name           = "icss_ocp_clk_mux_ck",
1460         .parent         = &sysclk_div_ck,
1461         .ops            = &clkops_null,
1462         .recalc         = &followparent_recalc,
1463 };
1466 static const struct clksel lcd_clk_mux_sel[] = {
1467         { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
1468         { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
1469         { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
1470         { .parent = NULL },
1471 };
1473 static struct clk lcd_clk_mux_ck = {
1474         .name           = "lcd_clk_mux_ck",
1475         .parent         = &dpll_disp_m2_ck,
1476         .ops            = &clkops_null,
1477         .recalc         = &followparent_recalc,
1478 };
1480 static struct clk lcdc_fck = {
1481         .name           = "lcdc_fck",
1482         .ops            = &clkops_omap2_dflt,
1483         .init           = &omap2_init_clksel_parent,
1484         .clksel         = lcd_clk_mux_sel,
1485         .enable_reg     = AM33XX_CM_PER_LCDC_CLKCTRL,
1486         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1487         .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
1488         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1489         .clkdm_name     = "lcdc_clkdm",
1490         .parent         = &dpll_disp_m2_ck,
1491         .recalc         = &followparent_recalc,
1492 };
1494 static struct clk mmc0_ick = {
1495         .name           = "mmc0_ick",
1496         .parent         = &l4ls_fck,
1497         .ops            = &clkops_null,
1498         .recalc         = &followparent_recalc,
1499 };
1501 static struct clk mmc1_ick = {
1502         .name           = "mmc1_ick",
1503         .parent         = &l4ls_fck,
1504         .ops            = &clkops_null,
1505         .recalc         = &followparent_recalc,
1506 };
1508 static struct clk mmc2_ick = {
1509         .name           = "mmc2_ick",
1510         .parent         = &l3_main_fck,
1511         .ops            = &clkops_null,
1512         .recalc         = &followparent_recalc,
1513 };
1515 static struct clk mmc_clk = {
1516         .name           = "mmc_clk",
1517         .parent         = &dpll_per_m2_ck,
1518         .ops            = &clkops_null,
1519         .fixed_div      = 2,
1520         .recalc         = &omap_fixed_divisor_recalc,
1521 };
1523 static struct clk mmc0_fck = {
1524         .name           = "mmc0_fck",
1525         .ops            = &clkops_omap2_dflt,
1526         .enable_reg     = AM33XX_CM_PER_MMC0_CLKCTRL,
1527         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1528         .clkdm_name     = "l4ls_clkdm",
1529         .parent         = &mmc_clk,
1530         .recalc         = &followparent_recalc,
1531 };
1533 static struct clk mmc1_fck = {
1534         .name           = "mmc1_fck",
1535         .ops            = &clkops_omap2_dflt,
1536         .enable_reg     = AM33XX_CM_PER_MMC1_CLKCTRL,
1537         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1538         .clkdm_name     = "l4ls_clkdm",
1539         .parent         = &mmc_clk,
1540         .recalc         = &followparent_recalc,
1541 };
1543 static struct clk mmc2_fck = {
1544         .name           = "mmc2_fck",
1545         .ops            = &clkops_omap2_dflt,
1546         .enable_reg     = AM33XX_CM_PER_MMC2_CLKCTRL,
1547         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1548         .clkdm_name     = "l3s_clkdm",
1549         .parent         = &mmc_clk,
1550         .recalc         = &followparent_recalc,
1551 };
1553 static const struct clksel sgx_clksel_sel[] = {
1554         { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
1555         { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
1556         { .parent = NULL },
1557 };
1559 static struct clk sgx_clksel_ck = {
1560         .name           = "sgx_clksel_ck",
1561         .parent         = &dpll_core_m4_ck,
1562         .clksel         = sgx_clksel_sel,
1563         .ops            = &clkops_null,
1564         .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
1565         .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
1566         .recalc         = &omap2_clksel_recalc,
1567 };
1569 static const struct clksel_rate div_1_0_2_1_rates[] = {
1570         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
1571         { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
1572         { .div = 0 },
1573 };
1575 static const struct clksel sgx_div_sel[] = {
1576         { .parent = &sgx_clksel_ck, .rates = div_1_0_2_1_rates },
1577         { .parent = NULL },
1578 };
1580 static struct clk sgx_ck = {
1581         .name           = "sgx_ck",
1582         .parent         = &sgx_clksel_ck,
1583         .clksel         = sgx_div_sel,
1584         .ops            = &clkops_null,
1585         .enable_reg     = AM33XX_CM_GFX_GFX_CLKCTRL,
1586         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1587         .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
1588         .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
1589         .clkdm_name     = "gfx_l3_clkdm",
1590         .recalc         = &omap2_clksel_recalc,
1591         .round_rate     = &omap2_clksel_round_rate,
1592         .set_rate       = &omap2_clksel_set_rate,
1593 };
1595 static const struct clksel sysclkout_pre_sel[] = {
1596         { .parent = &clk_32768_ck, .rates = div_1_0_rates },
1597         { .parent = &sysclk_div_ck, .rates = div_1_1_rates },
1598         { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
1599         { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
1600         { .parent = &lcd_clk_mux_ck, .rates = div_1_4_rates },
1601         { .parent = NULL },
1602 };
1604 static struct clk sysclkout_pre_ck = {
1605         .name           = "sysclkout_pre_ck",
1606         .init           = &omap2_init_clksel_parent,
1607         .ops            = &clkops_null,
1608         .clksel         = sysclkout_pre_sel,
1609         .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
1610         .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
1611         .recalc         = &omap2_clksel_recalc,
1612 };
1614 /* Divide by 8 clock rates with default clock is 1/1*/
1615 static const struct clksel_rate div8_rates[] = {
1616         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
1617         { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
1618         { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
1619         { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
1620         { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
1621         { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
1622         { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
1623         { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
1624         { .div = 0 },
1625 };
1627 static const struct clksel clkout2_div[] = {
1628         { .parent = &sysclkout_pre_ck, .rates = div8_rates },
1629         { .parent = NULL },
1630 };
1632 static struct clk clkout2_ck = {
1633         .name           = "clkout2_ck",
1634         .parent         = &sysclkout_pre_ck,
1635         .ops            = &clkops_omap2_dflt,
1636         .clksel         = clkout2_div,
1637         .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
1638         .clksel_mask    = AM33XX_CLKOUT2DIV_MASK,
1639         .enable_reg     = AM33XX_CM_CLKOUT_CTRL,
1640         .enable_bit     = AM33XX_CLKOUT2EN_SHIFT,
1641         .recalc         = &omap2_clksel_recalc,
1642         .round_rate     = &omap2_clksel_round_rate,
1643         .set_rate       = &omap2_clksel_set_rate,
1644 };
1646 static const struct clksel timer0_clkmux_sel[] = {
1647         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1648         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1649         { .parent = &sys_clkin_ck, .rates = div_1_2_rates },
1650         { .parent = &tclkin_ck, .rates = div_1_3_rates },
1651         { .parent = NULL },
1652 };
1654 static struct clk timer0_clkmux_ck = {
1655         .name           = "timer0_clkmux_ck",
1656         .parent         = &clk_rc32k_ck,
1657         .ops            = &clkops_null,
1658         .recalc         = &followparent_recalc,
1659 };
1661 static struct clk timer0_ick = {
1662         .name           = "timer0_ick",
1663         .parent         = &div_l4_wkup_gclk_ck,
1664         .ops            = &clkops_null,
1665         .recalc         = &followparent_recalc,
1666 };
1669 static struct clk timer0_fck = {
1670         .name           = "timer0_fck",
1671         .ops            = &clkops_omap2_dflt,
1672         .enable_reg     = AM33XX_CM_WKUP_TIMER0_CLKCTRL,
1673         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1674         .clkdm_name     = "l4_wkup_clkdm",
1675         .parent         = &timer0_clkmux_ck,
1676         .recalc         = &followparent_recalc,
1677 };
1679 static const struct clksel timer1_clkmux_sel[] = {
1680         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1681         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1682         { .parent = &tclkin_ck, .rates = div_1_2_rates },
1683         { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
1684         { .parent = &clk_32768_ck, .rates = div_1_4_rates },
1685         { .parent = NULL },
1686 };
1688 static struct clk timer1_ick = {
1689         .name           = "timer1_ick",
1690         .parent         = &div_l4_wkup_gclk_ck,
1691         .ops            = &clkops_null,
1692         .recalc         = &followparent_recalc,
1693 };
1695 static struct clk timer1_fck = {
1696         .name           = "timer1_fck",
1697         .parent         = &sys_clkin_ck,
1698         .init           = &omap2_init_clksel_parent,
1699         .clksel         = timer1_clkmux_sel,
1700         .ops            = &clkops_omap2_dflt,
1701         .enable_reg     = AM33XX_CM_WKUP_TIMER1_CLKCTRL,
1702         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1703         .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
1704         .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
1705         .clkdm_name     = "l4ls_clkdm",
1706         .recalc         = &omap2_clksel_recalc,
1707 };
1709 static struct clk vtp_clk_div_ck = {
1710         .name           = "vtp_clk_div_ck",
1711         .parent         = &sys_clkin_ck,
1712         .ops            = &clkops_null,
1713         .recalc         = &followparent_recalc,
1714         .flags          = ENABLE_ON_INIT,
1715 };
1719 static const struct clksel wdt0_clkmux_sel[] = {
1720         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1721         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1722         { .parent = NULL },
1723 };
1725 static struct clk wdt0_clkmux_ck = {
1726         .name           = "wdt0_clkmux_ck",
1727         .parent         = &clk_32khz_ck,
1728         .ops            = &clkops_null,
1729         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_PER,
1730         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1731         .recalc         = &followparent_recalc,
1732 };
1734 static struct clk wd_timer1_fck = {
1735         .name           = "wd_timer1_fck",
1736         .init           = &omap2_init_clksel_parent,
1737         .clksel         = wdt0_clkmux_sel,
1738         .ops            = &clkops_omap2_dflt,
1739         .enable_reg     = AM33XX_CM_WKUP_WDT1_CLKCTRL,
1740         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1741         .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
1742         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1743         .clkdm_name     = "l4_wkup_clkdm",
1744         .recalc         = &omap2_clksel_recalc,
1745 };
1747 static struct clk wdt0_fck = {
1748         .name           = "wdt0_fck",
1749         .ops            = &clkops_omap2_dflt,
1750         .enable_reg     = AM33XX_CM_WKUP_WDT0_CLKCTRL,
1751         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1752         .clkdm_name     = "l4_wkup_clkdm",
1753         .parent         = &wdt0_clkmux_ck,
1754         .recalc         = &followparent_recalc,
1755 };
1757 /*
1758  * clkdev
1759  */
1760 static struct omap_clk am33xx_clks[] = {
1761         CLK(NULL,       "clk_32768_ck",         &clk_32768_ck,  CK_AM33XX),
1762         CLK(NULL,       "clk_32khz_ck",         &clk_32khz_ck,  CK_AM33XX),
1763         CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck,  CK_AM33XX),
1764         CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck,  CK_AM33XX),
1765         CLK(NULL,       "tclkin_ck",            &tclkin_ck,     CK_AM33XX),
1766         CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck,   CK_AM33XX),
1767         CLK(NULL,       "adc_tsc_ick",          &adc_tsc_ick,   CK_AM33XX),
1768         CLK(NULL,       "aes0_fck",             &aes0_fck,      CK_AM33XX),
1769         CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
1770         CLK(NULL,       "clkdiv32k_fck",        &clkdiv32k_fck, CK_AM33XX),
1771         CLK(NULL,       "control_fck",          &control_fck,   CK_AM33XX),
1772         CLK("cpsw.0",   NULL,                   &cpgmac0_fck,   CK_AM33XX),
1773         CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
1774         CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
1775         CLK(NULL,       "dcan0_ick",            &dcan0_ick,     CK_AM33XX),
1776         CLK(NULL,       "dcan1_ick",            &dcan1_ick,     CK_AM33XX),
1777         CLK(NULL,       "debugss_fck",          &debugss_fck,   CK_AM33XX),
1778         CLK(NULL,       "elm_fck",              &elm_fck,       CK_AM33XX),
1779         CLK(NULL,       "emif_fck",             &emif_fck,      CK_AM33XX),
1780         CLK(NULL,       "emif_fw_fck",          &emif_fw_fck,   CK_AM33XX),
1781         CLK(NULL,       "epwmss0_fck",          &epwmss0_fck,   CK_AM33XX),
1782         CLK(NULL,       "epwmss1_fck",          &epwmss1_fck,   CK_AM33XX),
1783         CLK(NULL,       "epwmss2_fck",          &epwmss2_fck,   CK_AM33XX),
1784         CLK(NULL,       "gpio0_fck",            &gpio0_fck,     CK_AM33XX),
1785         CLK(NULL,       "gpio1_fck",            &gpio1_fck,     CK_AM33XX),
1786         CLK(NULL,       "gpio2_fck",            &gpio2_fck,     CK_AM33XX),
1787         CLK(NULL,       "gpio3_fck",            &gpio3_fck,     CK_AM33XX),
1788         CLK(NULL,       "gpmc_fck",             &gpmc_fck,      CK_AM33XX),
1789         CLK("omap_i2c.1",       "fck",          &i2c1_fck,      CK_AM33XX),
1790         CLK("omap_i2c.2",       "fck",          &i2c2_fck,      CK_AM33XX),
1791         CLK("omap_i2c.3",       "fck",          &i2c3_fck,      CK_AM33XX),
1792         CLK(NULL,       "icss_fck",             &icss_fck,      CK_AM33XX),
1793         CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
1794         CLK(NULL,       "l3_instr_fck",         &l3_instr_fck,  CK_AM33XX),
1795         CLK(NULL,       "l3_main_fck",          &l3_main_fck,   CK_AM33XX),
1796         CLK(NULL,       "l4_hs_fck",            &l4_hs_fck,     CK_AM33XX),
1797         CLK(NULL,       "l4fw_fck",             &l4fw_fck,      CK_AM33XX),
1798         CLK(NULL,       "l4ls_fck",             &l4ls_fck,      CK_AM33XX),
1799         CLK(NULL,       "l4wkup_fck",           &l4wkup_fck,    CK_AM33XX),
1800         CLK("da8xx_lcdc.0",     NULL,           &lcdc_fck,      CK_AM33XX),
1801         CLK(NULL,       "mailbox0_fck",         &mailbox0_fck,  CK_AM33XX),
1802         CLK(NULL,       "mcasp1_ick",           &mcasp0_ick,    CK_AM33XX),
1803         CLK(NULL,       "mcasp2_ick",           &mcasp1_ick,    CK_AM33XX),
1804         CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
1805         CLK("davinci-mcasp.1",  NULL,           &mcasp1_fck,    CK_AM33XX),
1806         CLK(NULL,       "mlb_fck",              &mlb_fck,       CK_AM33XX),
1807         CLK("omap_hsmmc.0",     "ick",          &mmc0_ick,      CK_AM33XX),
1808         CLK("omap_hsmmc.1",     "ick",          &mmc1_ick,      CK_AM33XX),
1809         CLK("omap_hsmmc.2",     "ick",          &mmc2_ick,      CK_AM33XX),
1810         CLK("omap_hsmmc.0",     "fck",          &mmc0_fck,      CK_AM33XX),
1811         CLK("omap_hsmmc.1",     "fck",          &mmc1_fck,      CK_AM33XX),
1812         CLK("omap_hsmmc.2",     "fck",          &mmc2_fck,      CK_AM33XX),
1813         CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
1814         CLK(NULL,       "mpu_ck",               &mpu_fck,       CK_AM33XX),
1815         CLK(NULL,       "mstr_exps_fck",        &mstr_exps_fck, CK_AM33XX),
1816         CLK(NULL,       "ocmcram_fck",          &ocmcram_fck,   CK_AM33XX),
1817         CLK(NULL,       "ocpwp_fck",            &ocpwp_fck,     CK_AM33XX),
1818         CLK(NULL,       "pka_fck",              &pka_fck,       CK_AM33XX),
1819         CLK(NULL,       "rng_fck",              &rng_fck,       CK_AM33XX),
1820         CLK(NULL,       "rtc_fck",              &rtc_fck,       CK_AM33XX),
1821         CLK(NULL,       "sha0_fck",             &sha0_fck,      CK_AM33XX),
1822         CLK(NULL,       "slv_exps_fck",         &slv_exps_fck,  CK_AM33XX),
1823         CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
1824         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
1825         CLK(NULL,       "spare0_fck",           &spare0_fck,    CK_AM33XX),
1826         CLK(NULL,       "spare1_fck",           &spare1_fck,    CK_AM33XX),
1827         CLK("omap2_mcspi.1",    "fck",          &spi0_fck,      CK_AM33XX),
1828         CLK("omap2_mcspi.2",    "fck",          &spi1_fck,      CK_AM33XX),
1829         CLK("omap2_mcspi.1",    "ick",          &spi0_ick,      CK_AM33XX),
1830         CLK("omap2_mcspi.2",    "ick",          &spi1_ick,      CK_AM33XX),
1831         CLK(NULL,       "spinlock_fck",         &spinlock_fck,  CK_AM33XX),
1832         CLK(NULL,       "timer0_fck",           &timer0_fck,    CK_AM33XX),
1833         CLK(NULL,       "gpt1_fck",             &timer1_fck,    CK_AM33XX),
1834         CLK(NULL,       "gpt2_fck",             &timer2_fck,    CK_AM33XX),
1835         CLK(NULL,       "gpt3_fck",             &timer3_fck,    CK_AM33XX),
1836         CLK(NULL,       "gpt4_fck",             &timer4_fck,    CK_AM33XX),
1837         CLK(NULL,       "gpt5_fck",             &timer5_fck,    CK_AM33XX),
1838         CLK(NULL,       "gpt6_fck",             &timer6_fck,    CK_AM33XX),
1839         CLK(NULL,       "gpt7_fck",             &timer7_fck,    CK_AM33XX),
1840         CLK(NULL,       "lcdc_ick_l3_clk",      &lcdc_l3ick,    CK_AM33XX),
1841         CLK(NULL,       "lcdc_ick_l4_clk",      &lcdc_l4ick,    CK_AM33XX),
1842         CLK(NULL,       "tpcc_ick",             &tpcc_ick,      CK_AM33XX),
1843         CLK(NULL,       "tptc0_ick",            &tptc0_ick,     CK_AM33XX),
1844         CLK(NULL,       "tptc1_ick",            &tptc1_ick,     CK_AM33XX),
1845         CLK(NULL,       "tptc2_ick",            &tptc2_ick,     CK_AM33XX),
1846         CLK(NULL,       "uart1_fck",            &uart1_fck,     CK_AM33XX),
1847         CLK(NULL,       "uart2_fck",            &uart2_fck,     CK_AM33XX),
1848         CLK(NULL,       "uart3_fck",            &uart3_fck,     CK_AM33XX),
1849         CLK(NULL,       "uart4_fck",            &uart4_fck,     CK_AM33XX),
1850         CLK(NULL,       "uart5_fck",            &uart5_fck,     CK_AM33XX),
1851         CLK(NULL,       "uart6_fck",            &uart6_fck,     CK_AM33XX),
1852         CLK(NULL,       "uart1_ick",            &uart1_ick,     CK_AM33XX),
1853         CLK(NULL,       "uart2_ick",            &uart2_ick,     CK_AM33XX),
1854         CLK(NULL,       "uart3_ick",            &uart3_ick,     CK_AM33XX),
1855         CLK(NULL,       "uart4_ick",            &uart4_ick,     CK_AM33XX),
1856         CLK(NULL,       "uart5_ick",            &uart5_ick,     CK_AM33XX),
1857         CLK(NULL,       "uart6_ick",            &uart6_ick,     CK_AM33XX),
1858         CLK(NULL,       "usbotg_ick",           &usbotg_ick,    CK_AM33XX),
1859         CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
1860         CLK(NULL,       "wd_timer1_fck",        &wd_timer1_fck, CK_AM33XX),
1861         CLK(NULL,       "wdt0_fck",             &wdt0_fck,      CK_AM33XX),
1862         CLK(NULL,       "wkup_m3_fck",          &wkup_m3_fck,   CK_AM33XX),
1863         CLK(NULL,       "dpll_per_ck",          &dpll_per_ck,   CK_AM33XX),
1864         CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck,        CK_AM33XX),
1865         CLK(NULL,       "i2c_clk",              &i2c_clk,               CK_AM33XX),
1866         CLK(NULL,       "clk_div_24_ck",        &clk_div_24_ck,         CK_AM33XX),
1867         CLK(NULL,       "dpll_core_ck",         &dpll_core_ck,          CK_AM33XX),
1868         CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck,       CK_AM33XX),
1869         CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck,       CK_AM33XX),
1870         CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck,         CK_AM33XX),
1871         CLK(NULL,       "core_100m_ck",         &core_100m_ck,          CK_AM33XX),
1872         CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
1873         CLK(NULL,       "cpsw_250m_clkdiv_ck",  &cpsw_250m_clkdiv_ck,   CK_AM33XX),
1874         CLK(NULL,       "cpsw_125mhz_ocp_ck",   &cpsw_125mhz_ocp_ck,    CK_AM33XX),
1875         CLK(NULL,       "cpsw_50m_clkdiv_ck",   &cpsw_50m_clkdiv_ck,    CK_AM33XX),
1876         CLK(NULL,       "cpsw_5m_clkdiv_ck",    &cpsw_5m_clkdiv_ck,     CK_AM33XX),
1877         CLK(NULL,       "cpts_rft_clkmux_ck",   &cpts_rft_clkmux_ck,    CK_AM33XX),
1878         CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,           CK_AM33XX),
1879         CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
1880         CLK(NULL,       "ddr_pll_div_clk",      &ddr_pll_div_clk,       CK_AM33XX),
1881         CLK(NULL,       "div_l4_rtc_gclk_ck",   &div_l4_rtc_gclk_ck,    CK_AM33XX),
1882         CLK(NULL,       "div_l4_wkup_gclk_ck",  &div_l4_wkup_gclk_ck,   CK_AM33XX),
1883         CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck,          CK_AM33XX),
1884         CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck,       CK_AM33XX),
1885         CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,           CK_AM33XX),
1886         CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
1887         CLK(NULL,       "dpll_per_clkdcoldo_ck", &dpll_per_clkdcoldo_ck,        CK_AM33XX),
1888         CLK(NULL,       "gpio_dbclk_mux_ck",    &gpio_dbclk_mux_ck,     CK_AM33XX),
1889         CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk,           CK_AM33XX),
1890         CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk,           CK_AM33XX),
1891         CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk,           CK_AM33XX),
1892         CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk,           CK_AM33XX),
1893         CLK(NULL,       "icss_ocp_clk_mux_ck",  &icss_ocp_clk_mux_ck,   CK_AM33XX),
1894         CLK(NULL,       "lcd_clk_mux_ck",       &lcd_clk_mux_ck,        CK_AM33XX),
1895         CLK(NULL,       "mmc_clk",              &mmc_clk,               CK_AM33XX),
1896         CLK(NULL,       "sgx_clksel_ck",        &sgx_clksel_ck,         CK_AM33XX),
1897         CLK(NULL,       "sgx_ck",               &sgx_ck,                CK_AM33XX),
1898         CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck,      CK_AM33XX),
1899         CLK(NULL,       "clkout2_ck",           &clkout2_ck,            CK_AM33XX),
1900         CLK(NULL,       "timer0_clkmux_ck",     &timer0_clkmux_ck,      CK_AM33XX),
1901         CLK(NULL,       "gpt0_ick",             &timer0_ick,            CK_AM33XX),
1902         CLK(NULL,       "gpt1_ick",             &timer1_ick,            CK_AM33XX),
1903         CLK(NULL,       "gpt2_ick",             &timer2_ick,            CK_AM33XX),
1904         CLK(NULL,       "gpt3_ick",             &timer3_ick,            CK_AM33XX),
1905         CLK(NULL,       "gpt4_ick",             &timer4_ick,            CK_AM33XX),
1906         CLK(NULL,       "gpt5_ick",             &timer5_ick,            CK_AM33XX),
1907         CLK(NULL,       "gpt6_ick",             &timer6_ick,            CK_AM33XX),
1908         CLK(NULL,       "gpt7_ick",             &timer7_ick,            CK_AM33XX),
1909         CLK(NULL,       "vtp_clk_div_ck",       &vtp_clk_div_ck,        CK_AM33XX),
1910         CLK(NULL,       "wdt0_clkmux_ck",       &wdt0_clkmux_ck,        CK_AM33XX),
1911 };
1913 int __init am33xx_clk_init(void)
1915         struct omap_clk *c;
1916         u32 cpu_clkflg;
1918         if (cpu_is_am33xx()) {
1919                 cpu_mask = RATE_IN_AM33XX;
1920                 cpu_clkflg = CK_AM33XX;
1921         }
1923         clk_init(&omap2_clk_functions);
1925         for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
1926                 clk_preinit(c->lk.clk);
1928         for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
1929                 if (c->cpu & cpu_clkflg) {
1930                         clkdev_add(&c->lk);
1931                         clk_register(c->lk.clk);
1932                         omap2_init_clk_clkdm(c->lk.clk);
1933                 }
1935         recalculate_root_clocks();
1937         /*
1938          * Only enable those clocks we will need, let the drivers
1939          * enable other clocks as necessary
1940          */
1941         clk_enable_init_clocks();
1943         return 0;