fb88543fa4c73e8570d204bdbe10a93656c5467c
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / clock33xx_data.c
1 /*
2  * AM33XX Clock data
3  *
4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  */
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/clk.h>
19 #include <plat/clkdev_omap.h>
21 #include "control.h"
22 #include "clock.h"
23 #include "clock33xx.h"
24 #include "cm.h"
25 #include "cm33xx.h"
26 #include "cm-regbits-33xx.h"
27 #include "prm.h"
29 /* Modulemode control */
30 #define AM33XX_MODULEMODE_HWCTRL        0
31 #define AM33XX_MODULEMODE_SWCTRL        1
33 /* Root clocks */
34 static struct clk clk_32768_ck = {
35         .name           = "clk_32768_ck",
36         .rate           = 32768,
37         .ops            = &clkops_null,
38 };
40 static struct clk clk_32khz_ck = {
41         .name           = "clk_32khz_ck",
42         .rate           = 32768,
43         .ops            = &clkops_null,
44 };
46 /* On-Chip 32KHz RC OSC */
47 static struct clk clk_rc32k_ck = {
48         .name           = "clk_rc32k_ck",
49         .rate           = 32000,
50         .ops            = &clkops_null,
51 };
53 static struct clk tclkin_ck = {
54         .name           = "tclkin_ck",
55         .rate           = 12000000,
56         .ops            = &clkops_null,
57 };
59 static const struct clksel_rate div_1_0_rates[] = {
60         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
61         { .div = 0 },
62 };
64 static const struct clksel_rate div_1_1_rates[] = {
65         { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
66         { .div = 0 },
67 };
69 static const struct clksel_rate div_1_2_rates[] = {
70         { .div = 1, .val = 2, .flags = RATE_IN_AM33XX },
71         { .div = 0 },
72 };
74 static const struct clksel_rate div_1_3_rates[] = {
75         { .div = 1, .val = 3, .flags = RATE_IN_AM33XX },
76         { .div = 0 },
77 };
79 static const struct clksel_rate div_1_4_rates[] = {
80         { .div = 1, .val = 4, .flags = RATE_IN_AM33XX },
81         { .div = 0 },
82 };
84 static struct clk sys_clkin_ck = {
85         .name           = "sys_clkin_ck",
86         .rate           = 24000000,
87         .ops            = &clkops_null,
88 };
90 /* DPLL_PER */
91 static struct dpll_data dpll_per_dd = {
92         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
93         .clk_bypass     = &sys_clkin_ck,
94         .clk_ref        = &sys_clkin_ck,
95         .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
96         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
97         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_PER,
98         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
99         .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
100         .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
101         .enable_mask    = AM33XX_DPLL_EN_MASK,
102         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
103         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
104         .max_multiplier = AM33XX_MAX_DPLL_MULT,
105         .max_divider    = AM33XX_MAX_DPLL_DIV,
106         .min_divider    = 1,
107 };
109 static struct clk dpll_per_ck = {
110         .name           = "dpll_per_ck",
111         .parent         = &sys_clkin_ck,
112         .dpll_data      = &dpll_per_dd,
113         .init           = &omap2_init_dpll_parent,
114         .ops            = &clkops_null,
115         .recalc         = &omap3_dpll_recalc,
116 };
118 static const struct clksel_rate div31_1to31_rates[] = {
119         { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
120         { .div = 2, .val = 2, .flags = RATE_IN_AM33XX },
121         { .div = 3, .val = 3, .flags = RATE_IN_AM33XX },
122         { .div = 4, .val = 4, .flags = RATE_IN_AM33XX },
123         { .div = 5, .val = 5, .flags = RATE_IN_AM33XX },
124         { .div = 6, .val = 6, .flags = RATE_IN_AM33XX },
125         { .div = 7, .val = 7, .flags = RATE_IN_AM33XX },
126         { .div = 8, .val = 8, .flags = RATE_IN_AM33XX },
127         { .div = 9, .val = 9, .flags = RATE_IN_AM33XX },
128         { .div = 10, .val = 10, .flags = RATE_IN_AM33XX },
129         { .div = 11, .val = 11, .flags = RATE_IN_AM33XX },
130         { .div = 12, .val = 12, .flags = RATE_IN_AM33XX },
131         { .div = 13, .val = 13, .flags = RATE_IN_AM33XX },
132         { .div = 14, .val = 14, .flags = RATE_IN_AM33XX },
133         { .div = 15, .val = 15, .flags = RATE_IN_AM33XX },
134         { .div = 16, .val = 16, .flags = RATE_IN_AM33XX },
135         { .div = 17, .val = 17, .flags = RATE_IN_AM33XX },
136         { .div = 18, .val = 18, .flags = RATE_IN_AM33XX },
137         { .div = 19, .val = 19, .flags = RATE_IN_AM33XX },
138         { .div = 20, .val = 20, .flags = RATE_IN_AM33XX },
139         { .div = 21, .val = 21, .flags = RATE_IN_AM33XX },
140         { .div = 22, .val = 22, .flags = RATE_IN_AM33XX },
141         { .div = 23, .val = 23, .flags = RATE_IN_AM33XX },
142         { .div = 24, .val = 24, .flags = RATE_IN_AM33XX },
143         { .div = 25, .val = 25, .flags = RATE_IN_AM33XX },
144         { .div = 26, .val = 26, .flags = RATE_IN_AM33XX },
145         { .div = 27, .val = 27, .flags = RATE_IN_AM33XX },
146         { .div = 28, .val = 28, .flags = RATE_IN_AM33XX },
147         { .div = 29, .val = 29, .flags = RATE_IN_AM33XX },
148         { .div = 30, .val = 30, .flags = RATE_IN_AM33XX },
149         { .div = 31, .val = 31, .flags = RATE_IN_AM33XX },
150         { .div = 0 },
151 };
153 static const struct clksel dpll_per_m2_div[] = {
154         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
155         { .parent = NULL },
156 };
158 static struct clk dpll_per_m2_ck = {
159         .name           = "dpll_per_m2_ck",
160         .parent         = &dpll_per_ck,
161         .clksel         = dpll_per_m2_div,
162         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_PER,
163         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
164         .ops            = &clkops_null,
165         .recalc         = &omap2_clksel_recalc,
166         .round_rate     = &omap2_clksel_round_rate,
167         .set_rate       = &omap2_clksel_set_rate,
168 };
170 static struct clk i2c_clk = {
171         .name           = "i2c_clk",
172         .parent         = &dpll_per_m2_ck,
173         .ops            = &clkops_null,
174         .recalc         = &followparent_recalc,
175 };
177 static struct clk clk_div_24_ck = {
178         .name           = "clk_div_24_ck",
179         .parent         = &i2c_clk,
180         .ops            = &clkops_null,
181         .recalc         = &followparent_recalc,
182 };
184 /* DPLL_CORE */
185 static struct dpll_data dpll_core_dd = {
186         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
187         .clk_bypass     = &sys_clkin_ck,
188         .clk_ref        = &sys_clkin_ck,
189         .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
190         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
191         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_CORE,
192         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
193         .mult_mask      = AM33XX_DPLL_MULT_MASK,
194         .div1_mask      = AM33XX_DPLL_DIV_MASK,
195         .enable_mask    = AM33XX_DPLL_EN_MASK,
196         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
197         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
198         .max_multiplier = AM33XX_MAX_DPLL_MULT,
199         .max_divider    = AM33XX_MAX_DPLL_DIV,
200         .min_divider    = 1,
201 };
203 static struct clk dpll_core_ck = {
204         .name           = "dpll_core_ck",
205         .parent         = &sys_clkin_ck,
206         .dpll_data      = &dpll_core_dd,
207         .init           = &omap2_init_dpll_parent,
208         .ops            = &clkops_null,
209         .recalc         = &omap3_dpll_recalc,
210 };
212 static struct clk dpll_core_x2_ck = {
213         .name           = "dpll_core_x2_ck",
214         .parent         = &dpll_core_ck,
215         .ops            = &clkops_null,
216         .recalc         = &omap3_clkoutx2_recalc,
217 };
219 static const struct clksel dpll_core_m4_div[] = {
220         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
221         { .parent = NULL },
222 };
224 static struct clk dpll_core_m4_ck = {
225         .name           = "dpll_core_m4_ck",
226         .parent         = &dpll_core_x2_ck,
227         .clksel         = dpll_core_m4_div,
228         .clksel_reg     = AM33XX_CM_DIV_M4_DPLL_CORE,
229         .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
230         .ops            = &clkops_null,
231         .recalc         = &omap2_clksel_recalc,
232         .round_rate     = &omap2_clksel_round_rate,
233         .set_rate       = &omap2_clksel_set_rate,
234 };
236 static struct clk sysclk_div_ck = {
237         .name           = "sysclk_div_ck",
238         .parent         = &dpll_core_m4_ck,
239         .ops            = &clkops_null,
240         .recalc         = &followparent_recalc,
241 };
243 static struct clk div_l4_wkup_gclk_ck = {
244         .name           = "div_l4_wkup_gclk_ck",
245         .parent         = &dpll_core_m4_ck,
246         .ops            = &clkops_null,
247         .fixed_div      = 2,
248         .recalc         = &omap_fixed_divisor_recalc,
249 };
251 static struct clk core_100m_ck = {
252         .name           = "core_100m_ck",
253         .parent         = &sysclk_div_ck,
254         .ops            = &clkops_null,
255         .fixed_div      = 2,
256         .recalc         = &omap_fixed_divisor_recalc,
257 };
259 static struct clk l4ls_fck = {
260         .name           = "l4ls_fck",
261         .ops            = &clkops_omap2_dflt,
262         .enable_reg     = AM33XX_CM_PER_L4LS_CLKCTRL,
263         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
264         .clkdm_name     = "l4ls_clkdm",
265         .parent         = &core_100m_ck,
266         .recalc         = &followparent_recalc,
267         .flags          = ENABLE_ON_INIT,
268 };
270 static struct clk timer2_ick = {
271         .name           = "timer2_ick",
272         .parent         = &l4ls_fck,
273         .ops            = &clkops_null,
274         .recalc         = &followparent_recalc,
275 };
277 static struct clk timer3_ick = {
278         .name           = "timer3_ick",
279         .parent         = &l4ls_fck,
280         .ops            = &clkops_null,
281         .recalc         = &followparent_recalc,
282 };
284 static struct clk timer4_ick = {
285         .name           = "timer4_ick",
286         .parent         = &l4ls_fck,
287         .ops            = &clkops_null,
288         .recalc         = &followparent_recalc,
289 };
291 static struct clk timer5_ick = {
292         .name           = "timer5_ick",
293         .parent         = &l4ls_fck,
294         .ops            = &clkops_null,
295         .recalc         = &followparent_recalc,
296 };
298 static struct clk timer6_ick = {
299         .name           = "timer6_ick",
300         .parent         = &l4ls_fck,
301         .ops            = &clkops_null,
302         .recalc         = &followparent_recalc,
303 };
305 static struct clk timer7_ick = {
306         .name           = "timer7_ick",
307         .parent         = &l4ls_fck,
308         .ops            = &clkops_null,
309         .recalc         = &followparent_recalc,
310 };
312 static struct clk lcdc_l3ick = {
313         .name           = "lcdc_ick_l3_clk",
314         .enable_reg     = AM33XX_CM_PER_L3_CLKCTRL,
315         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
316         .parent         = &dpll_core_m4_ck,
317         .ops            = &clkops_null,
318         .clkdm_name     = "l3_clkdm",
319         .recalc         = &followparent_recalc,
320 };
322 static struct clk lcdc_l4ick = {
323         .name           = "lcdc_ick_l4_clk",
324         .enable_reg     = AM33XX_CM_PER_L4LS_CLKCTRL,
325         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
326         .parent         = &dpll_core_m4_ck,
327         .ops            = &clkops_null,
328         .clkdm_name     = "l4ls_clkdm",
329         .recalc         = &followparent_recalc,
330 };
332 /* Leaf clocks controlled by modules */
333 static struct clk adc_tsc_fck = {
334         .name           = "adc_tsc_fck",
335         .ops            = &clkops_null,
336         .parent         = &sys_clkin_ck,
337         .clkdm_name     = "l4_wkup_clkdm",
338         .recalc         = &followparent_recalc,
339 };
341 static struct clk adc_tsc_ick = {
342         .name           = "adc_tsc_ick",
343         .ops            = &clkops_omap2_dflt,
344         .enable_reg     = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL,
345         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
346         .parent         = &div_l4_wkup_gclk_ck,
347         .recalc         = &followparent_recalc,
348 };
350 static struct clk aes0_fck = {
351         .name           = "aes0_fck",
352         .ops            = &clkops_omap2_dflt,
353         .enable_reg     = AM33XX_CM_PER_AES0_CLKCTRL,
354         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
355         .clkdm_name     = "l3_clkdm",
356         .parent         = &sysclk_div_ck,
357         .recalc         = &followparent_recalc,
358 };
360 static struct clk cefuse_fck = {
361         .name           = "cefuse_fck",
362         .ops            = &clkops_omap2_dflt,
363         .enable_reg     = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
364         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
365         .clkdm_name     = "l4_cefuse_clkdm",
366         .parent         = &sys_clkin_ck,
367         .recalc         = &followparent_recalc,
368 };
370 static struct clk clkdiv32k_fck = {
371         .name           = "clkdiv32k_fck",
372         .ops            = &clkops_omap2_dflt,
373         .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
374         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
375         .clkdm_name     = "clk_24mhz_clkdm",
376         .parent         = &clk_div_24_ck,
377         .recalc         = &followparent_recalc,
378 };
380 static struct clk control_fck = {
381         .name           = "control_fck",
382         .ops            = &clkops_omap2_dflt,
383         .enable_reg     = AM33XX_CM_WKUP_CONTROL_CLKCTRL,
384         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
385         .clkdm_name     = "l4_wkup_clkdm",
386         .parent         = &div_l4_wkup_gclk_ck,
387         .recalc         = &followparent_recalc,
388         .flags          = ENABLE_ON_INIT,
389 };
391 static struct clk dcan0_fck = {
392         .name           = "dcan0_fck",
393         .ops            = &clkops_omap2_dflt,
394         .enable_reg     = AM33XX_CM_PER_DCAN0_CLKCTRL,
395         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
396         .clkdm_name     = "l4ls_clkdm",
397         .parent         = &sys_clkin_ck,
398         .recalc         = &followparent_recalc,
399 };
401 static struct clk dcan1_fck = {
402         .name           = "dcan1_fck",
403         .ops            = &clkops_omap2_dflt,
404         .enable_reg     = AM33XX_CM_PER_DCAN1_CLKCTRL,
405         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
406         .clkdm_name     = "l4ls_clkdm",
407         .parent         = &sys_clkin_ck,
408         .recalc         = &followparent_recalc,
409 };
411 static struct clk dcan0_ick = {
412         .name           = "dcan0_ick",
413         .parent         = &dpll_per_m2_ck ,
414         .ops            = &clkops_null,
415         .clkdm_name     = "l4ls_clkdm",
416         .recalc         = &followparent_recalc,
417 };
419 static struct clk dcan1_ick = {
420         .name           = "dcan1_ick",
421         .parent         = &dpll_per_m2_ck ,
422         .ops            = &clkops_null,
423         .clkdm_name     = "l4ls_clkdm",
424         .recalc         = &followparent_recalc,
425 };
427 static struct clk debugss_fck = {
428         .name           = "debugss_fck",
429         .ops            = &clkops_omap2_dflt,
430         .enable_reg     = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
431         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
432         .clkdm_name     = "l3_aon_clkdm",
433         .parent         = &dpll_core_m4_ck,
434         .recalc         = &followparent_recalc,
435 };
437 static struct clk elm_fck = {
438         .name           = "elm_fck",
439         .ops            = &clkops_omap2_dflt,
440         .enable_reg     = AM33XX_CM_PER_ELM_CLKCTRL,
441         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
442         .clkdm_name     = "l4ls_clkdm",
443         .parent         = &core_100m_ck,
444         .recalc         = &followparent_recalc,
445 };
447 static struct clk emif_fw_fck = {
448         .name           = "emif_fw_fck",
449         .ops            = &clkops_omap2_dflt,
450         .enable_reg     = AM33XX_CM_PER_EMIF_FW_CLKCTRL,
451         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
452         .clkdm_name     = "l4fw_clkdm",
453         .parent         = &core_100m_ck,
454         .recalc         = &followparent_recalc,
455         .flags          = ENABLE_ON_INIT,
456 };
458 static struct clk epwmss0_fck = {
459         .name           = "epwmss0_fck",
460         .ops            = &clkops_omap2_dflt,
461         .enable_reg     = AM33XX_CM_PER_EPWMSS0_CLKCTRL,
462         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
463         .clkdm_name     = "l4ls_clkdm",
464         .parent         = &core_100m_ck,
465         .recalc         = &followparent_recalc,
466 };
468 static struct clk epwmss1_fck = {
469         .name           = "epwmss1_fck",
470         .ops            = &clkops_omap2_dflt,
471         .enable_reg     = AM33XX_CM_PER_EPWMSS1_CLKCTRL,
472         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
473         .clkdm_name     = "l4ls_clkdm",
474         .parent         = &core_100m_ck,
475         .recalc         = &followparent_recalc,
476 };
478 static struct clk epwmss2_fck = {
479         .name           = "epwmss2_fck",
480         .ops            = &clkops_omap2_dflt,
481         .enable_reg     = AM33XX_CM_PER_EPWMSS2_CLKCTRL,
482         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
483         .clkdm_name     = "l4ls_clkdm",
484         .parent         = &core_100m_ck,
485         .recalc         = &followparent_recalc,
486 };
488 static struct clk gpio0_fck = {
489         .name           = "gpio0_fck",
490         .ops            = &clkops_omap2_dflt,
491         .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
492         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
493         .clkdm_name     = "l4_wkup_clkdm",
494         .parent         = &div_l4_wkup_gclk_ck,
495         .recalc         = &followparent_recalc,
496 };
498 static struct clk gpio1_fck = {
499         .name           = "gpio1_fck",
500         .ops            = &clkops_omap2_dflt,
501         .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
502         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
503         .clkdm_name     = "l4ls_clkdm",
504         .parent         = &core_100m_ck,
505         .recalc         = &followparent_recalc,
506 };
508 static struct clk gpio2_fck = {
509         .name           = "gpio2_fck",
510         .ops            = &clkops_omap2_dflt,
511         .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
512         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
513         .clkdm_name     = "l4ls_clkdm",
514         .parent         = &core_100m_ck,
515         .recalc         = &followparent_recalc,
516 };
518 static struct clk gpio3_fck = {
519         .name           = "gpio3_fck",
520         .ops            = &clkops_omap2_dflt,
521         .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
522         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
523         .clkdm_name     = "l4ls_clkdm",
524         .parent         = &core_100m_ck,
525         .recalc         = &followparent_recalc,
526 };
528 static struct clk gpmc_fck = {
529         .name           = "gpmc_fck",
530         .ops            = &clkops_omap2_dflt,
531         .enable_reg     = AM33XX_CM_PER_GPMC_CLKCTRL,
532         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
533         .clkdm_name     = "l3s_clkdm",
534         .parent         = &core_100m_ck,
535         .recalc         = &followparent_recalc,
536 };
538 static struct clk i2c1_fck = {
539         .name           = "i2c1_fck",
540         .ops            = &clkops_omap2_dflt,
541         .enable_reg     = AM33XX_CM_WKUP_I2C0_CLKCTRL,
542         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
543         .clkdm_name     = "l4_wkup_clkdm",
544         .parent         = &dpll_per_m2_ck,
545         .fixed_div      = 4,
546         .recalc         = &omap_fixed_divisor_recalc,
547 };
549 static struct clk i2c2_fck = {
550         .name           = "i2c2_fck",
551         .ops            = &clkops_omap2_dflt,
552         .enable_reg     = AM33XX_CM_PER_I2C1_CLKCTRL,
553         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
554         .clkdm_name     = "l4ls_clkdm",
555         .parent         = &i2c_clk,
556         .recalc         = &followparent_recalc,
557 };
559 static struct clk i2c3_fck = {
560         .name           = "i2c3_fck",
561         .ops            = &clkops_omap2_dflt,
562         .enable_reg     = AM33XX_CM_PER_I2C2_CLKCTRL,
563         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
564         .clkdm_name     = "l4ls_clkdm",
565         .parent         = &i2c_clk,
566         .recalc         = &followparent_recalc,
567 };
569 static struct clk icss_fck = {
570         .name           = "icss_fck",
571         .ops            = &clkops_omap2_dflt,
572         .enable_reg     = AM33XX_CM_PER_ICSS_CLKCTRL,
573         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
574         .clkdm_name     = "icss_ocp_clkdm",
575         .parent         = &dpll_per_m2_ck,
576         .recalc         = &followparent_recalc,
577 };
579 static struct clk ieee5000_fck = {
580         .name           = "ieee5000_fck",
581         .ops            = &clkops_omap2_dflt,
582         .enable_reg     = AM33XX_CM_PER_IEEE5000_CLKCTRL,
583         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
584         .clkdm_name     = "l3s_clkdm",
585         .parent         = &core_100m_ck,
586         .recalc         = &followparent_recalc,
587         .flags          = ENABLE_ON_INIT,
588 };
590 static struct clk l3_instr_fck = {
591         .name           = "l3_instr_fck",
592         .ops            = &clkops_omap2_dflt,
593         .enable_reg     = AM33XX_CM_PER_L3_INSTR_CLKCTRL,
594         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
595         .clkdm_name     = "l3_clkdm",
596         .parent         = &sysclk_div_ck,
597         .recalc         = &followparent_recalc,
598         .flags          = ENABLE_ON_INIT,
599 };
601 static struct clk l3_main_fck = {
602         .name           = "l3_main_fck",
603         .ops            = &clkops_omap2_dflt,
604         .enable_reg     = AM33XX_CM_PER_L3_CLKCTRL,
605         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
606         .clkdm_name     = "l3_clkdm",
607         .parent         = &sysclk_div_ck,
608         .recalc         = &followparent_recalc,
609         .flags          = ENABLE_ON_INIT,
610 };
612 static struct clk l4_hs_fck = {
613         .name           = "l4_hs_fck",
614         .ops            = &clkops_omap2_dflt,
615         .enable_reg     = AM33XX_CM_PER_L4HS_CLKCTRL,
616         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
617         .clkdm_name     = "l4hs_clkdm",
618         .parent         = &sysclk_div_ck,
619         .recalc         = &followparent_recalc,
620         .flags          = ENABLE_ON_INIT,
621 };
623 static struct clk l4fw_fck = {
624         .name           = "l4fw_fck",
625         .ops            = &clkops_omap2_dflt,
626         .enable_reg     = AM33XX_CM_PER_L4FW_CLKCTRL,
627         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
628         .clkdm_name     = "l4fw_clkdm",
629         .parent         = &core_100m_ck,
630         .recalc         = &followparent_recalc,
631         .flags          = ENABLE_ON_INIT,
632 };
634 static struct clk l4wkup_fck = {
635         .name           = "l4wkup_fck",
636         .ops            = &clkops_omap2_dflt,
637         .enable_reg     = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
638         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
639         .clkdm_name     = "l4_wkup_aon_clkdm",
640         .parent         = &div_l4_wkup_gclk_ck,
641         .recalc         = &followparent_recalc,
642         .flags          = ENABLE_ON_INIT,
643 };
645 static struct clk mailbox0_fck = {
646         .name           = "mailbox0_fck",
647         .ops            = &clkops_omap2_dflt,
648         .enable_reg     = AM33XX_CM_PER_MAILBOX0_CLKCTRL,
649         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
650         .clkdm_name     = "l4ls_clkdm",
651         .parent         = &core_100m_ck,
652         .recalc         = &followparent_recalc,
653 };
655 static struct clk mcasp0_ick = {
656         .name           = "mcasp0_ick",
657         .parent         = &l3_main_fck,
658         .ops            = &clkops_null,
659         .recalc         = &followparent_recalc,
660 };
662 static struct clk mcasp1_ick = {
663         .name           = "mcasp1_ick",
664         .parent         = &l3_main_fck,
665         .ops            = &clkops_null,
666         .recalc         = &followparent_recalc,
667 };
669 static struct clk mcasp0_fck = {
670         .name           = "mcasp0_fck",
671         .ops            = &clkops_omap2_dflt,
672         .enable_reg     = AM33XX_CM_PER_MCASP0_CLKCTRL,
673         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
674         .clkdm_name     = "l3s_clkdm",
675         .parent         = &sys_clkin_ck,
676         .recalc         = &followparent_recalc,
677 };
679 static struct clk mcasp1_fck = {
680         .name           = "mcasp1_fck",
681         .ops            = &clkops_omap2_dflt,
682         .enable_reg     = AM33XX_CM_PER_MCASP1_CLKCTRL,
683         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
684         .clkdm_name     = "l3s_clkdm",
685         .parent         = &sys_clkin_ck,
686         .recalc         = &followparent_recalc,
687 };
689 static struct clk mlb_fck = {
690         .name           = "mlb_fck",
691         .ops            = &clkops_omap2_dflt,
692         .enable_reg     = AM33XX_CM_PER_MLB_CLKCTRL,
693         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
694         .clkdm_name     = "l3_clkdm",
695         .parent         = &sysclk_div_ck,
696         .recalc         = &followparent_recalc,
697 };
699 static struct clk mmu_fck = {
700         .name           = "mmu_fck",
701         .ops            = &clkops_omap2_dflt,
702         .enable_reg     = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
703         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
704         .clkdm_name     = "gfx_l3_clkdm",
705         .parent         = &dpll_core_m4_ck,
706         .recalc         = &followparent_recalc,
707 };
710 static struct clk mstr_exps_fck = {
711         .name           = "mstr_exps_fck",
712         .ops            = &clkops_omap2_dflt,
713         .enable_reg     = AM33XX_CM_PER_MSTR_EXPS_CLKCTRL,
714         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
715         .clkdm_name     = "l3_clkdm",
716         .parent         = &sysclk_div_ck,
717         .recalc         = &followparent_recalc,
718 };
720 static struct clk ocmcram_fck = {
721         .name           = "ocmcram_fck",
722         .ops            = &clkops_omap2_dflt,
723         .enable_reg     = AM33XX_CM_PER_OCMCRAM_CLKCTRL,
724         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
725         .clkdm_name     = "l3_clkdm",
726         .parent         = &sysclk_div_ck,
727         .recalc         = &followparent_recalc,
728 };
730 static struct clk ocpwp_fck = {
731         .name           = "ocpwp_fck",
732         .ops            = &clkops_omap2_dflt,
733         .enable_reg     = AM33XX_CM_PER_OCPWP_CLKCTRL,
734         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
735         .clkdm_name     = "l4ls_clkdm",
736         .parent         = &core_100m_ck,
737         .recalc         = &followparent_recalc,
738 };
740 static struct clk pka_fck = {
741         .name           = "pka_fck",
742         .ops            = &clkops_omap2_dflt,
743         .enable_reg     = AM33XX_CM_PER_PKA_CLKCTRL,
744         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
745         .clkdm_name     = "l4ls_clkdm",
746         .parent         = &core_100m_ck,
747         .recalc         = &followparent_recalc,
748 };
750 static struct clk rng_fck = {
751         .name           = "rng_fck",
752         .ops            = &clkops_omap2_dflt,
753         .enable_reg     = AM33XX_CM_PER_RNG_CLKCTRL,
754         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
755         .clkdm_name     = "l4ls_clkdm",
756         .parent         = &core_100m_ck,
757         .recalc         = &followparent_recalc,
758 };
760 static struct clk rtc_fck = {
761         .name           = "rtc_fck",
762         .ops            = &clkops_omap2_dflt,
763         .enable_reg     = AM33XX_CM_RTC_RTC_CLKCTRL,
764         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
765         .clkdm_name     = "l4_rtc_clkdm",
766         .parent         = &clk_32khz_ck,
767         .recalc         = &followparent_recalc,
768 };
770 static struct clk sha0_fck = {
771         .name           = "sha0_fck",
772         .ops            = &clkops_omap2_dflt,
773         .enable_reg     = AM33XX_CM_PER_SHA0_CLKCTRL,
774         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
775         .clkdm_name     = "l3_clkdm",
776         .parent         = &sysclk_div_ck,
777         .recalc         = &followparent_recalc,
778 };
780 static struct clk slv_exps_fck = {
781         .name           = "slv_exps_fck",
782         .ops            = &clkops_omap2_dflt,
783         .enable_reg     = AM33XX_CM_PER_SLV_EXPS_CLKCTRL,
784         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
785         .clkdm_name     = "l3_clkdm",
786         .parent         = &sysclk_div_ck,
787         .recalc         = &followparent_recalc,
788 };
790 static struct clk smartreflex0_fck = {
791         .name           = "smartreflex0_fck",
792         .ops            = &clkops_omap2_dflt,
793         .enable_reg     = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL,
794         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
795         .clkdm_name     = "l4_wkup_clkdm",
796         .parent         = &sys_clkin_ck,
797         .recalc         = &followparent_recalc,
798 };
800 static struct clk smartreflex1_fck = {
801         .name           = "smartreflex1_fck",
802         .ops            = &clkops_omap2_dflt,
803         .enable_reg     = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL,
804         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
805         .clkdm_name     = "l4_wkup_clkdm",
806         .parent         = &sys_clkin_ck,
807         .recalc         = &followparent_recalc,
808 };
810 static struct clk spare0_fck = {
811         .name           = "spare0_fck",
812         .ops            = &clkops_omap2_dflt,
813         .enable_reg     = AM33XX_CM_PER_SPARE0_CLKCTRL,
814         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
815         .clkdm_name     = "l4ls_clkdm",
816         .parent         = &core_100m_ck,
817         .recalc         = &followparent_recalc,
818 };
820 static struct clk spare1_fck = {
821         .name           = "spare1_fck",
822         .ops            = &clkops_omap2_dflt,
823         .enable_reg     = AM33XX_CM_PER_SPARE1_CLKCTRL,
824         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
825         .clkdm_name     = "l4ls_clkdm",
826         .parent         = &core_100m_ck,
827         .recalc         = &followparent_recalc,
828 };
830 static struct clk spi0_fck = {
831         .name           = "spi0_fck",
832         .parent         = &dpll_per_m2_ck ,
833         .ops            = &clkops_omap2_dflt,
834         .enable_reg     = AM33XX_CM_PER_SPI0_CLKCTRL,
835         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
836         .clkdm_name     = "l4ls_clkdm",
837         .fixed_div      = 4,
838         .recalc         = &omap_fixed_divisor_recalc,
839 };
841 static struct clk spi1_fck = {
842         .name           = "spi1_fck",
843         .parent         = &dpll_per_m2_ck ,
844         .ops            = &clkops_omap2_dflt,
845         .enable_reg     = AM33XX_CM_PER_SPI1_CLKCTRL,
846         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
847         .clkdm_name     = "l4ls_clkdm",
848         .fixed_div      = 4,
849         .recalc         = &omap_fixed_divisor_recalc,
850 };
852 static struct clk spi0_ick = {
853         .name           = "spi0_ick",
854         .parent         = &l4ls_fck,
855         .ops            = &clkops_null,
856         .recalc         = &followparent_recalc,
857 };
859 static struct clk spi1_ick = {
860         .name           = "spi1_ick",
861         .parent         = &l4ls_fck,
862         .ops            = &clkops_null,
863         .recalc         = &followparent_recalc,
864 };
866 static struct clk spinlock_fck = {
867         .name           = "spinlock_fck",
868         .ops            = &clkops_omap2_dflt,
869         .enable_reg     = AM33XX_CM_PER_SPINLOCK_CLKCTRL,
870         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
871         .clkdm_name     = "l4ls_clkdm",
872         .parent         = &core_100m_ck,
873         .recalc         = &followparent_recalc,
874 };
876 static const struct clksel timer2_to_7_clk_sel[] = {
877         { .parent = &tclkin_ck, .rates = div_1_0_rates },
878         { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
879         { .parent = &clk_32khz_ck, .rates = div_1_2_rates },
880         { .parent = NULL },
881 };
883 static struct clk timer2_fck = {
884         .name           = "timer2_fck",
885         .parent         = &sys_clkin_ck,
886         .init           = &omap2_init_clksel_parent,
887         .clksel         = timer2_to_7_clk_sel,
888         .ops            = &clkops_omap2_dflt,
889         .enable_reg     = AM33XX_CM_PER_TIMER2_CLKCTRL,
890         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
891         .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
892         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
893         .clkdm_name     = "l4ls_clkdm",
894         .recalc         = &omap2_clksel_recalc,
895 };
897 static struct clk timer3_fck = {
898         .name           = "timer3_fck",
899         .parent         = &sys_clkin_ck,
900         .init           = &am33xx_init_timer_parent,
901         .clksel         = timer2_to_7_clk_sel,
902         .ops            = &clkops_omap2_dflt,
903         .enable_reg     = AM33XX_CM_PER_TIMER3_CLKCTRL,
904         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
905         .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
906         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
907         .clkdm_name     = "l4ls_clkdm",
908         .recalc         = &omap2_clksel_recalc,
909 };
911 static struct clk timer4_fck = {
912         .name           = "timer4_fck",
913         .parent         = &sys_clkin_ck,
914         .init           = &omap2_init_clksel_parent,
915         .clksel         = timer2_to_7_clk_sel,
916         .ops            = &clkops_omap2_dflt,
917         .enable_reg     = AM33XX_CM_PER_TIMER4_CLKCTRL,
918         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
919         .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
920         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
921         .clkdm_name     = "l4ls_clkdm",
922         .recalc         = &omap2_clksel_recalc,
923 };
925 static struct clk timer5_fck = {
926         .name           = "timer5_fck",
927         .parent         = &sys_clkin_ck,
928         .init           = &omap2_init_clksel_parent,
929         .clksel         = timer2_to_7_clk_sel,
930         .ops            = &clkops_omap2_dflt,
931         .enable_reg     = AM33XX_CM_PER_TIMER5_CLKCTRL,
932         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
933         .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
934         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
935         .clkdm_name     = "l4ls_clkdm",
936         .recalc         = &omap2_clksel_recalc,
937 };
939 static struct clk timer6_fck = {
940         .name           = "timer6_fck",
941         .parent         = &sys_clkin_ck,
942         .init           = &am33xx_init_timer_parent,
943         .clksel         = timer2_to_7_clk_sel,
944         .ops            = &clkops_omap2_dflt,
945         .enable_reg     = AM33XX_CM_PER_TIMER6_CLKCTRL,
946         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
947         .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
948         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
949         .clkdm_name     = "l4ls_clkdm",
950         .recalc         = &omap2_clksel_recalc,
951 };
953 static struct clk timer7_fck = {
954         .name           = "timer7_fck",
955         .parent         = &sys_clkin_ck,
956         .init           = &omap2_init_clksel_parent,
957         .clksel         = timer2_to_7_clk_sel,
958         .ops            = &clkops_omap2_dflt,
959         .enable_reg     = AM33XX_CM_PER_TIMER7_CLKCTRL,
960         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
961         .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
962         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
963         .clkdm_name     = "l4ls_clkdm",
964         .recalc         = &omap2_clksel_recalc,
965 };
967 static struct clk tpcc_ick = {
968         .name           = "tpcc_ick",
969         .ops            = &clkops_omap2_dflt,
970         .enable_reg     = AM33XX_CM_PER_TPCC_CLKCTRL,
971         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
972         .clkdm_name     = "l3_clkdm",
973         .parent         = &l3_main_fck,
974         .recalc         = &followparent_recalc,
975 };
977 static struct clk tptc0_ick = {
978         .name           = "tptc0_ick",
979         .ops            = &clkops_omap2_dflt,
980         .enable_reg     = AM33XX_CM_PER_TPTC0_CLKCTRL,
981         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
982         .clkdm_name     = "l3_clkdm",
983         .parent         = &l3_main_fck,
984         .recalc         = &followparent_recalc,
985 };
987 static struct clk tptc1_ick = {
988         .name           = "tptc1_ick",
989         .ops            = &clkops_omap2_dflt,
990         .enable_reg     = AM33XX_CM_PER_TPTC1_CLKCTRL,
991         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
992         .clkdm_name     = "l3_clkdm",
993         .parent         = &l3_main_fck,
994         .recalc         = &followparent_recalc,
995 };
997 static struct clk tptc2_ick = {
998         .name           = "tptc2_ick",
999         .ops            = &clkops_omap2_dflt,
1000         .enable_reg     = AM33XX_CM_PER_TPTC2_CLKCTRL,
1001         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1002         .clkdm_name     = "l3_clkdm",
1003         .parent         = &l3_main_fck,
1004         .recalc         = &followparent_recalc,
1005 };
1007 static struct clk uart1_fck = {
1008         .name           = "uart1_fck",
1009         .parent         = &dpll_per_m2_ck ,
1010         .ops            = &clkops_omap2_dflt,
1011         .enable_reg     = AM33XX_CM_WKUP_UART0_CLKCTRL,
1012         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1013         .clkdm_name     = "l4_wkup_clkdm",
1014         .fixed_div      = 4,
1015         .recalc         = &omap_fixed_divisor_recalc,
1016 };
1018 static struct clk uart2_fck = {
1019         .name           = "uart2_fck",
1020         .parent         = &dpll_per_m2_ck ,
1021         .ops            = &clkops_omap2_dflt,
1022         .enable_reg     = AM33XX_CM_PER_UART1_CLKCTRL,
1023         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1024         .clkdm_name     = "l4ls_clkdm",
1025         .fixed_div      = 4,
1026         .recalc         = &omap_fixed_divisor_recalc,
1027 };
1029 static struct clk uart3_fck = {
1030         .name           = "uart3_fck",
1031         .parent         = &dpll_per_m2_ck ,
1032         .ops            = &clkops_omap2_dflt,
1033         .enable_reg     = AM33XX_CM_PER_UART2_CLKCTRL,
1034         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1035         .clkdm_name     = "l4ls_clkdm",
1036         .fixed_div      = 4,
1037         .recalc         = &omap_fixed_divisor_recalc,
1038 };
1040 static struct clk uart4_fck = {
1041         .name           = "uart4_fck",
1042         .parent         = &dpll_per_m2_ck ,
1043         .ops            = &clkops_omap2_dflt,
1044         .enable_reg     = AM33XX_CM_PER_UART3_CLKCTRL,
1045         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1046         .clkdm_name     = "l4ls_clkdm",
1047         .fixed_div      = 4,
1048         .recalc         = &omap_fixed_divisor_recalc,
1049 };
1051 static struct clk uart5_fck = {
1052         .name           = "uart5_fck",
1053         .parent         = &dpll_per_m2_ck ,
1054         .ops            = &clkops_omap2_dflt,
1055         .enable_reg     = AM33XX_CM_PER_UART4_CLKCTRL,
1056         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1057         .clkdm_name     = "l4ls_clkdm",
1058         .fixed_div      = 4,
1059         .recalc         = &omap_fixed_divisor_recalc,
1060 };
1062 static struct clk uart6_fck = {
1063         .name           = "uart6_fck",
1064         .parent         = &dpll_per_m2_ck ,
1065         .ops            = &clkops_omap2_dflt,
1066         .enable_reg     = AM33XX_CM_PER_UART5_CLKCTRL,
1067         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1068         .clkdm_name     = "l4ls_clkdm",
1069         .fixed_div      = 4,
1070         .recalc         = &omap_fixed_divisor_recalc,
1071 };
1073 static struct clk uart1_ick = {
1074         .name           = "uart1_ick",
1075         .parent         = &div_l4_wkup_gclk_ck,
1076         .ops            = &clkops_null,
1077         .recalc         = &followparent_recalc,
1078 };
1080 static struct clk uart2_ick = {
1081         .name           = "uart2_ick",
1082         .parent         = &l4ls_fck,
1083         .ops            = &clkops_null,
1084         .recalc         = &followparent_recalc,
1085 };
1087 static struct clk uart3_ick = {
1088         .name           = "uart3_ick",
1089         .parent         = &l4ls_fck,
1090         .ops            = &clkops_null,
1091         .recalc         = &followparent_recalc,
1092 };
1094 static struct clk uart4_ick = {
1095         .name           = "uart4_ick",
1096         .parent         = &l4ls_fck,
1097         .ops            = &clkops_null,
1098         .recalc         = &followparent_recalc,
1099 };
1101 static struct clk uart5_ick = {
1102         .name           = "uart5_ick",
1103         .parent         = &l4ls_fck,
1104         .ops            = &clkops_null,
1105         .recalc         = &followparent_recalc,
1106 };
1108 static struct clk uart6_ick = {
1109         .name           = "uart6_ick",
1110         .parent         = &l4ls_fck,
1111         .ops            = &clkops_null,
1112         .recalc         = &followparent_recalc,
1113 };
1115 static struct clk wkup_m3_fck = {
1116         .name           = "wkup_m3_fck",
1117         .ops            = &clkops_omap2_dflt,
1118         .enable_reg     = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL,
1119         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1120         .clkdm_name     = "l4_wkup_aon_clkdm",
1121         .parent         = &div_l4_wkup_gclk_ck,
1122         .recalc         = &followparent_recalc,
1123 };
1125 static struct clk dpll_core_m5_ck = {
1126         .name           = "dpll_core_m5_ck",
1127         .parent         = &dpll_core_x2_ck,
1128         .clksel         = dpll_core_m4_div,
1129         .clksel_reg     = AM33XX_CM_DIV_M5_DPLL_CORE,
1130         .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
1131         .ops            = &clkops_null,
1132         .recalc         = &omap2_clksel_recalc,
1133         .round_rate     = &omap2_clksel_round_rate,
1134         .set_rate       = &omap2_clksel_set_rate,
1135 };
1137 static struct clk cpsw_250m_clkdiv_ck = {
1138         .name           = "cpsw_250m_clkdiv_ck",
1139         .parent         = &dpll_core_m5_ck,
1140         .ops            = &clkops_null,
1141         .recalc         = &followparent_recalc,
1142 };
1144 static struct clk cpsw_125mhz_ocp_ck = {
1145         .name           = "cpsw_125mhz_ocp_ck",
1146         .parent         = &dpll_core_m5_ck,
1147         .ops            = &clkops_null,
1148         .fixed_div      = 2,
1149         .recalc         = &omap_fixed_divisor_recalc,
1150 };
1152 static struct clk cpsw_50m_clkdiv_ck = {
1153         .name           = "cpsw_50m_clkdiv_ck",
1154         .parent         = &dpll_core_m5_ck,
1155         .ops            = &clkops_null,
1156         .fixed_div      = 5,
1157         .recalc         = &omap_fixed_divisor_recalc,
1158 };
1160 static struct clk cpgmac0_fck = {
1161         .name           = "cpgmac0_fck",
1162         .ops            = &clkops_omap2_dflt,
1163         .enable_reg     = AM33XX_CM_PER_CPGMAC0_CLKCTRL,
1164         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1165         .clkdm_name     = "cpsw_125mhz_clkdm",
1166         .parent         = &cpsw_125mhz_ocp_ck,
1167         .recalc         = &followparent_recalc,
1168 };
1170 static struct clk cpsw_5m_clkdiv_ck = {
1171         .name           = "cpsw_5m_clkdiv_ck",
1172         .parent         = &cpsw_50m_clkdiv_ck,
1173         .ops            = &clkops_null,
1174         .fixed_div      = 10,
1175         .recalc         = &omap_fixed_divisor_recalc,
1176 };
1179 static const struct clksel cpts_rft_clkmux_sel[] = {
1180         { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
1181         { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
1182         { .parent = NULL },
1183 };
1185 static struct clk cpts_rft_clkmux_ck = {
1186         .name           = "cpts_rft_clkmux_ck",
1187         .parent         = &dpll_core_m5_ck,
1188         .ops            = &clkops_null,
1189         .recalc         = &followparent_recalc,
1190 };
1194 /* DPLL_DDR */
1195 static struct dpll_data dpll_ddr_dd = {
1196         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
1197         .clk_bypass     = &sys_clkin_ck,
1198         .clk_ref        = &sys_clkin_ck,
1199         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
1200         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1201         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_DDR,
1202         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
1203         .mult_mask      = AM33XX_DPLL_MULT_MASK,
1204         .div1_mask      = AM33XX_DPLL_DIV_MASK,
1205         .enable_mask    = AM33XX_DPLL_EN_MASK,
1206         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
1207         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
1208         .max_multiplier = AM33XX_MAX_DPLL_MULT,
1209         .max_divider    = AM33XX_MAX_DPLL_DIV,
1210         .min_divider    = 1,
1211 };
1214 static struct clk dpll_ddr_ck = {
1215         .name           = "dpll_ddr_ck",
1216         .parent         = &sys_clkin_ck,
1217         .dpll_data      = &dpll_ddr_dd,
1218         .init           = &omap2_init_dpll_parent,
1219         .ops            = &clkops_null,
1220         .recalc         = &omap3_dpll_recalc,
1221 };
1223 static const struct clksel dpll_ddr_m2_div[] = {
1224         { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
1225         { .parent = NULL },
1226 };
1228 static struct clk dpll_ddr_m2_ck = {
1229         .name           = "dpll_ddr_m2_ck",
1230         .parent         = &dpll_ddr_ck,
1231         .clksel         = dpll_ddr_m2_div,
1232         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DDR,
1233         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1234         .ops            = &clkops_null,
1235         .recalc         = &omap2_clksel_recalc,
1236         .round_rate     = &omap2_clksel_round_rate,
1237         .set_rate       = &omap2_clksel_set_rate,
1238 };
1240 static struct clk ddr_pll_div_clk = {
1241         .name           = "ddr_pll_div_clk",
1242         .parent         = &dpll_ddr_m2_ck,
1243         .ops            = &clkops_null,
1244         .recalc         = &followparent_recalc,
1245 };
1247 static struct clk emif_fck = {
1248         .name           = "emif_fck",
1249         .ops            = &clkops_omap2_dflt,
1250         .enable_reg     = AM33XX_CM_PER_EMIF_CLKCTRL,
1251         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1252         .clkdm_name     = "l3_clkdm",
1253         .parent         = &ddr_pll_div_clk,
1254         .recalc         = &followparent_recalc,
1255         .flags          = ENABLE_ON_INIT,
1256 };
1258 static struct clk div_l4_rtc_gclk_ck = {
1259         .name           = "div_l4_rtc_gclk_ck",
1260         .parent         = &dpll_core_m4_ck,
1261         .ops            = &clkops_null,
1262         .recalc         = &followparent_recalc,
1263 };
1265 /* DPLL_DISP */
1266 static struct dpll_data dpll_disp_dd = {
1267         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
1268         .clk_bypass     = &sys_clkin_ck,
1269         .clk_ref        = &sys_clkin_ck,
1270         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
1271         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1272         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_DISP,
1273         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
1274         .mult_mask      = AM33XX_DPLL_MULT_MASK,
1275         .div1_mask      = AM33XX_DPLL_DIV_MASK,
1276         .enable_mask    = AM33XX_DPLL_EN_MASK,
1277         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
1278         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
1279         .max_multiplier = AM33XX_MAX_DPLL_MULT,
1280         .max_divider    = AM33XX_MAX_DPLL_DIV,
1281         .min_divider    = 1,
1282 };
1284 static struct clk dpll_disp_ck = {
1285         .name           = "dpll_disp_ck",
1286         .parent         = &sys_clkin_ck,
1287         .dpll_data      = &dpll_disp_dd,
1288         .init           = &omap2_init_dpll_parent,
1289         .ops            = &clkops_omap3_noncore_dpll_ops,
1290         .recalc         = &omap3_dpll_recalc,
1291         .round_rate     = &omap2_dpll_round_rate,
1292         .set_rate       = &omap3_noncore_dpll_set_rate,
1293 };
1295 static const struct clksel dpll_disp_m2_div[] = {
1296         { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
1297         { .parent = NULL },
1298 };
1300 static struct clk dpll_disp_m2_ck = {
1301         .name           = "dpll_disp_m2_ck",
1302         .parent         = &dpll_disp_ck,
1303         .clksel         = dpll_disp_m2_div,
1304         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DISP,
1305         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1306         .ops            = &clkops_null,
1307         .recalc         = &omap2_clksel_recalc,
1308         .round_rate     = &omap2_clksel_round_rate,
1309         .set_rate       = &omap2_clksel_set_rate,
1310 };
1312 /* DPLL_MPU */
1313 static struct dpll_data dpll_mpu_dd = {
1314         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
1315         .clk_bypass     = &sys_clkin_ck,
1316         .clk_ref        = &sys_clkin_ck,
1317         .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
1318         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1319         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_MPU,
1320         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
1321         .mult_mask      = AM33XX_DPLL_MULT_MASK,
1322         .div1_mask      = AM33XX_DPLL_DIV_MASK,
1323         .enable_mask    = AM33XX_DPLL_EN_MASK,
1324         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
1325         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
1326         .max_multiplier = AM33XX_MAX_DPLL_MULT,
1327         .max_divider    = AM33XX_MAX_DPLL_DIV,
1328         .min_divider    = 1,
1329 };
1331 static struct clk dpll_mpu_ck = {
1332         .name           = "dpll_mpu_ck",
1333         .parent         = &sys_clkin_ck,
1334         .dpll_data      = &dpll_mpu_dd,
1335         .init           = &omap2_init_dpll_parent,
1336         .ops            = &clkops_omap3_noncore_dpll_ops,
1337         .recalc         = &omap3_dpll_recalc,
1338         .round_rate     = &omap2_dpll_round_rate,
1339         .set_rate       = &omap3_noncore_dpll_set_rate,
1340 };
1343 static const struct clksel dpll_mpu_m2_div[] = {
1344         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
1345         { .parent = NULL },
1346 };
1348 static struct clk dpll_mpu_m2_ck = {
1349         .name           = "dpll_mpu_m2_ck",
1350         .parent         = &dpll_mpu_ck,
1351         .clksel         = dpll_mpu_m2_div,
1352         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_MPU,
1353         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1354         .ops            = &clkops_null,
1355         .recalc         = &omap2_clksel_recalc,
1356         .round_rate     = &omap2_clksel_round_rate,
1357         .set_rate       = &omap2_clksel_set_rate,
1358 };
1360 static struct clk mpu_fck = {
1361         .name           = "mpu_fck",
1362         .ops            = &clkops_omap2_dflt,
1363         .enable_reg     = AM33XX_CM_MPU_MPU_CLKCTRL,
1364         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1365         .clkdm_name     = "mpu_clkdm",
1366         .parent         = &dpll_mpu_m2_ck,
1367         .recalc         = &followparent_recalc,
1368 };
1370 static struct clk dpll_per_clkdcoldo_ck = {
1371         .name           = "dpll_per_clkdcoldo_ck",
1372         .parent         = &dpll_per_ck,
1373         .ops            = &clkops_null,
1374         .recalc         = &followparent_recalc,
1375 };
1378 static const struct clksel gpio_dbclk_mux_sel[] = {
1379         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1380         { .parent = &clk_32768_ck, .rates = div_1_1_rates },
1381         { .parent = &clk_32khz_ck, .rates = div_1_2_rates },
1382         { .parent = NULL },
1383 };
1385 static struct clk usbotg_ick = {
1386         .name           = "usbotg_ick",
1387         .parent         = &core_100m_ck,
1388         .ops            = &clkops_omap2_dflt,
1389         .clkdm_name     = "l3s_clkdm",
1390         .enable_reg     = AM33XX_CM_PER_USB0_CLKCTRL,
1391         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1392         .recalc         = &followparent_recalc,
1393 };
1395 static struct clk usbotg_fck = {
1396         .name           = "usbotg_fck",
1397         .ops            = &clkops_omap2_dflt,
1398         .clkdm_name     = "wkup_usb_clkdm",
1399         .enable_reg     = AM33XX_CM_CLKDCOLDO_DPLL_PER,
1400         .enable_bit     = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
1401         .parent         = &dpll_per_clkdcoldo_ck,
1402         .recalc         = &followparent_recalc,
1403 };
1405 static struct clk gpio_dbclk_mux_ck = {
1406         .name           = "gpio_dbclk_mux_ck",
1407         .parent         = &sys_clkin_ck,
1408         .init           = &omap2_init_clksel_parent,
1409         .clksel         = gpio_dbclk_mux_sel,
1410         .ops            = &clkops_null,
1411         .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
1412         .clksel_mask    = (3 << 0),
1413         .clkdm_name     = "l4_wkup_clkdm",
1414         .recalc         = &omap2_clksel_recalc,
1415 };
1417 static struct clk gpio0_dbclk = {
1418         .name           = "gpio0_dbclk",
1419         .parent         = &gpio_dbclk_mux_ck,
1420         .ops            = &clkops_omap2_dflt,
1421         .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
1422         .enable_bit     = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
1423         .clkdm_name     = "l4_wkup_clkdm",
1424         .recalc         = &followparent_recalc,
1425 };
1427 static struct clk gpio1_dbclk = {
1428         .name           = "gpio1_dbclk",
1429         .parent         = &clkdiv32k_fck,
1430         .ops            = &clkops_omap2_dflt,
1431         .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
1432         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
1433         .clkdm_name     = "l4ls_clkdm",
1434         .recalc         = &followparent_recalc,
1435 };
1437 static struct clk gpio2_dbclk = {
1438         .name           = "gpio2_dbclk",
1439         .parent         = &clkdiv32k_fck,
1440         .ops            = &clkops_omap2_dflt,
1441         .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
1442         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
1443         .clkdm_name     = "l4ls_clkdm",
1444         .recalc         = &followparent_recalc,
1445 };
1447 static struct clk gpio3_dbclk = {
1448         .name           = "gpio3_dbclk",
1449         .parent         = &clkdiv32k_fck,
1450         .ops            = &clkops_omap2_dflt,
1451         .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
1452         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
1453         .clkdm_name     = "l4ls_clkdm",
1454         .recalc         = &followparent_recalc,
1455 };
1457 static const struct clksel icss_ocp_clk_mux_sel[] = {
1458         { .parent = &sysclk_div_ck, .rates = div_1_0_rates },
1459         { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
1460         { .parent = NULL },
1461 };
1463 static struct clk icss_ocp_clk_mux_ck = {
1464         .name           = "icss_ocp_clk_mux_ck",
1465         .parent         = &sysclk_div_ck,
1466         .ops            = &clkops_null,
1467         .recalc         = &followparent_recalc,
1468 };
1471 static const struct clksel lcd_clk_mux_sel[] = {
1472         { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
1473         { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
1474         { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
1475         { .parent = NULL },
1476 };
1478 static struct clk lcd_clk_mux_ck = {
1479         .name           = "lcd_clk_mux_ck",
1480         .parent         = &dpll_disp_m2_ck,
1481         .ops            = &clkops_null,
1482         .recalc         = &followparent_recalc,
1483 };
1485 static struct clk lcdc_fck = {
1486         .name           = "lcdc_fck",
1487         .ops            = &clkops_omap2_dflt,
1488         .init           = &omap2_init_clksel_parent,
1489         .clksel         = lcd_clk_mux_sel,
1490         .enable_reg     = AM33XX_CM_PER_LCDC_CLKCTRL,
1491         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1492         .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
1493         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1494         .clkdm_name     = "lcdc_clkdm",
1495         .parent         = &dpll_disp_m2_ck,
1496         .recalc         = &followparent_recalc,
1497 };
1499 static struct clk mmc0_ick = {
1500         .name           = "mmc0_ick",
1501         .parent         = &l4ls_fck,
1502         .ops            = &clkops_null,
1503         .recalc         = &followparent_recalc,
1504 };
1506 static struct clk mmc1_ick = {
1507         .name           = "mmc1_ick",
1508         .parent         = &l4ls_fck,
1509         .ops            = &clkops_null,
1510         .recalc         = &followparent_recalc,
1511 };
1513 static struct clk mmc2_ick = {
1514         .name           = "mmc2_ick",
1515         .parent         = &l3_main_fck,
1516         .ops            = &clkops_null,
1517         .recalc         = &followparent_recalc,
1518 };
1520 static struct clk mmc_clk = {
1521         .name           = "mmc_clk",
1522         .parent         = &dpll_per_m2_ck,
1523         .ops            = &clkops_null,
1524         .fixed_div      = 2,
1525         .recalc         = &omap_fixed_divisor_recalc,
1526 };
1528 static struct clk mmc0_fck = {
1529         .name           = "mmc0_fck",
1530         .ops            = &clkops_omap2_dflt,
1531         .enable_reg     = AM33XX_CM_PER_MMC0_CLKCTRL,
1532         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1533         .clkdm_name     = "l4ls_clkdm",
1534         .parent         = &mmc_clk,
1535         .recalc         = &followparent_recalc,
1536 };
1538 static struct clk mmc1_fck = {
1539         .name           = "mmc1_fck",
1540         .ops            = &clkops_omap2_dflt,
1541         .enable_reg     = AM33XX_CM_PER_MMC1_CLKCTRL,
1542         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1543         .clkdm_name     = "l4ls_clkdm",
1544         .parent         = &mmc_clk,
1545         .recalc         = &followparent_recalc,
1546 };
1548 static struct clk mmc2_fck = {
1549         .name           = "mmc2_fck",
1550         .ops            = &clkops_omap2_dflt,
1551         .enable_reg     = AM33XX_CM_PER_MMC2_CLKCTRL,
1552         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1553         .clkdm_name     = "l3s_clkdm",
1554         .parent         = &mmc_clk,
1555         .recalc         = &followparent_recalc,
1556 };
1558 static const struct clksel sgx_clksel_sel[] = {
1559         { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
1560         { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
1561         { .parent = NULL },
1562 };
1564 static struct clk sgx_clksel_ck = {
1565         .name           = "sgx_clksel_ck",
1566         .parent         = &dpll_core_m4_ck,
1567         .clksel         = sgx_clksel_sel,
1568         .ops            = &clkops_null,
1569         .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
1570         .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
1571         .recalc         = &omap2_clksel_recalc,
1572 };
1574 static const struct clksel_rate div_1_0_2_1_rates[] = {
1575         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
1576         { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
1577         { .div = 0 },
1578 };
1580 static const struct clksel sgx_div_sel[] = {
1581         { .parent = &sgx_clksel_ck, .rates = div_1_0_2_1_rates },
1582         { .parent = NULL },
1583 };
1585 static struct clk sgx_ck = {
1586         .name           = "sgx_ck",
1587         .parent         = &sgx_clksel_ck,
1588         .clksel         = sgx_div_sel,
1589         .ops            = &clkops_null,
1590         .enable_reg     = AM33XX_CM_GFX_GFX_CLKCTRL,
1591         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1592         .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
1593         .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
1594         .clkdm_name     = "gfx_l3_clkdm",
1595         .recalc         = &omap2_clksel_recalc,
1596         .round_rate     = &omap2_clksel_round_rate,
1597         .set_rate       = &omap2_clksel_set_rate,
1598 };
1600 static const struct clksel sysclkout_pre_sel[] = {
1601         { .parent = &clk_32768_ck, .rates = div_1_0_rates },
1602         { .parent = &sysclk_div_ck, .rates = div_1_1_rates },
1603         { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
1604         { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
1605         { .parent = &lcd_clk_mux_ck, .rates = div_1_4_rates },
1606         { .parent = NULL },
1607 };
1609 static struct clk sysclkout_pre_ck = {
1610         .name           = "sysclkout_pre_ck",
1611         .init           = &omap2_init_clksel_parent,
1612         .ops            = &clkops_null,
1613         .clksel         = sysclkout_pre_sel,
1614         .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
1615         .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
1616         .recalc         = &omap2_clksel_recalc,
1617 };
1619 /* Divide by 8 clock rates with default clock is 1/1*/
1620 static const struct clksel_rate div8_rates[] = {
1621         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
1622         { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
1623         { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
1624         { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
1625         { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
1626         { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
1627         { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
1628         { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
1629         { .div = 0 },
1630 };
1632 static const struct clksel clkout2_div[] = {
1633         { .parent = &sysclkout_pre_ck, .rates = div8_rates },
1634         { .parent = NULL },
1635 };
1637 static struct clk clkout2_ck = {
1638         .name           = "clkout2_ck",
1639         .parent         = &sysclkout_pre_ck,
1640         .ops            = &clkops_omap2_dflt,
1641         .clksel         = clkout2_div,
1642         .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
1643         .clksel_mask    = AM33XX_CLKOUT2DIV_MASK,
1644         .enable_reg     = AM33XX_CM_CLKOUT_CTRL,
1645         .enable_bit     = AM33XX_CLKOUT2EN_SHIFT,
1646         .recalc         = &omap2_clksel_recalc,
1647         .round_rate     = &omap2_clksel_round_rate,
1648         .set_rate       = &omap2_clksel_set_rate,
1649 };
1651 static const struct clksel timer0_clkmux_sel[] = {
1652         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1653         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1654         { .parent = &sys_clkin_ck, .rates = div_1_2_rates },
1655         { .parent = &tclkin_ck, .rates = div_1_3_rates },
1656         { .parent = NULL },
1657 };
1659 static struct clk timer0_clkmux_ck = {
1660         .name           = "timer0_clkmux_ck",
1661         .parent         = &clk_rc32k_ck,
1662         .ops            = &clkops_null,
1663         .recalc         = &followparent_recalc,
1664 };
1666 static struct clk timer0_ick = {
1667         .name           = "timer0_ick",
1668         .parent         = &div_l4_wkup_gclk_ck,
1669         .ops            = &clkops_null,
1670         .recalc         = &followparent_recalc,
1671 };
1674 static struct clk timer0_fck = {
1675         .name           = "timer0_fck",
1676         .ops            = &clkops_omap2_dflt,
1677         .enable_reg     = AM33XX_CM_WKUP_TIMER0_CLKCTRL,
1678         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1679         .clkdm_name     = "l4_wkup_clkdm",
1680         .parent         = &timer0_clkmux_ck,
1681         .recalc         = &followparent_recalc,
1682 };
1684 static const struct clksel timer1_clkmux_sel[] = {
1685         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1686         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1687         { .parent = &tclkin_ck, .rates = div_1_2_rates },
1688         { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
1689         { .parent = &clk_32768_ck, .rates = div_1_4_rates },
1690         { .parent = NULL },
1691 };
1693 static struct clk timer1_ick = {
1694         .name           = "timer1_ick",
1695         .parent         = &div_l4_wkup_gclk_ck,
1696         .ops            = &clkops_null,
1697         .recalc         = &followparent_recalc,
1698 };
1700 static struct clk timer1_fck = {
1701         .name           = "timer1_fck",
1702         .parent         = &sys_clkin_ck,
1703         .init           = &omap2_init_clksel_parent,
1704         .clksel         = timer1_clkmux_sel,
1705         .ops            = &clkops_omap2_dflt,
1706         .enable_reg     = AM33XX_CM_WKUP_TIMER1_CLKCTRL,
1707         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1708         .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
1709         .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
1710         .clkdm_name     = "l4ls_clkdm",
1711         .recalc         = &omap2_clksel_recalc,
1712 };
1714 static struct clk vtp_clk_div_ck = {
1715         .name           = "vtp_clk_div_ck",
1716         .parent         = &sys_clkin_ck,
1717         .ops            = &clkops_null,
1718         .recalc         = &followparent_recalc,
1719         .flags          = ENABLE_ON_INIT,
1720 };
1724 static const struct clksel wdt0_clkmux_sel[] = {
1725         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1726         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1727         { .parent = NULL },
1728 };
1730 static struct clk wdt0_clkmux_ck = {
1731         .name           = "wdt0_clkmux_ck",
1732         .parent         = &clk_32khz_ck,
1733         .ops            = &clkops_null,
1734         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_PER,
1735         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1736         .recalc         = &followparent_recalc,
1737 };
1739 static struct clk wd_timer1_fck = {
1740         .name           = "wd_timer1_fck",
1741         .init           = &omap2_init_clksel_parent,
1742         .clksel         = wdt0_clkmux_sel,
1743         .ops            = &clkops_omap2_dflt,
1744         .enable_reg     = AM33XX_CM_WKUP_WDT1_CLKCTRL,
1745         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1746         .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
1747         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1748         .clkdm_name     = "l4_wkup_clkdm",
1749         .recalc         = &omap2_clksel_recalc,
1750 };
1752 static struct clk wdt0_fck = {
1753         .name           = "wdt0_fck",
1754         .ops            = &clkops_omap2_dflt,
1755         .enable_reg     = AM33XX_CM_WKUP_WDT0_CLKCTRL,
1756         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1757         .clkdm_name     = "l4_wkup_clkdm",
1758         .parent         = &wdt0_clkmux_ck,
1759         .recalc         = &followparent_recalc,
1760 };
1762 /*
1763  * clkdev
1764  */
1765 static struct omap_clk am33xx_clks[] = {
1766         CLK(NULL,       "clk_32768_ck",         &clk_32768_ck,  CK_AM33XX),
1767         CLK(NULL,       "clk_32khz_ck",         &clk_32khz_ck,  CK_AM33XX),
1768         CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck,  CK_AM33XX),
1769         CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck,  CK_AM33XX),
1770         CLK(NULL,       "tclkin_ck",            &tclkin_ck,     CK_AM33XX),
1771         CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck,   CK_AM33XX),
1772         CLK(NULL,       "adc_tsc_ick",          &adc_tsc_ick,   CK_AM33XX),
1773         CLK(NULL,       "aes0_fck",             &aes0_fck,      CK_AM33XX),
1774         CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
1775         CLK(NULL,       "clkdiv32k_fck",        &clkdiv32k_fck, CK_AM33XX),
1776         CLK(NULL,       "control_fck",          &control_fck,   CK_AM33XX),
1777         CLK("cpsw.0",   NULL,                   &cpgmac0_fck,   CK_AM33XX),
1778         CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
1779         CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
1780         CLK(NULL,       "dcan0_ick",            &dcan0_ick,     CK_AM33XX),
1781         CLK(NULL,       "dcan1_ick",            &dcan1_ick,     CK_AM33XX),
1782         CLK(NULL,       "debugss_fck",          &debugss_fck,   CK_AM33XX),
1783         CLK(NULL,       "elm_fck",              &elm_fck,       CK_AM33XX),
1784         CLK(NULL,       "emif_fck",             &emif_fck,      CK_AM33XX),
1785         CLK(NULL,       "emif_fw_fck",          &emif_fw_fck,   CK_AM33XX),
1786         CLK(NULL,       "epwmss0_fck",          &epwmss0_fck,   CK_AM33XX),
1787         CLK(NULL,       "epwmss1_fck",          &epwmss1_fck,   CK_AM33XX),
1788         CLK(NULL,       "epwmss2_fck",          &epwmss2_fck,   CK_AM33XX),
1789         CLK(NULL,       "gpio0_fck",            &gpio0_fck,     CK_AM33XX),
1790         CLK(NULL,       "gpio1_fck",            &gpio1_fck,     CK_AM33XX),
1791         CLK(NULL,       "gpio2_fck",            &gpio2_fck,     CK_AM33XX),
1792         CLK(NULL,       "gpio3_fck",            &gpio3_fck,     CK_AM33XX),
1793         CLK(NULL,       "gpmc_fck",             &gpmc_fck,      CK_AM33XX),
1794         CLK("omap_i2c.1",       "fck",          &i2c1_fck,      CK_AM33XX),
1795         CLK("omap_i2c.2",       "fck",          &i2c2_fck,      CK_AM33XX),
1796         CLK("omap_i2c.3",       "fck",          &i2c3_fck,      CK_AM33XX),
1797         CLK(NULL,       "icss_fck",             &icss_fck,      CK_AM33XX),
1798         CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
1799         CLK(NULL,       "l3_instr_fck",         &l3_instr_fck,  CK_AM33XX),
1800         CLK(NULL,       "l3_main_fck",          &l3_main_fck,   CK_AM33XX),
1801         CLK(NULL,       "l4_hs_fck",            &l4_hs_fck,     CK_AM33XX),
1802         CLK(NULL,       "l4fw_fck",             &l4fw_fck,      CK_AM33XX),
1803         CLK(NULL,       "l4ls_fck",             &l4ls_fck,      CK_AM33XX),
1804         CLK(NULL,       "l4wkup_fck",           &l4wkup_fck,    CK_AM33XX),
1805         CLK("da8xx_lcdc.0",     NULL,           &lcdc_fck,      CK_AM33XX),
1806         CLK(NULL,       "mailbox0_fck",         &mailbox0_fck,  CK_AM33XX),
1807         CLK(NULL,       "mcasp1_ick",           &mcasp0_ick,    CK_AM33XX),
1808         CLK(NULL,       "mcasp2_ick",           &mcasp1_ick,    CK_AM33XX),
1809         CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
1810         CLK("davinci-mcasp.1",  NULL,           &mcasp1_fck,    CK_AM33XX),
1811         CLK(NULL,       "mlb_fck",              &mlb_fck,       CK_AM33XX),
1812         CLK("omap_hsmmc.0",     "ick",          &mmc0_ick,      CK_AM33XX),
1813         CLK("omap_hsmmc.1",     "ick",          &mmc1_ick,      CK_AM33XX),
1814         CLK("omap_hsmmc.2",     "ick",          &mmc2_ick,      CK_AM33XX),
1815         CLK("omap_hsmmc.0",     "fck",          &mmc0_fck,      CK_AM33XX),
1816         CLK("omap_hsmmc.1",     "fck",          &mmc1_fck,      CK_AM33XX),
1817         CLK("omap_hsmmc.2",     "fck",          &mmc2_fck,      CK_AM33XX),
1818         CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
1819         CLK(NULL,       "mpu_ck",               &mpu_fck,       CK_AM33XX),
1820         CLK(NULL,       "mstr_exps_fck",        &mstr_exps_fck, CK_AM33XX),
1821         CLK(NULL,       "ocmcram_fck",          &ocmcram_fck,   CK_AM33XX),
1822         CLK(NULL,       "ocpwp_fck",            &ocpwp_fck,     CK_AM33XX),
1823         CLK(NULL,       "pka_fck",              &pka_fck,       CK_AM33XX),
1824         CLK(NULL,       "rng_fck",              &rng_fck,       CK_AM33XX),
1825         CLK(NULL,       "rtc_fck",              &rtc_fck,       CK_AM33XX),
1826         CLK(NULL,       "sha0_fck",             &sha0_fck,      CK_AM33XX),
1827         CLK(NULL,       "slv_exps_fck",         &slv_exps_fck,  CK_AM33XX),
1828         CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
1829         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
1830         CLK(NULL,       "spare0_fck",           &spare0_fck,    CK_AM33XX),
1831         CLK(NULL,       "spare1_fck",           &spare1_fck,    CK_AM33XX),
1832         CLK("omap2_mcspi.1",    "fck",          &spi0_fck,      CK_AM33XX),
1833         CLK("omap2_mcspi.2",    "fck",          &spi1_fck,      CK_AM33XX),
1834         CLK("omap2_mcspi.1",    "ick",          &spi0_ick,      CK_AM33XX),
1835         CLK("omap2_mcspi.2",    "ick",          &spi1_ick,      CK_AM33XX),
1836         CLK(NULL,       "spinlock_fck",         &spinlock_fck,  CK_AM33XX),
1837         CLK(NULL,       "timer0_fck",           &timer0_fck,    CK_AM33XX),
1838         CLK(NULL,       "gpt1_fck",             &timer1_fck,    CK_AM33XX),
1839         CLK(NULL,       "gpt2_fck",             &timer2_fck,    CK_AM33XX),
1840         CLK(NULL,       "gpt3_fck",             &timer3_fck,    CK_AM33XX),
1841         CLK(NULL,       "gpt4_fck",             &timer4_fck,    CK_AM33XX),
1842         CLK(NULL,       "gpt5_fck",             &timer5_fck,    CK_AM33XX),
1843         CLK(NULL,       "gpt6_fck",             &timer6_fck,    CK_AM33XX),
1844         CLK(NULL,       "gpt7_fck",             &timer7_fck,    CK_AM33XX),
1845         CLK(NULL,       "lcdc_ick_l3_clk",      &lcdc_l3ick,    CK_AM33XX),
1846         CLK(NULL,       "lcdc_ick_l4_clk",      &lcdc_l4ick,    CK_AM33XX),
1847         CLK(NULL,       "tpcc_ick",             &tpcc_ick,      CK_AM33XX),
1848         CLK(NULL,       "tptc0_ick",            &tptc0_ick,     CK_AM33XX),
1849         CLK(NULL,       "tptc1_ick",            &tptc1_ick,     CK_AM33XX),
1850         CLK(NULL,       "tptc2_ick",            &tptc2_ick,     CK_AM33XX),
1851         CLK(NULL,       "uart1_fck",            &uart1_fck,     CK_AM33XX),
1852         CLK(NULL,       "uart2_fck",            &uart2_fck,     CK_AM33XX),
1853         CLK(NULL,       "uart3_fck",            &uart3_fck,     CK_AM33XX),
1854         CLK(NULL,       "uart4_fck",            &uart4_fck,     CK_AM33XX),
1855         CLK(NULL,       "uart5_fck",            &uart5_fck,     CK_AM33XX),
1856         CLK(NULL,       "uart6_fck",            &uart6_fck,     CK_AM33XX),
1857         CLK(NULL,       "uart1_ick",            &uart1_ick,     CK_AM33XX),
1858         CLK(NULL,       "uart2_ick",            &uart2_ick,     CK_AM33XX),
1859         CLK(NULL,       "uart3_ick",            &uart3_ick,     CK_AM33XX),
1860         CLK(NULL,       "uart4_ick",            &uart4_ick,     CK_AM33XX),
1861         CLK(NULL,       "uart5_ick",            &uart5_ick,     CK_AM33XX),
1862         CLK(NULL,       "uart6_ick",            &uart6_ick,     CK_AM33XX),
1863         CLK(NULL,       "usbotg_ick",           &usbotg_ick,    CK_AM33XX),
1864         CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
1865         CLK(NULL,       "wd_timer1_fck",        &wd_timer1_fck, CK_AM33XX),
1866         CLK(NULL,       "wdt0_fck",             &wdt0_fck,      CK_AM33XX),
1867         CLK(NULL,       "wkup_m3_fck",          &wkup_m3_fck,   CK_AM33XX),
1868         CLK(NULL,       "dpll_per_ck",          &dpll_per_ck,   CK_AM33XX),
1869         CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck,        CK_AM33XX),
1870         CLK(NULL,       "i2c_clk",              &i2c_clk,               CK_AM33XX),
1871         CLK(NULL,       "clk_div_24_ck",        &clk_div_24_ck,         CK_AM33XX),
1872         CLK(NULL,       "dpll_core_ck",         &dpll_core_ck,          CK_AM33XX),
1873         CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck,       CK_AM33XX),
1874         CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck,       CK_AM33XX),
1875         CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck,         CK_AM33XX),
1876         CLK(NULL,       "core_100m_ck",         &core_100m_ck,          CK_AM33XX),
1877         CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
1878         CLK(NULL,       "cpsw_250m_clkdiv_ck",  &cpsw_250m_clkdiv_ck,   CK_AM33XX),
1879         CLK(NULL,       "cpsw_125mhz_ocp_ck",   &cpsw_125mhz_ocp_ck,    CK_AM33XX),
1880         CLK(NULL,       "cpsw_50m_clkdiv_ck",   &cpsw_50m_clkdiv_ck,    CK_AM33XX),
1881         CLK(NULL,       "cpsw_5m_clkdiv_ck",    &cpsw_5m_clkdiv_ck,     CK_AM33XX),
1882         CLK(NULL,       "cpts_rft_clkmux_ck",   &cpts_rft_clkmux_ck,    CK_AM33XX),
1883         CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,           CK_AM33XX),
1884         CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
1885         CLK(NULL,       "ddr_pll_div_clk",      &ddr_pll_div_clk,       CK_AM33XX),
1886         CLK(NULL,       "div_l4_rtc_gclk_ck",   &div_l4_rtc_gclk_ck,    CK_AM33XX),
1887         CLK(NULL,       "div_l4_wkup_gclk_ck",  &div_l4_wkup_gclk_ck,   CK_AM33XX),
1888         CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck,          CK_AM33XX),
1889         CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck,       CK_AM33XX),
1890         CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,           CK_AM33XX),
1891         CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
1892         CLK(NULL,       "dpll_per_clkdcoldo_ck", &dpll_per_clkdcoldo_ck,        CK_AM33XX),
1893         CLK(NULL,       "gpio_dbclk_mux_ck",    &gpio_dbclk_mux_ck,     CK_AM33XX),
1894         CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk,           CK_AM33XX),
1895         CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk,           CK_AM33XX),
1896         CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk,           CK_AM33XX),
1897         CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk,           CK_AM33XX),
1898         CLK(NULL,       "icss_ocp_clk_mux_ck",  &icss_ocp_clk_mux_ck,   CK_AM33XX),
1899         CLK(NULL,       "lcd_clk_mux_ck",       &lcd_clk_mux_ck,        CK_AM33XX),
1900         CLK(NULL,       "mmc_clk",              &mmc_clk,               CK_AM33XX),
1901         CLK(NULL,       "sgx_clksel_ck",        &sgx_clksel_ck,         CK_AM33XX),
1902         CLK(NULL,       "sgx_ck",               &sgx_ck,                CK_AM33XX),
1903         CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck,      CK_AM33XX),
1904         CLK(NULL,       "clkout2_ck",           &clkout2_ck,            CK_AM33XX),
1905         CLK(NULL,       "timer0_clkmux_ck",     &timer0_clkmux_ck,      CK_AM33XX),
1906         CLK(NULL,       "gpt0_ick",             &timer0_ick,            CK_AM33XX),
1907         CLK(NULL,       "gpt1_ick",             &timer1_ick,            CK_AM33XX),
1908         CLK(NULL,       "gpt2_ick",             &timer2_ick,            CK_AM33XX),
1909         CLK(NULL,       "gpt3_ick",             &timer3_ick,            CK_AM33XX),
1910         CLK(NULL,       "gpt4_ick",             &timer4_ick,            CK_AM33XX),
1911         CLK(NULL,       "gpt5_ick",             &timer5_ick,            CK_AM33XX),
1912         CLK(NULL,       "gpt6_ick",             &timer6_ick,            CK_AM33XX),
1913         CLK(NULL,       "gpt7_ick",             &timer7_ick,            CK_AM33XX),
1914         CLK(NULL,       "vtp_clk_div_ck",       &vtp_clk_div_ck,        CK_AM33XX),
1915         CLK(NULL,       "wdt0_clkmux_ck",       &wdt0_clkmux_ck,        CK_AM33XX),
1916 };
1918 int __init am33xx_clk_init(void)
1920         struct omap_clk *c;
1921         u32 cpu_clkflg;
1923         if (cpu_is_am33xx()) {
1924                 cpu_mask = RATE_IN_AM33XX;
1925                 cpu_clkflg = CK_AM33XX;
1926         }
1928         clk_init(&omap2_clk_functions);
1930         for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
1931                 clk_preinit(c->lk.clk);
1933         for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
1934                 if (c->cpu & cpu_clkflg) {
1935                         clkdev_add(&c->lk);
1936                         clk_register(c->lk.clk);
1937                         omap2_init_clk_clkdm(c->lk.clk);
1938                 }
1940         recalculate_root_clocks();
1942         /*
1943          * Only enable those clocks we will need, let the drivers
1944          * enable other clocks as necessary
1945          */
1946         clk_enable_init_clocks();
1948         return 0;