arm:omap:am33xx: dpll mpu clock config helpers
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / clock33xx_data.c
1 /*
2  * AM33XX Clock data
3  *
4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  */
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/clk.h>
19 #include <plat/clkdev_omap.h>
21 #include "control.h"
22 #include "clock.h"
23 #include "clock33xx.h"
24 #include "cm.h"
25 #include "cm33xx.h"
26 #include "cm-regbits-33xx.h"
27 #include "prm.h"
29 /* Modulemode control */
30 #define AM33XX_MODULEMODE_HWCTRL        0
31 #define AM33XX_MODULEMODE_SWCTRL        1
33 /* Root clocks */
34 static struct clk clk_32768_ck = {
35         .name           = "clk_32768_ck",
36         .rate           = 32768,
37         .ops            = &clkops_null,
38 };
40 static struct clk clk_32khz_ck = {
41         .name           = "clk_32khz_ck",
42         .rate           = 32768,
43         .ops            = &clkops_null,
44 };
46 /* On-Chip 32KHz RC OSC */
47 static struct clk clk_rc32k_ck = {
48         .name           = "clk_rc32k_ck",
49         .rate           = 32000,
50         .ops            = &clkops_null,
51 };
53 static struct clk tclkin_ck = {
54         .name           = "tclkin_ck",
55         .rate           = 12000000,
56         .ops            = &clkops_null,
57 };
59 static const struct clksel_rate div_1_0_rates[] = {
60         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
61         { .div = 0 },
62 };
64 static const struct clksel_rate div_1_1_rates[] = {
65         { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
66         { .div = 0 },
67 };
69 static const struct clksel_rate div_1_2_rates[] = {
70         { .div = 1, .val = 2, .flags = RATE_IN_AM33XX },
71         { .div = 0 },
72 };
74 static const struct clksel_rate div_1_3_rates[] = {
75         { .div = 1, .val = 3, .flags = RATE_IN_AM33XX },
76         { .div = 0 },
77 };
79 static const struct clksel_rate div_1_4_rates[] = {
80         { .div = 1, .val = 4, .flags = RATE_IN_AM33XX },
81         { .div = 0 },
82 };
84 static struct clk sys_clkin_ck = {
85         .name           = "sys_clkin_ck",
86         .rate           = 24000000,
87         .ops            = &clkops_null,
88 };
90 /* DPLL_PER */
91 static struct dpll_data dpll_per_dd = {
92         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
93         .clk_bypass     = &sys_clkin_ck,
94         .clk_ref        = &sys_clkin_ck,
95         .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
96         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
97         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_PER,
98         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
99         .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
100         .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
101         .enable_mask    = AM33XX_DPLL_EN_MASK,
102         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
103         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
104         .max_multiplier = AM33XX_MAX_DPLL_MULT,
105         .max_divider    = AM33XX_MAX_DPLL_DIV,
106         .min_divider    = 1,
107 };
109 static struct clk dpll_per_ck = {
110         .name           = "dpll_per_ck",
111         .parent         = &sys_clkin_ck,
112         .dpll_data      = &dpll_per_dd,
113         .init           = &omap2_init_dpll_parent,
114         .ops            = &clkops_null,
115         .recalc         = &omap3_dpll_recalc,
116 };
118 static const struct clksel_rate div31_1to31_rates[] = {
119         { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
120         { .div = 2, .val = 2, .flags = RATE_IN_AM33XX },
121         { .div = 3, .val = 3, .flags = RATE_IN_AM33XX },
122         { .div = 4, .val = 4, .flags = RATE_IN_AM33XX },
123         { .div = 5, .val = 5, .flags = RATE_IN_AM33XX },
124         { .div = 6, .val = 6, .flags = RATE_IN_AM33XX },
125         { .div = 7, .val = 7, .flags = RATE_IN_AM33XX },
126         { .div = 8, .val = 8, .flags = RATE_IN_AM33XX },
127         { .div = 9, .val = 9, .flags = RATE_IN_AM33XX },
128         { .div = 10, .val = 10, .flags = RATE_IN_AM33XX },
129         { .div = 11, .val = 11, .flags = RATE_IN_AM33XX },
130         { .div = 12, .val = 12, .flags = RATE_IN_AM33XX },
131         { .div = 13, .val = 13, .flags = RATE_IN_AM33XX },
132         { .div = 14, .val = 14, .flags = RATE_IN_AM33XX },
133         { .div = 15, .val = 15, .flags = RATE_IN_AM33XX },
134         { .div = 16, .val = 16, .flags = RATE_IN_AM33XX },
135         { .div = 17, .val = 17, .flags = RATE_IN_AM33XX },
136         { .div = 18, .val = 18, .flags = RATE_IN_AM33XX },
137         { .div = 19, .val = 19, .flags = RATE_IN_AM33XX },
138         { .div = 20, .val = 20, .flags = RATE_IN_AM33XX },
139         { .div = 21, .val = 21, .flags = RATE_IN_AM33XX },
140         { .div = 22, .val = 22, .flags = RATE_IN_AM33XX },
141         { .div = 23, .val = 23, .flags = RATE_IN_AM33XX },
142         { .div = 24, .val = 24, .flags = RATE_IN_AM33XX },
143         { .div = 25, .val = 25, .flags = RATE_IN_AM33XX },
144         { .div = 26, .val = 26, .flags = RATE_IN_AM33XX },
145         { .div = 27, .val = 27, .flags = RATE_IN_AM33XX },
146         { .div = 28, .val = 28, .flags = RATE_IN_AM33XX },
147         { .div = 29, .val = 29, .flags = RATE_IN_AM33XX },
148         { .div = 30, .val = 30, .flags = RATE_IN_AM33XX },
149         { .div = 31, .val = 31, .flags = RATE_IN_AM33XX },
150         { .div = 0 },
151 };
153 static const struct clksel dpll_per_m2_div[] = {
154         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
155         { .parent = NULL },
156 };
158 static struct clk dpll_per_m2_ck = {
159         .name           = "dpll_per_m2_ck",
160         .parent         = &dpll_per_ck,
161         .clksel         = dpll_per_m2_div,
162         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_PER,
163         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
164         .ops            = &clkops_null,
165         .recalc         = &omap2_clksel_recalc,
166         .round_rate     = &omap2_clksel_round_rate,
167         .set_rate       = &omap2_clksel_set_rate,
168 };
170 static struct clk i2c_clk = {
171         .name           = "i2c_clk",
172         .parent         = &dpll_per_m2_ck,
173         .ops            = &clkops_null,
174         .recalc         = &followparent_recalc,
175 };
177 static struct clk clk_div_24_ck = {
178         .name           = "clk_div_24_ck",
179         .parent         = &i2c_clk,
180         .ops            = &clkops_null,
181         .recalc         = &followparent_recalc,
182 };
184 /* DPLL_CORE */
185 static struct dpll_data dpll_core_dd = {
186         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
187         .clk_bypass     = &sys_clkin_ck,
188         .clk_ref        = &sys_clkin_ck,
189         .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
190         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
191         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_CORE,
192         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
193         .mult_mask      = AM33XX_DPLL_MULT_MASK,
194         .div1_mask      = AM33XX_DPLL_DIV_MASK,
195         .enable_mask    = AM33XX_DPLL_EN_MASK,
196         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
197         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
198         .max_multiplier = AM33XX_MAX_DPLL_MULT,
199         .max_divider    = AM33XX_MAX_DPLL_DIV,
200         .min_divider    = 1,
201 };
203 static struct clk dpll_core_ck = {
204         .name           = "dpll_core_ck",
205         .parent         = &sys_clkin_ck,
206         .dpll_data      = &dpll_core_dd,
207         .init           = &omap2_init_dpll_parent,
208         .ops            = &clkops_null,
209         .recalc         = &omap3_dpll_recalc,
210 };
212 static struct clk dpll_core_x2_ck = {
213         .name           = "dpll_core_x2_ck",
214         .parent         = &dpll_core_ck,
215         .ops            = &clkops_null,
216         .recalc         = &omap3_clkoutx2_recalc,
217 };
219 static const struct clksel dpll_core_m4_div[] = {
220         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
221         { .parent = NULL },
222 };
224 static struct clk dpll_core_m4_ck = {
225         .name           = "dpll_core_m4_ck",
226         .parent         = &dpll_core_x2_ck,
227         .clksel         = dpll_core_m4_div,
228         .clksel_reg     = AM33XX_CM_DIV_M4_DPLL_CORE,
229         .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
230         .ops            = &clkops_null,
231         .recalc         = &omap2_clksel_recalc,
232         .round_rate     = &omap2_clksel_round_rate,
233         .set_rate       = &omap2_clksel_set_rate,
234 };
236 static struct clk sysclk_div_ck = {
237         .name           = "sysclk_div_ck",
238         .parent         = &dpll_core_m4_ck,
239         .ops            = &clkops_null,
240         .recalc         = &followparent_recalc,
241 };
243 static struct clk div_l4_wkup_gclk_ck = {
244         .name           = "div_l4_wkup_gclk_ck",
245         .parent         = &dpll_core_m4_ck,
246         .ops            = &clkops_null,
247         .fixed_div      = 2,
248         .recalc         = &omap_fixed_divisor_recalc,
249 };
251 static struct clk core_100m_ck = {
252         .name           = "core_100m_ck",
253         .parent         = &sysclk_div_ck,
254         .ops            = &clkops_null,
255         .fixed_div      = 2,
256         .recalc         = &omap_fixed_divisor_recalc,
257 };
259 static struct clk l4ls_fck = {
260         .name           = "l4ls_fck",
261         .ops            = &clkops_omap2_dflt,
262         .enable_reg     = AM33XX_CM_PER_L4LS_CLKCTRL,
263         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
264         .clkdm_name     = "l4ls_clkdm",
265         .parent         = &core_100m_ck,
266         .recalc         = &followparent_recalc,
267 };
269 static struct clk timer2_ick = {
270         .name           = "timer2_ick",
271         .parent         = &l4ls_fck,
272         .ops            = &clkops_null,
273         .recalc         = &followparent_recalc,
274 };
276 static struct clk timer3_ick = {
277         .name           = "timer3_ick",
278         .parent         = &l4ls_fck,
279         .ops            = &clkops_null,
280         .recalc         = &followparent_recalc,
281 };
283 static struct clk timer4_ick = {
284         .name           = "timer4_ick",
285         .parent         = &l4ls_fck,
286         .ops            = &clkops_null,
287         .recalc         = &followparent_recalc,
288 };
290 static struct clk timer5_ick = {
291         .name           = "timer5_ick",
292         .parent         = &l4ls_fck,
293         .ops            = &clkops_null,
294         .recalc         = &followparent_recalc,
295 };
297 static struct clk timer6_ick = {
298         .name           = "timer6_ick",
299         .parent         = &l4ls_fck,
300         .ops            = &clkops_null,
301         .recalc         = &followparent_recalc,
302 };
304 static struct clk timer7_ick = {
305         .name           = "timer7_ick",
306         .parent         = &l4ls_fck,
307         .ops            = &clkops_null,
308         .recalc         = &followparent_recalc,
309 };
311 static struct clk lcdc_l3ick = {
312         .name           = "lcdc_ick_l3_clk",
313         .enable_reg     = AM33XX_CM_PER_L3_CLKCTRL,
314         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
315         .parent         = &dpll_core_m4_ck,
316         .ops            = &clkops_null,
317         .clkdm_name     = "l3_clkdm",
318         .recalc         = &followparent_recalc,
319 };
321 static struct clk lcdc_l4ick = {
322         .name           = "lcdc_ick_l4_clk",
323         .enable_reg     = AM33XX_CM_PER_L4LS_CLKCTRL,
324         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
325         .parent         = &dpll_core_m4_ck,
326         .ops            = &clkops_null,
327         .clkdm_name     = "l4ls_clkdm",
328         .recalc         = &followparent_recalc,
329 };
331 /* Leaf clocks controlled by modules */
332 static struct clk adc_tsc_fck = {
333         .name           = "adc_tsc_fck",
334         .ops            = &clkops_null,
335         .parent         = &sys_clkin_ck,
336         .clkdm_name     = "l4_wkup_clkdm",
337         .recalc         = &followparent_recalc,
338 };
340 static struct clk adc_tsc_ick = {
341         .name           = "adc_tsc_ick",
342         .ops            = &clkops_omap2_dflt,
343         .enable_reg     = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL,
344         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
345         .parent         = &div_l4_wkup_gclk_ck,
346         .recalc         = &followparent_recalc,
347 };
349 static struct clk aes0_fck = {
350         .name           = "aes0_fck",
351         .ops            = &clkops_omap2_dflt,
352         .enable_reg     = AM33XX_CM_PER_AES0_CLKCTRL,
353         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
354         .clkdm_name     = "l3_clkdm",
355         .parent         = &sysclk_div_ck,
356         .recalc         = &followparent_recalc,
357 };
359 static struct clk cefuse_fck = {
360         .name           = "cefuse_fck",
361         .ops            = &clkops_omap2_dflt,
362         .enable_reg     = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
363         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
364         .clkdm_name     = "l4_cefuse_clkdm",
365         .parent         = &sys_clkin_ck,
366         .recalc         = &followparent_recalc,
367 };
369 static struct clk clkdiv32k_fck = {
370         .name           = "clkdiv32k_fck",
371         .ops            = &clkops_omap2_dflt,
372         .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
373         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
374         .clkdm_name     = "clk_24mhz_clkdm",
375         .parent         = &clk_div_24_ck,
376         .recalc         = &followparent_recalc,
377 };
379 static struct clk control_fck = {
380         .name           = "control_fck",
381         .ops            = &clkops_omap2_dflt,
382         .enable_reg     = AM33XX_CM_WKUP_CONTROL_CLKCTRL,
383         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
384         .clkdm_name     = "l4_wkup_clkdm",
385         .parent         = &div_l4_wkup_gclk_ck,
386         .recalc         = &followparent_recalc,
387 };
389 static struct clk dcan0_fck = {
390         .name           = "dcan0_fck",
391         .ops            = &clkops_omap2_dflt,
392         .enable_reg     = AM33XX_CM_PER_DCAN0_CLKCTRL,
393         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
394         .clkdm_name     = "l4ls_clkdm",
395         .parent         = &sys_clkin_ck,
396         .recalc         = &followparent_recalc,
397 };
399 static struct clk dcan1_fck = {
400         .name           = "dcan1_fck",
401         .ops            = &clkops_omap2_dflt,
402         .enable_reg     = AM33XX_CM_PER_DCAN1_CLKCTRL,
403         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
404         .clkdm_name     = "l4ls_clkdm",
405         .parent         = &sys_clkin_ck,
406         .recalc         = &followparent_recalc,
407 };
409 static struct clk dcan0_ick = {
410         .name           = "dcan0_ick",
411         .parent         = &dpll_per_m2_ck ,
412         .ops            = &clkops_null,
413         .clkdm_name     = "l4ls_clkdm",
414         .recalc         = &followparent_recalc,
415 };
417 static struct clk dcan1_ick = {
418         .name           = "dcan1_ick",
419         .parent         = &dpll_per_m2_ck ,
420         .ops            = &clkops_null,
421         .clkdm_name     = "l4ls_clkdm",
422         .recalc         = &followparent_recalc,
423 };
425 static struct clk debugss_fck = {
426         .name           = "debugss_fck",
427         .ops            = &clkops_omap2_dflt,
428         .enable_reg     = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
429         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
430         .clkdm_name     = "l3_aon_clkdm",
431         .parent         = &dpll_core_m4_ck,
432         .recalc         = &followparent_recalc,
433 };
435 static struct clk elm_fck = {
436         .name           = "elm_fck",
437         .ops            = &clkops_omap2_dflt,
438         .enable_reg     = AM33XX_CM_PER_ELM_CLKCTRL,
439         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
440         .clkdm_name     = "l4ls_clkdm",
441         .parent         = &core_100m_ck,
442         .recalc         = &followparent_recalc,
443 };
445 static struct clk emif_fw_fck = {
446         .name           = "emif_fw_fck",
447         .ops            = &clkops_omap2_dflt,
448         .enable_reg     = AM33XX_CM_PER_EMIF_FW_CLKCTRL,
449         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
450         .clkdm_name     = "l4fw_clkdm",
451         .parent         = &core_100m_ck,
452         .recalc         = &followparent_recalc,
453 };
455 static struct clk epwmss0_fck = {
456         .name           = "epwmss0_fck",
457         .ops            = &clkops_omap2_dflt,
458         .enable_reg     = AM33XX_CM_PER_EPWMSS0_CLKCTRL,
459         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
460         .clkdm_name     = "l4ls_clkdm",
461         .parent         = &core_100m_ck,
462         .recalc         = &followparent_recalc,
463 };
465 static struct clk epwmss1_fck = {
466         .name           = "epwmss1_fck",
467         .ops            = &clkops_omap2_dflt,
468         .enable_reg     = AM33XX_CM_PER_EPWMSS1_CLKCTRL,
469         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
470         .clkdm_name     = "l4ls_clkdm",
471         .parent         = &core_100m_ck,
472         .recalc         = &followparent_recalc,
473 };
475 static struct clk epwmss2_fck = {
476         .name           = "epwmss2_fck",
477         .ops            = &clkops_omap2_dflt,
478         .enable_reg     = AM33XX_CM_PER_EPWMSS2_CLKCTRL,
479         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
480         .clkdm_name     = "l4ls_clkdm",
481         .parent         = &core_100m_ck,
482         .recalc         = &followparent_recalc,
483 };
485 static struct clk gpio0_fck = {
486         .name           = "gpio0_fck",
487         .ops            = &clkops_omap2_dflt,
488         .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
489         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
490         .clkdm_name     = "l4_wkup_clkdm",
491         .parent         = &div_l4_wkup_gclk_ck,
492         .recalc         = &followparent_recalc,
493 };
495 static struct clk gpio1_fck = {
496         .name           = "gpio1_fck",
497         .ops            = &clkops_omap2_dflt,
498         .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
499         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
500         .clkdm_name     = "l4ls_clkdm",
501         .parent         = &core_100m_ck,
502         .recalc         = &followparent_recalc,
503 };
505 static struct clk gpio2_fck = {
506         .name           = "gpio2_fck",
507         .ops            = &clkops_omap2_dflt,
508         .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
509         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
510         .clkdm_name     = "l4ls_clkdm",
511         .parent         = &core_100m_ck,
512         .recalc         = &followparent_recalc,
513 };
515 static struct clk gpio3_fck = {
516         .name           = "gpio3_fck",
517         .ops            = &clkops_omap2_dflt,
518         .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
519         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
520         .clkdm_name     = "l4ls_clkdm",
521         .parent         = &core_100m_ck,
522         .recalc         = &followparent_recalc,
523 };
525 static struct clk gpmc_fck = {
526         .name           = "gpmc_fck",
527         .ops            = &clkops_omap2_dflt,
528         .enable_reg     = AM33XX_CM_PER_GPMC_CLKCTRL,
529         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
530         .clkdm_name     = "l3s_clkdm",
531         .parent         = &core_100m_ck,
532         .recalc         = &followparent_recalc,
533 };
535 static struct clk i2c1_fck = {
536         .name           = "i2c1_fck",
537         .ops            = &clkops_omap2_dflt,
538         .enable_reg     = AM33XX_CM_WKUP_I2C0_CLKCTRL,
539         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
540         .clkdm_name     = "l4_wkup_clkdm",
541         .parent         = &dpll_per_m2_ck,
542         .fixed_div      = 4,
543         .recalc         = &omap_fixed_divisor_recalc,
544 };
546 static struct clk i2c2_fck = {
547         .name           = "i2c2_fck",
548         .ops            = &clkops_omap2_dflt,
549         .enable_reg     = AM33XX_CM_PER_I2C1_CLKCTRL,
550         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
551         .clkdm_name     = "l4ls_clkdm",
552         .parent         = &i2c_clk,
553         .recalc         = &followparent_recalc,
554 };
556 static struct clk i2c3_fck = {
557         .name           = "i2c3_fck",
558         .ops            = &clkops_omap2_dflt,
559         .enable_reg     = AM33XX_CM_PER_I2C2_CLKCTRL,
560         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
561         .clkdm_name     = "l4ls_clkdm",
562         .parent         = &i2c_clk,
563         .recalc         = &followparent_recalc,
564 };
566 static struct clk icss_fck = {
567         .name           = "icss_fck",
568         .ops            = &clkops_omap2_dflt,
569         .enable_reg     = AM33XX_CM_PER_ICSS_CLKCTRL,
570         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
571         .clkdm_name     = "icss_ocp_clkdm",
572         .parent         = &dpll_per_m2_ck,
573         .recalc         = &followparent_recalc,
574 };
576 static struct clk ieee5000_fck = {
577         .name           = "ieee5000_fck",
578         .ops            = &clkops_omap2_dflt,
579         .enable_reg     = AM33XX_CM_PER_IEEE5000_CLKCTRL,
580         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
581         .clkdm_name     = "l3s_clkdm",
582         .parent         = &core_100m_ck,
583         .recalc         = &followparent_recalc,
584 };
586 static struct clk l3_instr_fck = {
587         .name           = "l3_instr_fck",
588         .ops            = &clkops_omap2_dflt,
589         .enable_reg     = AM33XX_CM_PER_L3_INSTR_CLKCTRL,
590         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
591         .clkdm_name     = "l3_clkdm",
592         .parent         = &sysclk_div_ck,
593         .recalc         = &followparent_recalc,
594 };
596 static struct clk l3_main_fck = {
597         .name           = "l3_main_fck",
598         .ops            = &clkops_omap2_dflt,
599         .enable_reg     = AM33XX_CM_PER_L3_CLKCTRL,
600         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
601         .clkdm_name     = "l3_clkdm",
602         .parent         = &sysclk_div_ck,
603         .recalc         = &followparent_recalc,
604 };
606 static struct clk l4_hs_fck = {
607         .name           = "l4_hs_fck",
608         .ops            = &clkops_omap2_dflt,
609         .enable_reg     = AM33XX_CM_PER_L4HS_CLKCTRL,
610         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
611         .clkdm_name     = "l4hs_clkdm",
612         .parent         = &sysclk_div_ck,
613         .recalc         = &followparent_recalc,
614 };
616 static struct clk l4fw_fck = {
617         .name           = "l4fw_fck",
618         .ops            = &clkops_omap2_dflt,
619         .enable_reg     = AM33XX_CM_PER_L4FW_CLKCTRL,
620         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
621         .clkdm_name     = "l4fw_clkdm",
622         .parent         = &core_100m_ck,
623         .recalc         = &followparent_recalc,
624 };
626 static struct clk l4wkup_fck = {
627         .name           = "l4wkup_fck",
628         .ops            = &clkops_omap2_dflt,
629         .enable_reg     = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
630         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
631         .clkdm_name     = "l4_wkup_aon_clkdm",
632         .parent         = &div_l4_wkup_gclk_ck,
633         .recalc         = &followparent_recalc,
634 };
636 static struct clk mailbox0_fck = {
637         .name           = "mailbox0_fck",
638         .ops            = &clkops_omap2_dflt,
639         .enable_reg     = AM33XX_CM_PER_MAILBOX0_CLKCTRL,
640         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
641         .clkdm_name     = "l4ls_clkdm",
642         .parent         = &core_100m_ck,
643         .recalc         = &followparent_recalc,
644 };
646 static struct clk mcasp0_ick = {
647         .name           = "mcasp0_ick",
648         .parent         = &l3_main_fck,
649         .ops            = &clkops_null,
650         .recalc         = &followparent_recalc,
651 };
653 static struct clk mcasp1_ick = {
654         .name           = "mcasp1_ick",
655         .parent         = &l3_main_fck,
656         .ops            = &clkops_null,
657         .recalc         = &followparent_recalc,
658 };
660 static struct clk mcasp0_fck = {
661         .name           = "mcasp0_fck",
662         .ops            = &clkops_omap2_dflt,
663         .enable_reg     = AM33XX_CM_PER_MCASP0_CLKCTRL,
664         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
665         .clkdm_name     = "l3s_clkdm",
666         .parent         = &sys_clkin_ck,
667         .recalc         = &followparent_recalc,
668 };
670 static struct clk mcasp1_fck = {
671         .name           = "mcasp1_fck",
672         .ops            = &clkops_omap2_dflt,
673         .enable_reg     = AM33XX_CM_PER_MCASP1_CLKCTRL,
674         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
675         .clkdm_name     = "l3s_clkdm",
676         .parent         = &sys_clkin_ck,
677         .recalc         = &followparent_recalc,
678 };
680 static struct clk mlb_fck = {
681         .name           = "mlb_fck",
682         .ops            = &clkops_omap2_dflt,
683         .enable_reg     = AM33XX_CM_PER_MLB_CLKCTRL,
684         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
685         .clkdm_name     = "l3_clkdm",
686         .parent         = &sysclk_div_ck,
687         .recalc         = &followparent_recalc,
688 };
690 static struct clk mmu_fck = {
691         .name           = "mmu_fck",
692         .ops            = &clkops_omap2_dflt,
693         .enable_reg     = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
694         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
695         .clkdm_name     = "gfx_l3_clkdm",
696         .parent         = &dpll_core_m4_ck,
697         .recalc         = &followparent_recalc,
698 };
701 static struct clk mstr_exps_fck = {
702         .name           = "mstr_exps_fck",
703         .ops            = &clkops_omap2_dflt,
704         .enable_reg     = AM33XX_CM_PER_MSTR_EXPS_CLKCTRL,
705         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
706         .clkdm_name     = "l3_clkdm",
707         .parent         = &sysclk_div_ck,
708         .recalc         = &followparent_recalc,
709 };
711 static struct clk ocmcram_fck = {
712         .name           = "ocmcram_fck",
713         .ops            = &clkops_omap2_dflt,
714         .enable_reg     = AM33XX_CM_PER_OCMCRAM_CLKCTRL,
715         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
716         .clkdm_name     = "l3_clkdm",
717         .parent         = &sysclk_div_ck,
718         .recalc         = &followparent_recalc,
719 };
721 static struct clk ocpwp_fck = {
722         .name           = "ocpwp_fck",
723         .ops            = &clkops_omap2_dflt,
724         .enable_reg     = AM33XX_CM_PER_OCPWP_CLKCTRL,
725         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
726         .clkdm_name     = "l4ls_clkdm",
727         .parent         = &core_100m_ck,
728         .recalc         = &followparent_recalc,
729 };
731 static struct clk pka_fck = {
732         .name           = "pka_fck",
733         .ops            = &clkops_omap2_dflt,
734         .enable_reg     = AM33XX_CM_PER_PKA_CLKCTRL,
735         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
736         .clkdm_name     = "l4ls_clkdm",
737         .parent         = &core_100m_ck,
738         .recalc         = &followparent_recalc,
739 };
741 static struct clk rng_fck = {
742         .name           = "rng_fck",
743         .ops            = &clkops_omap2_dflt,
744         .enable_reg     = AM33XX_CM_PER_RNG_CLKCTRL,
745         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
746         .clkdm_name     = "l4ls_clkdm",
747         .parent         = &core_100m_ck,
748         .recalc         = &followparent_recalc,
749 };
751 static struct clk rtc_fck = {
752         .name           = "rtc_fck",
753         .ops            = &clkops_omap2_dflt,
754         .enable_reg     = AM33XX_CM_RTC_RTC_CLKCTRL,
755         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
756         .clkdm_name     = "l4_rtc_clkdm",
757         .parent         = &clk_32khz_ck,
758         .recalc         = &followparent_recalc,
759 };
761 static struct clk sha0_fck = {
762         .name           = "sha0_fck",
763         .ops            = &clkops_omap2_dflt,
764         .enable_reg     = AM33XX_CM_PER_SHA0_CLKCTRL,
765         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
766         .clkdm_name     = "l3_clkdm",
767         .parent         = &sysclk_div_ck,
768         .recalc         = &followparent_recalc,
769 };
771 static struct clk slv_exps_fck = {
772         .name           = "slv_exps_fck",
773         .ops            = &clkops_omap2_dflt,
774         .enable_reg     = AM33XX_CM_PER_SLV_EXPS_CLKCTRL,
775         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
776         .clkdm_name     = "l3_clkdm",
777         .parent         = &sysclk_div_ck,
778         .recalc         = &followparent_recalc,
779 };
781 static struct clk smartreflex0_fck = {
782         .name           = "smartreflex0_fck",
783         .ops            = &clkops_omap2_dflt,
784         .enable_reg     = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL,
785         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
786         .clkdm_name     = "l4_wkup_clkdm",
787         .parent         = &sys_clkin_ck,
788         .recalc         = &followparent_recalc,
789 };
791 static struct clk smartreflex1_fck = {
792         .name           = "smartreflex1_fck",
793         .ops            = &clkops_omap2_dflt,
794         .enable_reg     = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL,
795         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
796         .clkdm_name     = "l4_wkup_clkdm",
797         .parent         = &sys_clkin_ck,
798         .recalc         = &followparent_recalc,
799 };
801 static struct clk spare0_fck = {
802         .name           = "spare0_fck",
803         .ops            = &clkops_omap2_dflt,
804         .enable_reg     = AM33XX_CM_PER_SPARE0_CLKCTRL,
805         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
806         .clkdm_name     = "l4ls_clkdm",
807         .parent         = &core_100m_ck,
808         .recalc         = &followparent_recalc,
809 };
811 static struct clk spare1_fck = {
812         .name           = "spare1_fck",
813         .ops            = &clkops_omap2_dflt,
814         .enable_reg     = AM33XX_CM_PER_SPARE1_CLKCTRL,
815         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
816         .clkdm_name     = "l4ls_clkdm",
817         .parent         = &core_100m_ck,
818         .recalc         = &followparent_recalc,
819 };
821 static struct clk spi0_fck = {
822         .name           = "spi0_fck",
823         .parent         = &dpll_per_m2_ck ,
824         .ops            = &clkops_omap2_dflt,
825         .enable_reg     = AM33XX_CM_PER_SPI0_CLKCTRL,
826         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
827         .clkdm_name     = "l4ls_clkdm",
828         .fixed_div      = 4,
829         .recalc         = &omap_fixed_divisor_recalc,
830 };
832 static struct clk spi1_fck = {
833         .name           = "spi1_fck",
834         .parent         = &dpll_per_m2_ck ,
835         .ops            = &clkops_omap2_dflt,
836         .enable_reg     = AM33XX_CM_PER_SPI1_CLKCTRL,
837         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
838         .clkdm_name     = "l4ls_clkdm",
839         .fixed_div      = 4,
840         .recalc         = &omap_fixed_divisor_recalc,
841 };
843 static struct clk spi0_ick = {
844         .name           = "spi0_ick",
845         .parent         = &l4ls_fck,
846         .ops            = &clkops_null,
847         .recalc         = &followparent_recalc,
848 };
850 static struct clk spi1_ick = {
851         .name           = "spi1_ick",
852         .parent         = &l4ls_fck,
853         .ops            = &clkops_null,
854         .recalc         = &followparent_recalc,
855 };
857 static struct clk spinlock_fck = {
858         .name           = "spinlock_fck",
859         .ops            = &clkops_omap2_dflt,
860         .enable_reg     = AM33XX_CM_PER_SPINLOCK_CLKCTRL,
861         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
862         .clkdm_name     = "l4ls_clkdm",
863         .parent         = &core_100m_ck,
864         .recalc         = &followparent_recalc,
865 };
867 static const struct clksel timer2_to_7_clk_sel[] = {
868         { .parent = &tclkin_ck, .rates = div_1_0_rates },
869         { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
870         { .parent = &clk_32khz_ck, .rates = div_1_2_rates },
871         { .parent = NULL },
872 };
874 static struct clk timer2_fck = {
875         .name           = "timer2_fck",
876         .parent         = &sys_clkin_ck,
877         .init           = &omap2_init_clksel_parent,
878         .clksel         = timer2_to_7_clk_sel,
879         .ops            = &clkops_omap2_dflt,
880         .enable_reg     = AM33XX_CM_PER_TIMER2_CLKCTRL,
881         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
882         .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
883         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
884         .clkdm_name     = "l4ls_clkdm",
885         .recalc         = &omap2_clksel_recalc,
886 };
888 static struct clk timer3_fck = {
889         .name           = "timer3_fck",
890         .parent         = &sys_clkin_ck,
891         .init           = &am33xx_init_timer_parent,
892         .clksel         = timer2_to_7_clk_sel,
893         .ops            = &clkops_omap2_dflt,
894         .enable_reg     = AM33XX_CM_PER_TIMER3_CLKCTRL,
895         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
896         .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
897         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
898         .clkdm_name     = "l4ls_clkdm",
899         .recalc         = &omap2_clksel_recalc,
900 };
902 static struct clk timer4_fck = {
903         .name           = "timer4_fck",
904         .parent         = &sys_clkin_ck,
905         .init           = &omap2_init_clksel_parent,
906         .clksel         = timer2_to_7_clk_sel,
907         .ops            = &clkops_omap2_dflt,
908         .enable_reg     = AM33XX_CM_PER_TIMER4_CLKCTRL,
909         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
910         .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
911         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
912         .clkdm_name     = "l4ls_clkdm",
913         .recalc         = &omap2_clksel_recalc,
914 };
916 static struct clk timer5_fck = {
917         .name           = "timer5_fck",
918         .parent         = &sys_clkin_ck,
919         .init           = &omap2_init_clksel_parent,
920         .clksel         = timer2_to_7_clk_sel,
921         .ops            = &clkops_omap2_dflt,
922         .enable_reg     = AM33XX_CM_PER_TIMER5_CLKCTRL,
923         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
924         .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
925         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
926         .clkdm_name     = "l4ls_clkdm",
927         .recalc         = &omap2_clksel_recalc,
928 };
930 static struct clk timer6_fck = {
931         .name           = "timer6_fck",
932         .parent         = &sys_clkin_ck,
933         .init           = &am33xx_init_timer_parent,
934         .clksel         = timer2_to_7_clk_sel,
935         .ops            = &clkops_omap2_dflt,
936         .enable_reg     = AM33XX_CM_PER_TIMER6_CLKCTRL,
937         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
938         .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
939         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
940         .clkdm_name     = "l4ls_clkdm",
941         .recalc         = &omap2_clksel_recalc,
942 };
944 static struct clk timer7_fck = {
945         .name           = "timer7_fck",
946         .parent         = &sys_clkin_ck,
947         .init           = &omap2_init_clksel_parent,
948         .clksel         = timer2_to_7_clk_sel,
949         .ops            = &clkops_omap2_dflt,
950         .enable_reg     = AM33XX_CM_PER_TIMER7_CLKCTRL,
951         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
952         .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
953         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
954         .clkdm_name     = "l4ls_clkdm",
955         .recalc         = &omap2_clksel_recalc,
956 };
958 static struct clk tpcc_ick = {
959         .name           = "tpcc_ick",
960         .ops            = &clkops_omap2_dflt,
961         .enable_reg     = AM33XX_CM_PER_TPCC_CLKCTRL,
962         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
963         .clkdm_name     = "l3_clkdm",
964         .parent         = &l3_main_fck,
965         .recalc         = &followparent_recalc,
966 };
968 static struct clk tptc0_ick = {
969         .name           = "tptc0_ick",
970         .ops            = &clkops_omap2_dflt,
971         .enable_reg     = AM33XX_CM_PER_TPTC0_CLKCTRL,
972         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
973         .clkdm_name     = "l3_clkdm",
974         .parent         = &l3_main_fck,
975         .recalc         = &followparent_recalc,
976 };
978 static struct clk tptc1_ick = {
979         .name           = "tptc1_ick",
980         .ops            = &clkops_omap2_dflt,
981         .enable_reg     = AM33XX_CM_PER_TPTC1_CLKCTRL,
982         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
983         .clkdm_name     = "l3_clkdm",
984         .parent         = &l3_main_fck,
985         .recalc         = &followparent_recalc,
986 };
988 static struct clk tptc2_ick = {
989         .name           = "tptc2_ick",
990         .ops            = &clkops_omap2_dflt,
991         .enable_reg     = AM33XX_CM_PER_TPTC2_CLKCTRL,
992         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
993         .clkdm_name     = "l3_clkdm",
994         .parent         = &l3_main_fck,
995         .recalc         = &followparent_recalc,
996 };
998 static struct clk uart1_fck = {
999         .name           = "uart1_fck",
1000         .parent         = &dpll_per_m2_ck ,
1001         .ops            = &clkops_omap2_dflt,
1002         .enable_reg     = AM33XX_CM_WKUP_UART0_CLKCTRL,
1003         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1004         .clkdm_name     = "l4_wkup_clkdm",
1005         .fixed_div      = 4,
1006         .recalc         = &omap_fixed_divisor_recalc,
1007 };
1009 static struct clk uart2_fck = {
1010         .name           = "uart2_fck",
1011         .parent         = &dpll_per_m2_ck ,
1012         .ops            = &clkops_omap2_dflt,
1013         .enable_reg     = AM33XX_CM_PER_UART1_CLKCTRL,
1014         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1015         .clkdm_name     = "l4ls_clkdm",
1016         .fixed_div      = 4,
1017         .recalc         = &omap_fixed_divisor_recalc,
1018 };
1020 static struct clk uart3_fck = {
1021         .name           = "uart3_fck",
1022         .parent         = &dpll_per_m2_ck ,
1023         .ops            = &clkops_omap2_dflt,
1024         .enable_reg     = AM33XX_CM_PER_UART2_CLKCTRL,
1025         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1026         .clkdm_name     = "l4ls_clkdm",
1027         .fixed_div      = 4,
1028         .recalc         = &omap_fixed_divisor_recalc,
1029 };
1031 static struct clk uart4_fck = {
1032         .name           = "uart4_fck",
1033         .parent         = &dpll_per_m2_ck ,
1034         .ops            = &clkops_omap2_dflt,
1035         .enable_reg     = AM33XX_CM_PER_UART3_CLKCTRL,
1036         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1037         .clkdm_name     = "l4ls_clkdm",
1038         .fixed_div      = 4,
1039         .recalc         = &omap_fixed_divisor_recalc,
1040 };
1042 static struct clk uart5_fck = {
1043         .name           = "uart5_fck",
1044         .parent         = &dpll_per_m2_ck ,
1045         .ops            = &clkops_omap2_dflt,
1046         .enable_reg     = AM33XX_CM_PER_UART4_CLKCTRL,
1047         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1048         .clkdm_name     = "l4ls_clkdm",
1049         .fixed_div      = 4,
1050         .recalc         = &omap_fixed_divisor_recalc,
1051 };
1053 static struct clk uart6_fck = {
1054         .name           = "uart6_fck",
1055         .parent         = &dpll_per_m2_ck ,
1056         .ops            = &clkops_omap2_dflt,
1057         .enable_reg     = AM33XX_CM_PER_UART5_CLKCTRL,
1058         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1059         .clkdm_name     = "l4ls_clkdm",
1060         .fixed_div      = 4,
1061         .recalc         = &omap_fixed_divisor_recalc,
1062 };
1064 static struct clk uart1_ick = {
1065         .name           = "uart1_ick",
1066         .parent         = &div_l4_wkup_gclk_ck,
1067         .ops            = &clkops_null,
1068         .recalc         = &followparent_recalc,
1069 };
1071 static struct clk uart2_ick = {
1072         .name           = "uart2_ick",
1073         .parent         = &l4ls_fck,
1074         .ops            = &clkops_null,
1075         .recalc         = &followparent_recalc,
1076 };
1078 static struct clk uart3_ick = {
1079         .name           = "uart3_ick",
1080         .parent         = &l4ls_fck,
1081         .ops            = &clkops_null,
1082         .recalc         = &followparent_recalc,
1083 };
1085 static struct clk uart4_ick = {
1086         .name           = "uart4_ick",
1087         .parent         = &l4ls_fck,
1088         .ops            = &clkops_null,
1089         .recalc         = &followparent_recalc,
1090 };
1092 static struct clk uart5_ick = {
1093         .name           = "uart5_ick",
1094         .parent         = &l4ls_fck,
1095         .ops            = &clkops_null,
1096         .recalc         = &followparent_recalc,
1097 };
1099 static struct clk uart6_ick = {
1100         .name           = "uart6_ick",
1101         .parent         = &l4ls_fck,
1102         .ops            = &clkops_null,
1103         .recalc         = &followparent_recalc,
1104 };
1106 static struct clk wkup_m3_fck = {
1107         .name           = "wkup_m3_fck",
1108         .ops            = &clkops_omap2_dflt,
1109         .enable_reg     = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL,
1110         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1111         .clkdm_name     = "l4_wkup_aon_clkdm",
1112         .parent         = &div_l4_wkup_gclk_ck,
1113         .recalc         = &followparent_recalc,
1114 };
1116 static struct clk dpll_core_m5_ck = {
1117         .name           = "dpll_core_m5_ck",
1118         .parent         = &dpll_core_x2_ck,
1119         .clksel         = dpll_core_m4_div,
1120         .clksel_reg     = AM33XX_CM_DIV_M5_DPLL_CORE,
1121         .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
1122         .ops            = &clkops_null,
1123         .recalc         = &omap2_clksel_recalc,
1124         .round_rate     = &omap2_clksel_round_rate,
1125         .set_rate       = &omap2_clksel_set_rate,
1126 };
1128 static struct clk cpsw_250m_clkdiv_ck = {
1129         .name           = "cpsw_250m_clkdiv_ck",
1130         .parent         = &dpll_core_m5_ck,
1131         .ops            = &clkops_null,
1132         .recalc         = &followparent_recalc,
1133 };
1135 static struct clk cpsw_125mhz_ocp_ck = {
1136         .name           = "cpsw_125mhz_ocp_ck",
1137         .parent         = &dpll_core_m5_ck,
1138         .ops            = &clkops_null,
1139         .fixed_div      = 2,
1140         .recalc         = &omap_fixed_divisor_recalc,
1141 };
1143 static struct clk cpsw_50m_clkdiv_ck = {
1144         .name           = "cpsw_50m_clkdiv_ck",
1145         .parent         = &dpll_core_m5_ck,
1146         .ops            = &clkops_null,
1147         .fixed_div      = 5,
1148         .recalc         = &omap_fixed_divisor_recalc,
1149 };
1151 static struct clk cpgmac0_fck = {
1152         .name           = "cpgmac0_fck",
1153         .ops            = &clkops_omap2_dflt,
1154         .enable_reg     = AM33XX_CM_PER_CPGMAC0_CLKCTRL,
1155         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1156         .clkdm_name     = "cpsw_125mhz_clkdm",
1157         .parent         = &cpsw_125mhz_ocp_ck,
1158         .recalc         = &followparent_recalc,
1159 };
1161 static struct clk cpsw_5m_clkdiv_ck = {
1162         .name           = "cpsw_5m_clkdiv_ck",
1163         .parent         = &cpsw_50m_clkdiv_ck,
1164         .ops            = &clkops_null,
1165         .fixed_div      = 10,
1166         .recalc         = &omap_fixed_divisor_recalc,
1167 };
1170 static const struct clksel cpts_rft_clkmux_sel[] = {
1171         { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
1172         { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
1173         { .parent = NULL },
1174 };
1176 static struct clk cpts_rft_clkmux_ck = {
1177         .name           = "cpts_rft_clkmux_ck",
1178         .parent         = &dpll_core_m5_ck,
1179         .ops            = &clkops_null,
1180         .recalc         = &followparent_recalc,
1181 };
1185 /* DPLL_DDR */
1186 static struct dpll_data dpll_ddr_dd = {
1187         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
1188         .clk_bypass     = &sys_clkin_ck,
1189         .clk_ref        = &sys_clkin_ck,
1190         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
1191         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1192         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_DDR,
1193         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
1194         .mult_mask      = AM33XX_DPLL_MULT_MASK,
1195         .div1_mask      = AM33XX_DPLL_DIV_MASK,
1196         .enable_mask    = AM33XX_DPLL_EN_MASK,
1197         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
1198         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
1199         .max_multiplier = AM33XX_MAX_DPLL_MULT,
1200         .max_divider    = AM33XX_MAX_DPLL_DIV,
1201         .min_divider    = 1,
1202 };
1205 static struct clk dpll_ddr_ck = {
1206         .name           = "dpll_ddr_ck",
1207         .parent         = &sys_clkin_ck,
1208         .dpll_data      = &dpll_ddr_dd,
1209         .init           = &omap2_init_dpll_parent,
1210         .ops            = &clkops_null,
1211         .recalc         = &omap3_dpll_recalc,
1212 };
1214 static const struct clksel dpll_ddr_m2_div[] = {
1215         { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
1216         { .parent = NULL },
1217 };
1219 static struct clk dpll_ddr_m2_ck = {
1220         .name           = "dpll_ddr_m2_ck",
1221         .parent         = &dpll_ddr_ck,
1222         .clksel         = dpll_ddr_m2_div,
1223         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DDR,
1224         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1225         .ops            = &clkops_null,
1226         .recalc         = &omap2_clksel_recalc,
1227         .round_rate     = &omap2_clksel_round_rate,
1228         .set_rate       = &omap2_clksel_set_rate,
1229 };
1231 static struct clk ddr_pll_div_clk = {
1232         .name           = "ddr_pll_div_clk",
1233         .parent         = &dpll_ddr_m2_ck,
1234         .ops            = &clkops_null,
1235         .recalc         = &followparent_recalc,
1236 };
1238 static struct clk emif_fck = {
1239         .name           = "emif_fck",
1240         .ops            = &clkops_omap2_dflt,
1241         .enable_reg     = AM33XX_CM_PER_EMIF_CLKCTRL,
1242         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1243         .clkdm_name     = "l3_clkdm",
1244         .parent         = &ddr_pll_div_clk,
1245         .recalc         = &followparent_recalc,
1246 };
1248 static struct clk div_l4_rtc_gclk_ck = {
1249         .name           = "div_l4_rtc_gclk_ck",
1250         .parent         = &dpll_core_m4_ck,
1251         .ops            = &clkops_null,
1252         .recalc         = &followparent_recalc,
1253 };
1255 /* DPLL_DISP */
1256 static struct dpll_data dpll_disp_dd = {
1257         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
1258         .clk_bypass     = &sys_clkin_ck,
1259         .clk_ref        = &sys_clkin_ck,
1260         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
1261         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1262         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_DISP,
1263         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
1264         .mult_mask      = AM33XX_DPLL_MULT_MASK,
1265         .div1_mask      = AM33XX_DPLL_DIV_MASK,
1266         .enable_mask    = AM33XX_DPLL_EN_MASK,
1267         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
1268         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
1269         .max_multiplier = AM33XX_MAX_DPLL_MULT,
1270         .max_divider    = AM33XX_MAX_DPLL_DIV,
1271         .min_divider    = 1,
1272 };
1274 static struct clk dpll_disp_ck = {
1275         .name           = "dpll_disp_ck",
1276         .parent         = &sys_clkin_ck,
1277         .dpll_data      = &dpll_disp_dd,
1278         .init           = &omap2_init_dpll_parent,
1279         .ops            = &clkops_omap3_noncore_dpll_ops,
1280         .recalc         = &omap3_dpll_recalc,
1281         .round_rate     = &omap2_dpll_round_rate,
1282         .set_rate       = &omap3_noncore_dpll_set_rate,
1283 };
1285 static const struct clksel dpll_disp_m2_div[] = {
1286         { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
1287         { .parent = NULL },
1288 };
1290 static struct clk dpll_disp_m2_ck = {
1291         .name           = "dpll_disp_m2_ck",
1292         .parent         = &dpll_disp_ck,
1293         .clksel         = dpll_disp_m2_div,
1294         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DISP,
1295         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1296         .ops            = &clkops_null,
1297         .recalc         = &omap2_clksel_recalc,
1298         .round_rate     = &omap2_clksel_round_rate,
1299         .set_rate       = &omap2_clksel_set_rate,
1300 };
1302 /* DPLL_MPU */
1303 static struct dpll_data dpll_mpu_dd = {
1304         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
1305         .clk_bypass     = &sys_clkin_ck,
1306         .clk_ref        = &sys_clkin_ck,
1307         .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
1308         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1309         .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_MPU,
1310         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
1311         .mult_mask      = AM33XX_DPLL_MULT_MASK,
1312         .div1_mask      = AM33XX_DPLL_DIV_MASK,
1313         .enable_mask    = AM33XX_DPLL_EN_MASK,
1314         .autoidle_mask  = AM33XX_AUTO_DPLL_MODE_MASK,
1315         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
1316         .max_multiplier = AM33XX_MAX_DPLL_MULT,
1317         .max_divider    = AM33XX_MAX_DPLL_DIV,
1318         .min_divider    = 1,
1319 };
1321 static struct clk dpll_mpu_ck = {
1322         .name           = "dpll_mpu_ck",
1323         .parent         = &sys_clkin_ck,
1324         .dpll_data      = &dpll_mpu_dd,
1325         .init           = &omap2_init_dpll_parent,
1326         .ops            = &clkops_omap3_noncore_dpll_ops,
1327         .recalc         = &omap3_dpll_recalc,
1328         .round_rate     = &omap2_dpll_round_rate,
1329         .set_rate       = &omap3_noncore_dpll_set_rate,
1330 };
1333 static const struct clksel dpll_mpu_m2_div[] = {
1334         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
1335         { .parent = NULL },
1336 };
1338 static struct clk dpll_mpu_m2_ck = {
1339         .name           = "dpll_mpu_m2_ck",
1340         .parent         = &dpll_mpu_ck,
1341         .clksel         = dpll_mpu_m2_div,
1342         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_MPU,
1343         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1344         .ops            = &clkops_null,
1345         .recalc         = &omap2_clksel_recalc,
1346         .round_rate     = &omap2_clksel_round_rate,
1347         .set_rate       = &omap2_clksel_set_rate,
1348 };
1350 static struct clk mpu_fck = {
1351         .name           = "mpu_fck",
1352         .ops            = &clkops_omap2_dflt,
1353         .enable_reg     = AM33XX_CM_MPU_MPU_CLKCTRL,
1354         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1355         .clkdm_name     = "mpu_clkdm",
1356         .parent         = &dpll_mpu_m2_ck,
1357         .recalc         = &followparent_recalc,
1358 };
1360 static struct clk dpll_per_clkdcoldo_ck = {
1361         .name           = "dpll_per_clkdcoldo_ck",
1362         .parent         = &dpll_per_ck,
1363         .ops            = &clkops_null,
1364         .recalc         = &followparent_recalc,
1365 };
1368 static const struct clksel gpio_dbclk_mux_sel[] = {
1369         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1370         { .parent = &clk_32768_ck, .rates = div_1_1_rates },
1371         { .parent = &clk_32khz_ck, .rates = div_1_2_rates },
1372         { .parent = NULL },
1373 };
1375 static struct clk usbotg_ick = {
1376         .name           = "usbotg_ick",
1377         .parent         = &core_100m_ck,
1378         .ops            = &clkops_omap2_dflt,
1379         .clkdm_name     = "l3s_clkdm",
1380         .enable_reg     = AM33XX_CM_PER_USB0_CLKCTRL,
1381         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1382         .recalc         = &followparent_recalc,
1383 };
1385 static struct clk usbotg_fck = {
1386         .name           = "usbotg_fck",
1387         .ops            = &clkops_omap2_dflt,
1388         .clkdm_name     = "wkup_usb_clkdm",
1389         .enable_reg     = AM33XX_CM_CLKDCOLDO_DPLL_PER,
1390         .enable_bit     = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
1391         .parent         = &dpll_per_clkdcoldo_ck,
1392         .recalc         = &followparent_recalc,
1393 };
1395 static struct clk gpio_dbclk_mux_ck = {
1396         .name           = "gpio_dbclk_mux_ck",
1397         .parent         = &sys_clkin_ck,
1398         .init           = &omap2_init_clksel_parent,
1399         .clksel         = gpio_dbclk_mux_sel,
1400         .ops            = &clkops_null,
1401         .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
1402         .clksel_mask    = (3 << 0),
1403         .clkdm_name     = "l4_wkup_clkdm",
1404         .recalc         = &omap2_clksel_recalc,
1405 };
1407 static struct clk gpio0_dbclk = {
1408         .name           = "gpio0_dbclk",
1409         .parent         = &gpio_dbclk_mux_ck,
1410         .ops            = &clkops_omap2_dflt,
1411         .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
1412         .enable_bit     = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
1413         .clkdm_name     = "l4_wkup_clkdm",
1414         .recalc         = &followparent_recalc,
1415 };
1417 static struct clk gpio1_dbclk = {
1418         .name           = "gpio1_dbclk",
1419         .parent         = &clkdiv32k_fck,
1420         .ops            = &clkops_omap2_dflt,
1421         .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
1422         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
1423         .clkdm_name     = "l4ls_clkdm",
1424         .recalc         = &followparent_recalc,
1425 };
1427 static struct clk gpio2_dbclk = {
1428         .name           = "gpio2_dbclk",
1429         .parent         = &clkdiv32k_fck,
1430         .ops            = &clkops_omap2_dflt,
1431         .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
1432         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
1433         .clkdm_name     = "l4ls_clkdm",
1434         .recalc         = &followparent_recalc,
1435 };
1437 static struct clk gpio3_dbclk = {
1438         .name           = "gpio3_dbclk",
1439         .parent         = &clkdiv32k_fck,
1440         .ops            = &clkops_omap2_dflt,
1441         .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
1442         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
1443         .clkdm_name     = "l4ls_clkdm",
1444         .recalc         = &followparent_recalc,
1445 };
1447 static const struct clksel icss_ocp_clk_mux_sel[] = {
1448         { .parent = &sysclk_div_ck, .rates = div_1_0_rates },
1449         { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
1450         { .parent = NULL },
1451 };
1453 static struct clk icss_ocp_clk_mux_ck = {
1454         .name           = "icss_ocp_clk_mux_ck",
1455         .parent         = &sysclk_div_ck,
1456         .ops            = &clkops_null,
1457         .recalc         = &followparent_recalc,
1458 };
1461 static const struct clksel lcd_clk_mux_sel[] = {
1462         { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
1463         { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
1464         { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
1465         { .parent = NULL },
1466 };
1468 static struct clk lcd_clk_mux_ck = {
1469         .name           = "lcd_clk_mux_ck",
1470         .parent         = &dpll_disp_m2_ck,
1471         .ops            = &clkops_null,
1472         .recalc         = &followparent_recalc,
1473 };
1475 static struct clk lcdc_fck = {
1476         .name           = "lcdc_fck",
1477         .ops            = &clkops_omap2_dflt,
1478         .init           = &omap2_init_clksel_parent,
1479         .clksel         = lcd_clk_mux_sel,
1480         .enable_reg     = AM33XX_CM_PER_LCDC_CLKCTRL,
1481         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1482         .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
1483         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1484         .clkdm_name     = "lcdc_clkdm",
1485         .parent         = &dpll_disp_m2_ck,
1486         .recalc         = &followparent_recalc,
1487 };
1489 static struct clk mmc0_ick = {
1490         .name           = "mmc0_ick",
1491         .parent         = &l4ls_fck,
1492         .ops            = &clkops_null,
1493         .recalc         = &followparent_recalc,
1494 };
1496 static struct clk mmc1_ick = {
1497         .name           = "mmc1_ick",
1498         .parent         = &l4ls_fck,
1499         .ops            = &clkops_null,
1500         .recalc         = &followparent_recalc,
1501 };
1503 static struct clk mmc2_ick = {
1504         .name           = "mmc2_ick",
1505         .parent         = &l3_main_fck,
1506         .ops            = &clkops_null,
1507         .recalc         = &followparent_recalc,
1508 };
1510 static struct clk mmc_clk = {
1511         .name           = "mmc_clk",
1512         .parent         = &dpll_per_m2_ck,
1513         .ops            = &clkops_null,
1514         .fixed_div      = 2,
1515         .recalc         = &omap_fixed_divisor_recalc,
1516 };
1518 static struct clk mmc0_fck = {
1519         .name           = "mmc0_fck",
1520         .ops            = &clkops_omap2_dflt,
1521         .enable_reg     = AM33XX_CM_PER_MMC0_CLKCTRL,
1522         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1523         .clkdm_name     = "l4ls_clkdm",
1524         .parent         = &mmc_clk,
1525         .recalc         = &followparent_recalc,
1526 };
1528 static struct clk mmc1_fck = {
1529         .name           = "mmc1_fck",
1530         .ops            = &clkops_omap2_dflt,
1531         .enable_reg     = AM33XX_CM_PER_MMC1_CLKCTRL,
1532         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1533         .clkdm_name     = "l4ls_clkdm",
1534         .parent         = &mmc_clk,
1535         .recalc         = &followparent_recalc,
1536 };
1538 static struct clk mmc2_fck = {
1539         .name           = "mmc2_fck",
1540         .ops            = &clkops_omap2_dflt,
1541         .enable_reg     = AM33XX_CM_PER_MMC2_CLKCTRL,
1542         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1543         .clkdm_name     = "l3s_clkdm",
1544         .parent         = &mmc_clk,
1545         .recalc         = &followparent_recalc,
1546 };
1548 static const struct clksel sgx_clksel_sel[] = {
1549         { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
1550         { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
1551         { .parent = NULL },
1552 };
1554 static struct clk sgx_clksel_ck = {
1555         .name           = "sgx_clksel_ck",
1556         .parent         = &dpll_core_m4_ck,
1557         .clksel         = sgx_clksel_sel,
1558         .ops            = &clkops_null,
1559         .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
1560         .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
1561         .recalc         = &omap2_clksel_recalc,
1562 };
1564 static const struct clksel_rate div_1_0_2_1_rates[] = {
1565         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
1566         { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
1567         { .div = 0 },
1568 };
1570 static const struct clksel sgx_div_sel[] = {
1571         { .parent = &sgx_clksel_ck, .rates = div_1_0_2_1_rates },
1572         { .parent = NULL },
1573 };
1575 static struct clk sgx_ck = {
1576         .name           = "sgx_ck",
1577         .parent         = &sgx_clksel_ck,
1578         .clksel         = sgx_div_sel,
1579         .ops            = &clkops_null,
1580         .enable_reg     = AM33XX_CM_GFX_GFX_CLKCTRL,
1581         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1582         .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
1583         .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
1584         .clkdm_name     = "gfx_l3_clkdm",
1585         .recalc         = &omap2_clksel_recalc,
1586         .round_rate     = &omap2_clksel_round_rate,
1587         .set_rate       = &omap2_clksel_set_rate,
1588 };
1590 static const struct clksel sysclkout_pre_sel[] = {
1591         { .parent = &clk_32768_ck, .rates = div_1_0_rates },
1592         { .parent = &sysclk_div_ck, .rates = div_1_1_rates },
1593         { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
1594         { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
1595         { .parent = &lcd_clk_mux_ck, .rates = div_1_4_rates },
1596         { .parent = NULL },
1597 };
1599 static struct clk sysclkout_pre_ck = {
1600         .name           = "sysclkout_pre_ck",
1601         .init           = &omap2_init_clksel_parent,
1602         .ops            = &clkops_null,
1603         .clksel         = sysclkout_pre_sel,
1604         .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
1605         .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
1606         .recalc         = &omap2_clksel_recalc,
1607 };
1609 /* Divide by 8 clock rates with default clock is 1/1*/
1610 static const struct clksel_rate div8_rates[] = {
1611         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
1612         { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
1613         { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
1614         { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
1615         { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
1616         { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
1617         { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
1618         { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
1619         { .div = 0 },
1620 };
1622 static const struct clksel clkout2_div[] = {
1623         { .parent = &sysclkout_pre_ck, .rates = div8_rates },
1624         { .parent = NULL },
1625 };
1627 static struct clk clkout2_ck = {
1628         .name           = "clkout2_ck",
1629         .parent         = &sysclkout_pre_ck,
1630         .ops            = &clkops_omap2_dflt,
1631         .clksel         = clkout2_div,
1632         .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
1633         .clksel_mask    = AM33XX_CLKOUT2DIV_MASK,
1634         .enable_reg     = AM33XX_CM_CLKOUT_CTRL,
1635         .enable_bit     = AM33XX_CLKOUT2EN_SHIFT,
1636         .recalc         = &omap2_clksel_recalc,
1637         .round_rate     = &omap2_clksel_round_rate,
1638         .set_rate       = &omap2_clksel_set_rate,
1639 };
1641 static const struct clksel timer0_clkmux_sel[] = {
1642         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1643         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1644         { .parent = &sys_clkin_ck, .rates = div_1_2_rates },
1645         { .parent = &tclkin_ck, .rates = div_1_3_rates },
1646         { .parent = NULL },
1647 };
1649 static struct clk timer0_clkmux_ck = {
1650         .name           = "timer0_clkmux_ck",
1651         .parent         = &clk_rc32k_ck,
1652         .ops            = &clkops_null,
1653         .recalc         = &followparent_recalc,
1654 };
1656 static struct clk timer0_ick = {
1657         .name           = "timer0_ick",
1658         .parent         = &div_l4_wkup_gclk_ck,
1659         .ops            = &clkops_null,
1660         .recalc         = &followparent_recalc,
1661 };
1664 static struct clk timer0_fck = {
1665         .name           = "timer0_fck",
1666         .ops            = &clkops_omap2_dflt,
1667         .enable_reg     = AM33XX_CM_WKUP_TIMER0_CLKCTRL,
1668         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1669         .clkdm_name     = "l4_wkup_clkdm",
1670         .parent         = &timer0_clkmux_ck,
1671         .recalc         = &followparent_recalc,
1672 };
1674 static const struct clksel timer1_clkmux_sel[] = {
1675         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1676         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1677         { .parent = &tclkin_ck, .rates = div_1_2_rates },
1678         { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
1679         { .parent = &clk_32768_ck, .rates = div_1_4_rates },
1680         { .parent = NULL },
1681 };
1683 static struct clk timer1_ick = {
1684         .name           = "timer1_ick",
1685         .parent         = &div_l4_wkup_gclk_ck,
1686         .ops            = &clkops_null,
1687         .recalc         = &followparent_recalc,
1688 };
1690 static struct clk timer1_fck = {
1691         .name           = "timer1_fck",
1692         .parent         = &sys_clkin_ck,
1693         .init           = &omap2_init_clksel_parent,
1694         .clksel         = timer1_clkmux_sel,
1695         .ops            = &clkops_omap2_dflt,
1696         .enable_reg     = AM33XX_CM_WKUP_TIMER1_CLKCTRL,
1697         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1698         .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
1699         .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
1700         .clkdm_name     = "l4ls_clkdm",
1701         .recalc         = &omap2_clksel_recalc,
1702 };
1704 static struct clk vtp_clk_div_ck = {
1705         .name           = "vtp_clk_div_ck",
1706         .parent         = &sys_clkin_ck,
1707         .ops            = &clkops_null,
1708         .recalc         = &followparent_recalc,
1709 };
1713 static const struct clksel wdt0_clkmux_sel[] = {
1714         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1715         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1716         { .parent = NULL },
1717 };
1719 static struct clk wdt0_clkmux_ck = {
1720         .name           = "wdt0_clkmux_ck",
1721         .parent         = &clk_32khz_ck,
1722         .ops            = &clkops_null,
1723         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_PER,
1724         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
1725         .recalc         = &followparent_recalc,
1726 };
1728 static struct clk wd_timer1_fck = {
1729         .name           = "wd_timer1_fck",
1730         .init           = &omap2_init_clksel_parent,
1731         .clksel         = wdt0_clkmux_sel,
1732         .ops            = &clkops_omap2_dflt,
1733         .enable_reg     = AM33XX_CM_WKUP_WDT1_CLKCTRL,
1734         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1735         .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
1736         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1737         .clkdm_name     = "l4_wkup_clkdm",
1738         .recalc         = &omap2_clksel_recalc,
1739 };
1741 static struct clk wdt0_fck = {
1742         .name           = "wdt0_fck",
1743         .ops            = &clkops_omap2_dflt,
1744         .enable_reg     = AM33XX_CM_WKUP_WDT0_CLKCTRL,
1745         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1746         .clkdm_name     = "l4_wkup_clkdm",
1747         .parent         = &wdt0_clkmux_ck,
1748         .recalc         = &followparent_recalc,
1749 };
1751 /*
1752  * clkdev
1753  */
1754 static struct omap_clk am33xx_clks[] = {
1755         CLK(NULL,       "clk_32768_ck",         &clk_32768_ck,  CK_AM33XX),
1756         CLK(NULL,       "clk_32khz_ck",         &clk_32khz_ck,  CK_AM33XX),
1757         CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck,  CK_AM33XX),
1758         CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck,  CK_AM33XX),
1759         CLK(NULL,       "tclkin_ck",            &tclkin_ck,     CK_AM33XX),
1760         CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck,   CK_AM33XX),
1761         CLK(NULL,       "adc_tsc_ick",          &adc_tsc_ick,   CK_AM33XX),
1762         CLK(NULL,       "aes0_fck",             &aes0_fck,      CK_AM33XX),
1763         CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
1764         CLK(NULL,       "clkdiv32k_fck",        &clkdiv32k_fck, CK_AM33XX),
1765         CLK(NULL,       "control_fck",          &control_fck,   CK_AM33XX),
1766         CLK("cpsw.0",   NULL,                   &cpgmac0_fck,   CK_AM33XX),
1767         CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
1768         CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
1769         CLK(NULL,       "dcan0_ick",            &dcan0_ick,     CK_AM33XX),
1770         CLK(NULL,       "dcan1_ick",            &dcan1_ick,     CK_AM33XX),
1771         CLK(NULL,       "debugss_fck",          &debugss_fck,   CK_AM33XX),
1772         CLK(NULL,       "elm_fck",              &elm_fck,       CK_AM33XX),
1773         CLK(NULL,       "emif_fck",             &emif_fck,      CK_AM33XX),
1774         CLK(NULL,       "emif_fw_fck",          &emif_fw_fck,   CK_AM33XX),
1775         CLK(NULL,       "epwmss0_fck",          &epwmss0_fck,   CK_AM33XX),
1776         CLK(NULL,       "epwmss1_fck",          &epwmss1_fck,   CK_AM33XX),
1777         CLK(NULL,       "epwmss2_fck",          &epwmss2_fck,   CK_AM33XX),
1778         CLK(NULL,       "gpio0_fck",            &gpio0_fck,     CK_AM33XX),
1779         CLK(NULL,       "gpio1_fck",            &gpio1_fck,     CK_AM33XX),
1780         CLK(NULL,       "gpio2_fck",            &gpio2_fck,     CK_AM33XX),
1781         CLK(NULL,       "gpio3_fck",            &gpio3_fck,     CK_AM33XX),
1782         CLK(NULL,       "gpmc_fck",             &gpmc_fck,      CK_AM33XX),
1783         CLK("omap_i2c.1",       "fck",          &i2c1_fck,      CK_AM33XX),
1784         CLK("omap_i2c.2",       "fck",          &i2c2_fck,      CK_AM33XX),
1785         CLK("omap_i2c.3",       "fck",          &i2c3_fck,      CK_AM33XX),
1786         CLK(NULL,       "icss_fck",             &icss_fck,      CK_AM33XX),
1787         CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
1788         CLK(NULL,       "l3_instr_fck",         &l3_instr_fck,  CK_AM33XX),
1789         CLK(NULL,       "l3_main_fck",          &l3_main_fck,   CK_AM33XX),
1790         CLK(NULL,       "l4_hs_fck",            &l4_hs_fck,     CK_AM33XX),
1791         CLK(NULL,       "l4fw_fck",             &l4fw_fck,      CK_AM33XX),
1792         CLK(NULL,       "l4ls_fck",             &l4ls_fck,      CK_AM33XX),
1793         CLK(NULL,       "l4wkup_fck",           &l4wkup_fck,    CK_AM33XX),
1794         CLK("da8xx_lcdc.0",     NULL,           &lcdc_fck,      CK_AM33XX),
1795         CLK(NULL,       "mailbox0_fck",         &mailbox0_fck,  CK_AM33XX),
1796         CLK(NULL,       "mcasp1_ick",           &mcasp0_ick,    CK_AM33XX),
1797         CLK(NULL,       "mcasp2_ick",           &mcasp1_ick,    CK_AM33XX),
1798         CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
1799         CLK("davinci-mcasp.1",  NULL,           &mcasp1_fck,    CK_AM33XX),
1800         CLK(NULL,       "mlb_fck",              &mlb_fck,       CK_AM33XX),
1801         CLK("omap_hsmmc.0",     "ick",          &mmc0_ick,      CK_AM33XX),
1802         CLK("omap_hsmmc.1",     "ick",          &mmc1_ick,      CK_AM33XX),
1803         CLK("omap_hsmmc.2",     "ick",          &mmc2_ick,      CK_AM33XX),
1804         CLK("omap_hsmmc.0",     "fck",          &mmc0_fck,      CK_AM33XX),
1805         CLK("omap_hsmmc.1",     "fck",          &mmc1_fck,      CK_AM33XX),
1806         CLK("omap_hsmmc.2",     "fck",          &mmc2_fck,      CK_AM33XX),
1807         CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
1808         CLK(NULL,       "mpu_ck",               &mpu_fck,       CK_AM33XX),
1809         CLK(NULL,       "mstr_exps_fck",        &mstr_exps_fck, CK_AM33XX),
1810         CLK(NULL,       "ocmcram_fck",          &ocmcram_fck,   CK_AM33XX),
1811         CLK(NULL,       "ocpwp_fck",            &ocpwp_fck,     CK_AM33XX),
1812         CLK(NULL,       "pka_fck",              &pka_fck,       CK_AM33XX),
1813         CLK(NULL,       "rng_fck",              &rng_fck,       CK_AM33XX),
1814         CLK(NULL,       "rtc_fck",              &rtc_fck,       CK_AM33XX),
1815         CLK(NULL,       "sha0_fck",             &sha0_fck,      CK_AM33XX),
1816         CLK(NULL,       "slv_exps_fck",         &slv_exps_fck,  CK_AM33XX),
1817         CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
1818         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
1819         CLK(NULL,       "spare0_fck",           &spare0_fck,    CK_AM33XX),
1820         CLK(NULL,       "spare1_fck",           &spare1_fck,    CK_AM33XX),
1821         CLK("omap2_mcspi.1",    "fck",          &spi0_fck,      CK_AM33XX),
1822         CLK("omap2_mcspi.2",    "fck",          &spi1_fck,      CK_AM33XX),
1823         CLK("omap2_mcspi.1",    "ick",          &spi0_ick,      CK_AM33XX),
1824         CLK("omap2_mcspi.2",    "ick",          &spi1_ick,      CK_AM33XX),
1825         CLK(NULL,       "spinlock_fck",         &spinlock_fck,  CK_AM33XX),
1826         CLK(NULL,       "timer0_fck",           &timer0_fck,    CK_AM33XX),
1827         CLK(NULL,       "gpt1_fck",             &timer1_fck,    CK_AM33XX),
1828         CLK(NULL,       "gpt2_fck",             &timer2_fck,    CK_AM33XX),
1829         CLK(NULL,       "gpt3_fck",             &timer3_fck,    CK_AM33XX),
1830         CLK(NULL,       "gpt4_fck",             &timer4_fck,    CK_AM33XX),
1831         CLK(NULL,       "gpt5_fck",             &timer5_fck,    CK_AM33XX),
1832         CLK(NULL,       "gpt6_fck",             &timer6_fck,    CK_AM33XX),
1833         CLK(NULL,       "gpt7_fck",             &timer7_fck,    CK_AM33XX),
1834         CLK(NULL,       "lcdc_ick_l3_clk",      &lcdc_l3ick,    CK_AM33XX),
1835         CLK(NULL,       "lcdc_ick_l4_clk",      &lcdc_l4ick,    CK_AM33XX),
1836         CLK(NULL,       "tpcc_ick",             &tpcc_ick,      CK_AM33XX),
1837         CLK(NULL,       "tptc0_ick",            &tptc0_ick,     CK_AM33XX),
1838         CLK(NULL,       "tptc1_ick",            &tptc1_ick,     CK_AM33XX),
1839         CLK(NULL,       "tptc2_ick",            &tptc2_ick,     CK_AM33XX),
1840         CLK(NULL,       "uart1_fck",            &uart1_fck,     CK_AM33XX),
1841         CLK(NULL,       "uart2_fck",            &uart2_fck,     CK_AM33XX),
1842         CLK(NULL,       "uart3_fck",            &uart3_fck,     CK_AM33XX),
1843         CLK(NULL,       "uart4_fck",            &uart4_fck,     CK_AM33XX),
1844         CLK(NULL,       "uart5_fck",            &uart5_fck,     CK_AM33XX),
1845         CLK(NULL,       "uart6_fck",            &uart6_fck,     CK_AM33XX),
1846         CLK(NULL,       "uart1_ick",            &uart1_ick,     CK_AM33XX),
1847         CLK(NULL,       "uart2_ick",            &uart2_ick,     CK_AM33XX),
1848         CLK(NULL,       "uart3_ick",            &uart3_ick,     CK_AM33XX),
1849         CLK(NULL,       "uart4_ick",            &uart4_ick,     CK_AM33XX),
1850         CLK(NULL,       "uart5_ick",            &uart5_ick,     CK_AM33XX),
1851         CLK(NULL,       "uart6_ick",            &uart6_ick,     CK_AM33XX),
1852         CLK(NULL,       "usbotg_ick",           &usbotg_ick,    CK_AM33XX),
1853         CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
1854         CLK(NULL,       "wd_timer1_fck",        &wd_timer1_fck, CK_AM33XX),
1855         CLK(NULL,       "wdt0_fck",             &wdt0_fck,      CK_AM33XX),
1856         CLK(NULL,       "wkup_m3_fck",          &wkup_m3_fck,   CK_AM33XX),
1857         CLK(NULL,       "dpll_per_ck",          &dpll_per_ck,   CK_AM33XX),
1858         CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck,        CK_AM33XX),
1859         CLK(NULL,       "i2c_clk",              &i2c_clk,               CK_AM33XX),
1860         CLK(NULL,       "clk_div_24_ck",        &clk_div_24_ck,         CK_AM33XX),
1861         CLK(NULL,       "dpll_core_ck",         &dpll_core_ck,          CK_AM33XX),
1862         CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck,       CK_AM33XX),
1863         CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck,       CK_AM33XX),
1864         CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck,         CK_AM33XX),
1865         CLK(NULL,       "core_100m_ck",         &core_100m_ck,          CK_AM33XX),
1866         CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
1867         CLK(NULL,       "cpsw_250m_clkdiv_ck",  &cpsw_250m_clkdiv_ck,   CK_AM33XX),
1868         CLK(NULL,       "cpsw_125mhz_ocp_ck",   &cpsw_125mhz_ocp_ck,    CK_AM33XX),
1869         CLK(NULL,       "cpsw_50m_clkdiv_ck",   &cpsw_50m_clkdiv_ck,    CK_AM33XX),
1870         CLK(NULL,       "cpsw_5m_clkdiv_ck",    &cpsw_5m_clkdiv_ck,     CK_AM33XX),
1871         CLK(NULL,       "cpts_rft_clkmux_ck",   &cpts_rft_clkmux_ck,    CK_AM33XX),
1872         CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,           CK_AM33XX),
1873         CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
1874         CLK(NULL,       "ddr_pll_div_clk",      &ddr_pll_div_clk,       CK_AM33XX),
1875         CLK(NULL,       "div_l4_rtc_gclk_ck",   &div_l4_rtc_gclk_ck,    CK_AM33XX),
1876         CLK(NULL,       "div_l4_wkup_gclk_ck",  &div_l4_wkup_gclk_ck,   CK_AM33XX),
1877         CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck,          CK_AM33XX),
1878         CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck,       CK_AM33XX),
1879         CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,           CK_AM33XX),
1880         CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
1881         CLK(NULL,       "dpll_per_clkdcoldo_ck", &dpll_per_clkdcoldo_ck,        CK_AM33XX),
1882         CLK(NULL,       "gpio_dbclk_mux_ck",    &gpio_dbclk_mux_ck,     CK_AM33XX),
1883         CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk,           CK_AM33XX),
1884         CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk,           CK_AM33XX),
1885         CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk,           CK_AM33XX),
1886         CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk,           CK_AM33XX),
1887         CLK(NULL,       "icss_ocp_clk_mux_ck",  &icss_ocp_clk_mux_ck,   CK_AM33XX),
1888         CLK(NULL,       "lcd_clk_mux_ck",       &lcd_clk_mux_ck,        CK_AM33XX),
1889         CLK(NULL,       "mmc_clk",              &mmc_clk,               CK_AM33XX),
1890         CLK(NULL,       "sgx_clksel_ck",        &sgx_clksel_ck,         CK_AM33XX),
1891         CLK(NULL,       "sgx_ck",               &sgx_ck,                CK_AM33XX),
1892         CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck,      CK_AM33XX),
1893         CLK(NULL,       "clkout2_ck",           &clkout2_ck,            CK_AM33XX),
1894         CLK(NULL,       "timer0_clkmux_ck",     &timer0_clkmux_ck,      CK_AM33XX),
1895         CLK(NULL,       "gpt0_ick",             &timer0_ick,            CK_AM33XX),
1896         CLK(NULL,       "gpt1_ick",             &timer1_ick,            CK_AM33XX),
1897         CLK(NULL,       "gpt2_ick",             &timer2_ick,            CK_AM33XX),
1898         CLK(NULL,       "gpt3_ick",             &timer3_ick,            CK_AM33XX),
1899         CLK(NULL,       "gpt4_ick",             &timer4_ick,            CK_AM33XX),
1900         CLK(NULL,       "gpt5_ick",             &timer5_ick,            CK_AM33XX),
1901         CLK(NULL,       "gpt6_ick",             &timer6_ick,            CK_AM33XX),
1902         CLK(NULL,       "gpt7_ick",             &timer7_ick,            CK_AM33XX),
1903         CLK(NULL,       "vtp_clk_div_ck",       &vtp_clk_div_ck,        CK_AM33XX),
1904         CLK(NULL,       "wdt0_clkmux_ck",       &wdt0_clkmux_ck,        CK_AM33XX),
1905 };
1907 int __init am33xx_clk_init(void)
1909         struct omap_clk *c;
1910         u32 cpu_clkflg;
1912         if (cpu_is_am33xx()) {
1913                 cpu_mask = RATE_IN_AM33XX;
1914                 cpu_clkflg = CK_AM33XX;
1915         }
1917         clk_init(&omap2_clk_functions);
1919         for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
1920                 clk_preinit(c->lk.clk);
1922         for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
1923                 if (c->cpu & cpu_clkflg) {
1924                         clkdev_add(&c->lk);
1925                         clk_register(c->lk.clk);
1926                         omap2_init_clk_clkdm(c->lk.clk);
1927                 }
1929         recalculate_root_clocks();
1931         /*
1932          * Only enable those clocks we will need, let the drivers
1933          * enable other clocks as necessary
1934          */
1935         clk_enable_init_clocks();
1937         return 0;