1 /*
2 * AM33XX Clock Domain data.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 #include <linux/kernel.h>
17 #include <linux/io.h>
19 #include "clockdomain.h"
20 #include "cm.h"
21 #include "cm33xx.h"
22 #include "cm-regbits-33xx.h"
24 static struct clockdomain l4ls_am33xx_clkdm = {
25 .name = "l4ls_clkdm",
26 .pwrdm = { .name = "per_pwrdm" },
27 .cm_inst = AM33XX_CM_PER_MOD,
28 .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
29 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
30 .flags = CLKDM_CAN_SWSUP,
31 };
33 static struct clockdomain l3s_am33xx_clkdm = {
34 .name = "l3s_clkdm",
35 .pwrdm = { .name = "per_pwrdm" },
36 .cm_inst = AM33XX_CM_PER_MOD,
37 .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
38 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
39 .flags = CLKDM_CAN_SWSUP,
40 };
42 static struct clockdomain l4fw_am33xx_clkdm = {
43 .name = "l4fw_clkdm",
44 .pwrdm = { .name = "per_pwrdm" },
45 .cm_inst = AM33XX_CM_PER_MOD,
46 .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
47 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
48 .flags = CLKDM_CAN_SWSUP,
49 };
51 static struct clockdomain l3_am33xx_clkdm = {
52 .name = "l3_clkdm",
53 .pwrdm = { .name = "per_pwrdm" },
54 .cm_inst = AM33XX_CM_PER_MOD,
55 .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
56 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
57 .flags = CLKDM_CAN_SWSUP,
58 };
60 static struct clockdomain l4hs_am33xx_clkdm = {
61 .name = "l4hs_clkdm",
62 .pwrdm = { .name = "per_pwrdm" },
63 .cm_inst = AM33XX_CM_PER_MOD,
64 .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
65 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
66 .flags = CLKDM_CAN_SWSUP,
67 };
69 static struct clockdomain ocpwp_l3_am33xx_clkdm = {
70 .name = "ocpwp_l3_clkdm",
71 .pwrdm = { .name = "per_pwrdm" },
72 .cm_inst = AM33XX_CM_PER_MOD,
73 .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
74 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
75 .flags = CLKDM_CAN_SWSUP,
76 };
78 static struct clockdomain icss_ocp_am33xx_clkdm = {
79 .name = "icss_ocp_clkdm",
80 .pwrdm = { .name = "per_pwrdm" },
81 .cm_inst = AM33XX_CM_PER_MOD,
82 .clkdm_offs = AM33XX_CM_PER_ICSS_CLKSTCTRL_OFFSET,
83 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
84 .flags = CLKDM_CAN_SWSUP,
85 };
87 static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
88 .name = "cpsw_125mhz_clkdm",
89 .pwrdm = { .name = "per_pwrdm" },
90 .cm_inst = AM33XX_CM_PER_MOD,
91 .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
92 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
93 .flags = CLKDM_CAN_SWSUP,
94 };
96 static struct clockdomain lcdc_am33xx_clkdm = {
97 .name = "lcdc_clkdm",
98 .pwrdm = { .name = "per_pwrdm" },
99 .cm_inst = AM33XX_CM_PER_MOD,
100 .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
101 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
102 .flags = CLKDM_CAN_SWSUP,
103 };
105 static struct clockdomain clk_24mhz_am33xx_clkdm = {
106 .name = "clk_24mhz_clkdm",
107 .pwrdm = { .name = "per_pwrdm" },
108 .cm_inst = AM33XX_CM_PER_MOD,
109 .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
110 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
111 .flags = CLKDM_CAN_SWSUP,
112 };
114 static struct clockdomain l4_wkup_am33xx_clkdm = {
115 .name = "l4_wkup_clkdm",
116 .pwrdm = { .name = "wkup_pwrdm" },
117 .cm_inst = AM33XX_CM_WKUP_MOD,
118 .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
119 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
120 .flags = CLKDM_CAN_SWSUP,
121 };
123 static struct clockdomain l3_aon_am33xx_clkdm = {
124 .name = "l3_aon_clkdm",
125 .pwrdm = { .name = "wkup_pwrdm" },
126 .cm_inst = AM33XX_CM_WKUP_MOD,
127 .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
128 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
129 .flags = CLKDM_CAN_SWSUP,
130 };
132 static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
133 .name = "l4_wkup_aon_clkdm",
134 .pwrdm = { .name = "wkup_pwrdm" },
135 .cm_inst = AM33XX_CM_WKUP_MOD,
136 .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
137 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
138 .flags = CLKDM_CAN_SWSUP,
139 };
141 static struct clockdomain mpu_am33xx_clkdm = {
142 .name = "mpu_clkdm",
143 .pwrdm = { .name = "mpu_pwrdm" },
144 .cm_inst = AM33XX_CM_MPU_MOD,
145 .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
146 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
147 .flags = CLKDM_CAN_SWSUP,
148 };
150 static struct clockdomain l4_rtc_am33xx_clkdm = {
151 .name = "l4_rtc_clkdm",
152 .pwrdm = { .name = "rtc_pwrdm" },
153 .cm_inst = AM33XX_CM_RTC_MOD,
154 .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
155 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
156 .flags = CLKDM_CAN_SWSUP,
157 };
159 static struct clockdomain gfx_l3_am33xx_clkdm = {
160 .name = "gfx_l3_clkdm",
161 .pwrdm = { .name = "gfx_pwrdm" },
162 .cm_inst = AM33XX_CM_GFX_MOD,
163 .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
164 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
165 .flags = CLKDM_CAN_SWSUP,
166 };
168 static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
169 .name = "gfx_l4ls_gfx_clkdm",
170 .pwrdm = { .name = "gfx_pwrdm" },
171 .cm_inst = AM33XX_CM_GFX_MOD,
172 .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
173 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
174 .flags = CLKDM_CAN_SWSUP,
175 };
177 static struct clockdomain l4_cefuse_am33xx_clkdm = {
178 .name = "l4_cefuse_clkdm",
179 .pwrdm = { .name = "cefuse_pwrdm" },
180 .cm_inst = AM33XX_CM_CEFUSE_MOD,
181 .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
182 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
183 .flags = CLKDM_CAN_SWSUP,
184 };
186 static struct clockdomain wkup_usb_am33xx_clkdm = {
187 .name = "wkup_usb_clkdm",
188 .pwrdm = { .name = "wkup_pwrdm" },
189 .cm_inst = AM33XX_CM_WKUP_MOD,
190 .clkdm_offs = AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET,
191 .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
192 .flags = CLKDM_CAN_SWSUP,
193 };
195 static struct clockdomain *clockdomains_am33xx[] __initdata = {
196 &l4ls_am33xx_clkdm,
197 &l3s_am33xx_clkdm,
198 &l4fw_am33xx_clkdm,
199 &l3_am33xx_clkdm,
200 &l4hs_am33xx_clkdm,
201 &ocpwp_l3_am33xx_clkdm,
202 &icss_ocp_am33xx_clkdm,
203 &cpsw_125mhz_am33xx_clkdm,
204 &lcdc_am33xx_clkdm,
205 &clk_24mhz_am33xx_clkdm,
206 &l4_wkup_am33xx_clkdm,
207 &l3_aon_am33xx_clkdm,
208 &l4_wkup_aon_am33xx_clkdm,
209 &mpu_am33xx_clkdm,
210 &l4_rtc_am33xx_clkdm,
211 &gfx_l3_am33xx_clkdm,
212 &gfx_l4ls_gfx_am33xx_clkdm,
213 &l4_cefuse_am33xx_clkdm,
214 &wkup_usb_am33xx_clkdm,
215 NULL,
216 };
218 void __init am33xx_clockdomains_init(void)
219 {
220 clkdm_register_platform_funcs(&omap3_clkdm_operations);
221 clkdm_register_clkdms(clockdomains_am33xx);
222 clkdm_complete_init();
223 }