1 /*
2 * AM33XX Power Management register bits
3 *
4 * This file is automatically generated from the AM33XX hardware databases.
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
19 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
22 /*
23 * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
24 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
25 */
26 #define AM33XX_AUTO_DPLL_MODE_SHIFT 0
27 #define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
29 /* Used by CM_WKUP_CLKSTCTRL */
30 #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
31 #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
33 /* Used by CM_PER_L4LS_CLKSTCTRL */
34 #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
35 #define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
37 /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
38 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
39 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
41 /* Used by CM_PER_CPSW_CLKSTCTRL */
42 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
43 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
45 /* Used by CM_PER_L4HS_CLKSTCTRL */
46 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
47 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
49 /* Used by CM_PER_L4HS_CLKSTCTRL */
50 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
51 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
53 /* Used by CM_PER_L4HS_CLKSTCTRL */
54 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
55 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
57 /* Used by CM_PER_L3_CLKSTCTRL */
58 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
59 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
61 /* Used by CM_CEFUSE_CLKSTCTRL */
62 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
63 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
65 /* Used by CM_L3_AON_CLKSTCTRL */
66 #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
67 #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
69 /* Used by CM_L3_AON_CLKSTCTRL */
70 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
71 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
73 /* Used by CM_PER_L3_CLKSTCTRL */
74 #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
75 #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
77 /* Used by CM_GFX_L3_CLKSTCTRL */
78 #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
79 #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
81 /* Used by CM_GFX_L3_CLKSTCTRL */
82 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
83 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
85 /* Used by CM_WKUP_CLKSTCTRL */
86 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
87 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
89 /* Used by CM_PER_L4LS_CLKSTCTRL */
90 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
91 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
93 /* Used by CM_PER_L4LS_CLKSTCTRL */
94 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
95 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
97 /* Used by CM_PER_L4LS_CLKSTCTRL */
98 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
99 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
101 /* Used by CM_PER_L4LS_CLKSTCTRL */
102 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
103 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
105 /* Used by CM_PER_L4LS_CLKSTCTRL */
106 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
107 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
109 /* Used by CM_PER_L4LS_CLKSTCTRL */
110 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
111 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
113 /* Used by CM_WKUP_CLKSTCTRL */
114 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
115 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
117 /* Used by CM_PER_L4LS_CLKSTCTRL */
118 #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
119 #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
121 /* Used by CM_PER_ICSS_CLKSTCTRL */
122 #define AM33XX_CLKACTIVITY_ICSS_IEP_GCLK_SHIFT 5
123 #define AM33XX_CLKACTIVITY_ICSS_IEP_GCLK_MASK (1 << 5)
125 /* Used by CM_PER_ICSS_CLKSTCTRL */
126 #define AM33XX_CLKACTIVITY_ICSS_OCP_GCLK_SHIFT 4
127 #define AM33XX_CLKACTIVITY_ICSS_OCP_GCLK_MASK (1 << 4)
129 /* Used by CM_PER_ICSS_CLKSTCTRL */
130 #define AM33XX_CLKACTIVITY_ICSS_UART_GCLK_SHIFT 6
131 #define AM33XX_CLKACTIVITY_ICSS_UART_GCLK_MASK (1 << 6)
133 /* Used by CM_PER_L3S_CLKSTCTRL */
134 #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
135 #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
137 /* Used by CM_L3_AON_CLKSTCTRL */
138 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
139 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
141 /* Used by CM_PER_L3_CLKSTCTRL */
142 #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
143 #define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
145 /* Used by CM_PER_L4FW_CLKSTCTRL */
146 #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
147 #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
149 /* Used by CM_PER_L4HS_CLKSTCTRL */
150 #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
151 #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
153 /* Used by CM_PER_L4LS_CLKSTCTRL */
154 #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
155 #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
157 /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
158 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
159 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
161 /* Used by CM_CEFUSE_CLKSTCTRL */
162 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
163 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
165 /* Used by CM_RTC_CLKSTCTRL */
166 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
167 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
169 /* Used by CM_L4_WKUP_AON_CLKSTCTRL */
170 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
171 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
173 /* Used by CM_WKUP_CLKSTCTRL */
174 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
175 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
177 /* Used by CM_PER_L4LS_CLKSTCTRL */
178 #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
179 #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
181 /* Used by CM_PER_LCDC_CLKSTCTRL */
182 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
183 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
185 /* Used by CM_PER_LCDC_CLKSTCTRL */
186 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
187 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
189 /* Used by CM_PER_L3_CLKSTCTRL */
190 #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
191 #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
193 /* Used by CM_PER_L3_CLKSTCTRL */
194 #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
195 #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
197 /* Used by CM_MPU_CLKSTCTRL */
198 #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
199 #define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
201 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
202 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
203 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
205 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
206 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
207 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
209 /* Used by CM_RTC_CLKSTCTRL */
210 #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
211 #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
213 /* Used by CM_PER_L4LS_CLKSTCTRL */
214 #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
215 #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
217 /* Used by CM_WKUP_CLKSTCTRL */
218 #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
219 #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
221 /* Used by CM_WKUP_CLKSTCTRL */
222 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
223 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
225 /* Used by CM_WKUP_CLKSTCTRL */
226 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
227 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
229 /* Used by CM_PER_L4LS_CLKSTCTRL */
230 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
231 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
233 /* Used by CM_PER_L4LS_CLKSTCTRL */
234 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
235 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
237 /* Used by CM_PER_L4LS_CLKSTCTRL */
238 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
239 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
241 /* Used by CM_PER_L4LS_CLKSTCTRL */
242 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
243 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
245 /* Used by CM_PER_L4LS_CLKSTCTRL */
246 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
247 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
249 /* Used by CM_PER_L4LS_CLKSTCTRL */
250 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
251 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
253 /* Used by CM_WKUP_CLKSTCTRL */
254 #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
255 #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
257 /* Used by CM_PER_L4LS_CLKSTCTRL */
258 #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
259 #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
261 /* Used by CM_WKUP_CLKSTCTRL */
262 #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
263 #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
265 /* Used by CM_WKUP_CLKSTCTRL */
266 #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
267 #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
269 /* Used by CLKSEL_GFX_FCLK */
270 #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
271 #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
273 /* Used by CM_CLKOUT_CTRL */
274 #define AM33XX_CLKOUT2DIV_SHIFT 3
275 #define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)
277 /* Used by CM_CLKOUT_CTRL */
278 #define AM33XX_CLKOUT2EN_SHIFT 7
279 #define AM33XX_CLKOUT2EN_MASK (1 << 7)
281 /* Used by CM_CLKOUT_CTRL */
282 #define AM33XX_CLKOUT2SOURCE_SHIFT 0
283 #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
285 /*
286 * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
287 * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
288 * CLKSEL_TIMER7_CLK
289 */
290 #define AM33XX_CLKSEL_SHIFT 0
291 #define AM33XX_CLKSEL_MASK (0x01 << 0)
293 /*
294 * Renamed from CLKSEL Used by CLKSEL_ICSS_OCP_CLK, CLKSEL_WDT1_CLK,
295 * CM_CPTS_RFT_CLKSEL
296 */
297 #define AM33XX_CLKSEL_0_0_SHIFT 0
298 #define AM33XX_CLKSEL_0_0_MASK (1 << 0)
300 #define AM33XX_CLKSEL_0_1_SHIFT 0
301 #define AM33XX_CLKSEL_0_1_MASK (3 << 0)
303 /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
304 #define AM33XX_CLKSEL_0_2_SHIFT 0
305 #define AM33XX_CLKSEL_0_2_MASK (7 << 0)
307 /* Used by CLKSEL_GFX_FCLK */
308 #define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
309 #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
311 /*
312 * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
313 * CM_PER_CPSW_CLKSTCTRL, CM_PER_ICSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
314 * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
315 * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
316 * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
317 * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
318 */
319 #define AM33XX_CLKTRCTRL_SHIFT 0
320 #define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
322 /*
323 * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
324 * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
325 * CM_SSC_DELTAMSTEP_DPLL_PER
326 */
327 #define AM33XX_DELTAMSTEP_SHIFT 0
328 #define AM33XX_DELTAMSTEP_MASK (0x19 << 0)
330 /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
331 #define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
332 #define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
334 /* Used by CM_CLKDCOLDO_DPLL_PER */
335 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
336 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
338 /* Used by CM_CLKDCOLDO_DPLL_PER */
339 #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
340 #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
342 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
343 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
344 #define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
346 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
347 #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
348 #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0)
350 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
351 #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
352 #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
354 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
355 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
356 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
358 /*
359 * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
360 * CM_DIV_M2_DPLL_PER
361 */
362 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
363 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
365 /*
366 * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
367 * CM_CLKSEL_DPLL_MPU
368 */
369 #define AM33XX_DPLL_DIV_SHIFT 0
370 #define AM33XX_DPLL_DIV_MASK (0x7f << 0)
372 #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
374 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
375 #define AM33XX_DPLL_DIV_0_7_SHIFT 0
376 #define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0)
378 /*
379 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
380 * CM_CLKMODE_DPLL_MPU
381 */
382 #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
383 #define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
385 /*
386 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
387 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
388 */
389 #define AM33XX_DPLL_EN_SHIFT 0
390 #define AM33XX_DPLL_EN_MASK (0x7 << 0)
392 /*
393 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
394 * CM_CLKMODE_DPLL_MPU
395 */
396 #define AM33XX_DPLL_LPMODE_EN_SHIFT 10
397 #define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
399 /*
400 * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
401 * CM_CLKSEL_DPLL_MPU
402 */
403 #define AM33XX_DPLL_MULT_SHIFT 8
404 #define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
406 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
407 #define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
408 #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
410 /*
411 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
412 * CM_CLKMODE_DPLL_MPU
413 */
414 #define AM33XX_DPLL_REGM4XEN_SHIFT 11
415 #define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
417 /* Used by CM_CLKSEL_DPLL_PERIPH */
418 #define AM33XX_DPLL_SD_DIV_SHIFT 24
419 #define AM33XX_DPLL_SD_DIV_MASK (24, 31)
421 /*
422 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
423 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
424 */
425 #define AM33XX_DPLL_SSC_ACK_SHIFT 13
426 #define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
428 /*
429 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
430 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
431 */
432 #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
433 #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
435 /*
436 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
437 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
438 */
439 #define AM33XX_DPLL_SSC_EN_SHIFT 12
440 #define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
442 /* Used by CM_DIV_M4_DPLL_CORE */
443 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
444 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
446 /* Used by CM_DIV_M4_DPLL_CORE */
447 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
448 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
450 /* Used by CM_DIV_M4_DPLL_CORE */
451 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
452 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
454 /* Used by CM_DIV_M4_DPLL_CORE */
455 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
456 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
458 /* Used by CM_DIV_M5_DPLL_CORE */
459 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
460 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
462 /* Used by CM_DIV_M5_DPLL_CORE */
463 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
464 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
466 /* Used by CM_DIV_M5_DPLL_CORE */
467 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
468 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
470 /* Used by CM_DIV_M5_DPLL_CORE */
471 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
472 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
474 /* Used by CM_DIV_M6_DPLL_CORE */
475 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
476 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0)
478 /* Used by CM_DIV_M6_DPLL_CORE */
479 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
480 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
482 /* Used by CM_DIV_M6_DPLL_CORE */
483 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
484 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
486 /* Used by CM_DIV_M6_DPLL_CORE */
487 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
488 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
490 /*
491 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
492 * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
493 * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
494 * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
495 * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
496 * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
497 * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
498 * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
499 * CM_PER_ICSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
500 * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
501 * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
502 * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
503 * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
504 * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
505 * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
506 * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
507 * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
508 * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
509 * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
510 * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
511 * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
512 * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
513 * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
514 * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
515 * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
516 * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
517 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
518 * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
519 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
520 * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
521 * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
522 */
523 #define AM33XX_IDLEST_SHIFT 16
524 #define AM33XX_IDLEST_MASK (0x3 << 16)
525 #define AM33XX_IDLEST_VAL 0x3
527 /* Used by CM_MAC_CLKSEL */
528 #define AM33XX_MII_CLK_SEL_SHIFT 2
529 #define AM33XX_MII_CLK_SEL_MASK (1 << 2)
531 /*
532 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
533 * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
534 * CM_SSC_MODFREQDIV_DPLL_PER
535 */
536 #define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
537 #define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8)
539 /*
540 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
541 * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
542 * CM_SSC_MODFREQDIV_DPLL_PER
543 */
544 #define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
545 #define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0)
547 /*
548 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
549 * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
550 * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
551 * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
552 * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
553 * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
554 * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
555 * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
556 * CM_PER_ICSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
557 * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
558 * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
559 * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
560 * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
561 * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
562 * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
563 * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
564 * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
565 * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
566 * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
567 * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
568 * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
569 * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
570 * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
571 * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
572 * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
573 * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
574 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
575 * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
576 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
577 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
578 * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
579 * CM_CEFUSE_CEFUSE_CLKCTRL
580 */
581 #define AM33XX_MODULEMODE_SHIFT 0
582 #define AM33XX_MODULEMODE_MASK (0x3 << 0)
584 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
585 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
586 #define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
588 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
589 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
590 #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
592 /* Used by CM_WKUP_GPIO0_CLKCTRL */
593 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
594 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
596 /* Used by CM_PER_GPIO1_CLKCTRL */
597 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
598 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
600 /* Used by CM_PER_GPIO2_CLKCTRL */
601 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
602 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
604 /* Used by CM_PER_GPIO3_CLKCTRL */
605 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
606 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
608 /* Used by CM_PER_GPIO4_CLKCTRL */
609 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
610 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
612 /* Used by CM_PER_GPIO5_CLKCTRL */
613 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
614 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
616 /* Used by CM_PER_GPIO6_CLKCTRL */
617 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
618 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
620 /*
621 * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_ICSS_CLKCTRL,
622 * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
623 * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
624 * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
625 * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
626 * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
627 */
628 #define AM33XX_STBYST_SHIFT 18
629 #define AM33XX_STBYST_MASK (1 << 18)
631 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
632 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
633 #define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27)
635 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
636 #define AM33XX_STM_PMD_CLKSEL_SHIFT 22
637 #define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22)
639 /*
640 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
641 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
642 */
643 #define AM33XX_ST_DPLL_CLK_SHIFT 0
644 #define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
646 /* Used by CM_CLKDCOLDO_DPLL_PER */
647 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
648 #define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
650 /*
651 * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
652 * CM_DIV_M2_DPLL_PER
653 */
654 #define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
655 #define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
657 /* Used by CM_DIV_M4_DPLL_CORE */
658 #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
659 #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
661 /* Used by CM_DIV_M5_DPLL_CORE */
662 #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
663 #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
665 /* Used by CM_DIV_M6_DPLL_CORE */
666 #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
667 #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
669 /*
670 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
671 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
672 */
673 #define AM33XX_ST_MN_BYPASS_SHIFT 8
674 #define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
676 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
677 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
678 #define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24)
680 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
681 #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
682 #define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20)
683 #endif