00ce6544322867a5e1036a4626631eb4fa796ccf
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / devices.c
1 /*
2  * linux/arch/arm/mach-omap2/devices.c
3  *
4  * OMAP2 platform device setup/initialization
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 #include <linux/gpio.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
25 #include <mach/hardware.h>
26 #include <mach/irqs.h>
27 #include <asm/mach-types.h>
28 #include <asm/mach/map.h>
29 #include <asm/pmu.h>
31 #ifdef  CONFIG_OMAP3_EDMA
32 #include <mach/edma.h>
33 #endif
35 #include <plat/tc.h>
36 #include <plat/board.h>
37 #include <plat/mcbsp.h>
38 #include <plat/mmc.h>
39 #include <plat/dma.h>
40 #include <plat/omap_hwmod.h>
41 #include <plat/omap_device.h>
42 #include <plat/omap4-keypad.h>
44 /* LCD controller similar DA8xx */
45 #include <video/da8xx-fb.h>
47 #include "mux.h"
48 #include "control.h"
49 #include "devices.h"
51 #define L3_MODULES_MAX_LEN 12
52 #define L3_MODULES 3
54 void am33xx_cpsw_init(void);
56 static int __init omap3_l3_init(void)
57 {
58         int l;
59         struct omap_hwmod *oh;
60         struct platform_device *pdev;
61         char oh_name[L3_MODULES_MAX_LEN];
63         /*
64          * To avoid code running on other OMAPs in
65          * multi-omap builds
66          */
67         if (!(cpu_is_omap34xx()))
68                 return -ENODEV;
70         l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
72         oh = omap_hwmod_lookup(oh_name);
74         if (!oh)
75                 pr_err("could not look up %s\n", oh_name);
77         pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
78                                                            NULL, 0, 0);
80         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
82         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
83 }
84 postcore_initcall(omap3_l3_init);
86 static int __init omap4_l3_init(void)
87 {
88         int l, i;
89         struct omap_hwmod *oh[3];
90         struct platform_device *pdev;
91         char oh_name[L3_MODULES_MAX_LEN];
93         /* If dtb is there, the devices will be created dynamically */
94         if (of_have_populated_dt())
95                 return -ENODEV;
97         /*
98          * To avoid code running on other OMAPs in
99          * multi-omap builds
100          */
101         if (!(cpu_is_omap44xx()))
102                 return -ENODEV;
104         for (i = 0; i < L3_MODULES; i++) {
105                 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
107                 oh[i] = omap_hwmod_lookup(oh_name);
108                 if (!(oh[i]))
109                         pr_err("could not look up %s\n", oh_name);
110         }
112         pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
113                                                      0, NULL, 0, 0);
115         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
117         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
119 postcore_initcall(omap4_l3_init);
121 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
123 static struct resource omap2cam_resources[] = {
124         {
125                 .start          = OMAP24XX_CAMERA_BASE,
126                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
127                 .flags          = IORESOURCE_MEM,
128         },
129         {
130                 .start          = INT_24XX_CAM_IRQ,
131                 .flags          = IORESOURCE_IRQ,
132         }
133 };
135 static struct platform_device omap2cam_device = {
136         .name           = "omap24xxcam",
137         .id             = -1,
138         .num_resources  = ARRAY_SIZE(omap2cam_resources),
139         .resource       = omap2cam_resources,
140 };
141 #endif
142 #define L4_PER_LCDC_PHYS        0x4830E000
144 static struct resource am33xx_lcdc_resources[] = {
145         [0] = { /* registers */
146                 .start  = L4_PER_LCDC_PHYS,
147                 .end    = L4_PER_LCDC_PHYS + SZ_4K - 1,
148                 .flags  = IORESOURCE_MEM,
149         },
150         [1] = { /* interrupt */
151                 .start  = AM33XX_IRQ_LCD,
152                 .end    = AM33XX_IRQ_LCD,
153                 .flags  = IORESOURCE_IRQ,
154         },
155 };
157 static struct platform_device am33xx_lcdc_device = {
158         .name           = "da8xx_lcdc",
159         .id             = 0,
160         .num_resources  = ARRAY_SIZE(am33xx_lcdc_resources),
161         .resource       = am33xx_lcdc_resources,
162 };
164 void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
166         int ret;
168         am33xx_lcdc_device.dev.platform_data = pdata;
170         ret = platform_device_register(&am33xx_lcdc_device);
171         if (ret)
172                 pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n",
173                                 ret);
177 static struct resource omap3isp_resources[] = {
178         {
179                 .start          = OMAP3430_ISP_BASE,
180                 .end            = OMAP3430_ISP_END,
181                 .flags          = IORESOURCE_MEM,
182         },
183         {
184                 .start          = OMAP3430_ISP_CCP2_BASE,
185                 .end            = OMAP3430_ISP_CCP2_END,
186                 .flags          = IORESOURCE_MEM,
187         },
188         {
189                 .start          = OMAP3430_ISP_CCDC_BASE,
190                 .end            = OMAP3430_ISP_CCDC_END,
191                 .flags          = IORESOURCE_MEM,
192         },
193         {
194                 .start          = OMAP3430_ISP_HIST_BASE,
195                 .end            = OMAP3430_ISP_HIST_END,
196                 .flags          = IORESOURCE_MEM,
197         },
198         {
199                 .start          = OMAP3430_ISP_H3A_BASE,
200                 .end            = OMAP3430_ISP_H3A_END,
201                 .flags          = IORESOURCE_MEM,
202         },
203         {
204                 .start          = OMAP3430_ISP_PREV_BASE,
205                 .end            = OMAP3430_ISP_PREV_END,
206                 .flags          = IORESOURCE_MEM,
207         },
208         {
209                 .start          = OMAP3430_ISP_RESZ_BASE,
210                 .end            = OMAP3430_ISP_RESZ_END,
211                 .flags          = IORESOURCE_MEM,
212         },
213         {
214                 .start          = OMAP3430_ISP_SBL_BASE,
215                 .end            = OMAP3430_ISP_SBL_END,
216                 .flags          = IORESOURCE_MEM,
217         },
218         {
219                 .start          = OMAP3430_ISP_CSI2A_REGS1_BASE,
220                 .end            = OMAP3430_ISP_CSI2A_REGS1_END,
221                 .flags          = IORESOURCE_MEM,
222         },
223         {
224                 .start          = OMAP3430_ISP_CSIPHY2_BASE,
225                 .end            = OMAP3430_ISP_CSIPHY2_END,
226                 .flags          = IORESOURCE_MEM,
227         },
228         {
229                 .start          = OMAP3630_ISP_CSI2A_REGS2_BASE,
230                 .end            = OMAP3630_ISP_CSI2A_REGS2_END,
231                 .flags          = IORESOURCE_MEM,
232         },
233         {
234                 .start          = OMAP3630_ISP_CSI2C_REGS1_BASE,
235                 .end            = OMAP3630_ISP_CSI2C_REGS1_END,
236                 .flags          = IORESOURCE_MEM,
237         },
238         {
239                 .start          = OMAP3630_ISP_CSIPHY1_BASE,
240                 .end            = OMAP3630_ISP_CSIPHY1_END,
241                 .flags          = IORESOURCE_MEM,
242         },
243         {
244                 .start          = OMAP3630_ISP_CSI2C_REGS2_BASE,
245                 .end            = OMAP3630_ISP_CSI2C_REGS2_END,
246                 .flags          = IORESOURCE_MEM,
247         },
248         {
249                 .start          = INT_34XX_CAM_IRQ,
250                 .flags          = IORESOURCE_IRQ,
251         }
252 };
254 static struct platform_device omap3isp_device = {
255         .name           = "omap3isp",
256         .id             = -1,
257         .num_resources  = ARRAY_SIZE(omap3isp_resources),
258         .resource       = omap3isp_resources,
259 };
261 int omap3_init_camera(struct isp_platform_data *pdata)
263         omap3isp_device.dev.platform_data = pdata;
264         return platform_device_register(&omap3isp_device);
267 static inline void omap_init_camera(void)
269 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
270         if (cpu_is_omap24xx())
271                 platform_device_register(&omap2cam_device);
272 #endif
275 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
276                         *sdp4430_keypad_data, struct omap_board_data *bdata)
278         struct platform_device *pdev;
279         struct omap_hwmod *oh;
280         struct omap4_keypad_platform_data *keypad_data;
281         unsigned int id = -1;
282         char *oh_name = "kbd";
283         char *name = "omap4-keypad";
285         oh = omap_hwmod_lookup(oh_name);
286         if (!oh) {
287                 pr_err("Could not look up %s\n", oh_name);
288                 return -ENODEV;
289         }
291         keypad_data = sdp4430_keypad_data;
293         pdev = omap_device_build(name, id, oh, keypad_data,
294                         sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
296         if (IS_ERR(pdev)) {
297                 WARN(1, "Can't build omap_device for %s:%s.\n",
298                                                 name, oh->name);
299                 return PTR_ERR(pdev);
300         }
301         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
303         return 0;
306 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
307 static inline void omap_init_mbox(void)
309         struct omap_hwmod *oh;
310         struct platform_device *pdev;
312         oh = omap_hwmod_lookup("mailbox");
313         if (!oh) {
314                 pr_err("%s: unable to find hwmod\n", __func__);
315                 return;
316         }
318         pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
319         WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
320                                                 __func__, PTR_ERR(pdev));
322 #else
323 static inline void omap_init_mbox(void) { }
324 #endif /* CONFIG_OMAP_MBOX_FWK */
326 static inline void omap_init_sti(void) {}
328 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
330 static struct platform_device omap_pcm = {
331         .name   = "omap-pcm-audio",
332         .id     = -1,
333 };
335 /*
336  * OMAP2420 has 2 McBSP ports
337  * OMAP2430 has 5 McBSP ports
338  * OMAP3 has 5 McBSP ports
339  * OMAP4 has 4 McBSP ports
340  */
341 OMAP_MCBSP_PLATFORM_DEVICE(1);
342 OMAP_MCBSP_PLATFORM_DEVICE(2);
343 OMAP_MCBSP_PLATFORM_DEVICE(3);
344 OMAP_MCBSP_PLATFORM_DEVICE(4);
345 OMAP_MCBSP_PLATFORM_DEVICE(5);
347 static void omap_init_audio(void)
349         platform_device_register(&omap_mcbsp1);
350         platform_device_register(&omap_mcbsp2);
351         if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
352                 platform_device_register(&omap_mcbsp3);
353                 platform_device_register(&omap_mcbsp4);
354         }
355         if (cpu_is_omap243x() || cpu_is_omap34xx())
356                 platform_device_register(&omap_mcbsp5);
358         platform_device_register(&omap_pcm);
361 #else
362 static inline void omap_init_audio(void) {}
363 #endif
365 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
366                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
368 static void omap_init_mcpdm(void)
370         struct omap_hwmod *oh;
371         struct platform_device *pdev;
373         oh = omap_hwmod_lookup("mcpdm");
374         if (!oh) {
375                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
376                 return;
377         }
379         pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
380         WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
382 #else
383 static inline void omap_init_mcpdm(void) {}
384 #endif
386 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
387                 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
389 static void omap_init_dmic(void)
391         struct omap_hwmod *oh;
392         struct platform_device *pdev;
394         oh = omap_hwmod_lookup("dmic");
395         if (!oh) {
396                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
397                 return;
398         }
400         pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
401         WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
403 #else
404 static inline void omap_init_dmic(void) {}
405 #endif
407 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
409 #include <plat/mcspi.h>
411 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
413         struct platform_device *pdev;
414         char *name = "omap2_mcspi";
415         struct omap2_mcspi_platform_config *pdata;
416         static int spi_num;
417         struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
419         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
420         if (!pdata) {
421                 pr_err("Memory allocation for McSPI device failed\n");
422                 return -ENOMEM;
423         }
425         pdata->num_cs = mcspi_attrib->num_chipselect;
426         switch (oh->class->rev) {
427         case OMAP2_MCSPI_REV:
428         case OMAP3_MCSPI_REV:
429                         pdata->regs_offset = 0;
430                         break;
431         case OMAP4_MCSPI_REV:
432                         pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
433                         break;
434         default:
435                         pr_err("Invalid McSPI Revision value\n");
436                         return -EINVAL;
437         }
439         spi_num++;
440         pdev = omap_device_build(name, spi_num, oh, pdata,
441                                 sizeof(*pdata), NULL, 0, 0);
442         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
443                                 name, oh->name);
444         kfree(pdata);
445         return 0;
448 static void omap_init_mcspi(void)
450         omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
453 #else
454 static inline void omap_init_mcspi(void) {}
455 #endif
457 static struct resource omap2_pmu_resource = {
458         .start  = 3,
459         .end    = 3,
460         .flags  = IORESOURCE_IRQ,
461 };
463 static struct resource omap3_pmu_resource = {
464         .start  = INT_34XX_BENCH_MPU_EMUL,
465         .end    = INT_34XX_BENCH_MPU_EMUL,
466         .flags  = IORESOURCE_IRQ,
467 };
469 static struct platform_device omap_pmu_device = {
470         .name           = "arm-pmu",
471         .id             = ARM_PMU_DEVICE_CPU,
472         .num_resources  = 1,
473 };
475 static void omap_init_pmu(void)
477         if (cpu_is_omap24xx())
478                 omap_pmu_device.resource = &omap2_pmu_resource;
479         else if (cpu_is_omap34xx())
480                 omap_pmu_device.resource = &omap3_pmu_resource;
481         else
482                 return;
484         platform_device_register(&omap_pmu_device);
488 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
490 #ifdef CONFIG_ARCH_OMAP2
491 static struct resource omap2_sham_resources[] = {
492         {
493                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
494                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
495                 .flags  = IORESOURCE_MEM,
496         },
497         {
498                 .start  = INT_24XX_SHA1MD5,
499                 .flags  = IORESOURCE_IRQ,
500         }
501 };
502 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
503 #else
504 #define omap2_sham_resources            NULL
505 #define omap2_sham_resources_sz         0
506 #endif
508 #ifdef CONFIG_ARCH_OMAP3
509 static struct resource omap3_sham_resources[] = {
510         {
511                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
512                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
513                 .flags  = IORESOURCE_MEM,
514         },
515         {
516                 .start  = INT_34XX_SHA1MD52_IRQ,
517                 .flags  = IORESOURCE_IRQ,
518         },
519         {
520                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
521                 .flags  = IORESOURCE_DMA,
522         }
523 };
524 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
525 #else
526 #define omap3_sham_resources            NULL
527 #define omap3_sham_resources_sz         0
528 #endif
530 static struct platform_device sham_device = {
531         .name           = "omap-sham",
532         .id             = -1,
533 };
535 static void omap_init_sham(void)
537         if (cpu_is_omap24xx()) {
538                 sham_device.resource = omap2_sham_resources;
539                 sham_device.num_resources = omap2_sham_resources_sz;
540         } else if (cpu_is_omap34xx()) {
541                 sham_device.resource = omap3_sham_resources;
542                 sham_device.num_resources = omap3_sham_resources_sz;
543         } else {
544                 pr_err("%s: platform not supported\n", __func__);
545                 return;
546         }
547         platform_device_register(&sham_device);
549 #else
550 static inline void omap_init_sham(void) { }
551 #endif
553 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
555 #ifdef CONFIG_ARCH_OMAP2
556 static struct resource omap2_aes_resources[] = {
557         {
558                 .start  = OMAP24XX_SEC_AES_BASE,
559                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
560                 .flags  = IORESOURCE_MEM,
561         },
562         {
563                 .start  = OMAP24XX_DMA_AES_TX,
564                 .flags  = IORESOURCE_DMA,
565         },
566         {
567                 .start  = OMAP24XX_DMA_AES_RX,
568                 .flags  = IORESOURCE_DMA,
569         }
570 };
571 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
572 #else
573 #define omap2_aes_resources             NULL
574 #define omap2_aes_resources_sz          0
575 #endif
577 #ifdef CONFIG_ARCH_OMAP3
578 static struct resource omap3_aes_resources[] = {
579         {
580                 .start  = OMAP34XX_SEC_AES_BASE,
581                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
582                 .flags  = IORESOURCE_MEM,
583         },
584         {
585                 .start  = OMAP34XX_DMA_AES2_TX,
586                 .flags  = IORESOURCE_DMA,
587         },
588         {
589                 .start  = OMAP34XX_DMA_AES2_RX,
590                 .flags  = IORESOURCE_DMA,
591         }
592 };
593 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
594 #else
595 #define omap3_aes_resources             NULL
596 #define omap3_aes_resources_sz          0
597 #endif
599 static struct platform_device aes_device = {
600         .name           = "omap-aes",
601         .id             = -1,
602 };
604 static void omap_init_aes(void)
606         if (cpu_is_omap24xx()) {
607                 aes_device.resource = omap2_aes_resources;
608                 aes_device.num_resources = omap2_aes_resources_sz;
609         } else if (cpu_is_omap34xx()) {
610                 aes_device.resource = omap3_aes_resources;
611                 aes_device.num_resources = omap3_aes_resources_sz;
612         } else {
613                 pr_err("%s: platform not supported\n", __func__);
614                 return;
615         }
616         platform_device_register(&aes_device);
619 #else
620 static inline void omap_init_aes(void) { }
621 #endif
623 /*-------------------------------------------------------------------------*/
625 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
627 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
628                                                         *mmc_controller)
630         if ((mmc_controller->slots[0].switch_pin > 0) && \
631                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
632                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
633                                         OMAP_PIN_INPUT_PULLUP);
634         if ((mmc_controller->slots[0].gpio_wp > 0) && \
635                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
636                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
637                                         OMAP_PIN_INPUT_PULLUP);
639         omap_mux_init_signal("sdmmc_cmd", 0);
640         omap_mux_init_signal("sdmmc_clki", 0);
641         omap_mux_init_signal("sdmmc_clko", 0);
642         omap_mux_init_signal("sdmmc_dat0", 0);
643         omap_mux_init_signal("sdmmc_dat_dir0", 0);
644         omap_mux_init_signal("sdmmc_cmd_dir", 0);
645         if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
646                 omap_mux_init_signal("sdmmc_dat1", 0);
647                 omap_mux_init_signal("sdmmc_dat2", 0);
648                 omap_mux_init_signal("sdmmc_dat3", 0);
649                 omap_mux_init_signal("sdmmc_dat_dir1", 0);
650                 omap_mux_init_signal("sdmmc_dat_dir2", 0);
651                 omap_mux_init_signal("sdmmc_dat_dir3", 0);
652         }
654         /*
655          * Use internal loop-back in MMC/SDIO Module Input Clock
656          * selection
657          */
658         if (mmc_controller->slots[0].internal_clock) {
659                 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
660                 v |= (1 << 24);
661                 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
662         }
665 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
667         char *name = "mmci-omap";
669         if (!mmc_data[0]) {
670                 pr_err("%s fails: Incomplete platform data\n", __func__);
671                 return;
672         }
674         omap242x_mmc_mux(mmc_data[0]);
675         omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
676                                         INT_24XX_MMC_IRQ, mmc_data[0]);
679 #endif
681 /*-------------------------------------------------------------------------*/
683 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
684 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
685 #define OMAP_HDQ_BASE   0x480B2000
686 #endif
687 static struct resource omap_hdq_resources[] = {
688         {
689                 .start          = OMAP_HDQ_BASE,
690                 .end            = OMAP_HDQ_BASE + 0x1C,
691                 .flags          = IORESOURCE_MEM,
692         },
693         {
694                 .start          = INT_24XX_HDQ_IRQ,
695                 .flags          = IORESOURCE_IRQ,
696         },
697 };
698 static struct platform_device omap_hdq_dev = {
699         .name = "omap_hdq",
700         .id = 0,
701         .dev = {
702                 .platform_data = NULL,
703         },
704         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
705         .resource       = omap_hdq_resources,
706 };
707 static inline void omap_hdq_init(void)
709         (void) platform_device_register(&omap_hdq_dev);
711 #else
712 static inline void omap_hdq_init(void) {}
713 #endif
715 /*---------------------------------------------------------------------------*/
717 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
718         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
719 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
720 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
721 };
722 #else
723 static struct resource omap_vout_resource[2] = {
724 };
725 #endif
727 static struct platform_device omap_vout_device = {
728         .name           = "omap_vout",
729         .num_resources  = ARRAY_SIZE(omap_vout_resource),
730         .resource       = &omap_vout_resource[0],
731         .id             = -1,
732 };
733 static void omap_init_vout(void)
735         if (platform_device_register(&omap_vout_device) < 0)
736                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
738 #else
739 static inline void omap_init_vout(void) {}
740 #endif
742 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
744 #define AM33XX_TPCC_BASE                0x49000000
745 #define AM33XX_TPTC0_BASE               0x49800000
746 #define AM33XX_TPTC1_BASE               0x49900000
747 #define AM33XX_TPTC2_BASE               0x49a00000
749 #define AM33XX_SCM_BASE_EDMA            0x00000f90
751 static struct resource am33xx_edma_resources[] = {
752         {
753                 .name   = "edma_cc0",
754                 .start  = AM33XX_TPCC_BASE,
755                 .end    = AM33XX_TPCC_BASE + SZ_32K - 1,
756                 .flags  = IORESOURCE_MEM,
757         },
758         {
759                 .name   = "edma_tc0",
760                 .start  = AM33XX_TPTC0_BASE,
761                 .end    = AM33XX_TPTC0_BASE + SZ_1K - 1,
762                 .flags  = IORESOURCE_MEM,
763         },
764         {
765                 .name   = "edma_tc1",
766                 .start  = AM33XX_TPTC1_BASE,
767                 .end    = AM33XX_TPTC1_BASE + SZ_1K - 1,
768                 .flags  = IORESOURCE_MEM,
769         },
770         {
771                 .name   = "edma_tc2",
772                 .start  = AM33XX_TPTC2_BASE,
773                 .end    = AM33XX_TPTC2_BASE + SZ_1K - 1,
774                 .flags  = IORESOURCE_MEM,
775         },
776         {
777                 .name   = "edma0",
778                 .start  = AM33XX_IRQ_TPCC0_INT_PO0,
779                 .flags  = IORESOURCE_IRQ,
780         },
781         {
782                 .name   = "edma0_err",
783                 .start  = AM33XX_IRQ_TPCC0_ERRINT_PO,
784                 .flags  = IORESOURCE_IRQ,
785         },
786 };
788 static const s16 am33xx_dma_rsv_chans[][2] = {
789         /* (offset, number) */
790         {0, 2},
791         {14, 2},
792         {26, 6},
793         {48, 4},
794         {56, 8},
795         {-1, -1}
796 };
798 static const s16 am33xx_dma_rsv_slots[][2] = {
799         /* (offset, number) */
800         {0, 2},
801         {14, 2},
802         {26, 6},
803         {48, 4},
804         {56, 8},
805         {64, 127},
806         {-1, -1}
807 };
809 /* Three Transfer Controllers on AM33XX */
810 static const s8 am33xx_queue_tc_mapping[][2] = {
811         /* {event queue no, TC no} */
812         {0, 0},
813         {1, 1},
814         {2, 2},
815         {-1, -1}
816 };
818 static const s8 am33xx_queue_priority_mapping[][2] = {
819         /* {event queue no, Priority} */
820         {0, 0},
821         {1, 1},
822         {2, 2},
823         {-1, -1}
824 };
826 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
827         /* {xbar event no, Channel} */
828         {1, 12},        /* SDTXEVT1 -> MMCHS2 */
829         {2, 13},        /* SDRXEVT1 -> MMCHS2 */
830         {3, -1},
831         {4, -1},
832         {5, -1},
833         {6, -1},
834         {7, -1},
835         {8, -1},
836         {9, -1},
837         {10, -1},
838         {11, -1},
839         {12, -1},
840         {13, -1},
841         {14, -1},
842         {15, -1},
843         {16, -1},
844         {17, -1},
845         {18, -1},
846         {19, -1},
847         {20, -1},
848         {21, -1},
849         {22, -1},
850         {23, -1},
851         {24, -1},
852         {25, -1},
853         {26, -1},
854         {27, -1},
855         {28, -1},
856         {29, -1},
857         {30, -1},
858         {31, -1},
859         {-1, -1}
860 };
862 /**
863  * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
864  * according to the configuration provided
865  * @event: the event number for which mapping is required
866  * @channel: channel being activated
867  * @xbar_event_mapping: array that has the event to channel map
868  *
869  * Events that are routed by default are not mapped. Only events that
870  * are crossbar mapped are routed to available channels according to
871  * the configuration provided
872  *
873  * Returns zero on success, else negative errno.
874  */
875 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
876                         struct event_to_channel_map *xbar_event_mapping)
878         unsigned int ctrl = 0;
879         unsigned int xbar_evt_no = 0;
880         unsigned int val = 0;
881         unsigned int offset = 0;
882         unsigned int mask = 0;
884         ctrl = EDMA_CTLR(event);
885         xbar_evt_no = event - (edma_info[ctrl]->num_channels);
887         if (event < edma_info[ctrl]->num_channels) {
888                 *channel = event;
889         } else if (event < edma_info[ctrl]->num_events) {
890                 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
891                 /* confirm the range */
892                 if (*channel < EDMA_MAX_DMACH)
893                         clear_bit(*channel, edma_info[ctrl]->edma_unused);
894                 mask = (*channel)%4;
895                 offset = (*channel)/4;
896                 offset *= 4;
897                 offset += mask;
898                 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
899                                         AM33XX_SCM_BASE_EDMA + offset));
900                 val = val & (~(0xFF));
901                 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
902                 __raw_writel(val,
903                         AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
904                 return 0;
905         } else {
906                 return -EINVAL;
907         }
909         return 0;
912 static struct edma_soc_info am33xx_edma_info[] = {
913         {
914                 .n_channel              = 64,
915                 .n_region               = 4,
916                 .n_slot                 = 256,
917                 .n_tc                   = 3,
918                 .n_cc                   = 1,
919                 .rsv_chans              = am33xx_dma_rsv_chans,
920                 .rsv_slots              = am33xx_dma_rsv_slots,
921                 .queue_tc_mapping       = am33xx_queue_tc_mapping,
922                 .queue_priority_mapping = am33xx_queue_priority_mapping,
923                 .is_xbar                = 1,
924                 .n_events               = 95,
925                 .xbar_event_mapping     = am33xx_xbar_event_mapping,
926                 .map_xbar_channel       = map_xbar_event_to_channel,
927         },
928 };
930 static struct platform_device am33xx_edma_device = {
931         .name           = "edma",
932         .id             = -1,
933         .dev = {
934                 .platform_data = am33xx_edma_info,
935         },
936         .num_resources  = ARRAY_SIZE(am33xx_edma_resources),
937         .resource       = am33xx_edma_resources,
938 };
940 int __init am33xx_register_edma(void)
942         struct platform_device *pdev;
943         static struct clk *edma_clk;
945         if (cpu_is_am33xx())
946                 pdev = &am33xx_edma_device;
947         else {
948                 pr_err("%s: platform not supported\n", __func__);
949                 return -ENODEV;
950         }
952         edma_clk = clk_get(NULL, "tpcc_ick");
953         if (IS_ERR(edma_clk)) {
954                 printk(KERN_ERR "EDMA: Failed to get clock\n");
955                 return -EBUSY;
956         }
957         clk_enable(edma_clk);
958         edma_clk = clk_get(NULL, "tptc0_ick");
959         if (IS_ERR(edma_clk)) {
960                 printk(KERN_ERR "EDMA: Failed to get clock\n");
961                 return -EBUSY;
962         }
963         clk_enable(edma_clk);
964         edma_clk = clk_get(NULL, "tptc1_ick");
965         if (IS_ERR(edma_clk)) {
966                 printk(KERN_ERR "EDMA: Failed to get clock\n");
967                 return -EBUSY;
968         }
969         clk_enable(edma_clk);
970         edma_clk = clk_get(NULL, "tptc2_ick");
971         if (IS_ERR(edma_clk)) {
972                 printk(KERN_ERR "EDMA: Failed to get clock\n");
973                 return -EBUSY;
974         }
975         clk_enable(edma_clk);
977         return platform_device_register(pdev);
980 #else
981 static inline void am33xx_register_edma(void) {}
982 #endif
984 /*-------------------------------------------------------------------------*/
986 static int __init omap2_init_devices(void)
988         /*
989          * please keep these calls, and their implementations above,
990          * in alphabetical order so they're easier to sort through.
991          */
992         omap_init_audio();
993         omap_init_mcpdm();
994         omap_init_dmic();
995         omap_init_camera();
996         omap_init_mbox();
997         omap_init_mcspi();
998         omap_init_pmu();
999         omap_hdq_init();
1000         omap_init_sti();
1001         omap_init_sham();
1002         omap_init_aes();
1003         omap_init_vout();
1004         am33xx_register_edma();
1006         return 0;
1008 arch_initcall(omap2_init_devices);
1010 #define AM33XX_CPSW_BASE                (0x4A100000)
1011 #define AM33XX_CPSW_MDIO_BASE           (0x4A101000)
1012 #define AM33XX_CPSW_SS_BASE             (0x4A101200)
1013 #define AM33XX_EMAC_MDIO_FREQ           (1000000)
1015 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
1016 /* TODO : Verify the offsets */
1017 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
1018         {
1019                 .slave_reg_ofs  = 0x208,
1020                 .sliver_reg_ofs = 0xd80,
1021                 .phy_id         = "0:00",
1022         },
1023         {
1024                 .slave_reg_ofs  = 0x308,
1025                 .sliver_reg_ofs = 0xdc0,
1026                 .phy_id         = "0:01",
1027         },
1028 };
1030 static struct cpsw_platform_data am33xx_cpsw_pdata = {
1031         .ss_reg_ofs             = 0x1200,
1032         .channels               = 8,
1033         .cpdma_reg_ofs          = 0x800,
1034         .slaves                 = 2,
1035         .slave_data             = am33xx_cpsw_slaves,
1036         .ale_reg_ofs            = 0xd00,
1037         .ale_entries            = 1024,
1038         .host_port_reg_ofs      = 0x108,
1039         .hw_stats_reg_ofs       = 0x900,
1040         .bd_ram_ofs             = 0x2000,
1041         .bd_ram_size            = SZ_8K,
1042         .rx_descs               = 64,
1043         .mac_control            = BIT(5), /* MIIEN */
1044         .gigabit_en             = 1,
1045         .host_port_num          = 0,
1046         .no_bd_ram              = false,
1047         .version                = CPSW_VERSION_2,
1048 };
1050 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1051         .bus_freq       = AM33XX_EMAC_MDIO_FREQ,
1052 };
1054 static struct resource am33xx_cpsw_mdioresources[] = {
1055         {
1056                 .start  = AM33XX_CPSW_MDIO_BASE,
1057                 .end    = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1058                 .flags  = IORESOURCE_MEM,
1059         },
1060 };
1062 static struct platform_device am33xx_cpsw_mdiodevice = {
1063         .name           = "davinci_mdio",
1064         .id             = 0,
1065         .num_resources  = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1066         .resource       = am33xx_cpsw_mdioresources,
1067         .dev.platform_data = &am33xx_cpsw_mdiopdata,
1068 };
1070 static struct resource am33xx_cpsw_resources[] = {
1071         {
1072                 .start  = AM33XX_CPSW_BASE,
1073                 .end    = AM33XX_CPSW_BASE + SZ_2K - 1,
1074                 .flags  = IORESOURCE_MEM,
1075         },
1076         {
1077                 .start  = AM33XX_CPSW_SS_BASE,
1078                 .end    = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1079                 .flags  = IORESOURCE_MEM,
1080         },
1081         {
1082                 .start  = AM33XX_IRQ_CPSW_C0_RX,
1083                 .end    = AM33XX_IRQ_CPSW_C0_RX,
1084                 .flags  = IORESOURCE_IRQ,
1085         },
1086         {
1087                 .start  = AM33XX_IRQ_CPSW_RX,
1088                 .end    = AM33XX_IRQ_CPSW_RX,
1089                 .flags  = IORESOURCE_IRQ,
1090         },
1091         {
1092                 .start  = AM33XX_IRQ_CPSW_TX,
1093                 .end    = AM33XX_IRQ_CPSW_TX,
1094                 .flags  = IORESOURCE_IRQ,
1095         },
1096         {
1097                 .start  = AM33XX_IRQ_CPSW_C0,
1098                 .end    = AM33XX_IRQ_CPSW_C0,
1099                 .flags  = IORESOURCE_IRQ,
1100         },
1101 };
1103 static struct platform_device am33xx_cpsw_device = {
1104         .name           =       "cpsw",
1105         .id             =       0,
1106         .num_resources  =       ARRAY_SIZE(am33xx_cpsw_resources),
1107         .resource       =       am33xx_cpsw_resources,
1108         .dev            =       {
1109                                         .platform_data  = &am33xx_cpsw_pdata,
1110                                         .dma_mask       = &am33xx_cpsw_dmamask,
1111                                         .coherent_dma_mask = DMA_BIT_MASK(32),
1112                                 },
1113 };
1115 static unsigned char  am33xx_macid0[ETH_ALEN];
1116 static unsigned char  am33xx_macid1[ETH_ALEN];
1117 static unsigned int   am33xx_evmid;
1119 /*
1120 * am33xx_evmid_fillup - set up board evmid
1121 * @evmid - evm id which needs to be configured
1123 * This function is called to configure board evm id.
1124 * IA Motor Control EVM needs special setting of MAC PHY Id.
1125 * This function is called when IA Motor Control EVM is detected
1126 * during boot-up.
1127 */
1128 void am33xx_evmid_fillup(unsigned int evmid)
1130         am33xx_evmid = evmid;
1131         return;
1134 /*
1135 * am33xx_cpsw_macidfillup - setup mac adrresses
1136 * @eeprommacid0 - mac id 0 which needs to be configured
1137 * @eeprommacid1 - mac id 1 which needs to be configured
1139 * This function is called to configure mac addresses.
1140 * Mac addresses are read from eeprom and this function is called
1141 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1142 * In case, mac address read from eFuse are invalid, mac addresses
1143 * stored in these variable are used.
1144 */
1145 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1147         u32 i;
1149         /* Fillup these mac addresses with the mac adresses from eeprom */
1150         for (i = 0; i < ETH_ALEN; i++) {
1151                 am33xx_macid0[i] = eeprommacid0[i];
1152                 am33xx_macid1[i] = eeprommacid1[i];
1153         }
1155         return;
1158 void am33xx_cpsw_init(void)
1160         u32 mac_lo, mac_hi;
1161         u32 i;
1163         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1164         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1165         am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1166         am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1167         am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1168         am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1169         am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1170         am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1172         /* Read MACID0 from eeprom if eFuse MACID is invalid */
1173         if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1174                 for (i = 0; i < ETH_ALEN; i++)
1175                         am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1176         }
1178         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1179         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1180         am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1181         am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1182         am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1183         am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1184         am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1185         am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1187         /* Read MACID1 from eeprom if eFuse MACID is invalid */
1188         if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1189                 for (i = 0; i < ETH_ALEN; i++)
1190                         am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1191         }
1193         platform_device_register(&am33xx_cpsw_mdiodevice);
1194         platform_device_register(&am33xx_cpsw_device);
1195         clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1196                         NULL, &am33xx_cpsw_device.dev);
1200 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1201 static int __init omap_init_wdt(void)
1203         int id = -1;
1204         struct platform_device *pdev;
1205         struct omap_hwmod *oh;
1206         char *oh_name = "wd_timer2";
1207         char *dev_name = "omap_wdt";
1209         if (!cpu_class_is_omap2())
1210                 return 0;
1212         oh = omap_hwmod_lookup(oh_name);
1213         if (!oh) {
1214                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1215                 return -EINVAL;
1216         }
1218         pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1219         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1220                                 dev_name, oh->name);
1221         return 0;
1223 subsys_initcall(omap_init_wdt);
1224 #endif