arch:arm:elm - updated Hardware mode data for ELM
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / devices.c
1 /*
2  * linux/arch/arm/mach-omap2/devices.c
3  *
4  * OMAP2 platform device setup/initialization
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 #include <linux/gpio.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
25 #include <mach/hardware.h>
26 #include <mach/irqs.h>
27 #include <asm/mach-types.h>
28 #include <asm/mach/map.h>
29 #include <asm/pmu.h>
31 #ifdef  CONFIG_OMAP3_EDMA
32 #include <mach/edma.h>
33 #endif
35 #include <plat/tc.h>
36 #include <plat/board.h>
37 #include <plat/mcbsp.h>
38 #include <plat/mmc.h>
39 #include <plat/dma.h>
40 #include <plat/omap_hwmod.h>
41 #include <plat/omap_device.h>
42 #include <plat/omap4-keypad.h>
44 /* LCD controller similar DA8xx */
45 #include <video/da8xx-fb.h>
47 #include "mux.h"
48 #include "control.h"
49 #include "devices.h"
51 #define L3_MODULES_MAX_LEN 12
52 #define L3_MODULES 3
54 void am33xx_cpsw_init(void);
56 static int __init omap3_l3_init(void)
57 {
58         int l;
59         struct omap_hwmod *oh;
60         struct platform_device *pdev;
61         char oh_name[L3_MODULES_MAX_LEN];
63         /*
64          * To avoid code running on other OMAPs in
65          * multi-omap builds
66          */
67         if (!(cpu_is_omap34xx()))
68                 return -ENODEV;
70         l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
72         oh = omap_hwmod_lookup(oh_name);
74         if (!oh)
75                 pr_err("could not look up %s\n", oh_name);
77         pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
78                                                            NULL, 0, 0);
80         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
82         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
83 }
84 postcore_initcall(omap3_l3_init);
86 static int __init omap4_l3_init(void)
87 {
88         int l, i;
89         struct omap_hwmod *oh[3];
90         struct platform_device *pdev;
91         char oh_name[L3_MODULES_MAX_LEN];
93         /* If dtb is there, the devices will be created dynamically */
94         if (of_have_populated_dt())
95                 return -ENODEV;
97         /*
98          * To avoid code running on other OMAPs in
99          * multi-omap builds
100          */
101         if (!(cpu_is_omap44xx()))
102                 return -ENODEV;
104         for (i = 0; i < L3_MODULES; i++) {
105                 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
107                 oh[i] = omap_hwmod_lookup(oh_name);
108                 if (!(oh[i]))
109                         pr_err("could not look up %s\n", oh_name);
110         }
112         pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
113                                                      0, NULL, 0, 0);
115         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
117         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
119 postcore_initcall(omap4_l3_init);
121 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
123 static struct resource omap2cam_resources[] = {
124         {
125                 .start          = OMAP24XX_CAMERA_BASE,
126                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
127                 .flags          = IORESOURCE_MEM,
128         },
129         {
130                 .start          = INT_24XX_CAM_IRQ,
131                 .flags          = IORESOURCE_IRQ,
132         }
133 };
135 static struct platform_device omap2cam_device = {
136         .name           = "omap24xxcam",
137         .id             = -1,
138         .num_resources  = ARRAY_SIZE(omap2cam_resources),
139         .resource       = omap2cam_resources,
140 };
141 #endif
142 #define L4_PER_LCDC_PHYS        0x4830E000
144 static struct resource am33xx_lcdc_resources[] = {
145         [0] = { /* registers */
146                 .start  = L4_PER_LCDC_PHYS,
147                 .end    = L4_PER_LCDC_PHYS + SZ_4K - 1,
148                 .flags  = IORESOURCE_MEM,
149         },
150         [1] = { /* interrupt */
151                 .start  = AM33XX_IRQ_LCD,
152                 .end    = AM33XX_IRQ_LCD,
153                 .flags  = IORESOURCE_IRQ,
154         },
155 };
157 static struct platform_device am33xx_lcdc_device = {
158         .name           = "da8xx_lcdc",
159         .id             = 0,
160         .num_resources  = ARRAY_SIZE(am33xx_lcdc_resources),
161         .resource       = am33xx_lcdc_resources,
162 };
164 void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
166         int ret;
168         am33xx_lcdc_device.dev.platform_data = pdata;
170         ret = platform_device_register(&am33xx_lcdc_device);
171         if (ret)
172                 pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n",
173                                 ret);
177 static struct resource omap3isp_resources[] = {
178         {
179                 .start          = OMAP3430_ISP_BASE,
180                 .end            = OMAP3430_ISP_END,
181                 .flags          = IORESOURCE_MEM,
182         },
183         {
184                 .start          = OMAP3430_ISP_CCP2_BASE,
185                 .end            = OMAP3430_ISP_CCP2_END,
186                 .flags          = IORESOURCE_MEM,
187         },
188         {
189                 .start          = OMAP3430_ISP_CCDC_BASE,
190                 .end            = OMAP3430_ISP_CCDC_END,
191                 .flags          = IORESOURCE_MEM,
192         },
193         {
194                 .start          = OMAP3430_ISP_HIST_BASE,
195                 .end            = OMAP3430_ISP_HIST_END,
196                 .flags          = IORESOURCE_MEM,
197         },
198         {
199                 .start          = OMAP3430_ISP_H3A_BASE,
200                 .end            = OMAP3430_ISP_H3A_END,
201                 .flags          = IORESOURCE_MEM,
202         },
203         {
204                 .start          = OMAP3430_ISP_PREV_BASE,
205                 .end            = OMAP3430_ISP_PREV_END,
206                 .flags          = IORESOURCE_MEM,
207         },
208         {
209                 .start          = OMAP3430_ISP_RESZ_BASE,
210                 .end            = OMAP3430_ISP_RESZ_END,
211                 .flags          = IORESOURCE_MEM,
212         },
213         {
214                 .start          = OMAP3430_ISP_SBL_BASE,
215                 .end            = OMAP3430_ISP_SBL_END,
216                 .flags          = IORESOURCE_MEM,
217         },
218         {
219                 .start          = OMAP3430_ISP_CSI2A_REGS1_BASE,
220                 .end            = OMAP3430_ISP_CSI2A_REGS1_END,
221                 .flags          = IORESOURCE_MEM,
222         },
223         {
224                 .start          = OMAP3430_ISP_CSIPHY2_BASE,
225                 .end            = OMAP3430_ISP_CSIPHY2_END,
226                 .flags          = IORESOURCE_MEM,
227         },
228         {
229                 .start          = OMAP3630_ISP_CSI2A_REGS2_BASE,
230                 .end            = OMAP3630_ISP_CSI2A_REGS2_END,
231                 .flags          = IORESOURCE_MEM,
232         },
233         {
234                 .start          = OMAP3630_ISP_CSI2C_REGS1_BASE,
235                 .end            = OMAP3630_ISP_CSI2C_REGS1_END,
236                 .flags          = IORESOURCE_MEM,
237         },
238         {
239                 .start          = OMAP3630_ISP_CSIPHY1_BASE,
240                 .end            = OMAP3630_ISP_CSIPHY1_END,
241                 .flags          = IORESOURCE_MEM,
242         },
243         {
244                 .start          = OMAP3630_ISP_CSI2C_REGS2_BASE,
245                 .end            = OMAP3630_ISP_CSI2C_REGS2_END,
246                 .flags          = IORESOURCE_MEM,
247         },
248         {
249                 .start          = INT_34XX_CAM_IRQ,
250                 .flags          = IORESOURCE_IRQ,
251         }
252 };
254 static struct platform_device omap3isp_device = {
255         .name           = "omap3isp",
256         .id             = -1,
257         .num_resources  = ARRAY_SIZE(omap3isp_resources),
258         .resource       = omap3isp_resources,
259 };
261 int omap3_init_camera(struct isp_platform_data *pdata)
263         omap3isp_device.dev.platform_data = pdata;
264         return platform_device_register(&omap3isp_device);
267 static inline void omap_init_camera(void)
269 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
270         if (cpu_is_omap24xx())
271                 platform_device_register(&omap2cam_device);
272 #endif
275 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
276                         *sdp4430_keypad_data, struct omap_board_data *bdata)
278         struct platform_device *pdev;
279         struct omap_hwmod *oh;
280         struct omap4_keypad_platform_data *keypad_data;
281         unsigned int id = -1;
282         char *oh_name = "kbd";
283         char *name = "omap4-keypad";
285         oh = omap_hwmod_lookup(oh_name);
286         if (!oh) {
287                 pr_err("Could not look up %s\n", oh_name);
288                 return -ENODEV;
289         }
291         keypad_data = sdp4430_keypad_data;
293         pdev = omap_device_build(name, id, oh, keypad_data,
294                         sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
296         if (IS_ERR(pdev)) {
297                 WARN(1, "Can't build omap_device for %s:%s.\n",
298                                                 name, oh->name);
299                 return PTR_ERR(pdev);
300         }
301         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
303         return 0;
306 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
307 static inline void omap_init_mbox(void)
309         struct omap_hwmod *oh;
310         struct platform_device *pdev;
312         oh = omap_hwmod_lookup("mailbox");
313         if (!oh) {
314                 pr_err("%s: unable to find hwmod\n", __func__);
315                 return;
316         }
318         pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
319         WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
320                                                 __func__, PTR_ERR(pdev));
322 #else
323 static inline void omap_init_mbox(void) { }
324 #endif /* CONFIG_OMAP_MBOX_FWK */
326 static inline void omap_init_sti(void) {}
328 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
330 static struct platform_device omap_pcm = {
331         .name   = "omap-pcm-audio",
332         .id     = -1,
333 };
335 /*
336  * OMAP2420 has 2 McBSP ports
337  * OMAP2430 has 5 McBSP ports
338  * OMAP3 has 5 McBSP ports
339  * OMAP4 has 4 McBSP ports
340  */
341 OMAP_MCBSP_PLATFORM_DEVICE(1);
342 OMAP_MCBSP_PLATFORM_DEVICE(2);
343 OMAP_MCBSP_PLATFORM_DEVICE(3);
344 OMAP_MCBSP_PLATFORM_DEVICE(4);
345 OMAP_MCBSP_PLATFORM_DEVICE(5);
347 static void omap_init_audio(void)
349         platform_device_register(&omap_mcbsp1);
350         platform_device_register(&omap_mcbsp2);
351         if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
352                 platform_device_register(&omap_mcbsp3);
353                 platform_device_register(&omap_mcbsp4);
354         }
355         if (cpu_is_omap243x() || cpu_is_omap34xx())
356                 platform_device_register(&omap_mcbsp5);
358         platform_device_register(&omap_pcm);
361 #else
362 static inline void omap_init_audio(void) {}
363 #endif
365 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
366                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
368 static void omap_init_mcpdm(void)
370         struct omap_hwmod *oh;
371         struct platform_device *pdev;
373         oh = omap_hwmod_lookup("mcpdm");
374         if (!oh) {
375                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
376                 return;
377         }
379         pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
380         WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
382 #else
383 static inline void omap_init_mcpdm(void) {}
384 #endif
386 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
387                 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
389 static void omap_init_dmic(void)
391         struct omap_hwmod *oh;
392         struct platform_device *pdev;
394         oh = omap_hwmod_lookup("dmic");
395         if (!oh) {
396                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
397                 return;
398         }
400         pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
401         WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
403 #else
404 static inline void omap_init_dmic(void) {}
405 #endif
407 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
409 #include <plat/mcspi.h>
411 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
413         struct platform_device *pdev;
414         char *name = "omap2_mcspi";
415         struct omap2_mcspi_platform_config *pdata;
416         static int spi_num;
417         struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
419         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
420         if (!pdata) {
421                 pr_err("Memory allocation for McSPI device failed\n");
422                 return -ENOMEM;
423         }
425         pdata->num_cs = mcspi_attrib->num_chipselect;
426         switch (oh->class->rev) {
427         case OMAP2_MCSPI_REV:
428         case OMAP3_MCSPI_REV:
429                         pdata->regs_offset = 0;
430                         break;
431         case OMAP4_MCSPI_REV:
432                         pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
433                         break;
434         default:
435                         pr_err("Invalid McSPI Revision value\n");
436                         return -EINVAL;
437         }
439         spi_num++;
440         pdev = omap_device_build(name, spi_num, oh, pdata,
441                                 sizeof(*pdata), NULL, 0, 0);
442         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
443                                 name, oh->name);
444         kfree(pdata);
445         return 0;
448 static void omap_init_mcspi(void)
450         omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
453 #else
454 static inline void omap_init_mcspi(void) {}
455 #endif
457 #ifdef CONFIG_SOC_OMAPAM33XX
459 static int omap_elm_init(struct omap_hwmod *oh, void *unused)
461         struct platform_device *pdev;
462         char *name = "omap2_elm";
463         static int elm_num;
466         elm_num++;
467         pdev = omap_device_build(name, elm_num, oh, NULL,
468                                 0,      NULL,
469                                 0, 0);
470         return 0;
473 static void omap_init_elm(void)
476         omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL);
479 #else
480 static void omap_init_elm(void) {}
481 #endif
484 static struct resource omap2_pmu_resource = {
485         .start  = 3,
486         .end    = 3,
487         .flags  = IORESOURCE_IRQ,
488 };
490 static struct resource omap3_pmu_resource = {
491         .start  = INT_34XX_BENCH_MPU_EMUL,
492         .end    = INT_34XX_BENCH_MPU_EMUL,
493         .flags  = IORESOURCE_IRQ,
494 };
496 static struct platform_device omap_pmu_device = {
497         .name           = "arm-pmu",
498         .id             = ARM_PMU_DEVICE_CPU,
499         .num_resources  = 1,
500 };
502 static void omap_init_pmu(void)
504         if (cpu_is_omap24xx())
505                 omap_pmu_device.resource = &omap2_pmu_resource;
506         else if (cpu_is_omap34xx())
507                 omap_pmu_device.resource = &omap3_pmu_resource;
508         else
509                 return;
511         platform_device_register(&omap_pmu_device);
515 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
517 #ifdef CONFIG_ARCH_OMAP2
518 static struct resource omap2_sham_resources[] = {
519         {
520                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
521                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
522                 .flags  = IORESOURCE_MEM,
523         },
524         {
525                 .start  = INT_24XX_SHA1MD5,
526                 .flags  = IORESOURCE_IRQ,
527         }
528 };
529 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
530 #else
531 #define omap2_sham_resources            NULL
532 #define omap2_sham_resources_sz         0
533 #endif
535 #ifdef CONFIG_ARCH_OMAP3
536 static struct resource omap3_sham_resources[] = {
537         {
538                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
539                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
540                 .flags  = IORESOURCE_MEM,
541         },
542         {
543                 .start  = INT_34XX_SHA1MD52_IRQ,
544                 .flags  = IORESOURCE_IRQ,
545         },
546         {
547                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
548                 .flags  = IORESOURCE_DMA,
549         }
550 };
551 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
552 #else
553 #define omap3_sham_resources            NULL
554 #define omap3_sham_resources_sz         0
555 #endif
557 static struct platform_device sham_device = {
558         .name           = "omap-sham",
559         .id             = -1,
560 };
562 static void omap_init_sham(void)
564         if (cpu_is_omap24xx()) {
565                 sham_device.resource = omap2_sham_resources;
566                 sham_device.num_resources = omap2_sham_resources_sz;
567         } else if (cpu_is_omap34xx()) {
568                 sham_device.resource = omap3_sham_resources;
569                 sham_device.num_resources = omap3_sham_resources_sz;
570         } else {
571                 pr_err("%s: platform not supported\n", __func__);
572                 return;
573         }
574         platform_device_register(&sham_device);
576 #else
577 static inline void omap_init_sham(void) { }
578 #endif
580 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
582 #ifdef CONFIG_ARCH_OMAP2
583 static struct resource omap2_aes_resources[] = {
584         {
585                 .start  = OMAP24XX_SEC_AES_BASE,
586                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
587                 .flags  = IORESOURCE_MEM,
588         },
589         {
590                 .start  = OMAP24XX_DMA_AES_TX,
591                 .flags  = IORESOURCE_DMA,
592         },
593         {
594                 .start  = OMAP24XX_DMA_AES_RX,
595                 .flags  = IORESOURCE_DMA,
596         }
597 };
598 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
599 #else
600 #define omap2_aes_resources             NULL
601 #define omap2_aes_resources_sz          0
602 #endif
604 #ifdef CONFIG_ARCH_OMAP3
605 static struct resource omap3_aes_resources[] = {
606         {
607                 .start  = OMAP34XX_SEC_AES_BASE,
608                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
609                 .flags  = IORESOURCE_MEM,
610         },
611         {
612                 .start  = OMAP34XX_DMA_AES2_TX,
613                 .flags  = IORESOURCE_DMA,
614         },
615         {
616                 .start  = OMAP34XX_DMA_AES2_RX,
617                 .flags  = IORESOURCE_DMA,
618         }
619 };
620 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
621 #else
622 #define omap3_aes_resources             NULL
623 #define omap3_aes_resources_sz          0
624 #endif
626 static struct platform_device aes_device = {
627         .name           = "omap-aes",
628         .id             = -1,
629 };
631 static void omap_init_aes(void)
633         if (cpu_is_omap24xx()) {
634                 aes_device.resource = omap2_aes_resources;
635                 aes_device.num_resources = omap2_aes_resources_sz;
636         } else if (cpu_is_omap34xx()) {
637                 aes_device.resource = omap3_aes_resources;
638                 aes_device.num_resources = omap3_aes_resources_sz;
639         } else {
640                 pr_err("%s: platform not supported\n", __func__);
641                 return;
642         }
643         platform_device_register(&aes_device);
646 #else
647 static inline void omap_init_aes(void) { }
648 #endif
650 /*-------------------------------------------------------------------------*/
652 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
654 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
655                                                         *mmc_controller)
657         if ((mmc_controller->slots[0].switch_pin > 0) && \
658                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
659                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
660                                         OMAP_PIN_INPUT_PULLUP);
661         if ((mmc_controller->slots[0].gpio_wp > 0) && \
662                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
663                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
664                                         OMAP_PIN_INPUT_PULLUP);
666         omap_mux_init_signal("sdmmc_cmd", 0);
667         omap_mux_init_signal("sdmmc_clki", 0);
668         omap_mux_init_signal("sdmmc_clko", 0);
669         omap_mux_init_signal("sdmmc_dat0", 0);
670         omap_mux_init_signal("sdmmc_dat_dir0", 0);
671         omap_mux_init_signal("sdmmc_cmd_dir", 0);
672         if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
673                 omap_mux_init_signal("sdmmc_dat1", 0);
674                 omap_mux_init_signal("sdmmc_dat2", 0);
675                 omap_mux_init_signal("sdmmc_dat3", 0);
676                 omap_mux_init_signal("sdmmc_dat_dir1", 0);
677                 omap_mux_init_signal("sdmmc_dat_dir2", 0);
678                 omap_mux_init_signal("sdmmc_dat_dir3", 0);
679         }
681         /*
682          * Use internal loop-back in MMC/SDIO Module Input Clock
683          * selection
684          */
685         if (mmc_controller->slots[0].internal_clock) {
686                 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
687                 v |= (1 << 24);
688                 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
689         }
692 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
694         char *name = "mmci-omap";
696         if (!mmc_data[0]) {
697                 pr_err("%s fails: Incomplete platform data\n", __func__);
698                 return;
699         }
701         omap242x_mmc_mux(mmc_data[0]);
702         omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
703                                         INT_24XX_MMC_IRQ, mmc_data[0]);
706 #endif
708 /*-------------------------------------------------------------------------*/
710 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
711 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
712 #define OMAP_HDQ_BASE   0x480B2000
713 #endif
714 static struct resource omap_hdq_resources[] = {
715         {
716                 .start          = OMAP_HDQ_BASE,
717                 .end            = OMAP_HDQ_BASE + 0x1C,
718                 .flags          = IORESOURCE_MEM,
719         },
720         {
721                 .start          = INT_24XX_HDQ_IRQ,
722                 .flags          = IORESOURCE_IRQ,
723         },
724 };
725 static struct platform_device omap_hdq_dev = {
726         .name = "omap_hdq",
727         .id = 0,
728         .dev = {
729                 .platform_data = NULL,
730         },
731         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
732         .resource       = omap_hdq_resources,
733 };
734 static inline void omap_hdq_init(void)
736         (void) platform_device_register(&omap_hdq_dev);
738 #else
739 static inline void omap_hdq_init(void) {}
740 #endif
742 /*---------------------------------------------------------------------------*/
744 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
745         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
746 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
747 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
748 };
749 #else
750 static struct resource omap_vout_resource[2] = {
751 };
752 #endif
754 static struct platform_device omap_vout_device = {
755         .name           = "omap_vout",
756         .num_resources  = ARRAY_SIZE(omap_vout_resource),
757         .resource       = &omap_vout_resource[0],
758         .id             = -1,
759 };
760 static void omap_init_vout(void)
762         if (platform_device_register(&omap_vout_device) < 0)
763                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
765 #else
766 static inline void omap_init_vout(void) {}
767 #endif
769 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
771 #define AM33XX_TPCC_BASE                0x49000000
772 #define AM33XX_TPTC0_BASE               0x49800000
773 #define AM33XX_TPTC1_BASE               0x49900000
774 #define AM33XX_TPTC2_BASE               0x49a00000
776 #define AM33XX_SCM_BASE_EDMA            0x00000f90
778 static struct resource am33xx_edma_resources[] = {
779         {
780                 .name   = "edma_cc0",
781                 .start  = AM33XX_TPCC_BASE,
782                 .end    = AM33XX_TPCC_BASE + SZ_32K - 1,
783                 .flags  = IORESOURCE_MEM,
784         },
785         {
786                 .name   = "edma_tc0",
787                 .start  = AM33XX_TPTC0_BASE,
788                 .end    = AM33XX_TPTC0_BASE + SZ_1K - 1,
789                 .flags  = IORESOURCE_MEM,
790         },
791         {
792                 .name   = "edma_tc1",
793                 .start  = AM33XX_TPTC1_BASE,
794                 .end    = AM33XX_TPTC1_BASE + SZ_1K - 1,
795                 .flags  = IORESOURCE_MEM,
796         },
797         {
798                 .name   = "edma_tc2",
799                 .start  = AM33XX_TPTC2_BASE,
800                 .end    = AM33XX_TPTC2_BASE + SZ_1K - 1,
801                 .flags  = IORESOURCE_MEM,
802         },
803         {
804                 .name   = "edma0",
805                 .start  = AM33XX_IRQ_TPCC0_INT_PO0,
806                 .flags  = IORESOURCE_IRQ,
807         },
808         {
809                 .name   = "edma0_err",
810                 .start  = AM33XX_IRQ_TPCC0_ERRINT_PO,
811                 .flags  = IORESOURCE_IRQ,
812         },
813 };
815 static const s16 am33xx_dma_rsv_chans[][2] = {
816         /* (offset, number) */
817         {0, 2},
818         {14, 2},
819         {26, 6},
820         {48, 4},
821         {56, 8},
822         {-1, -1}
823 };
825 static const s16 am33xx_dma_rsv_slots[][2] = {
826         /* (offset, number) */
827         {0, 2},
828         {14, 2},
829         {26, 6},
830         {48, 4},
831         {56, 8},
832         {64, 127},
833         {-1, -1}
834 };
836 /* Three Transfer Controllers on AM33XX */
837 static const s8 am33xx_queue_tc_mapping[][2] = {
838         /* {event queue no, TC no} */
839         {0, 0},
840         {1, 1},
841         {2, 2},
842         {-1, -1}
843 };
845 static const s8 am33xx_queue_priority_mapping[][2] = {
846         /* {event queue no, Priority} */
847         {0, 0},
848         {1, 1},
849         {2, 2},
850         {-1, -1}
851 };
853 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
854         /* {xbar event no, Channel} */
855         {1, 12},        /* SDTXEVT1 -> MMCHS2 */
856         {2, 13},        /* SDRXEVT1 -> MMCHS2 */
857         {3, -1},
858         {4, -1},
859         {5, -1},
860         {6, -1},
861         {7, -1},
862         {8, -1},
863         {9, -1},
864         {10, -1},
865         {11, -1},
866         {12, -1},
867         {13, -1},
868         {14, -1},
869         {15, -1},
870         {16, -1},
871         {17, -1},
872         {18, -1},
873         {19, -1},
874         {20, -1},
875         {21, -1},
876         {22, -1},
877         {23, -1},
878         {24, -1},
879         {25, -1},
880         {26, -1},
881         {27, -1},
882         {28, -1},
883         {29, -1},
884         {30, -1},
885         {31, -1},
886         {-1, -1}
887 };
889 /**
890  * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
891  * according to the configuration provided
892  * @event: the event number for which mapping is required
893  * @channel: channel being activated
894  * @xbar_event_mapping: array that has the event to channel map
895  *
896  * Events that are routed by default are not mapped. Only events that
897  * are crossbar mapped are routed to available channels according to
898  * the configuration provided
899  *
900  * Returns zero on success, else negative errno.
901  */
902 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
903                         struct event_to_channel_map *xbar_event_mapping)
905         unsigned int ctrl = 0;
906         unsigned int xbar_evt_no = 0;
907         unsigned int val = 0;
908         unsigned int offset = 0;
909         unsigned int mask = 0;
911         ctrl = EDMA_CTLR(event);
912         xbar_evt_no = event - (edma_info[ctrl]->num_channels);
914         if (event < edma_info[ctrl]->num_channels) {
915                 *channel = event;
916         } else if (event < edma_info[ctrl]->num_events) {
917                 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
918                 /* confirm the range */
919                 if (*channel < EDMA_MAX_DMACH)
920                         clear_bit(*channel, edma_info[ctrl]->edma_unused);
921                 mask = (*channel)%4;
922                 offset = (*channel)/4;
923                 offset *= 4;
924                 offset += mask;
925                 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
926                                         AM33XX_SCM_BASE_EDMA + offset));
927                 val = val & (~(0xFF));
928                 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
929                 __raw_writel(val,
930                         AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
931                 return 0;
932         } else {
933                 return -EINVAL;
934         }
936         return 0;
939 static struct edma_soc_info am33xx_edma_info[] = {
940         {
941                 .n_channel              = 64,
942                 .n_region               = 4,
943                 .n_slot                 = 256,
944                 .n_tc                   = 3,
945                 .n_cc                   = 1,
946                 .rsv_chans              = am33xx_dma_rsv_chans,
947                 .rsv_slots              = am33xx_dma_rsv_slots,
948                 .queue_tc_mapping       = am33xx_queue_tc_mapping,
949                 .queue_priority_mapping = am33xx_queue_priority_mapping,
950                 .is_xbar                = 1,
951                 .n_events               = 95,
952                 .xbar_event_mapping     = am33xx_xbar_event_mapping,
953                 .map_xbar_channel       = map_xbar_event_to_channel,
954         },
955 };
957 static struct platform_device am33xx_edma_device = {
958         .name           = "edma",
959         .id             = -1,
960         .dev = {
961                 .platform_data = am33xx_edma_info,
962         },
963         .num_resources  = ARRAY_SIZE(am33xx_edma_resources),
964         .resource       = am33xx_edma_resources,
965 };
967 int __init am33xx_register_edma(void)
969         struct platform_device *pdev;
970         static struct clk *edma_clk;
972         if (cpu_is_am33xx())
973                 pdev = &am33xx_edma_device;
974         else {
975                 pr_err("%s: platform not supported\n", __func__);
976                 return -ENODEV;
977         }
979         edma_clk = clk_get(NULL, "tpcc_ick");
980         if (IS_ERR(edma_clk)) {
981                 printk(KERN_ERR "EDMA: Failed to get clock\n");
982                 return -EBUSY;
983         }
984         clk_enable(edma_clk);
985         edma_clk = clk_get(NULL, "tptc0_ick");
986         if (IS_ERR(edma_clk)) {
987                 printk(KERN_ERR "EDMA: Failed to get clock\n");
988                 return -EBUSY;
989         }
990         clk_enable(edma_clk);
991         edma_clk = clk_get(NULL, "tptc1_ick");
992         if (IS_ERR(edma_clk)) {
993                 printk(KERN_ERR "EDMA: Failed to get clock\n");
994                 return -EBUSY;
995         }
996         clk_enable(edma_clk);
997         edma_clk = clk_get(NULL, "tptc2_ick");
998         if (IS_ERR(edma_clk)) {
999                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1000                 return -EBUSY;
1001         }
1002         clk_enable(edma_clk);
1004         return platform_device_register(pdev);
1007 #else
1008 static inline void am33xx_register_edma(void) {}
1009 #endif
1011 /*-------------------------------------------------------------------------*/
1013 static int __init omap2_init_devices(void)
1015         /*
1016          * please keep these calls, and their implementations above,
1017          * in alphabetical order so they're easier to sort through.
1018          */
1019         omap_init_audio();
1020         omap_init_mcpdm();
1021         omap_init_dmic();
1022         omap_init_camera();
1023         omap_init_mbox();
1024         omap_init_mcspi();
1025         omap_init_elm();
1026         omap_init_pmu();
1027         omap_hdq_init();
1028         omap_init_sti();
1029         omap_init_sham();
1030         omap_init_aes();
1031         omap_init_vout();
1032         am33xx_register_edma();
1034         return 0;
1036 arch_initcall(omap2_init_devices);
1038 #define AM33XX_CPSW_BASE                (0x4A100000)
1039 #define AM33XX_CPSW_MDIO_BASE           (0x4A101000)
1040 #define AM33XX_CPSW_SS_BASE             (0x4A101200)
1041 #define AM33XX_EMAC_MDIO_FREQ           (1000000)
1043 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
1044 /* TODO : Verify the offsets */
1045 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
1046         {
1047                 .slave_reg_ofs  = 0x208,
1048                 .sliver_reg_ofs = 0xd80,
1049                 .phy_id         = "0:00",
1050         },
1051         {
1052                 .slave_reg_ofs  = 0x308,
1053                 .sliver_reg_ofs = 0xdc0,
1054                 .phy_id         = "0:01",
1055         },
1056 };
1058 static struct cpsw_platform_data am33xx_cpsw_pdata = {
1059         .ss_reg_ofs             = 0x1200,
1060         .channels               = 8,
1061         .cpdma_reg_ofs          = 0x800,
1062         .slaves                 = 2,
1063         .slave_data             = am33xx_cpsw_slaves,
1064         .ale_reg_ofs            = 0xd00,
1065         .ale_entries            = 1024,
1066         .host_port_reg_ofs      = 0x108,
1067         .hw_stats_reg_ofs       = 0x900,
1068         .bd_ram_ofs             = 0x2000,
1069         .bd_ram_size            = SZ_8K,
1070         .rx_descs               = 64,
1071         .mac_control            = BIT(5), /* MIIEN */
1072         .gigabit_en             = 1,
1073         .host_port_num          = 0,
1074         .no_bd_ram              = false,
1075         .version                = CPSW_VERSION_2,
1076 };
1078 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1079         .bus_freq       = AM33XX_EMAC_MDIO_FREQ,
1080 };
1082 static struct resource am33xx_cpsw_mdioresources[] = {
1083         {
1084                 .start  = AM33XX_CPSW_MDIO_BASE,
1085                 .end    = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1086                 .flags  = IORESOURCE_MEM,
1087         },
1088 };
1090 static struct platform_device am33xx_cpsw_mdiodevice = {
1091         .name           = "davinci_mdio",
1092         .id             = 0,
1093         .num_resources  = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1094         .resource       = am33xx_cpsw_mdioresources,
1095         .dev.platform_data = &am33xx_cpsw_mdiopdata,
1096 };
1098 static struct resource am33xx_cpsw_resources[] = {
1099         {
1100                 .start  = AM33XX_CPSW_BASE,
1101                 .end    = AM33XX_CPSW_BASE + SZ_2K - 1,
1102                 .flags  = IORESOURCE_MEM,
1103         },
1104         {
1105                 .start  = AM33XX_CPSW_SS_BASE,
1106                 .end    = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1107                 .flags  = IORESOURCE_MEM,
1108         },
1109         {
1110                 .start  = AM33XX_IRQ_CPSW_C0_RX,
1111                 .end    = AM33XX_IRQ_CPSW_C0_RX,
1112                 .flags  = IORESOURCE_IRQ,
1113         },
1114         {
1115                 .start  = AM33XX_IRQ_CPSW_RX,
1116                 .end    = AM33XX_IRQ_CPSW_RX,
1117                 .flags  = IORESOURCE_IRQ,
1118         },
1119         {
1120                 .start  = AM33XX_IRQ_CPSW_TX,
1121                 .end    = AM33XX_IRQ_CPSW_TX,
1122                 .flags  = IORESOURCE_IRQ,
1123         },
1124         {
1125                 .start  = AM33XX_IRQ_CPSW_C0,
1126                 .end    = AM33XX_IRQ_CPSW_C0,
1127                 .flags  = IORESOURCE_IRQ,
1128         },
1129 };
1131 static struct platform_device am33xx_cpsw_device = {
1132         .name           =       "cpsw",
1133         .id             =       0,
1134         .num_resources  =       ARRAY_SIZE(am33xx_cpsw_resources),
1135         .resource       =       am33xx_cpsw_resources,
1136         .dev            =       {
1137                                         .platform_data  = &am33xx_cpsw_pdata,
1138                                         .dma_mask       = &am33xx_cpsw_dmamask,
1139                                         .coherent_dma_mask = DMA_BIT_MASK(32),
1140                                 },
1141 };
1143 static unsigned char  am33xx_macid0[ETH_ALEN];
1144 static unsigned char  am33xx_macid1[ETH_ALEN];
1145 static unsigned int   am33xx_evmid;
1147 /*
1148 * am33xx_evmid_fillup - set up board evmid
1149 * @evmid - evm id which needs to be configured
1151 * This function is called to configure board evm id.
1152 * IA Motor Control EVM needs special setting of MAC PHY Id.
1153 * This function is called when IA Motor Control EVM is detected
1154 * during boot-up.
1155 */
1156 void am33xx_evmid_fillup(unsigned int evmid)
1158         am33xx_evmid = evmid;
1159         return;
1162 /*
1163 * am33xx_cpsw_macidfillup - setup mac adrresses
1164 * @eeprommacid0 - mac id 0 which needs to be configured
1165 * @eeprommacid1 - mac id 1 which needs to be configured
1167 * This function is called to configure mac addresses.
1168 * Mac addresses are read from eeprom and this function is called
1169 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1170 * In case, mac address read from eFuse are invalid, mac addresses
1171 * stored in these variable are used.
1172 */
1173 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1175         u32 i;
1177         /* Fillup these mac addresses with the mac adresses from eeprom */
1178         for (i = 0; i < ETH_ALEN; i++) {
1179                 am33xx_macid0[i] = eeprommacid0[i];
1180                 am33xx_macid1[i] = eeprommacid1[i];
1181         }
1183         return;
1186 void am33xx_cpsw_init(void)
1188         u32 mac_lo, mac_hi;
1189         u32 i;
1191         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1192         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1193         am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1194         am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1195         am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1196         am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1197         am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1198         am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1200         /* Read MACID0 from eeprom if eFuse MACID is invalid */
1201         if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1202                 for (i = 0; i < ETH_ALEN; i++)
1203                         am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1204         }
1206         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1207         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1208         am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1209         am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1210         am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1211         am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1212         am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1213         am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1215         /* Read MACID1 from eeprom if eFuse MACID is invalid */
1216         if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1217                 for (i = 0; i < ETH_ALEN; i++)
1218                         am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1219         }
1221         platform_device_register(&am33xx_cpsw_mdiodevice);
1222         platform_device_register(&am33xx_cpsw_device);
1223         clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1224                         NULL, &am33xx_cpsw_device.dev);
1228 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1229 static int __init omap_init_wdt(void)
1231         int id = -1;
1232         struct platform_device *pdev;
1233         struct omap_hwmod *oh;
1234         char *oh_name = "wd_timer2";
1235         char *dev_name = "omap_wdt";
1237         if (!cpu_class_is_omap2())
1238                 return 0;
1240         oh = omap_hwmod_lookup(oh_name);
1241         if (!oh) {
1242                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1243                 return -EINVAL;
1244         }
1246         pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1247         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1248                                 dev_name, oh->name);
1249         return 0;
1251 subsys_initcall(omap_init_wdt);
1252 #endif