2f342fbb0e7854ce10eb9087389230b21a3a3cbb
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / devices.c
1 /*
2  * linux/arch/arm/mach-omap2/devices.c
3  *
4  * OMAP2 platform device setup/initialization
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 #include <linux/gpio.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
25 #include <mach/hardware.h>
26 #include <mach/irqs.h>
27 #include <mach/board-am335xevm.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/map.h>
30 #include <asm/pmu.h>
32 #ifdef  CONFIG_OMAP3_EDMA
33 #include <mach/edma.h>
34 #endif
36 #include <asm/hardware/asp.h>
38 #include <plat/tc.h>
39 #include <plat/board.h>
40 #include <plat/mcbsp.h>
41 #include <plat/mmc.h>
42 #include <plat/dma.h>
43 #include <plat/omap_hwmod.h>
44 #include <plat/omap_device.h>
45 #include <plat/omap4-keypad.h>
47 /* LCD controller similar DA8xx */
48 #include <video/da8xx-fb.h>
50 #include "mux.h"
51 #include "control.h"
52 #include "devices.h"
54 #define L3_MODULES_MAX_LEN 12
55 #define L3_MODULES 3
57 void am33xx_cpsw_init(void);
59 static int __init omap3_l3_init(void)
60 {
61         int l;
62         struct omap_hwmod *oh;
63         struct platform_device *pdev;
64         char oh_name[L3_MODULES_MAX_LEN];
66         /*
67          * To avoid code running on other OMAPs in
68          * multi-omap builds
69          */
70         if (!(cpu_is_omap34xx()))
71                 return -ENODEV;
73         l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
75         oh = omap_hwmod_lookup(oh_name);
77         if (!oh)
78                 pr_err("could not look up %s\n", oh_name);
80         pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
81                                                            NULL, 0, 0);
83         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
85         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
86 }
87 postcore_initcall(omap3_l3_init);
89 static int __init omap4_l3_init(void)
90 {
91         int l, i;
92         struct omap_hwmod *oh[3];
93         struct platform_device *pdev;
94         char oh_name[L3_MODULES_MAX_LEN];
96         /* If dtb is there, the devices will be created dynamically */
97         if (of_have_populated_dt())
98                 return -ENODEV;
100         /*
101          * To avoid code running on other OMAPs in
102          * multi-omap builds
103          */
104         if (!(cpu_is_omap44xx()))
105                 return -ENODEV;
107         for (i = 0; i < L3_MODULES; i++) {
108                 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
110                 oh[i] = omap_hwmod_lookup(oh_name);
111                 if (!(oh[i]))
112                         pr_err("could not look up %s\n", oh_name);
113         }
115         pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
116                                                      0, NULL, 0, 0);
118         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
120         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
122 postcore_initcall(omap4_l3_init);
124 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
126 static struct resource omap2cam_resources[] = {
127         {
128                 .start          = OMAP24XX_CAMERA_BASE,
129                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
130                 .flags          = IORESOURCE_MEM,
131         },
132         {
133                 .start          = INT_24XX_CAM_IRQ,
134                 .flags          = IORESOURCE_IRQ,
135         }
136 };
138 static struct platform_device omap2cam_device = {
139         .name           = "omap24xxcam",
140         .id             = -1,
141         .num_resources  = ARRAY_SIZE(omap2cam_resources),
142         .resource       = omap2cam_resources,
143 };
144 #endif
145 #define L4_PER_LCDC_PHYS        0x4830E000
147 static struct resource am33xx_lcdc_resources[] = {
148         [0] = { /* registers */
149                 .start  = L4_PER_LCDC_PHYS,
150                 .end    = L4_PER_LCDC_PHYS + SZ_4K - 1,
151                 .flags  = IORESOURCE_MEM,
152         },
153         [1] = { /* interrupt */
154                 .start  = AM33XX_IRQ_LCD,
155                 .end    = AM33XX_IRQ_LCD,
156                 .flags  = IORESOURCE_IRQ,
157         },
158 };
160 static struct platform_device am33xx_lcdc_device = {
161         .name           = "da8xx_lcdc",
162         .id             = 0,
163         .num_resources  = ARRAY_SIZE(am33xx_lcdc_resources),
164         .resource       = am33xx_lcdc_resources,
165 };
167 void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
169         int ret;
171         am33xx_lcdc_device.dev.platform_data = pdata;
173         ret = platform_device_register(&am33xx_lcdc_device);
174         if (ret)
175                 pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n",
176                                 ret);
180 #if defined(CONFIG_SND_AM335X_SOC_EVM) || \
181                                 defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
182 static struct resource am335x_mcasp1_resource[] = {
183         {
184                 .name = "mcasp1",
185                 .start = AM33XX_ASP1_BASE,
186                 .end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
187                 .flags = IORESOURCE_MEM,
188         },
189         /* TX event */
190         {
191                 .start = AM33XX_DMA_MCASP1_X,
192                 .end = AM33XX_DMA_MCASP1_X,
193                 .flags = IORESOURCE_DMA,
194         },
195         /* RX event */
196         {
197                 .start = AM33XX_DMA_MCASP1_R,
198                 .end = AM33XX_DMA_MCASP1_R,
199                 .flags = IORESOURCE_DMA,
200         },
201 };
203 static struct platform_device am335x_mcasp1_device = {
204         .name = "davinci-mcasp",
205         .id = 1,
206         .num_resources = ARRAY_SIZE(am335x_mcasp1_resource),
207         .resource = am335x_mcasp1_resource,
208 };
210 void __init am335x_register_mcasp1(struct snd_platform_data *pdata)
212         am335x_mcasp1_device.dev.platform_data = pdata;
213         platform_device_register(&am335x_mcasp1_device);
216 #else
217 void __init am335x_register_mcasp1(struct snd_platform_data *pdata) {}
218 #endif
220 #if (defined(CONFIG_SND_AM33XX_SOC) || (defined(CONFIG_SND_AM33XX_SOC_MODULE)))
221 struct platform_device am33xx_pcm_device = {
222         .name           = "davinci-pcm-audio",
223         .id             = -1,
224 };
226 static void am33xx_init_pcm(void)
228         platform_device_register(&am33xx_pcm_device);
231 #else
232 static inline void am33xx_init_pcm(void) {}
233 #endif
235 static struct resource omap3isp_resources[] = {
236         {
237                 .start          = OMAP3430_ISP_BASE,
238                 .end            = OMAP3430_ISP_END,
239                 .flags          = IORESOURCE_MEM,
240         },
241         {
242                 .start          = OMAP3430_ISP_CCP2_BASE,
243                 .end            = OMAP3430_ISP_CCP2_END,
244                 .flags          = IORESOURCE_MEM,
245         },
246         {
247                 .start          = OMAP3430_ISP_CCDC_BASE,
248                 .end            = OMAP3430_ISP_CCDC_END,
249                 .flags          = IORESOURCE_MEM,
250         },
251         {
252                 .start          = OMAP3430_ISP_HIST_BASE,
253                 .end            = OMAP3430_ISP_HIST_END,
254                 .flags          = IORESOURCE_MEM,
255         },
256         {
257                 .start          = OMAP3430_ISP_H3A_BASE,
258                 .end            = OMAP3430_ISP_H3A_END,
259                 .flags          = IORESOURCE_MEM,
260         },
261         {
262                 .start          = OMAP3430_ISP_PREV_BASE,
263                 .end            = OMAP3430_ISP_PREV_END,
264                 .flags          = IORESOURCE_MEM,
265         },
266         {
267                 .start          = OMAP3430_ISP_RESZ_BASE,
268                 .end            = OMAP3430_ISP_RESZ_END,
269                 .flags          = IORESOURCE_MEM,
270         },
271         {
272                 .start          = OMAP3430_ISP_SBL_BASE,
273                 .end            = OMAP3430_ISP_SBL_END,
274                 .flags          = IORESOURCE_MEM,
275         },
276         {
277                 .start          = OMAP3430_ISP_CSI2A_REGS1_BASE,
278                 .end            = OMAP3430_ISP_CSI2A_REGS1_END,
279                 .flags          = IORESOURCE_MEM,
280         },
281         {
282                 .start          = OMAP3430_ISP_CSIPHY2_BASE,
283                 .end            = OMAP3430_ISP_CSIPHY2_END,
284                 .flags          = IORESOURCE_MEM,
285         },
286         {
287                 .start          = OMAP3630_ISP_CSI2A_REGS2_BASE,
288                 .end            = OMAP3630_ISP_CSI2A_REGS2_END,
289                 .flags          = IORESOURCE_MEM,
290         },
291         {
292                 .start          = OMAP3630_ISP_CSI2C_REGS1_BASE,
293                 .end            = OMAP3630_ISP_CSI2C_REGS1_END,
294                 .flags          = IORESOURCE_MEM,
295         },
296         {
297                 .start          = OMAP3630_ISP_CSIPHY1_BASE,
298                 .end            = OMAP3630_ISP_CSIPHY1_END,
299                 .flags          = IORESOURCE_MEM,
300         },
301         {
302                 .start          = OMAP3630_ISP_CSI2C_REGS2_BASE,
303                 .end            = OMAP3630_ISP_CSI2C_REGS2_END,
304                 .flags          = IORESOURCE_MEM,
305         },
306         {
307                 .start          = INT_34XX_CAM_IRQ,
308                 .flags          = IORESOURCE_IRQ,
309         }
310 };
312 static struct platform_device omap3isp_device = {
313         .name           = "omap3isp",
314         .id             = -1,
315         .num_resources  = ARRAY_SIZE(omap3isp_resources),
316         .resource       = omap3isp_resources,
317 };
319 int omap3_init_camera(struct isp_platform_data *pdata)
321         omap3isp_device.dev.platform_data = pdata;
322         return platform_device_register(&omap3isp_device);
325 static inline void omap_init_camera(void)
327 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
328         if (cpu_is_omap24xx())
329                 platform_device_register(&omap2cam_device);
330 #endif
333 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
334                         *sdp4430_keypad_data, struct omap_board_data *bdata)
336         struct platform_device *pdev;
337         struct omap_hwmod *oh;
338         struct omap4_keypad_platform_data *keypad_data;
339         unsigned int id = -1;
340         char *oh_name = "kbd";
341         char *name = "omap4-keypad";
343         oh = omap_hwmod_lookup(oh_name);
344         if (!oh) {
345                 pr_err("Could not look up %s\n", oh_name);
346                 return -ENODEV;
347         }
349         keypad_data = sdp4430_keypad_data;
351         pdev = omap_device_build(name, id, oh, keypad_data,
352                         sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
354         if (IS_ERR(pdev)) {
355                 WARN(1, "Can't build omap_device for %s:%s.\n",
356                                                 name, oh->name);
357                 return PTR_ERR(pdev);
358         }
359         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
361         return 0;
364 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
365 static inline void omap_init_mbox(void)
367         struct omap_hwmod *oh;
368         struct platform_device *pdev;
370         oh = omap_hwmod_lookup("mailbox");
371         if (!oh) {
372                 pr_err("%s: unable to find hwmod\n", __func__);
373                 return;
374         }
376         pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
377         WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
378                                                 __func__, PTR_ERR(pdev));
380 #else
381 static inline void omap_init_mbox(void) { }
382 #endif /* CONFIG_OMAP_MBOX_FWK */
384 static inline void omap_init_sti(void) {}
386 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
388 static struct platform_device omap_pcm = {
389         .name   = "omap-pcm-audio",
390         .id     = -1,
391 };
393 /*
394  * OMAP2420 has 2 McBSP ports
395  * OMAP2430 has 5 McBSP ports
396  * OMAP3 has 5 McBSP ports
397  * OMAP4 has 4 McBSP ports
398  */
399 OMAP_MCBSP_PLATFORM_DEVICE(1);
400 OMAP_MCBSP_PLATFORM_DEVICE(2);
401 OMAP_MCBSP_PLATFORM_DEVICE(3);
402 OMAP_MCBSP_PLATFORM_DEVICE(4);
403 OMAP_MCBSP_PLATFORM_DEVICE(5);
405 static void omap_init_audio(void)
407         platform_device_register(&omap_mcbsp1);
408         platform_device_register(&omap_mcbsp2);
409         if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
410                 platform_device_register(&omap_mcbsp3);
411                 platform_device_register(&omap_mcbsp4);
412         }
413         if (cpu_is_omap243x() || cpu_is_omap34xx())
414                 platform_device_register(&omap_mcbsp5);
416         platform_device_register(&omap_pcm);
419 #else
420 static inline void omap_init_audio(void) {}
421 #endif
423 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
424                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
426 static void omap_init_mcpdm(void)
428         struct omap_hwmod *oh;
429         struct platform_device *pdev;
431         oh = omap_hwmod_lookup("mcpdm");
432         if (!oh) {
433                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
434                 return;
435         }
437         pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
438         WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
440 #else
441 static inline void omap_init_mcpdm(void) {}
442 #endif
444 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
445                 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
447 static void omap_init_dmic(void)
449         struct omap_hwmod *oh;
450         struct platform_device *pdev;
452         oh = omap_hwmod_lookup("dmic");
453         if (!oh) {
454                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
455                 return;
456         }
458         pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
459         WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
461 #else
462 static inline void omap_init_dmic(void) {}
463 #endif
465 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
467 #include <plat/mcspi.h>
469 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
471         struct platform_device *pdev;
472         char *name = "omap2_mcspi";
473         struct omap2_mcspi_platform_config *pdata;
474         static int spi_num;
475         struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
477         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
478         if (!pdata) {
479                 pr_err("Memory allocation for McSPI device failed\n");
480                 return -ENOMEM;
481         }
483         pdata->num_cs = mcspi_attrib->num_chipselect;
484         switch (oh->class->rev) {
485         case OMAP2_MCSPI_REV:
486         case OMAP3_MCSPI_REV:
487                         pdata->regs_offset = 0;
488                         break;
489         case OMAP4_MCSPI_REV:
490                         pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
491                         break;
492         default:
493                         pr_err("Invalid McSPI Revision value\n");
494                         return -EINVAL;
495         }
497         spi_num++;
498         pdev = omap_device_build(name, spi_num, oh, pdata,
499                                 sizeof(*pdata), NULL, 0, 0);
500         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
501                                 name, oh->name);
502         kfree(pdata);
503         return 0;
506 static void omap_init_mcspi(void)
508         omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
511 #else
512 static inline void omap_init_mcspi(void) {}
513 #endif
515 #ifdef CONFIG_SOC_OMAPAM33XX
517 static int omap_elm_init(struct omap_hwmod *oh, void *unused)
519         struct platform_device *pdev;
520         char *name = "omap2_elm";
521         static int elm_num;
524         elm_num++;
525         pdev = omap_device_build(name, elm_num, oh, NULL,
526                                 0,      NULL,
527                                 0, 0);
528         return 0;
531 static void omap_init_elm(void)
534         omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL);
537 #else
538 static void omap_init_elm(void) {}
539 #endif
542 static struct resource omap2_pmu_resource = {
543         .start  = 3,
544         .end    = 3,
545         .flags  = IORESOURCE_IRQ,
546 };
548 static struct resource omap3_pmu_resource = {
549         .start  = INT_34XX_BENCH_MPU_EMUL,
550         .end    = INT_34XX_BENCH_MPU_EMUL,
551         .flags  = IORESOURCE_IRQ,
552 };
554 static struct platform_device omap_pmu_device = {
555         .name           = "arm-pmu",
556         .id             = ARM_PMU_DEVICE_CPU,
557         .num_resources  = 1,
558 };
560 static void omap_init_pmu(void)
562         if (cpu_is_omap24xx())
563                 omap_pmu_device.resource = &omap2_pmu_resource;
564         else if (cpu_is_omap34xx())
565                 omap_pmu_device.resource = &omap3_pmu_resource;
566         else
567                 return;
569         platform_device_register(&omap_pmu_device);
573 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
575 #ifdef CONFIG_ARCH_OMAP2
576 static struct resource omap2_sham_resources[] = {
577         {
578                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
579                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
580                 .flags  = IORESOURCE_MEM,
581         },
582         {
583                 .start  = INT_24XX_SHA1MD5,
584                 .flags  = IORESOURCE_IRQ,
585         }
586 };
587 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
588 #else
589 #define omap2_sham_resources            NULL
590 #define omap2_sham_resources_sz         0
591 #endif
593 #ifdef CONFIG_ARCH_OMAP3
594 static struct resource omap3_sham_resources[] = {
595         {
596                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
597                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
598                 .flags  = IORESOURCE_MEM,
599         },
600         {
601                 .start  = INT_34XX_SHA1MD52_IRQ,
602                 .flags  = IORESOURCE_IRQ,
603         },
604         {
605                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
606                 .flags  = IORESOURCE_DMA,
607         }
608 };
609 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
610 #else
611 #define omap3_sham_resources            NULL
612 #define omap3_sham_resources_sz         0
613 #endif
615 static struct platform_device sham_device = {
616         .name           = "omap-sham",
617         .id             = -1,
618 };
620 static void omap_init_sham(void)
622         if (cpu_is_omap24xx()) {
623                 sham_device.resource = omap2_sham_resources;
624                 sham_device.num_resources = omap2_sham_resources_sz;
625         } else if (cpu_is_omap34xx()) {
626                 sham_device.resource = omap3_sham_resources;
627                 sham_device.num_resources = omap3_sham_resources_sz;
628         } else {
629                 pr_err("%s: platform not supported\n", __func__);
630                 return;
631         }
632         platform_device_register(&sham_device);
634 #else
635 static inline void omap_init_sham(void) { }
636 #endif
638 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
640 #ifdef CONFIG_ARCH_OMAP2
641 static struct resource omap2_aes_resources[] = {
642         {
643                 .start  = OMAP24XX_SEC_AES_BASE,
644                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
645                 .flags  = IORESOURCE_MEM,
646         },
647         {
648                 .start  = OMAP24XX_DMA_AES_TX,
649                 .flags  = IORESOURCE_DMA,
650         },
651         {
652                 .start  = OMAP24XX_DMA_AES_RX,
653                 .flags  = IORESOURCE_DMA,
654         }
655 };
656 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
657 #else
658 #define omap2_aes_resources             NULL
659 #define omap2_aes_resources_sz          0
660 #endif
662 #ifdef CONFIG_ARCH_OMAP3
663 static struct resource omap3_aes_resources[] = {
664         {
665                 .start  = OMAP34XX_SEC_AES_BASE,
666                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
667                 .flags  = IORESOURCE_MEM,
668         },
669         {
670                 .start  = OMAP34XX_DMA_AES2_TX,
671                 .flags  = IORESOURCE_DMA,
672         },
673         {
674                 .start  = OMAP34XX_DMA_AES2_RX,
675                 .flags  = IORESOURCE_DMA,
676         }
677 };
678 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
679 #else
680 #define omap3_aes_resources             NULL
681 #define omap3_aes_resources_sz          0
682 #endif
684 static struct platform_device aes_device = {
685         .name           = "omap-aes",
686         .id             = -1,
687 };
689 static void omap_init_aes(void)
691         if (cpu_is_omap24xx()) {
692                 aes_device.resource = omap2_aes_resources;
693                 aes_device.num_resources = omap2_aes_resources_sz;
694         } else if (cpu_is_omap34xx()) {
695                 aes_device.resource = omap3_aes_resources;
696                 aes_device.num_resources = omap3_aes_resources_sz;
697         } else {
698                 pr_err("%s: platform not supported\n", __func__);
699                 return;
700         }
701         platform_device_register(&aes_device);
704 #else
705 static inline void omap_init_aes(void) { }
706 #endif
708 /*-------------------------------------------------------------------------*/
710 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
712 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
713                                                         *mmc_controller)
715         if ((mmc_controller->slots[0].switch_pin > 0) && \
716                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
717                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
718                                         OMAP_PIN_INPUT_PULLUP);
719         if ((mmc_controller->slots[0].gpio_wp > 0) && \
720                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
721                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
722                                         OMAP_PIN_INPUT_PULLUP);
724         omap_mux_init_signal("sdmmc_cmd", 0);
725         omap_mux_init_signal("sdmmc_clki", 0);
726         omap_mux_init_signal("sdmmc_clko", 0);
727         omap_mux_init_signal("sdmmc_dat0", 0);
728         omap_mux_init_signal("sdmmc_dat_dir0", 0);
729         omap_mux_init_signal("sdmmc_cmd_dir", 0);
730         if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
731                 omap_mux_init_signal("sdmmc_dat1", 0);
732                 omap_mux_init_signal("sdmmc_dat2", 0);
733                 omap_mux_init_signal("sdmmc_dat3", 0);
734                 omap_mux_init_signal("sdmmc_dat_dir1", 0);
735                 omap_mux_init_signal("sdmmc_dat_dir2", 0);
736                 omap_mux_init_signal("sdmmc_dat_dir3", 0);
737         }
739         /*
740          * Use internal loop-back in MMC/SDIO Module Input Clock
741          * selection
742          */
743         if (mmc_controller->slots[0].internal_clock) {
744                 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
745                 v |= (1 << 24);
746                 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
747         }
750 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
752         char *name = "mmci-omap";
754         if (!mmc_data[0]) {
755                 pr_err("%s fails: Incomplete platform data\n", __func__);
756                 return;
757         }
759         omap242x_mmc_mux(mmc_data[0]);
760         omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
761                                         INT_24XX_MMC_IRQ, mmc_data[0]);
764 #endif
766 /*-------------------------------------------------------------------------*/
768 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
769 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
770 #define OMAP_HDQ_BASE   0x480B2000
771 #endif
772 static struct resource omap_hdq_resources[] = {
773         {
774                 .start          = OMAP_HDQ_BASE,
775                 .end            = OMAP_HDQ_BASE + 0x1C,
776                 .flags          = IORESOURCE_MEM,
777         },
778         {
779                 .start          = INT_24XX_HDQ_IRQ,
780                 .flags          = IORESOURCE_IRQ,
781         },
782 };
783 static struct platform_device omap_hdq_dev = {
784         .name = "omap_hdq",
785         .id = 0,
786         .dev = {
787                 .platform_data = NULL,
788         },
789         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
790         .resource       = omap_hdq_resources,
791 };
792 static inline void omap_hdq_init(void)
794         (void) platform_device_register(&omap_hdq_dev);
796 #else
797 static inline void omap_hdq_init(void) {}
798 #endif
800 /*---------------------------------------------------------------------------*/
802 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
803         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
804 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
805 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
806 };
807 #else
808 static struct resource omap_vout_resource[2] = {
809 };
810 #endif
812 static struct platform_device omap_vout_device = {
813         .name           = "omap_vout",
814         .num_resources  = ARRAY_SIZE(omap_vout_resource),
815         .resource       = &omap_vout_resource[0],
816         .id             = -1,
817 };
818 static void omap_init_vout(void)
820         if (platform_device_register(&omap_vout_device) < 0)
821                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
823 #else
824 static inline void omap_init_vout(void) {}
825 #endif
827 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
829 #define AM33XX_TPCC_BASE                0x49000000
830 #define AM33XX_TPTC0_BASE               0x49800000
831 #define AM33XX_TPTC1_BASE               0x49900000
832 #define AM33XX_TPTC2_BASE               0x49a00000
834 #define AM33XX_SCM_BASE_EDMA            0x00000f90
836 static struct resource am33xx_edma_resources[] = {
837         {
838                 .name   = "edma_cc0",
839                 .start  = AM33XX_TPCC_BASE,
840                 .end    = AM33XX_TPCC_BASE + SZ_32K - 1,
841                 .flags  = IORESOURCE_MEM,
842         },
843         {
844                 .name   = "edma_tc0",
845                 .start  = AM33XX_TPTC0_BASE,
846                 .end    = AM33XX_TPTC0_BASE + SZ_1K - 1,
847                 .flags  = IORESOURCE_MEM,
848         },
849         {
850                 .name   = "edma_tc1",
851                 .start  = AM33XX_TPTC1_BASE,
852                 .end    = AM33XX_TPTC1_BASE + SZ_1K - 1,
853                 .flags  = IORESOURCE_MEM,
854         },
855         {
856                 .name   = "edma_tc2",
857                 .start  = AM33XX_TPTC2_BASE,
858                 .end    = AM33XX_TPTC2_BASE + SZ_1K - 1,
859                 .flags  = IORESOURCE_MEM,
860         },
861         {
862                 .name   = "edma0",
863                 .start  = AM33XX_IRQ_TPCC0_INT_PO0,
864                 .flags  = IORESOURCE_IRQ,
865         },
866         {
867                 .name   = "edma0_err",
868                 .start  = AM33XX_IRQ_TPCC0_ERRINT_PO,
869                 .flags  = IORESOURCE_IRQ,
870         },
871 };
873 static const s16 am33xx_dma_rsv_chans[][2] = {
874         /* (offset, number) */
875         {0, 2},
876         {14, 2},
877         {26, 6},
878         {48, 4},
879         {56, 8},
880         {-1, -1}
881 };
883 static const s16 am33xx_dma_rsv_slots[][2] = {
884         /* (offset, number) */
885         {0, 2},
886         {14, 2},
887         {26, 6},
888         {48, 4},
889         {56, 8},
890         {64, 127},
891         {-1, -1}
892 };
894 /* Three Transfer Controllers on AM33XX */
895 static const s8 am33xx_queue_tc_mapping[][2] = {
896         /* {event queue no, TC no} */
897         {0, 0},
898         {1, 1},
899         {2, 2},
900         {-1, -1}
901 };
903 static const s8 am33xx_queue_priority_mapping[][2] = {
904         /* {event queue no, Priority} */
905         {0, 0},
906         {1, 1},
907         {2, 2},
908         {-1, -1}
909 };
911 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
912         /* {xbar event no, Channel} */
913         {1, 12},        /* SDTXEVT1 -> MMCHS2 */
914         {2, 13},        /* SDRXEVT1 -> MMCHS2 */
915         {3, -1},
916         {4, -1},
917         {5, -1},
918         {6, -1},
919         {7, -1},
920         {8, -1},
921         {9, -1},
922         {10, -1},
923         {11, -1},
924         {12, -1},
925         {13, -1},
926         {14, -1},
927         {15, -1},
928         {16, -1},
929         {17, -1},
930         {18, -1},
931         {19, -1},
932         {20, -1},
933         {21, -1},
934         {22, -1},
935         {23, -1},
936         {24, -1},
937         {25, -1},
938         {26, -1},
939         {27, -1},
940         {28, -1},
941         {29, -1},
942         {30, -1},
943         {31, -1},
944         {-1, -1}
945 };
947 /**
948  * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
949  * according to the configuration provided
950  * @event: the event number for which mapping is required
951  * @channel: channel being activated
952  * @xbar_event_mapping: array that has the event to channel map
953  *
954  * Events that are routed by default are not mapped. Only events that
955  * are crossbar mapped are routed to available channels according to
956  * the configuration provided
957  *
958  * Returns zero on success, else negative errno.
959  */
960 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
961                         struct event_to_channel_map *xbar_event_mapping)
963         unsigned int ctrl = 0;
964         unsigned int xbar_evt_no = 0;
965         unsigned int val = 0;
966         unsigned int offset = 0;
967         unsigned int mask = 0;
969         ctrl = EDMA_CTLR(event);
970         xbar_evt_no = event - (edma_info[ctrl]->num_channels);
972         if (event < edma_info[ctrl]->num_channels) {
973                 *channel = event;
974         } else if (event < edma_info[ctrl]->num_events) {
975                 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
976                 /* confirm the range */
977                 if (*channel < EDMA_MAX_DMACH)
978                         clear_bit(*channel, edma_info[ctrl]->edma_unused);
979                 mask = (*channel)%4;
980                 offset = (*channel)/4;
981                 offset *= 4;
982                 offset += mask;
983                 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
984                                         AM33XX_SCM_BASE_EDMA + offset));
985                 val = val & (~(0xFF));
986                 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
987                 __raw_writel(val,
988                         AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
989                 return 0;
990         } else {
991                 return -EINVAL;
992         }
994         return 0;
997 static struct edma_soc_info am33xx_edma_info[] = {
998         {
999                 .n_channel              = 64,
1000                 .n_region               = 4,
1001                 .n_slot                 = 256,
1002                 .n_tc                   = 3,
1003                 .n_cc                   = 1,
1004                 .rsv_chans              = am33xx_dma_rsv_chans,
1005                 .rsv_slots              = am33xx_dma_rsv_slots,
1006                 .queue_tc_mapping       = am33xx_queue_tc_mapping,
1007                 .queue_priority_mapping = am33xx_queue_priority_mapping,
1008                 .is_xbar                = 1,
1009                 .n_events               = 95,
1010                 .xbar_event_mapping     = am33xx_xbar_event_mapping,
1011                 .map_xbar_channel       = map_xbar_event_to_channel,
1012         },
1013 };
1015 static struct platform_device am33xx_edma_device = {
1016         .name           = "edma",
1017         .id             = -1,
1018         .dev = {
1019                 .platform_data = am33xx_edma_info,
1020         },
1021         .num_resources  = ARRAY_SIZE(am33xx_edma_resources),
1022         .resource       = am33xx_edma_resources,
1023 };
1025 int __init am33xx_register_edma(void)
1027         struct platform_device *pdev;
1028         static struct clk *edma_clk;
1030         if (cpu_is_am33xx())
1031                 pdev = &am33xx_edma_device;
1032         else {
1033                 pr_err("%s: platform not supported\n", __func__);
1034                 return -ENODEV;
1035         }
1037         edma_clk = clk_get(NULL, "tpcc_ick");
1038         if (IS_ERR(edma_clk)) {
1039                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1040                 return -EBUSY;
1041         }
1042         clk_enable(edma_clk);
1043         edma_clk = clk_get(NULL, "tptc0_ick");
1044         if (IS_ERR(edma_clk)) {
1045                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1046                 return -EBUSY;
1047         }
1048         clk_enable(edma_clk);
1049         edma_clk = clk_get(NULL, "tptc1_ick");
1050         if (IS_ERR(edma_clk)) {
1051                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1052                 return -EBUSY;
1053         }
1054         clk_enable(edma_clk);
1055         edma_clk = clk_get(NULL, "tptc2_ick");
1056         if (IS_ERR(edma_clk)) {
1057                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1058                 return -EBUSY;
1059         }
1060         clk_enable(edma_clk);
1062         return platform_device_register(pdev);
1065 #else
1066 static inline void am33xx_register_edma(void) {}
1067 #endif
1069 /*-------------------------------------------------------------------------*/
1071 static int __init omap2_init_devices(void)
1073         /*
1074          * please keep these calls, and their implementations above,
1075          * in alphabetical order so they're easier to sort through.
1076          */
1077         omap_init_audio();
1078         omap_init_mcpdm();
1079         omap_init_dmic();
1080         omap_init_camera();
1081         omap_init_mbox();
1082         omap_init_mcspi();
1083         omap_init_elm();
1084         omap_init_pmu();
1085         omap_hdq_init();
1086         omap_init_sti();
1087         omap_init_sham();
1088         omap_init_aes();
1089         omap_init_vout();
1090         am33xx_register_edma();
1091         am33xx_init_pcm();
1093         return 0;
1095 arch_initcall(omap2_init_devices);
1097 #define AM33XX_CPSW_BASE                (0x4A100000)
1098 #define AM33XX_CPSW_MDIO_BASE           (0x4A101000)
1099 #define AM33XX_CPSW_SS_BASE             (0x4A101200)
1100 #define AM33XX_EMAC_MDIO_FREQ           (1000000)
1102 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
1103 /* TODO : Verify the offsets */
1104 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
1105         {
1106                 .slave_reg_ofs  = 0x208,
1107                 .sliver_reg_ofs = 0xd80,
1108                 .phy_id         = "0:00",
1109         },
1110         {
1111                 .slave_reg_ofs  = 0x308,
1112                 .sliver_reg_ofs = 0xdc0,
1113                 .phy_id         = "0:01",
1114         },
1115 };
1117 static struct cpsw_platform_data am33xx_cpsw_pdata = {
1118         .ss_reg_ofs             = 0x1200,
1119         .channels               = 8,
1120         .cpdma_reg_ofs          = 0x800,
1121         .slaves                 = 2,
1122         .slave_data             = am33xx_cpsw_slaves,
1123         .ale_reg_ofs            = 0xd00,
1124         .ale_entries            = 1024,
1125         .host_port_reg_ofs      = 0x108,
1126         .hw_stats_reg_ofs       = 0x900,
1127         .bd_ram_ofs             = 0x2000,
1128         .bd_ram_size            = SZ_8K,
1129         .rx_descs               = 64,
1130         .mac_control            = BIT(5), /* MIIEN */
1131         .gigabit_en             = 1,
1132         .host_port_num          = 0,
1133         .no_bd_ram              = false,
1134         .version                = CPSW_VERSION_2,
1135 };
1137 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1138         .bus_freq       = AM33XX_EMAC_MDIO_FREQ,
1139 };
1141 static struct resource am33xx_cpsw_mdioresources[] = {
1142         {
1143                 .start  = AM33XX_CPSW_MDIO_BASE,
1144                 .end    = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1145                 .flags  = IORESOURCE_MEM,
1146         },
1147 };
1149 static struct platform_device am33xx_cpsw_mdiodevice = {
1150         .name           = "davinci_mdio",
1151         .id             = 0,
1152         .num_resources  = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1153         .resource       = am33xx_cpsw_mdioresources,
1154         .dev.platform_data = &am33xx_cpsw_mdiopdata,
1155 };
1157 static struct resource am33xx_cpsw_resources[] = {
1158         {
1159                 .start  = AM33XX_CPSW_BASE,
1160                 .end    = AM33XX_CPSW_BASE + SZ_2K - 1,
1161                 .flags  = IORESOURCE_MEM,
1162         },
1163         {
1164                 .start  = AM33XX_CPSW_SS_BASE,
1165                 .end    = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1166                 .flags  = IORESOURCE_MEM,
1167         },
1168         {
1169                 .start  = AM33XX_IRQ_CPSW_C0_RX,
1170                 .end    = AM33XX_IRQ_CPSW_C0_RX,
1171                 .flags  = IORESOURCE_IRQ,
1172         },
1173         {
1174                 .start  = AM33XX_IRQ_CPSW_RX,
1175                 .end    = AM33XX_IRQ_CPSW_RX,
1176                 .flags  = IORESOURCE_IRQ,
1177         },
1178         {
1179                 .start  = AM33XX_IRQ_CPSW_TX,
1180                 .end    = AM33XX_IRQ_CPSW_TX,
1181                 .flags  = IORESOURCE_IRQ,
1182         },
1183         {
1184                 .start  = AM33XX_IRQ_CPSW_C0,
1185                 .end    = AM33XX_IRQ_CPSW_C0,
1186                 .flags  = IORESOURCE_IRQ,
1187         },
1188 };
1190 static struct platform_device am33xx_cpsw_device = {
1191         .name           =       "cpsw",
1192         .id             =       0,
1193         .num_resources  =       ARRAY_SIZE(am33xx_cpsw_resources),
1194         .resource       =       am33xx_cpsw_resources,
1195         .dev            =       {
1196                                         .platform_data  = &am33xx_cpsw_pdata,
1197                                         .dma_mask       = &am33xx_cpsw_dmamask,
1198                                         .coherent_dma_mask = DMA_BIT_MASK(32),
1199                                 },
1200 };
1202 static unsigned char  am33xx_macid0[ETH_ALEN];
1203 static unsigned char  am33xx_macid1[ETH_ALEN];
1204 static unsigned int   am33xx_evmid;
1206 /*
1207 * am33xx_evmid_fillup - set up board evmid
1208 * @evmid - evm id which needs to be configured
1210 * This function is called to configure board evm id.
1211 * IA Motor Control EVM needs special setting of MAC PHY Id.
1212 * This function is called when IA Motor Control EVM is detected
1213 * during boot-up.
1214 */
1215 void am33xx_evmid_fillup(unsigned int evmid)
1217         am33xx_evmid = evmid;
1218         return;
1221 /*
1222 * am33xx_cpsw_macidfillup - setup mac adrresses
1223 * @eeprommacid0 - mac id 0 which needs to be configured
1224 * @eeprommacid1 - mac id 1 which needs to be configured
1226 * This function is called to configure mac addresses.
1227 * Mac addresses are read from eeprom and this function is called
1228 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1229 * In case, mac address read from eFuse are invalid, mac addresses
1230 * stored in these variable are used.
1231 */
1232 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1234         u32 i;
1236         /* Fillup these mac addresses with the mac adresses from eeprom */
1237         for (i = 0; i < ETH_ALEN; i++) {
1238                 am33xx_macid0[i] = eeprommacid0[i];
1239                 am33xx_macid1[i] = eeprommacid1[i];
1240         }
1242         return;
1245 void am33xx_cpsw_init(void)
1247         u32 mac_lo, mac_hi;
1248         u32 i;
1250         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1251         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1252         am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1253         am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1254         am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1255         am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1256         am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1257         am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1259         /* Read MACID0 from eeprom if eFuse MACID is invalid */
1260         if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1261                 for (i = 0; i < ETH_ALEN; i++)
1262                         am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1263         }
1265         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1266         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1267         am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1268         am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1269         am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1270         am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1271         am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1272         am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1274         /* Read MACID1 from eeprom if eFuse MACID is invalid */
1275         if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1276                 for (i = 0; i < ETH_ALEN; i++)
1277                         am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1278         }
1280         if (am33xx_evmid == IND_AUT_MTR_EVM) {
1281                 am33xx_cpsw_slaves[0].phy_id = "0:1e";
1282                 am33xx_cpsw_slaves[1].phy_id = "0:00";
1283         }
1285         memcpy(am33xx_cpsw_pdata.mac_addr,
1286                         am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
1287         platform_device_register(&am33xx_cpsw_mdiodevice);
1288         platform_device_register(&am33xx_cpsw_device);
1289         clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1290                         NULL, &am33xx_cpsw_device.dev);
1294 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1295 static int __init omap_init_wdt(void)
1297         int id = -1;
1298         struct platform_device *pdev;
1299         struct omap_hwmod *oh;
1300         char *oh_name = "wd_timer2";
1301         char *dev_name = "omap_wdt";
1303         if (!cpu_class_is_omap2())
1304                 return 0;
1306         oh = omap_hwmod_lookup(oh_name);
1307         if (!oh) {
1308                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1309                 return -EINVAL;
1310         }
1312         pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1313         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1314                                 dev_name, oh->name);
1315         return 0;
1317 subsys_initcall(omap_init_wdt);
1318 #endif