33ecedf614aef7f7b26cd552aba986328ec939e0
1 /*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #include <linux/gpio.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/can/platform/d_can.h>
25 #include <linux/platform_data/uio_pruss.h>
26 #include <linux/pwm/pwm.h>
27 #include <linux/input/ti_tscadc.h>
29 #include <mach/hardware.h>
30 #include <mach/irqs.h>
31 #include <mach/board-am335xevm.h>
32 #include <asm/mach-types.h>
33 #include <asm/mach/map.h>
34 #include <asm/pmu.h>
36 #ifdef CONFIG_OMAP3_EDMA
37 #include <mach/edma.h>
38 #endif
40 #include <asm/hardware/asp.h>
42 #include <plat/tc.h>
43 #include <plat/board.h>
44 #include <plat/mcbsp.h>
45 #include <plat/mmc.h>
46 #include <plat/dma.h>
47 #include <plat/omap_hwmod.h>
48 #include <plat/omap_device.h>
49 #include <plat/omap4-keypad.h>
50 #include <plat/config_pwm.h>
51 #include <plat/cpu.h>
52 #include <plat/gpmc.h>
54 /* LCD controller similar DA8xx */
55 #include <video/da8xx-fb.h>
57 #include "mux.h"
58 #include "control.h"
59 #include "devices.h"
61 #define L3_MODULES_MAX_LEN 12
62 #define L3_MODULES 3
64 static int __init omap3_l3_init(void)
65 {
66 int l;
67 struct omap_hwmod *oh;
68 struct platform_device *pdev;
69 char oh_name[L3_MODULES_MAX_LEN];
71 /*
72 * To avoid code running on other OMAPs in
73 * multi-omap builds
74 */
75 if (!(cpu_is_omap34xx()) || (cpu_is_am33xx()))
76 return -ENODEV;
78 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
80 oh = omap_hwmod_lookup(oh_name);
82 if (!oh)
83 pr_err("could not look up %s\n", oh_name);
85 pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
86 NULL, 0, 0);
88 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
90 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
91 }
92 postcore_initcall(omap3_l3_init);
94 static int __init omap4_l3_init(void)
95 {
96 int l, i;
97 struct omap_hwmod *oh[3];
98 struct platform_device *pdev;
99 char oh_name[L3_MODULES_MAX_LEN];
101 /* If dtb is there, the devices will be created dynamically */
102 if (of_have_populated_dt())
103 return -ENODEV;
105 /*
106 * To avoid code running on other OMAPs in
107 * multi-omap builds
108 */
109 if (!(cpu_is_omap44xx()))
110 return -ENODEV;
112 for (i = 0; i < L3_MODULES; i++) {
113 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
115 oh[i] = omap_hwmod_lookup(oh_name);
116 if (!(oh[i]))
117 pr_err("could not look up %s\n", oh_name);
118 }
120 pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
121 0, NULL, 0, 0);
123 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
125 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
126 }
127 postcore_initcall(omap4_l3_init);
129 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
131 static struct resource omap2cam_resources[] = {
132 {
133 .start = OMAP24XX_CAMERA_BASE,
134 .end = OMAP24XX_CAMERA_BASE + 0xfff,
135 .flags = IORESOURCE_MEM,
136 },
137 {
138 .start = INT_24XX_CAM_IRQ,
139 .flags = IORESOURCE_IRQ,
140 }
141 };
143 static struct platform_device omap2cam_device = {
144 .name = "omap24xxcam",
145 .id = -1,
146 .num_resources = ARRAY_SIZE(omap2cam_resources),
147 .resource = omap2cam_resources,
148 };
149 #endif
151 int __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
152 {
153 int id = 0;
154 struct platform_device *pdev;
155 struct omap_hwmod *oh;
156 char *oh_name = "lcdc";
157 char *dev_name = "da8xx_lcdc";
159 oh = omap_hwmod_lookup(oh_name);
160 if (!oh) {
161 pr_err("Could not look up LCD%d hwmod\n", id);
162 return -ENODEV;
163 }
165 pdev = omap_device_build(dev_name, id, oh, pdata,
166 sizeof(struct da8xx_lcdc_platform_data), NULL, 0, 0);
167 if (IS_ERR(pdev)) {
168 WARN(1, "Can't build omap_device for %s:%s.\n",
169 dev_name, oh->name);
170 return PTR_ERR(pdev);
171 }
172 return 0;
173 }
175 int __init am33xx_register_tsc(struct tsc_data *pdata)
176 {
177 int id = -1;
178 struct platform_device *pdev;
179 struct omap_hwmod *oh;
180 char *oh_name = "adc_tsc";
181 char *dev_name = "tsc";
183 oh = omap_hwmod_lookup(oh_name);
184 if (!oh) {
185 pr_err("Could not look up TSC%d hwmod\n", id);
186 return -ENODEV;
187 }
189 pdev = omap_device_build(dev_name, id, oh, pdata,
190 sizeof(struct tsc_data), NULL, 0, 0);
192 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
193 dev_name, oh->name);
194 return 0;
195 }
197 #if defined(CONFIG_SND_AM335X_SOC_EVM) || \
198 defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
199 int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr)
200 {
201 int l;
202 struct omap_hwmod *oh;
203 struct platform_device *pdev;
204 char oh_name[12];
205 char *dev_name = "davinci-mcasp";
207 l = snprintf(oh_name, 12, "mcasp%d", ctrl_nr);
209 oh = omap_hwmod_lookup(oh_name);
210 if (!oh) {
211 pr_err("could not look up %s\n", oh_name);
212 return -ENODEV;
213 }
215 pdev = omap_device_build(dev_name, ctrl_nr, oh, pdata,
216 sizeof(struct snd_platform_data), NULL, 0, 0);
217 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
218 dev_name, oh->name);
219 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
220 }
222 #else
223 int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr)
224 {
225 return 0;
226 }
227 #endif
229 #if (defined(CONFIG_SND_AM33XX_SOC) || (defined(CONFIG_SND_AM33XX_SOC_MODULE)))
230 struct platform_device am33xx_pcm_device = {
231 .name = "davinci-pcm-audio",
232 .id = -1,
233 };
235 static void am33xx_init_pcm(void)
236 {
237 platform_device_register(&am33xx_pcm_device);
238 }
240 #else
241 static inline void am33xx_init_pcm(void) {}
242 #endif
244 static struct resource omap3isp_resources[] = {
245 {
246 .start = OMAP3430_ISP_BASE,
247 .end = OMAP3430_ISP_END,
248 .flags = IORESOURCE_MEM,
249 },
250 {
251 .start = OMAP3430_ISP_CCP2_BASE,
252 .end = OMAP3430_ISP_CCP2_END,
253 .flags = IORESOURCE_MEM,
254 },
255 {
256 .start = OMAP3430_ISP_CCDC_BASE,
257 .end = OMAP3430_ISP_CCDC_END,
258 .flags = IORESOURCE_MEM,
259 },
260 {
261 .start = OMAP3430_ISP_HIST_BASE,
262 .end = OMAP3430_ISP_HIST_END,
263 .flags = IORESOURCE_MEM,
264 },
265 {
266 .start = OMAP3430_ISP_H3A_BASE,
267 .end = OMAP3430_ISP_H3A_END,
268 .flags = IORESOURCE_MEM,
269 },
270 {
271 .start = OMAP3430_ISP_PREV_BASE,
272 .end = OMAP3430_ISP_PREV_END,
273 .flags = IORESOURCE_MEM,
274 },
275 {
276 .start = OMAP3430_ISP_RESZ_BASE,
277 .end = OMAP3430_ISP_RESZ_END,
278 .flags = IORESOURCE_MEM,
279 },
280 {
281 .start = OMAP3430_ISP_SBL_BASE,
282 .end = OMAP3430_ISP_SBL_END,
283 .flags = IORESOURCE_MEM,
284 },
285 {
286 .start = OMAP3430_ISP_CSI2A_REGS1_BASE,
287 .end = OMAP3430_ISP_CSI2A_REGS1_END,
288 .flags = IORESOURCE_MEM,
289 },
290 {
291 .start = OMAP3430_ISP_CSIPHY2_BASE,
292 .end = OMAP3430_ISP_CSIPHY2_END,
293 .flags = IORESOURCE_MEM,
294 },
295 {
296 .start = OMAP3630_ISP_CSI2A_REGS2_BASE,
297 .end = OMAP3630_ISP_CSI2A_REGS2_END,
298 .flags = IORESOURCE_MEM,
299 },
300 {
301 .start = OMAP3630_ISP_CSI2C_REGS1_BASE,
302 .end = OMAP3630_ISP_CSI2C_REGS1_END,
303 .flags = IORESOURCE_MEM,
304 },
305 {
306 .start = OMAP3630_ISP_CSIPHY1_BASE,
307 .end = OMAP3630_ISP_CSIPHY1_END,
308 .flags = IORESOURCE_MEM,
309 },
310 {
311 .start = OMAP3630_ISP_CSI2C_REGS2_BASE,
312 .end = OMAP3630_ISP_CSI2C_REGS2_END,
313 .flags = IORESOURCE_MEM,
314 },
315 {
316 .start = INT_34XX_CAM_IRQ,
317 .flags = IORESOURCE_IRQ,
318 }
319 };
321 static struct platform_device omap3isp_device = {
322 .name = "omap3isp",
323 .id = -1,
324 .num_resources = ARRAY_SIZE(omap3isp_resources),
325 .resource = omap3isp_resources,
326 };
328 int omap3_init_camera(struct isp_platform_data *pdata)
329 {
330 omap3isp_device.dev.platform_data = pdata;
331 return platform_device_register(&omap3isp_device);
332 }
334 static inline void omap_init_camera(void)
335 {
336 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
337 if (cpu_is_omap24xx())
338 platform_device_register(&omap2cam_device);
339 #endif
340 }
342 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
343 *sdp4430_keypad_data, struct omap_board_data *bdata)
344 {
345 struct platform_device *pdev;
346 struct omap_hwmod *oh;
347 struct omap4_keypad_platform_data *keypad_data;
348 unsigned int id = -1;
349 char *oh_name = "kbd";
350 char *name = "omap4-keypad";
352 oh = omap_hwmod_lookup(oh_name);
353 if (!oh) {
354 pr_err("Could not look up %s\n", oh_name);
355 return -ENODEV;
356 }
358 keypad_data = sdp4430_keypad_data;
360 pdev = omap_device_build(name, id, oh, keypad_data,
361 sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
363 if (IS_ERR(pdev)) {
364 WARN(1, "Can't build omap_device for %s:%s.\n",
365 name, oh->name);
366 return PTR_ERR(pdev);
367 }
368 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
370 return 0;
371 }
373 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
374 static inline void omap_init_mbox(void)
375 {
376 struct omap_hwmod *oh;
377 struct platform_device *pdev;
379 oh = omap_hwmod_lookup("mailbox");
380 if (!oh) {
381 pr_err("%s: unable to find hwmod\n", __func__);
382 return;
383 }
385 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
386 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
387 __func__, PTR_ERR(pdev));
388 }
389 #else
390 static inline void omap_init_mbox(void) { }
391 #endif /* CONFIG_OMAP_MBOX_FWK */
393 static inline void omap_init_sti(void) {}
395 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
397 static struct platform_device omap_pcm = {
398 .name = "omap-pcm-audio",
399 .id = -1,
400 };
402 /*
403 * OMAP2420 has 2 McBSP ports
404 * OMAP2430 has 5 McBSP ports
405 * OMAP3 has 5 McBSP ports
406 * OMAP4 has 4 McBSP ports
407 */
408 OMAP_MCBSP_PLATFORM_DEVICE(1);
409 OMAP_MCBSP_PLATFORM_DEVICE(2);
410 OMAP_MCBSP_PLATFORM_DEVICE(3);
411 OMAP_MCBSP_PLATFORM_DEVICE(4);
412 OMAP_MCBSP_PLATFORM_DEVICE(5);
414 static void omap_init_audio(void)
415 {
416 if (cpu_is_am33xx())
417 return;
419 platform_device_register(&omap_mcbsp1);
420 platform_device_register(&omap_mcbsp2);
421 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
422 platform_device_register(&omap_mcbsp3);
423 platform_device_register(&omap_mcbsp4);
424 }
425 if (cpu_is_omap243x() || cpu_is_omap34xx())
426 platform_device_register(&omap_mcbsp5);
428 platform_device_register(&omap_pcm);
429 }
431 #else
432 static inline void omap_init_audio(void) {}
433 #endif
435 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
436 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
438 static void omap_init_mcpdm(void)
439 {
440 struct omap_hwmod *oh;
441 struct platform_device *pdev;
443 oh = omap_hwmod_lookup("mcpdm");
444 if (!oh) {
445 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
446 return;
447 }
449 pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
450 WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
451 }
452 #else
453 static inline void omap_init_mcpdm(void) {}
454 #endif
456 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
457 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
459 static void omap_init_dmic(void)
460 {
461 struct omap_hwmod *oh;
462 struct platform_device *pdev;
464 oh = omap_hwmod_lookup("dmic");
465 if (!oh) {
466 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
467 return;
468 }
470 pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
471 WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
472 }
473 #else
474 static inline void omap_init_dmic(void) {}
475 #endif
477 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
479 #include <plat/mcspi.h>
481 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
482 {
483 struct platform_device *pdev;
484 char *name = "omap2_mcspi";
485 struct omap2_mcspi_platform_config *pdata;
486 static int spi_num;
487 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
489 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
490 if (!pdata) {
491 pr_err("Memory allocation for McSPI device failed\n");
492 return -ENOMEM;
493 }
495 pdata->num_cs = mcspi_attrib->num_chipselect;
496 switch (oh->class->rev) {
497 case OMAP2_MCSPI_REV:
498 case OMAP3_MCSPI_REV:
499 pdata->regs_offset = 0;
500 break;
501 case OMAP4_MCSPI_REV:
502 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
503 break;
504 default:
505 pr_err("Invalid McSPI Revision value\n");
506 return -EINVAL;
507 }
509 spi_num++;
510 pdev = omap_device_build(name, spi_num, oh, pdata,
511 sizeof(*pdata), NULL, 0, 0);
512 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
513 name, oh->name);
514 kfree(pdata);
515 return 0;
516 }
518 static void omap_init_mcspi(void)
519 {
520 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
521 }
523 #else
524 static inline void omap_init_mcspi(void) {}
525 #endif
527 int __init omap_init_elm(void)
528 {
529 int id = -1;
530 struct platform_device *pdev;
531 struct omap_hwmod *oh;
532 char *oh_name = "elm";
533 char *name = "omap2_elm";
535 oh = omap_hwmod_lookup(oh_name);
536 if (!oh) {
537 pr_err("Could not look up %s\n", oh_name);
538 return -ENODEV;
539 }
541 pdev = omap_device_build(name, id, oh, NULL, 0, NULL, 0, 0);
543 if (IS_ERR(pdev)) {
544 WARN(1, "Can't build omap_device for %s:%s.\n",
545 name, oh->name);
546 return PTR_ERR(pdev);
547 }
549 return 0;
550 }
552 static struct resource omap2_pmu_resource = {
553 .start = 3,
554 .end = 3,
555 .flags = IORESOURCE_IRQ,
556 };
558 static struct resource omap3_pmu_resource = {
559 .start = INT_34XX_BENCH_MPU_EMUL,
560 .end = INT_34XX_BENCH_MPU_EMUL,
561 .flags = IORESOURCE_IRQ,
562 };
564 static struct platform_device omap_pmu_device = {
565 .name = "arm-pmu",
566 .id = ARM_PMU_DEVICE_CPU,
567 .num_resources = 1,
568 };
570 static void omap_init_pmu(void)
571 {
572 if (cpu_is_omap24xx())
573 omap_pmu_device.resource = &omap2_pmu_resource;
574 else if (cpu_is_omap34xx() && !cpu_is_am33xx())
575 omap_pmu_device.resource = &omap3_pmu_resource;
576 else
577 return;
579 platform_device_register(&omap_pmu_device);
580 }
583 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
585 #ifdef CONFIG_ARCH_OMAP2
586 static struct resource omap2_sham_resources[] = {
587 {
588 .start = OMAP24XX_SEC_SHA1MD5_BASE,
589 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
590 .flags = IORESOURCE_MEM,
591 },
592 {
593 .start = INT_24XX_SHA1MD5,
594 .flags = IORESOURCE_IRQ,
595 }
596 };
597 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
598 #else
599 #define omap2_sham_resources NULL
600 #define omap2_sham_resources_sz 0
601 #endif
603 #ifdef CONFIG_ARCH_OMAP3
604 static struct resource omap3_sham_resources[] = {
605 {
606 .start = OMAP34XX_SEC_SHA1MD5_BASE,
607 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
608 .flags = IORESOURCE_MEM,
609 },
610 {
611 .start = INT_34XX_SHA1MD52_IRQ,
612 .flags = IORESOURCE_IRQ,
613 },
614 {
615 .start = OMAP34XX_DMA_SHA1MD5_RX,
616 .flags = IORESOURCE_DMA,
617 }
618 };
619 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
620 #else
621 #define omap3_sham_resources NULL
622 #define omap3_sham_resources_sz 0
623 #endif
625 static struct platform_device sham_device = {
626 .name = "omap-sham",
627 .id = -1,
628 };
630 static void omap_init_sham(void)
631 {
632 if (cpu_is_omap24xx()) {
633 sham_device.resource = omap2_sham_resources;
634 sham_device.num_resources = omap2_sham_resources_sz;
635 } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
636 sham_device.resource = omap3_sham_resources;
637 sham_device.num_resources = omap3_sham_resources_sz;
638 } else {
639 pr_err("%s: platform not supported\n", __func__);
640 return;
641 }
642 platform_device_register(&sham_device);
643 }
644 #else
645 static inline void omap_init_sham(void) { }
646 #endif
648 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
650 #ifdef CONFIG_ARCH_OMAP2
651 static struct resource omap2_aes_resources[] = {
652 {
653 .start = OMAP24XX_SEC_AES_BASE,
654 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
655 .flags = IORESOURCE_MEM,
656 },
657 {
658 .start = OMAP24XX_DMA_AES_TX,
659 .flags = IORESOURCE_DMA,
660 },
661 {
662 .start = OMAP24XX_DMA_AES_RX,
663 .flags = IORESOURCE_DMA,
664 }
665 };
666 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
667 #else
668 #define omap2_aes_resources NULL
669 #define omap2_aes_resources_sz 0
670 #endif
672 #ifdef CONFIG_ARCH_OMAP3
673 static struct resource omap3_aes_resources[] = {
674 {
675 .start = OMAP34XX_SEC_AES_BASE,
676 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
677 .flags = IORESOURCE_MEM,
678 },
679 {
680 .start = OMAP34XX_DMA_AES2_TX,
681 .flags = IORESOURCE_DMA,
682 },
683 {
684 .start = OMAP34XX_DMA_AES2_RX,
685 .flags = IORESOURCE_DMA,
686 }
687 };
688 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
689 #else
690 #define omap3_aes_resources NULL
691 #define omap3_aes_resources_sz 0
692 #endif
694 static struct platform_device aes_device = {
695 .name = "omap-aes",
696 .id = -1,
697 };
699 static void omap_init_aes(void)
700 {
701 if (cpu_is_omap24xx()) {
702 aes_device.resource = omap2_aes_resources;
703 aes_device.num_resources = omap2_aes_resources_sz;
704 } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
705 aes_device.resource = omap3_aes_resources;
706 aes_device.num_resources = omap3_aes_resources_sz;
707 } else {
708 pr_err("%s: platform not supported\n", __func__);
709 return;
710 }
711 platform_device_register(&aes_device);
712 }
714 #else
715 static inline void omap_init_aes(void) { }
716 #endif
718 /*-------------------------------------------------------------------------*/
720 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
722 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
723 *mmc_controller)
724 {
725 if ((mmc_controller->slots[0].switch_pin > 0) && \
726 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
727 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
728 OMAP_PIN_INPUT_PULLUP);
729 if ((mmc_controller->slots[0].gpio_wp > 0) && \
730 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
731 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
732 OMAP_PIN_INPUT_PULLUP);
734 omap_mux_init_signal("sdmmc_cmd", 0);
735 omap_mux_init_signal("sdmmc_clki", 0);
736 omap_mux_init_signal("sdmmc_clko", 0);
737 omap_mux_init_signal("sdmmc_dat0", 0);
738 omap_mux_init_signal("sdmmc_dat_dir0", 0);
739 omap_mux_init_signal("sdmmc_cmd_dir", 0);
740 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
741 omap_mux_init_signal("sdmmc_dat1", 0);
742 omap_mux_init_signal("sdmmc_dat2", 0);
743 omap_mux_init_signal("sdmmc_dat3", 0);
744 omap_mux_init_signal("sdmmc_dat_dir1", 0);
745 omap_mux_init_signal("sdmmc_dat_dir2", 0);
746 omap_mux_init_signal("sdmmc_dat_dir3", 0);
747 }
749 /*
750 * Use internal loop-back in MMC/SDIO Module Input Clock
751 * selection
752 */
753 if (mmc_controller->slots[0].internal_clock) {
754 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
755 v |= (1 << 24);
756 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
757 }
758 }
760 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
761 {
762 char *name = "mmci-omap";
764 if (!mmc_data[0]) {
765 pr_err("%s fails: Incomplete platform data\n", __func__);
766 return;
767 }
769 omap242x_mmc_mux(mmc_data[0]);
770 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
771 INT_24XX_MMC_IRQ, mmc_data[0]);
772 }
774 #endif
776 /*-------------------------------------------------------------------------*/
778 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
779 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
780 #define OMAP_HDQ_BASE 0x480B2000
781 #endif
782 static struct resource omap_hdq_resources[] = {
783 {
784 .start = OMAP_HDQ_BASE,
785 .end = OMAP_HDQ_BASE + 0x1C,
786 .flags = IORESOURCE_MEM,
787 },
788 {
789 .start = INT_24XX_HDQ_IRQ,
790 .flags = IORESOURCE_IRQ,
791 },
792 };
793 static struct platform_device omap_hdq_dev = {
794 .name = "omap_hdq",
795 .id = 0,
796 .dev = {
797 .platform_data = NULL,
798 },
799 .num_resources = ARRAY_SIZE(omap_hdq_resources),
800 .resource = omap_hdq_resources,
801 };
802 static inline void omap_hdq_init(void)
803 {
804 (void) platform_device_register(&omap_hdq_dev);
805 }
806 #else
807 static inline void omap_hdq_init(void) {}
808 #endif
810 /*---------------------------------------------------------------------------*/
812 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
813 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
814 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
815 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
816 };
817 #else
818 static struct resource omap_vout_resource[2] = {
819 };
820 #endif
822 static struct platform_device omap_vout_device = {
823 .name = "omap_vout",
824 .num_resources = ARRAY_SIZE(omap_vout_resource),
825 .resource = &omap_vout_resource[0],
826 .id = -1,
827 };
828 static void omap_init_vout(void)
829 {
830 if (platform_device_register(&omap_vout_device) < 0)
831 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
832 }
833 #else
834 static inline void omap_init_vout(void) {}
835 #endif
837 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
839 #define AM33XX_SCM_BASE_EDMA 0x00000f90
841 static const s16 am33xx_dma_rsv_chans[][2] = {
842 /* (offset, number) */
843 {0, 2},
844 {14, 2},
845 {26, 6},
846 {48, 4},
847 {56, 8},
848 {-1, -1}
849 };
851 static const s16 am33xx_dma_rsv_slots[][2] = {
852 /* (offset, number) */
853 {0, 2},
854 {14, 2},
855 {26, 6},
856 {48, 4},
857 {56, 8},
858 {64, 127},
859 {-1, -1}
860 };
862 /* Three Transfer Controllers on AM33XX */
863 static const s8 am33xx_queue_tc_mapping[][2] = {
864 /* {event queue no, TC no} */
865 {0, 0},
866 {1, 1},
867 {2, 2},
868 {-1, -1}
869 };
871 static const s8 am33xx_queue_priority_mapping[][2] = {
872 /* {event queue no, Priority} */
873 {0, 0},
874 {1, 1},
875 {2, 2},
876 {-1, -1}
877 };
879 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
880 /* {xbar event no, Channel} */
881 {1, 12}, /* SDTXEVT1 -> MMCHS2 */
882 {2, 13}, /* SDRXEVT1 -> MMCHS2 */
883 {3, -1},
884 {4, -1},
885 {5, -1},
886 {6, -1},
887 {7, -1},
888 {8, -1},
889 {9, -1},
890 {10, -1},
891 {11, -1},
892 {12, -1},
893 {13, -1},
894 {14, -1},
895 {15, -1},
896 {16, -1},
897 {17, -1},
898 {18, -1},
899 {19, -1},
900 {20, -1},
901 {21, -1},
902 {22, -1},
903 {23, -1},
904 {24, -1},
905 {25, -1},
906 {26, -1},
907 {27, -1},
908 {28, -1},
909 {29, -1},
910 {30, -1},
911 {31, -1},
912 {-1, -1}
913 };
915 /**
916 * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
917 * according to the configuration provided
918 * @event: the event number for which mapping is required
919 * @channel: channel being activated
920 * @xbar_event_mapping: array that has the event to channel map
921 *
922 * Events that are routed by default are not mapped. Only events that
923 * are crossbar mapped are routed to available channels according to
924 * the configuration provided
925 *
926 * Returns zero on success, else negative errno.
927 */
928 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
929 struct event_to_channel_map *xbar_event_mapping)
930 {
931 unsigned int ctrl = 0;
932 unsigned int xbar_evt_no = 0;
933 unsigned int val = 0;
934 unsigned int offset = 0;
935 unsigned int mask = 0;
937 ctrl = EDMA_CTLR(event);
938 xbar_evt_no = event - (edma_cc[ctrl]->num_channels);
940 if (event < edma_cc[ctrl]->num_channels) {
941 *channel = event;
942 } else if (event < edma_cc[ctrl]->num_events) {
943 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
944 /* confirm the range */
945 if (*channel < EDMA_MAX_DMACH)
946 clear_bit(*channel, edma_cc[ctrl]->edma_unused);
947 mask = (*channel)%4;
948 offset = (*channel)/4;
949 offset *= 4;
950 offset += mask;
951 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
952 AM33XX_SCM_BASE_EDMA + offset));
953 val = val & (~(0xFF));
954 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
955 __raw_writel(val,
956 AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
957 return 0;
958 } else {
959 return -EINVAL;
960 }
962 return 0;
963 }
965 static struct edma_soc_info am33xx_edma_info[] = {
966 {
967 .n_channel = 64,
968 .n_region = 4,
969 .n_slot = 256,
970 .n_tc = 3,
971 .n_cc = 1,
972 .rsv_chans = am33xx_dma_rsv_chans,
973 .rsv_slots = am33xx_dma_rsv_slots,
974 .queue_tc_mapping = am33xx_queue_tc_mapping,
975 .queue_priority_mapping = am33xx_queue_priority_mapping,
976 .is_xbar = 1,
977 .n_events = 95,
978 .xbar_event_mapping = am33xx_xbar_event_mapping,
979 .map_xbar_channel = map_xbar_event_to_channel,
980 },
981 };
983 static int __init am33xx_register_edma(void)
984 {
985 int i, l;
986 struct omap_hwmod *oh[4];
987 struct platform_device *pdev;
988 struct edma_soc_info *pdata = am33xx_edma_info;
989 char oh_name[8];
991 if (!cpu_is_am33xx())
992 return -ENODEV;
994 oh[0] = omap_hwmod_lookup("tpcc");
995 if (!oh[0]) {
996 pr_err("could not look up %s\n", "tpcc");
997 return -ENODEV;
998 }
1000 for (i = 0; i < 3; i++) {
1001 l = snprintf(oh_name, 8, "tptc%d", i);
1003 oh[i+1] = omap_hwmod_lookup(oh_name);
1004 if (!oh[i+1]) {
1005 pr_err("could not look up %s\n", oh_name);
1006 return -ENODEV;
1007 }
1008 }
1010 pdev = omap_device_build_ss("edma", 0, oh, 4, pdata, sizeof(*pdata),
1011 NULL, 0, 0);
1013 WARN(IS_ERR(pdev), "could not build omap_device for edma\n");
1015 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
1017 }
1019 #else
1020 static inline void am33xx_register_edma(void) {}
1021 #endif
1023 #if defined (CONFIG_SOC_OMAPAM33XX)
1024 struct uio_pruss_pdata am335x_pruss_uio_pdata = {
1025 .pintc_base = 0x20000,
1026 };
1028 static struct resource am335x_pruss_resources[] = {
1029 {
1030 .start = AM33XX_ICSS_BASE,
1031 .end = AM33XX_ICSS_BASE + AM33XX_ICSS_LEN,
1032 .flags = IORESOURCE_MEM,
1033 },
1034 {
1035 .start = AM33XX_IRQ_ICSS0_0,
1036 .end = AM33XX_IRQ_ICSS0_0,
1037 .flags = IORESOURCE_IRQ,
1038 },
1039 {
1040 .start = AM33XX_IRQ_ICSS0_1,
1041 .end = AM33XX_IRQ_ICSS0_1,
1042 .flags = IORESOURCE_IRQ,
1043 },
1044 {
1045 .start = AM33XX_IRQ_ICSS0_2,
1046 .end = AM33XX_IRQ_ICSS0_2,
1047 .flags = IORESOURCE_IRQ,
1048 },
1049 {
1050 .start = AM33XX_IRQ_ICSS0_3,
1051 .end = AM33XX_IRQ_ICSS0_3,
1052 .flags = IORESOURCE_IRQ,
1053 },
1054 {
1055 .start = AM33XX_IRQ_ICSS0_4,
1056 .end = AM33XX_IRQ_ICSS0_4,
1057 .flags = IORESOURCE_IRQ,
1058 },
1059 {
1060 .start = AM33XX_IRQ_ICSS0_5,
1061 .end = AM33XX_IRQ_ICSS0_5,
1062 .flags = IORESOURCE_IRQ,
1063 },
1064 {
1065 .start = AM33XX_IRQ_ICSS0_6,
1066 .end = AM33XX_IRQ_ICSS0_6,
1067 .flags = IORESOURCE_IRQ,
1068 },
1069 {
1070 .start = AM33XX_IRQ_ICSS0_7,
1071 .end = AM33XX_IRQ_ICSS0_7,
1072 .flags = IORESOURCE_IRQ,
1073 },
1074 };
1076 static struct platform_device am335x_pruss_uio_dev = {
1077 .name = "pruss_uio",
1078 .id = -1,
1079 .num_resources = ARRAY_SIZE(am335x_pruss_resources),
1080 .resource = am335x_pruss_resources,
1081 .dev = {
1082 .coherent_dma_mask = 0xffffffff,
1083 }
1084 };
1086 int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config)
1087 {
1088 am335x_pruss_uio_dev.dev.platform_data = config;
1089 return platform_device_register(&am335x_pruss_uio_dev);
1090 }
1092 static struct resource am335x_epwm0_resurce[] = {
1093 {
1094 .start = AM33XX_EPWMSS0_BASE ,
1095 .end = AM33XX_EPWMSS0_BASE + AM33XX_CONFIG_SIZE,
1096 .flags = IORESOURCE_MEM,
1097 },
1098 {
1099 .start = AM33XX_EPWMSS0_BASE + AM33XX_EPWM_BASE,
1100 .end = AM33XX_EPWMSS0_BASE + AM33XX_EPWM_SIZE,
1101 .flags = IORESOURCE_MEM,
1102 },
1103 {
1104 .start = AM33XX_IRQ_PWMSS0,
1105 .end = AM33XX_IRQ_PWMSS0,
1106 .flags = IORESOURCE_IRQ,
1107 },
1108 {
1109 .start = AM33XX_IRQ_PWMSS0_EPWM,
1110 .end = AM33XX_IRQ_PWMSS0_EPWM,
1111 .flags = IORESOURCE_IRQ,
1112 }
1113 };
1115 static struct pwmss_platform_data am335x_pwmss_config0;
1117 struct platform_device am335x_epwm0_device = {
1118 .name = "ehrpwm",
1119 .id = 0,
1120 .dev = {
1121 .platform_data = &am335x_pwmss_config0,
1122 },
1123 .num_resources = ARRAY_SIZE(am335x_epwm0_resurce),
1124 .resource = am335x_epwm0_resurce,
1125 };
1127 static struct resource am335x_epwm1_resurce[] = {
1128 {
1129 .start = AM33XX_EPWMSS1_BASE ,
1130 .end = AM33XX_EPWMSS1_BASE + AM33XX_CONFIG_SIZE,
1131 .flags = IORESOURCE_MEM,
1132 },
1133 {
1134 .start = AM33XX_EPWMSS1_BASE + AM33XX_EPWM_BASE,
1135 .end = AM33XX_EPWMSS1_BASE + AM33XX_EPWM_SIZE,
1136 .flags = IORESOURCE_MEM,
1137 },
1138 {
1139 .start = AM33XX_IRQ_PWMSS1,
1140 .end = AM33XX_IRQ_PWMSS1,
1141 .flags = IORESOURCE_IRQ,
1142 },
1143 {
1144 .start = AM33XX_IRQ_PWMSS1_EPWM,
1145 .end = AM33XX_IRQ_PWMSS1_EPWM,
1146 .flags = IORESOURCE_IRQ,
1147 }
1148 };
1150 static struct pwmss_platform_data am335x_pwmss_config1;
1152 struct platform_device am335x_epwm1_device = {
1153 .name = "ehrpwm",
1154 .id = 1,
1155 .dev = {
1156 .platform_data = &am335x_pwmss_config1,
1157 },
1158 .num_resources = ARRAY_SIZE(am335x_epwm1_resurce),
1159 .resource = am335x_epwm1_resurce,
1160 };
1162 static struct resource am335x_epwm2_resurce[] = {
1163 {
1164 .start = AM33XX_EPWMSS2_BASE ,
1165 .end = AM33XX_EPWMSS2_BASE + AM33XX_CONFIG_SIZE,
1166 .flags = IORESOURCE_MEM,
1167 },
1168 {
1169 .start = AM33XX_EPWMSS2_BASE + AM33XX_EPWM_BASE,
1170 .end = AM33XX_EPWMSS2_BASE + AM33XX_EPWM_SIZE,
1171 .flags = IORESOURCE_MEM,
1172 },
1173 {
1174 .start = AM33XX_IRQ_PWMSS2,
1175 .end = AM33XX_IRQ_PWMSS2,
1176 .flags = IORESOURCE_IRQ,
1177 },
1178 {
1179 .start = AM33XX_IRQ_PWMSS2_EPWM,
1180 .end = AM33XX_IRQ_PWMSS2_EPWM,
1181 .flags = IORESOURCE_IRQ,
1182 }
1183 };
1185 static struct pwmss_platform_data am335x_pwmss_config2;
1187 struct platform_device am335x_epwm2_device = {
1188 .name = "ehrpwm",
1189 .id = 2,
1190 .dev = {
1191 .platform_data = &am335x_pwmss_config2,
1192 },
1193 .num_resources = ARRAY_SIZE(am335x_epwm2_resurce),
1194 .resource = am335x_epwm2_resurce,
1195 };
1197 #define AM33XX_PWMSS_CTRL 0x664
1198 #define PWMSS2_TBCLKEN (1 << 2)
1199 #define PWMSS1_TBCLKEN (1 << 1)
1200 #define PWMSS0_TBCLKEN (1 << 0)
1202 void __init am335x_register_epwm(void)
1203 {
1205 __raw_writew((PWMSS1_TBCLKEN | PWMSS0_TBCLKEN),
1206 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_CTRL));
1207 am335x_pwmss_config0.version = PWM_VERSION_1;
1208 am335x_pwmss_config1.version = PWM_VERSION_1;
1209 sema_init(&am335x_pwmss_config0.config_semaphore, 1);
1210 sema_init(&am335x_pwmss_config1.config_semaphore, 1);
1211 platform_device_register(&am335x_epwm0_device);
1212 platform_device_register(&am335x_epwm1_device);
1213 }
1216 void register_ehrpwm(int max_freq)
1217 {
1218 int val;
1220 val = __raw_readw(AM33XX_CTRL_REGADDR(AM33XX_PWMSS_CTRL));
1221 val |= PWMSS2_TBCLKEN;
1222 __raw_writew(val, AM33XX_CTRL_REGADDR(AM33XX_PWMSS_CTRL));
1223 am335x_pwmss_config2.chan_attrib[1].max_freq = max_freq;
1224 sema_init(&am335x_pwmss_config2.config_semaphore, 1);
1225 am335x_pwmss_config2.version = PWM_VERSION_1;
1226 platform_device_register(&am335x_epwm2_device);
1227 }
1229 static struct resource am335x_ecap0_resurce[] = {
1230 {
1231 .start = AM33XX_EPWMSS0_BASE ,
1232 .end = AM33XX_EPWMSS0_BASE + AM33XX_CONFIG_SIZE,
1233 .flags = IORESOURCE_MEM,
1234 },
1235 {
1236 .start = AM33XX_EPWMSS0_BASE + AM33XX_ECAP_BASE,
1237 .end = AM33XX_EPWMSS0_BASE + AM33XX_ECAP_SIZE,
1238 .flags = IORESOURCE_MEM,
1239 },
1240 {
1241 .start = AM33XX_IRQ_PWMSS0_ECAP,
1242 .end = AM33XX_IRQ_PWMSS0_ECAP,
1243 .flags = IORESOURCE_IRQ,
1244 },
1245 };
1247 struct platform_device am335x_ecap0_device = {
1248 .name = "ecap",
1249 .id = 0,
1250 .dev = {
1251 .platform_data = &am335x_pwmss_config0,
1252 },
1253 .num_resources = ARRAY_SIZE(am335x_ecap0_resurce),
1254 .resource = am335x_ecap0_resurce,
1255 };
1257 static struct resource am335x_ecap1_resurce[] = {
1258 {
1259 .start = AM33XX_EPWMSS1_BASE ,
1260 .end = AM33XX_EPWMSS1_BASE + AM33XX_CONFIG_SIZE,
1261 .flags = IORESOURCE_MEM,
1262 },
1263 {
1264 .start = AM33XX_EPWMSS1_BASE + AM33XX_ECAP_BASE,
1265 .end = AM33XX_EPWMSS1_BASE + AM33XX_ECAP_SIZE,
1266 .flags = IORESOURCE_MEM,
1267 },
1268 {
1269 .start = AM33XX_IRQ_PWMSS1_ECAP,
1270 .end = AM33XX_IRQ_PWMSS1_ECAP,
1271 .flags = IORESOURCE_IRQ,
1272 },
1273 };
1275 struct platform_device am335x_ecap1_device = {
1276 .name = "ecap",
1277 .id = 1,
1278 .dev = {
1279 .platform_data = &am335x_pwmss_config1,
1280 },
1281 .num_resources = ARRAY_SIZE(am335x_ecap1_resurce),
1282 .resource = am335x_ecap1_resurce,
1283 };
1285 static struct resource am335x_ecap2_resurce[] = {
1286 {
1287 .start = AM33XX_EPWMSS2_BASE ,
1288 .end = AM33XX_EPWMSS2_BASE + AM33XX_CONFIG_SIZE,
1289 .flags = IORESOURCE_MEM,
1290 },
1291 {
1292 .start = AM33XX_EPWMSS2_BASE + AM33XX_ECAP_BASE,
1293 .end = AM33XX_EPWMSS2_BASE + AM33XX_ECAP_SIZE,
1294 .flags = IORESOURCE_MEM,
1295 },
1296 {
1297 .start = AM33XX_IRQ_PWMSS2_ECAP,
1298 .end = AM33XX_IRQ_PWMSS2_ECAP,
1299 .flags = IORESOURCE_IRQ,
1300 },
1301 };
1303 struct platform_device am335x_ecap2_device = {
1304 .name = "ecap",
1305 .id = 2,
1306 .dev = {
1307 .platform_data = &am335x_pwmss_config2,
1308 },
1309 .num_resources = ARRAY_SIZE(am335x_ecap2_resurce),
1310 .resource = am335x_ecap2_resurce,
1311 };
1313 void __init am335x_register_ecap(void)
1314 {
1315 platform_device_register(&am335x_ecap0_device);
1316 platform_device_register(&am335x_ecap1_device);
1317 platform_device_register(&am335x_ecap2_device);
1318 }
1320 void omap_init_pwmss(void)
1321 {
1322 am335x_register_epwm();
1323 am335x_register_ecap();
1324 }
1326 static struct platform_device am335x_sgx = {
1327 .name = "sgx",
1328 .id = -1,
1329 };
1331 #endif
1333 /*-------------------------------------------------------------------------*/
1335 static int __init omap2_init_devices(void)
1336 {
1337 /*
1338 * please keep these calls, and their implementations above,
1339 * in alphabetical order so they're easier to sort through.
1340 */
1341 omap_init_audio();
1342 omap_init_mcpdm();
1343 omap_init_dmic();
1344 omap_init_camera();
1345 omap_init_mbox();
1346 omap_init_mcspi();
1347 omap_init_pmu();
1348 omap_hdq_init();
1349 omap_init_sti();
1350 omap_init_sham();
1351 omap_init_aes();
1352 omap_init_vout();
1353 am33xx_register_edma();
1354 am33xx_init_pcm();
1355 #if defined (CONFIG_SOC_OMAPAM33XX)
1356 am335x_register_pruss_uio(&am335x_pruss_uio_pdata);
1357 omap_init_pwmss();
1358 if (omap3_has_sgx())
1359 platform_device_register(&am335x_sgx);
1360 #endif
1361 return 0;
1362 }
1363 arch_initcall(omap2_init_devices);
1365 #define AM33XX_EMAC_MDIO_FREQ (1000000)
1367 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
1368 /* TODO : Verify the offsets */
1369 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
1370 {
1371 .slave_reg_ofs = 0x208,
1372 .sliver_reg_ofs = 0xd80,
1373 .phy_id = "0:00",
1374 },
1375 {
1376 .slave_reg_ofs = 0x308,
1377 .sliver_reg_ofs = 0xdc0,
1378 .phy_id = "0:01",
1379 },
1380 };
1382 static struct cpsw_platform_data am33xx_cpsw_pdata = {
1383 .ss_reg_ofs = 0x1200,
1384 .channels = 8,
1385 .cpdma_reg_ofs = 0x800,
1386 .slaves = 2,
1387 .slave_data = am33xx_cpsw_slaves,
1388 .ale_reg_ofs = 0xd00,
1389 .ale_entries = 1024,
1390 .host_port_reg_ofs = 0x108,
1391 .hw_stats_reg_ofs = 0x900,
1392 .bd_ram_ofs = 0x2000,
1393 .bd_ram_size = SZ_8K,
1394 .rx_descs = 64,
1395 .mac_control = BIT(5), /* MIIEN */
1396 .gigabit_en = 1,
1397 .host_port_num = 0,
1398 .no_bd_ram = false,
1399 .version = CPSW_VERSION_2,
1400 };
1402 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1403 .bus_freq = AM33XX_EMAC_MDIO_FREQ,
1404 };
1406 static struct resource am33xx_cpsw_mdioresources[] = {
1407 {
1408 .start = AM33XX_CPSW_MDIO_BASE,
1409 .end = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1410 .flags = IORESOURCE_MEM,
1411 },
1412 };
1414 static struct platform_device am33xx_cpsw_mdiodevice = {
1415 .name = "davinci_mdio",
1416 .id = 0,
1417 .num_resources = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1418 .resource = am33xx_cpsw_mdioresources,
1419 .dev.platform_data = &am33xx_cpsw_mdiopdata,
1420 };
1422 static struct resource am33xx_cpsw_resources[] = {
1423 {
1424 .start = AM33XX_CPSW_BASE,
1425 .end = AM33XX_CPSW_BASE + SZ_2K - 1,
1426 .flags = IORESOURCE_MEM,
1427 },
1428 {
1429 .start = AM33XX_CPSW_SS_BASE,
1430 .end = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1431 .flags = IORESOURCE_MEM,
1432 },
1433 {
1434 .start = AM33XX_IRQ_CPSW_C0_RX,
1435 .end = AM33XX_IRQ_CPSW_C0_RX,
1436 .flags = IORESOURCE_IRQ,
1437 },
1438 {
1439 .start = AM33XX_IRQ_DMTIMER5,
1440 .end = AM33XX_IRQ_DMTIMER5,
1441 .flags = IORESOURCE_IRQ,
1442 },
1443 {
1444 .start = AM33XX_IRQ_DMTIMER6,
1445 .end = AM33XX_IRQ_DMTIMER6,
1446 .flags = IORESOURCE_IRQ,
1447 },
1448 {
1449 .start = AM33XX_IRQ_CPSW_C0,
1450 .end = AM33XX_IRQ_CPSW_C0,
1451 .flags = IORESOURCE_IRQ,
1452 },
1453 };
1455 static struct platform_device am33xx_cpsw_device = {
1456 .name = "cpsw",
1457 .id = 0,
1458 .num_resources = ARRAY_SIZE(am33xx_cpsw_resources),
1459 .resource = am33xx_cpsw_resources,
1460 .dev = {
1461 .platform_data = &am33xx_cpsw_pdata,
1462 .dma_mask = &am33xx_cpsw_dmamask,
1463 .coherent_dma_mask = DMA_BIT_MASK(32),
1464 },
1465 };
1467 static unsigned char am33xx_macid0[ETH_ALEN];
1468 static unsigned char am33xx_macid1[ETH_ALEN];
1469 static unsigned int am33xx_evmid;
1471 /*
1472 * am33xx_evmid_fillup - set up board evmid
1473 * @evmid - evm id which needs to be configured
1474 *
1475 * This function is called to configure board evm id.
1476 * IA Motor Control EVM needs special setting of MAC PHY Id.
1477 * This function is called when IA Motor Control EVM is detected
1478 * during boot-up.
1479 */
1480 void am33xx_evmid_fillup(unsigned int evmid)
1481 {
1482 am33xx_evmid = evmid;
1483 return;
1484 }
1486 /*
1487 * am33xx_cpsw_macidfillup - setup mac adrresses
1488 * @eeprommacid0 - mac id 0 which needs to be configured
1489 * @eeprommacid1 - mac id 1 which needs to be configured
1490 *
1491 * This function is called to configure mac addresses.
1492 * Mac addresses are read from eeprom and this function is called
1493 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1494 * In case, mac address read from eFuse are invalid, mac addresses
1495 * stored in these variable are used.
1496 */
1497 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1498 {
1499 u32 i;
1501 /* Fillup these mac addresses with the mac adresses from eeprom */
1502 for (i = 0; i < ETH_ALEN; i++) {
1503 am33xx_macid0[i] = eeprommacid0[i];
1504 am33xx_macid1[i] = eeprommacid1[i];
1505 }
1507 return;
1508 }
1510 #define MII_MODE_ENABLE 0x0
1511 #define RMII_MODE_ENABLE 0x5
1512 #define RGMII_MODE_ENABLE 0xA
1513 #define MAC_MII_SEL 0x650
1515 void am33xx_cpsw_init(unsigned int gigen)
1516 {
1517 u32 mac_lo, mac_hi;
1518 u32 i;
1520 mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1521 mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1522 am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1523 am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1524 am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1525 am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1526 am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1527 am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1529 /* Read MACID0 from eeprom if eFuse MACID is invalid */
1530 if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1531 for (i = 0; i < ETH_ALEN; i++)
1532 am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1533 }
1535 mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1536 mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1537 am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1538 am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1539 am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1540 am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1541 am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1542 am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1544 /* Read MACID1 from eeprom if eFuse MACID is invalid */
1545 if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1546 for (i = 0; i < ETH_ALEN; i++)
1547 am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1548 }
1550 if (am33xx_evmid == BEAGLE_BONE_OLD) {
1551 __raw_writel(RMII_MODE_ENABLE,
1552 AM33XX_CTRL_REGADDR(MAC_MII_SEL));
1553 } else if (am33xx_evmid == BEAGLE_BONE_A3) {
1554 __raw_writel(MII_MODE_ENABLE,
1555 AM33XX_CTRL_REGADDR(MAC_MII_SEL));
1556 } else if (am33xx_evmid == IND_AUT_MTR_EVM) {
1557 am33xx_cpsw_slaves[0].phy_id = "0:1e";
1558 am33xx_cpsw_slaves[1].phy_id = "0:00";
1559 } else {
1560 __raw_writel(RGMII_MODE_ENABLE,
1561 AM33XX_CTRL_REGADDR(MAC_MII_SEL));
1562 }
1564 am33xx_cpsw_pdata.gigabit_en = gigen;
1566 memcpy(am33xx_cpsw_pdata.mac_addr,
1567 am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
1568 platform_device_register(&am33xx_cpsw_mdiodevice);
1569 platform_device_register(&am33xx_cpsw_device);
1570 clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1571 NULL, &am33xx_cpsw_device.dev);
1572 }
1574 #define AM33XX_DCAN_NUM_MSG_OBJS 64
1575 #define AM33XX_DCAN_RAMINIT_OFFSET 0x644
1576 #define AM33XX_DCAN_RAMINIT_START(n) (0x1 << n)
1578 static void d_can_hw_raminit(unsigned int instance, unsigned int enable)
1579 {
1580 u32 val;
1582 /* Read the value */
1583 val = readl(AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
1584 if (enable) {
1585 /* Set to "1" */
1586 val &= ~AM33XX_DCAN_RAMINIT_START(instance);
1587 val |= AM33XX_DCAN_RAMINIT_START(instance);
1588 writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
1589 } else {
1590 /* Set to "0" */
1591 val &= ~AM33XX_DCAN_RAMINIT_START(instance);
1592 writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
1593 }
1594 }
1596 /* dcan dev_attr */
1597 static struct d_can_platform_data am33xx_dcan_info = {
1598 .num_of_msg_objs = AM33XX_DCAN_NUM_MSG_OBJS,
1599 .ram_init = d_can_hw_raminit,
1600 .dma_support = false,
1601 };
1603 void am33xx_d_can_init(unsigned int instance)
1604 {
1605 struct omap_hwmod *oh;
1606 struct platform_device *pdev;
1607 char oh_name[L3_MODULES_MAX_LEN];
1609 /* Copy string name to oh_name buffer */
1610 snprintf(oh_name, L3_MODULES_MAX_LEN, "d_can%d", instance);
1612 oh = omap_hwmod_lookup(oh_name);
1613 if (!oh) {
1614 pr_err("could not find %s hwmod data\n", oh_name);
1615 return;
1616 }
1618 pdev = omap_device_build("d_can", instance, oh, &am33xx_dcan_info,
1619 sizeof(am33xx_dcan_info), NULL, 0, 0);
1620 if (IS_ERR(pdev))
1621 pr_err("could not build omap_device for %s\n", oh_name);
1622 }
1624 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1625 static int __init omap_init_wdt(void)
1626 {
1627 int id = -1;
1628 struct platform_device *pdev;
1629 struct omap_hwmod *oh;
1630 char *oh_name = "wd_timer2";
1631 char *dev_name = "omap_wdt";
1633 if (!cpu_class_is_omap2())
1634 return 0;
1636 oh = omap_hwmod_lookup(oh_name);
1637 if (!oh) {
1638 pr_err("Could not look up wd_timer%d hwmod\n", id);
1639 return -EINVAL;
1640 }
1642 pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1643 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1644 dev_name, oh->name);
1645 return 0;
1646 }
1647 subsys_initcall(omap_init_wdt);
1648 #endif
1650 int __init omap_init_gpmc(struct gpmc_devices_info *pdata, int pdata_len)
1651 {
1652 struct omap_hwmod *oh;
1653 struct platform_device *pdev;
1654 char *name = "omap-gpmc";
1655 char *oh_name = "gpmc";
1657 oh = omap_hwmod_lookup(oh_name);
1658 if (!oh) {
1659 pr_err("Could not look up %s\n", oh_name);
1660 return -ENODEV;
1661 }
1663 pdev = omap_device_build(name, -1, oh, pdata,
1664 pdata_len, NULL, 0, 0);
1665 if (IS_ERR(pdev)) {
1666 WARN(1, "Can't build omap_device for %s:%s.\n",
1667 name, oh->name);
1668 return PTR_ERR(pdev);
1669 }
1671 return 0;
1672 }