8d43913f10d25bb9bd3b525c92740a70eb9440c6
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / devices.c
1 /*
2  * linux/arch/arm/mach-omap2/devices.c
3  *
4  * OMAP2 platform device setup/initialization
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 #include <linux/gpio.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/can/platform/d_can.h>
25 #include <linux/platform_data/uio_pruss.h>
27 #include <mach/hardware.h>
28 #include <mach/irqs.h>
29 #include <mach/board-am335xevm.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/map.h>
32 #include <asm/pmu.h>
34 #ifdef  CONFIG_OMAP3_EDMA
35 #include <mach/edma.h>
36 #endif
38 #include <asm/hardware/asp.h>
40 #include <plat/tc.h>
41 #include <plat/board.h>
42 #include <plat/mcbsp.h>
43 #include <plat/mmc.h>
44 #include <plat/dma.h>
45 #include <plat/omap_hwmod.h>
46 #include <plat/omap_device.h>
47 #include <plat/omap4-keypad.h>
49 /* LCD controller similar DA8xx */
50 #include <video/da8xx-fb.h>
52 #include "mux.h"
53 #include "control.h"
54 #include "devices.h"
56 #define L3_MODULES_MAX_LEN 12
57 #define L3_MODULES 3
59 static int __init omap3_l3_init(void)
60 {
61         int l;
62         struct omap_hwmod *oh;
63         struct platform_device *pdev;
64         char oh_name[L3_MODULES_MAX_LEN];
66         /*
67          * To avoid code running on other OMAPs in
68          * multi-omap builds
69          */
70         if (!(cpu_is_omap34xx()) || (cpu_is_am33xx()))
71                 return -ENODEV;
73         l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
75         oh = omap_hwmod_lookup(oh_name);
77         if (!oh)
78                 pr_err("could not look up %s\n", oh_name);
80         pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
81                                                            NULL, 0, 0);
83         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
85         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
86 }
87 postcore_initcall(omap3_l3_init);
89 static int __init omap4_l3_init(void)
90 {
91         int l, i;
92         struct omap_hwmod *oh[3];
93         struct platform_device *pdev;
94         char oh_name[L3_MODULES_MAX_LEN];
96         /* If dtb is there, the devices will be created dynamically */
97         if (of_have_populated_dt())
98                 return -ENODEV;
100         /*
101          * To avoid code running on other OMAPs in
102          * multi-omap builds
103          */
104         if (!(cpu_is_omap44xx()))
105                 return -ENODEV;
107         for (i = 0; i < L3_MODULES; i++) {
108                 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
110                 oh[i] = omap_hwmod_lookup(oh_name);
111                 if (!(oh[i]))
112                         pr_err("could not look up %s\n", oh_name);
113         }
115         pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
116                                                      0, NULL, 0, 0);
118         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
120         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
122 postcore_initcall(omap4_l3_init);
124 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
126 static struct resource omap2cam_resources[] = {
127         {
128                 .start          = OMAP24XX_CAMERA_BASE,
129                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
130                 .flags          = IORESOURCE_MEM,
131         },
132         {
133                 .start          = INT_24XX_CAM_IRQ,
134                 .flags          = IORESOURCE_IRQ,
135         }
136 };
138 static struct platform_device omap2cam_device = {
139         .name           = "omap24xxcam",
140         .id             = -1,
141         .num_resources  = ARRAY_SIZE(omap2cam_resources),
142         .resource       = omap2cam_resources,
143 };
144 #endif
145 #define L4_PER_LCDC_PHYS        0x4830E000
147 static struct resource am33xx_lcdc_resources[] = {
148         [0] = { /* registers */
149                 .start  = L4_PER_LCDC_PHYS,
150                 .end    = L4_PER_LCDC_PHYS + SZ_4K - 1,
151                 .flags  = IORESOURCE_MEM,
152         },
153         [1] = { /* interrupt */
154                 .start  = AM33XX_IRQ_LCD,
155                 .end    = AM33XX_IRQ_LCD,
156                 .flags  = IORESOURCE_IRQ,
157         },
158 };
160 static struct platform_device am33xx_lcdc_device = {
161         .name           = "da8xx_lcdc",
162         .id             = 0,
163         .num_resources  = ARRAY_SIZE(am33xx_lcdc_resources),
164         .resource       = am33xx_lcdc_resources,
165 };
167 void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
169         int ret;
171         am33xx_lcdc_device.dev.platform_data = pdata;
173         ret = platform_device_register(&am33xx_lcdc_device);
174         if (ret)
175                 pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n",
176                                 ret);
180 #if defined(CONFIG_SND_AM335X_SOC_EVM) || \
181                                 defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
182 static struct resource am335x_mcasp1_resource[] = {
183         {
184                 .name = "mcasp1",
185                 .start = AM33XX_ASP1_BASE,
186                 .end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
187                 .flags = IORESOURCE_MEM,
188         },
189         /* TX event */
190         {
191                 .start = AM33XX_DMA_MCASP1_X,
192                 .end = AM33XX_DMA_MCASP1_X,
193                 .flags = IORESOURCE_DMA,
194         },
195         /* RX event */
196         {
197                 .start = AM33XX_DMA_MCASP1_R,
198                 .end = AM33XX_DMA_MCASP1_R,
199                 .flags = IORESOURCE_DMA,
200         },
201 };
203 static struct platform_device am335x_mcasp1_device = {
204         .name = "davinci-mcasp",
205         .id = 1,
206         .num_resources = ARRAY_SIZE(am335x_mcasp1_resource),
207         .resource = am335x_mcasp1_resource,
208 };
210 void __init am335x_register_mcasp1(struct snd_platform_data *pdata)
212         am335x_mcasp1_device.dev.platform_data = pdata;
213         platform_device_register(&am335x_mcasp1_device);
216 #else
217 void __init am335x_register_mcasp1(struct snd_platform_data *pdata) {}
218 #endif
220 #if (defined(CONFIG_SND_AM33XX_SOC) || (defined(CONFIG_SND_AM33XX_SOC_MODULE)))
221 struct platform_device am33xx_pcm_device = {
222         .name           = "davinci-pcm-audio",
223         .id             = -1,
224 };
226 static void am33xx_init_pcm(void)
228         platform_device_register(&am33xx_pcm_device);
231 #else
232 static inline void am33xx_init_pcm(void) {}
233 #endif
235 static struct resource omap3isp_resources[] = {
236         {
237                 .start          = OMAP3430_ISP_BASE,
238                 .end            = OMAP3430_ISP_END,
239                 .flags          = IORESOURCE_MEM,
240         },
241         {
242                 .start          = OMAP3430_ISP_CCP2_BASE,
243                 .end            = OMAP3430_ISP_CCP2_END,
244                 .flags          = IORESOURCE_MEM,
245         },
246         {
247                 .start          = OMAP3430_ISP_CCDC_BASE,
248                 .end            = OMAP3430_ISP_CCDC_END,
249                 .flags          = IORESOURCE_MEM,
250         },
251         {
252                 .start          = OMAP3430_ISP_HIST_BASE,
253                 .end            = OMAP3430_ISP_HIST_END,
254                 .flags          = IORESOURCE_MEM,
255         },
256         {
257                 .start          = OMAP3430_ISP_H3A_BASE,
258                 .end            = OMAP3430_ISP_H3A_END,
259                 .flags          = IORESOURCE_MEM,
260         },
261         {
262                 .start          = OMAP3430_ISP_PREV_BASE,
263                 .end            = OMAP3430_ISP_PREV_END,
264                 .flags          = IORESOURCE_MEM,
265         },
266         {
267                 .start          = OMAP3430_ISP_RESZ_BASE,
268                 .end            = OMAP3430_ISP_RESZ_END,
269                 .flags          = IORESOURCE_MEM,
270         },
271         {
272                 .start          = OMAP3430_ISP_SBL_BASE,
273                 .end            = OMAP3430_ISP_SBL_END,
274                 .flags          = IORESOURCE_MEM,
275         },
276         {
277                 .start          = OMAP3430_ISP_CSI2A_REGS1_BASE,
278                 .end            = OMAP3430_ISP_CSI2A_REGS1_END,
279                 .flags          = IORESOURCE_MEM,
280         },
281         {
282                 .start          = OMAP3430_ISP_CSIPHY2_BASE,
283                 .end            = OMAP3430_ISP_CSIPHY2_END,
284                 .flags          = IORESOURCE_MEM,
285         },
286         {
287                 .start          = OMAP3630_ISP_CSI2A_REGS2_BASE,
288                 .end            = OMAP3630_ISP_CSI2A_REGS2_END,
289                 .flags          = IORESOURCE_MEM,
290         },
291         {
292                 .start          = OMAP3630_ISP_CSI2C_REGS1_BASE,
293                 .end            = OMAP3630_ISP_CSI2C_REGS1_END,
294                 .flags          = IORESOURCE_MEM,
295         },
296         {
297                 .start          = OMAP3630_ISP_CSIPHY1_BASE,
298                 .end            = OMAP3630_ISP_CSIPHY1_END,
299                 .flags          = IORESOURCE_MEM,
300         },
301         {
302                 .start          = OMAP3630_ISP_CSI2C_REGS2_BASE,
303                 .end            = OMAP3630_ISP_CSI2C_REGS2_END,
304                 .flags          = IORESOURCE_MEM,
305         },
306         {
307                 .start          = INT_34XX_CAM_IRQ,
308                 .flags          = IORESOURCE_IRQ,
309         }
310 };
312 static struct platform_device omap3isp_device = {
313         .name           = "omap3isp",
314         .id             = -1,
315         .num_resources  = ARRAY_SIZE(omap3isp_resources),
316         .resource       = omap3isp_resources,
317 };
319 int omap3_init_camera(struct isp_platform_data *pdata)
321         omap3isp_device.dev.platform_data = pdata;
322         return platform_device_register(&omap3isp_device);
325 static inline void omap_init_camera(void)
327 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
328         if (cpu_is_omap24xx())
329                 platform_device_register(&omap2cam_device);
330 #endif
333 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
334                         *sdp4430_keypad_data, struct omap_board_data *bdata)
336         struct platform_device *pdev;
337         struct omap_hwmod *oh;
338         struct omap4_keypad_platform_data *keypad_data;
339         unsigned int id = -1;
340         char *oh_name = "kbd";
341         char *name = "omap4-keypad";
343         oh = omap_hwmod_lookup(oh_name);
344         if (!oh) {
345                 pr_err("Could not look up %s\n", oh_name);
346                 return -ENODEV;
347         }
349         keypad_data = sdp4430_keypad_data;
351         pdev = omap_device_build(name, id, oh, keypad_data,
352                         sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
354         if (IS_ERR(pdev)) {
355                 WARN(1, "Can't build omap_device for %s:%s.\n",
356                                                 name, oh->name);
357                 return PTR_ERR(pdev);
358         }
359         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
361         return 0;
364 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
365 static inline void omap_init_mbox(void)
367         struct omap_hwmod *oh;
368         struct platform_device *pdev;
370         oh = omap_hwmod_lookup("mailbox");
371         if (!oh) {
372                 pr_err("%s: unable to find hwmod\n", __func__);
373                 return;
374         }
376         pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
377         WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
378                                                 __func__, PTR_ERR(pdev));
380 #else
381 static inline void omap_init_mbox(void) { }
382 #endif /* CONFIG_OMAP_MBOX_FWK */
384 static inline void omap_init_sti(void) {}
386 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
388 static struct platform_device omap_pcm = {
389         .name   = "omap-pcm-audio",
390         .id     = -1,
391 };
393 /*
394  * OMAP2420 has 2 McBSP ports
395  * OMAP2430 has 5 McBSP ports
396  * OMAP3 has 5 McBSP ports
397  * OMAP4 has 4 McBSP ports
398  */
399 OMAP_MCBSP_PLATFORM_DEVICE(1);
400 OMAP_MCBSP_PLATFORM_DEVICE(2);
401 OMAP_MCBSP_PLATFORM_DEVICE(3);
402 OMAP_MCBSP_PLATFORM_DEVICE(4);
403 OMAP_MCBSP_PLATFORM_DEVICE(5);
405 static void omap_init_audio(void)
407         platform_device_register(&omap_mcbsp1);
408         platform_device_register(&omap_mcbsp2);
409         if ((cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) &&
410                 !cpu_is_am33xx()) {
411                 platform_device_register(&omap_mcbsp3);
412                 platform_device_register(&omap_mcbsp4);
413         }
414         if ((cpu_is_omap243x() || cpu_is_omap34xx()) && !cpu_is_am33xx())
415                 platform_device_register(&omap_mcbsp5);
417         platform_device_register(&omap_pcm);
420 #else
421 static inline void omap_init_audio(void) {}
422 #endif
424 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
425                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
427 static void omap_init_mcpdm(void)
429         struct omap_hwmod *oh;
430         struct platform_device *pdev;
432         oh = omap_hwmod_lookup("mcpdm");
433         if (!oh) {
434                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
435                 return;
436         }
438         pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
439         WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
441 #else
442 static inline void omap_init_mcpdm(void) {}
443 #endif
445 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
446                 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
448 static void omap_init_dmic(void)
450         struct omap_hwmod *oh;
451         struct platform_device *pdev;
453         oh = omap_hwmod_lookup("dmic");
454         if (!oh) {
455                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
456                 return;
457         }
459         pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
460         WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
462 #else
463 static inline void omap_init_dmic(void) {}
464 #endif
466 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
468 #include <plat/mcspi.h>
470 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
472         struct platform_device *pdev;
473         char *name = "omap2_mcspi";
474         struct omap2_mcspi_platform_config *pdata;
475         static int spi_num;
476         struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
478         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
479         if (!pdata) {
480                 pr_err("Memory allocation for McSPI device failed\n");
481                 return -ENOMEM;
482         }
484         pdata->num_cs = mcspi_attrib->num_chipselect;
485         switch (oh->class->rev) {
486         case OMAP2_MCSPI_REV:
487         case OMAP3_MCSPI_REV:
488                         pdata->regs_offset = 0;
489                         break;
490         case OMAP4_MCSPI_REV:
491                         pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
492                         break;
493         default:
494                         pr_err("Invalid McSPI Revision value\n");
495                         return -EINVAL;
496         }
498         spi_num++;
499         pdev = omap_device_build(name, spi_num, oh, pdata,
500                                 sizeof(*pdata), NULL, 0, 0);
501         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
502                                 name, oh->name);
503         kfree(pdata);
504         return 0;
507 static void omap_init_mcspi(void)
509         omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
512 #else
513 static inline void omap_init_mcspi(void) {}
514 #endif
516 #ifdef CONFIG_SOC_OMAPAM33XX
518 static int omap_elm_init(struct omap_hwmod *oh, void *unused)
520         struct platform_device *pdev;
521         char *name = "omap2_elm";
522         static int elm_num;
525         elm_num++;
526         pdev = omap_device_build(name, elm_num, oh, NULL,
527                                 0,      NULL,
528                                 0, 0);
529         return 0;
532 static void omap_init_elm(void)
535         omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL);
538 #else
539 static void omap_init_elm(void) {}
540 #endif
543 static struct resource omap2_pmu_resource = {
544         .start  = 3,
545         .end    = 3,
546         .flags  = IORESOURCE_IRQ,
547 };
549 static struct resource omap3_pmu_resource = {
550         .start  = INT_34XX_BENCH_MPU_EMUL,
551         .end    = INT_34XX_BENCH_MPU_EMUL,
552         .flags  = IORESOURCE_IRQ,
553 };
555 static struct platform_device omap_pmu_device = {
556         .name           = "arm-pmu",
557         .id             = ARM_PMU_DEVICE_CPU,
558         .num_resources  = 1,
559 };
561 static void omap_init_pmu(void)
563         if (cpu_is_omap24xx())
564                 omap_pmu_device.resource = &omap2_pmu_resource;
565         else if (cpu_is_omap34xx() && !cpu_is_am33xx())
566                 omap_pmu_device.resource = &omap3_pmu_resource;
567         else
568                 return;
570         platform_device_register(&omap_pmu_device);
574 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
576 #ifdef CONFIG_ARCH_OMAP2
577 static struct resource omap2_sham_resources[] = {
578         {
579                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
580                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
581                 .flags  = IORESOURCE_MEM,
582         },
583         {
584                 .start  = INT_24XX_SHA1MD5,
585                 .flags  = IORESOURCE_IRQ,
586         }
587 };
588 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
589 #else
590 #define omap2_sham_resources            NULL
591 #define omap2_sham_resources_sz         0
592 #endif
594 #ifdef CONFIG_ARCH_OMAP3
595 static struct resource omap3_sham_resources[] = {
596         {
597                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
598                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
599                 .flags  = IORESOURCE_MEM,
600         },
601         {
602                 .start  = INT_34XX_SHA1MD52_IRQ,
603                 .flags  = IORESOURCE_IRQ,
604         },
605         {
606                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
607                 .flags  = IORESOURCE_DMA,
608         }
609 };
610 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
611 #else
612 #define omap3_sham_resources            NULL
613 #define omap3_sham_resources_sz         0
614 #endif
616 static struct platform_device sham_device = {
617         .name           = "omap-sham",
618         .id             = -1,
619 };
621 static void omap_init_sham(void)
623         if (cpu_is_omap24xx()) {
624                 sham_device.resource = omap2_sham_resources;
625                 sham_device.num_resources = omap2_sham_resources_sz;
626         } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
627                 sham_device.resource = omap3_sham_resources;
628                 sham_device.num_resources = omap3_sham_resources_sz;
629         } else {
630                 pr_err("%s: platform not supported\n", __func__);
631                 return;
632         }
633         platform_device_register(&sham_device);
635 #else
636 static inline void omap_init_sham(void) { }
637 #endif
639 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
641 #ifdef CONFIG_ARCH_OMAP2
642 static struct resource omap2_aes_resources[] = {
643         {
644                 .start  = OMAP24XX_SEC_AES_BASE,
645                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
646                 .flags  = IORESOURCE_MEM,
647         },
648         {
649                 .start  = OMAP24XX_DMA_AES_TX,
650                 .flags  = IORESOURCE_DMA,
651         },
652         {
653                 .start  = OMAP24XX_DMA_AES_RX,
654                 .flags  = IORESOURCE_DMA,
655         }
656 };
657 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
658 #else
659 #define omap2_aes_resources             NULL
660 #define omap2_aes_resources_sz          0
661 #endif
663 #ifdef CONFIG_ARCH_OMAP3
664 static struct resource omap3_aes_resources[] = {
665         {
666                 .start  = OMAP34XX_SEC_AES_BASE,
667                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
668                 .flags  = IORESOURCE_MEM,
669         },
670         {
671                 .start  = OMAP34XX_DMA_AES2_TX,
672                 .flags  = IORESOURCE_DMA,
673         },
674         {
675                 .start  = OMAP34XX_DMA_AES2_RX,
676                 .flags  = IORESOURCE_DMA,
677         }
678 };
679 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
680 #else
681 #define omap3_aes_resources             NULL
682 #define omap3_aes_resources_sz          0
683 #endif
685 static struct platform_device aes_device = {
686         .name           = "omap-aes",
687         .id             = -1,
688 };
690 static void omap_init_aes(void)
692         if (cpu_is_omap24xx()) {
693                 aes_device.resource = omap2_aes_resources;
694                 aes_device.num_resources = omap2_aes_resources_sz;
695         } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
696                 aes_device.resource = omap3_aes_resources;
697                 aes_device.num_resources = omap3_aes_resources_sz;
698         } else {
699                 pr_err("%s: platform not supported\n", __func__);
700                 return;
701         }
702         platform_device_register(&aes_device);
705 #else
706 static inline void omap_init_aes(void) { }
707 #endif
709 /*-------------------------------------------------------------------------*/
711 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
713 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
714                                                         *mmc_controller)
716         if ((mmc_controller->slots[0].switch_pin > 0) && \
717                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
718                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
719                                         OMAP_PIN_INPUT_PULLUP);
720         if ((mmc_controller->slots[0].gpio_wp > 0) && \
721                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
722                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
723                                         OMAP_PIN_INPUT_PULLUP);
725         omap_mux_init_signal("sdmmc_cmd", 0);
726         omap_mux_init_signal("sdmmc_clki", 0);
727         omap_mux_init_signal("sdmmc_clko", 0);
728         omap_mux_init_signal("sdmmc_dat0", 0);
729         omap_mux_init_signal("sdmmc_dat_dir0", 0);
730         omap_mux_init_signal("sdmmc_cmd_dir", 0);
731         if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
732                 omap_mux_init_signal("sdmmc_dat1", 0);
733                 omap_mux_init_signal("sdmmc_dat2", 0);
734                 omap_mux_init_signal("sdmmc_dat3", 0);
735                 omap_mux_init_signal("sdmmc_dat_dir1", 0);
736                 omap_mux_init_signal("sdmmc_dat_dir2", 0);
737                 omap_mux_init_signal("sdmmc_dat_dir3", 0);
738         }
740         /*
741          * Use internal loop-back in MMC/SDIO Module Input Clock
742          * selection
743          */
744         if (mmc_controller->slots[0].internal_clock) {
745                 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
746                 v |= (1 << 24);
747                 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
748         }
751 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
753         char *name = "mmci-omap";
755         if (!mmc_data[0]) {
756                 pr_err("%s fails: Incomplete platform data\n", __func__);
757                 return;
758         }
760         omap242x_mmc_mux(mmc_data[0]);
761         omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
762                                         INT_24XX_MMC_IRQ, mmc_data[0]);
765 #endif
767 /*-------------------------------------------------------------------------*/
769 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
770 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
771 #define OMAP_HDQ_BASE   0x480B2000
772 #endif
773 static struct resource omap_hdq_resources[] = {
774         {
775                 .start          = OMAP_HDQ_BASE,
776                 .end            = OMAP_HDQ_BASE + 0x1C,
777                 .flags          = IORESOURCE_MEM,
778         },
779         {
780                 .start          = INT_24XX_HDQ_IRQ,
781                 .flags          = IORESOURCE_IRQ,
782         },
783 };
784 static struct platform_device omap_hdq_dev = {
785         .name = "omap_hdq",
786         .id = 0,
787         .dev = {
788                 .platform_data = NULL,
789         },
790         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
791         .resource       = omap_hdq_resources,
792 };
793 static inline void omap_hdq_init(void)
795         (void) platform_device_register(&omap_hdq_dev);
797 #else
798 static inline void omap_hdq_init(void) {}
799 #endif
801 /*---------------------------------------------------------------------------*/
803 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
804         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
805 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
806 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
807 };
808 #else
809 static struct resource omap_vout_resource[2] = {
810 };
811 #endif
813 static struct platform_device omap_vout_device = {
814         .name           = "omap_vout",
815         .num_resources  = ARRAY_SIZE(omap_vout_resource),
816         .resource       = &omap_vout_resource[0],
817         .id             = -1,
818 };
819 static void omap_init_vout(void)
821         if (platform_device_register(&omap_vout_device) < 0)
822                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
824 #else
825 static inline void omap_init_vout(void) {}
826 #endif
828 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
830 #define AM33XX_TPCC_BASE                0x49000000
831 #define AM33XX_TPTC0_BASE               0x49800000
832 #define AM33XX_TPTC1_BASE               0x49900000
833 #define AM33XX_TPTC2_BASE               0x49a00000
835 #define AM33XX_SCM_BASE_EDMA            0x00000f90
837 static struct resource am33xx_edma_resources[] = {
838         {
839                 .name   = "edma_cc0",
840                 .start  = AM33XX_TPCC_BASE,
841                 .end    = AM33XX_TPCC_BASE + SZ_32K - 1,
842                 .flags  = IORESOURCE_MEM,
843         },
844         {
845                 .name   = "edma_tc0",
846                 .start  = AM33XX_TPTC0_BASE,
847                 .end    = AM33XX_TPTC0_BASE + SZ_1K - 1,
848                 .flags  = IORESOURCE_MEM,
849         },
850         {
851                 .name   = "edma_tc1",
852                 .start  = AM33XX_TPTC1_BASE,
853                 .end    = AM33XX_TPTC1_BASE + SZ_1K - 1,
854                 .flags  = IORESOURCE_MEM,
855         },
856         {
857                 .name   = "edma_tc2",
858                 .start  = AM33XX_TPTC2_BASE,
859                 .end    = AM33XX_TPTC2_BASE + SZ_1K - 1,
860                 .flags  = IORESOURCE_MEM,
861         },
862         {
863                 .name   = "edma0",
864                 .start  = AM33XX_IRQ_TPCC0_INT_PO0,
865                 .flags  = IORESOURCE_IRQ,
866         },
867         {
868                 .name   = "edma0_err",
869                 .start  = AM33XX_IRQ_TPCC0_ERRINT_PO,
870                 .flags  = IORESOURCE_IRQ,
871         },
872 };
874 static const s16 am33xx_dma_rsv_chans[][2] = {
875         /* (offset, number) */
876         {0, 2},
877         {14, 2},
878         {26, 6},
879         {48, 4},
880         {56, 8},
881         {-1, -1}
882 };
884 static const s16 am33xx_dma_rsv_slots[][2] = {
885         /* (offset, number) */
886         {0, 2},
887         {14, 2},
888         {26, 6},
889         {48, 4},
890         {56, 8},
891         {64, 127},
892         {-1, -1}
893 };
895 /* Three Transfer Controllers on AM33XX */
896 static const s8 am33xx_queue_tc_mapping[][2] = {
897         /* {event queue no, TC no} */
898         {0, 0},
899         {1, 1},
900         {2, 2},
901         {-1, -1}
902 };
904 static const s8 am33xx_queue_priority_mapping[][2] = {
905         /* {event queue no, Priority} */
906         {0, 0},
907         {1, 1},
908         {2, 2},
909         {-1, -1}
910 };
912 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
913         /* {xbar event no, Channel} */
914         {1, 12},        /* SDTXEVT1 -> MMCHS2 */
915         {2, 13},        /* SDRXEVT1 -> MMCHS2 */
916         {3, -1},
917         {4, -1},
918         {5, -1},
919         {6, -1},
920         {7, -1},
921         {8, -1},
922         {9, -1},
923         {10, -1},
924         {11, -1},
925         {12, -1},
926         {13, -1},
927         {14, -1},
928         {15, -1},
929         {16, -1},
930         {17, -1},
931         {18, -1},
932         {19, -1},
933         {20, -1},
934         {21, -1},
935         {22, -1},
936         {23, -1},
937         {24, -1},
938         {25, -1},
939         {26, -1},
940         {27, -1},
941         {28, -1},
942         {29, -1},
943         {30, -1},
944         {31, -1},
945         {-1, -1}
946 };
948 /**
949  * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
950  * according to the configuration provided
951  * @event: the event number for which mapping is required
952  * @channel: channel being activated
953  * @xbar_event_mapping: array that has the event to channel map
954  *
955  * Events that are routed by default are not mapped. Only events that
956  * are crossbar mapped are routed to available channels according to
957  * the configuration provided
958  *
959  * Returns zero on success, else negative errno.
960  */
961 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
962                         struct event_to_channel_map *xbar_event_mapping)
964         unsigned int ctrl = 0;
965         unsigned int xbar_evt_no = 0;
966         unsigned int val = 0;
967         unsigned int offset = 0;
968         unsigned int mask = 0;
970         ctrl = EDMA_CTLR(event);
971         xbar_evt_no = event - (edma_info[ctrl]->num_channels);
973         if (event < edma_info[ctrl]->num_channels) {
974                 *channel = event;
975         } else if (event < edma_info[ctrl]->num_events) {
976                 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
977                 /* confirm the range */
978                 if (*channel < EDMA_MAX_DMACH)
979                         clear_bit(*channel, edma_info[ctrl]->edma_unused);
980                 mask = (*channel)%4;
981                 offset = (*channel)/4;
982                 offset *= 4;
983                 offset += mask;
984                 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
985                                         AM33XX_SCM_BASE_EDMA + offset));
986                 val = val & (~(0xFF));
987                 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
988                 __raw_writel(val,
989                         AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
990                 return 0;
991         } else {
992                 return -EINVAL;
993         }
995         return 0;
998 static struct edma_soc_info am33xx_edma_info[] = {
999         {
1000                 .n_channel              = 64,
1001                 .n_region               = 4,
1002                 .n_slot                 = 256,
1003                 .n_tc                   = 3,
1004                 .n_cc                   = 1,
1005                 .rsv_chans              = am33xx_dma_rsv_chans,
1006                 .rsv_slots              = am33xx_dma_rsv_slots,
1007                 .queue_tc_mapping       = am33xx_queue_tc_mapping,
1008                 .queue_priority_mapping = am33xx_queue_priority_mapping,
1009                 .is_xbar                = 1,
1010                 .n_events               = 95,
1011                 .xbar_event_mapping     = am33xx_xbar_event_mapping,
1012                 .map_xbar_channel       = map_xbar_event_to_channel,
1013         },
1014 };
1016 static struct platform_device am33xx_edma_device = {
1017         .name           = "edma",
1018         .id             = -1,
1019         .dev = {
1020                 .platform_data = am33xx_edma_info,
1021         },
1022         .num_resources  = ARRAY_SIZE(am33xx_edma_resources),
1023         .resource       = am33xx_edma_resources,
1024 };
1026 int __init am33xx_register_edma(void)
1028         struct platform_device *pdev;
1029         static struct clk *edma_clk;
1031         if (cpu_is_am33xx())
1032                 pdev = &am33xx_edma_device;
1033         else {
1034                 pr_err("%s: platform not supported\n", __func__);
1035                 return -ENODEV;
1036         }
1038         edma_clk = clk_get(NULL, "tpcc_ick");
1039         if (IS_ERR(edma_clk)) {
1040                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1041                 return -EBUSY;
1042         }
1043         clk_enable(edma_clk);
1044         edma_clk = clk_get(NULL, "tptc0_ick");
1045         if (IS_ERR(edma_clk)) {
1046                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1047                 return -EBUSY;
1048         }
1049         clk_enable(edma_clk);
1050         edma_clk = clk_get(NULL, "tptc1_ick");
1051         if (IS_ERR(edma_clk)) {
1052                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1053                 return -EBUSY;
1054         }
1055         clk_enable(edma_clk);
1056         edma_clk = clk_get(NULL, "tptc2_ick");
1057         if (IS_ERR(edma_clk)) {
1058                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1059                 return -EBUSY;
1060         }
1061         clk_enable(edma_clk);
1063         return platform_device_register(pdev);
1066 #else
1067 static inline void am33xx_register_edma(void) {}
1068 #endif
1070 #if defined (CONFIG_SOC_OMAPAM33XX)
1071 struct uio_pruss_pdata am335x_pruss_uio_pdata = {
1072         .pintc_base     = 0x20000,
1073 };
1075 static struct resource am335x_pruss_resources[] = {
1076         {
1077                 .start  = AM33XX_ICSS_BASE,
1078                 .end    = AM33XX_ICSS_BASE + AM33XX_ICSS_LEN,
1079                 .flags  = IORESOURCE_MEM,
1080         },
1081         {
1082                 .start  = AM33XX_IRQ_ICSS0_0,
1083                 .end    = AM33XX_IRQ_ICSS0_0,
1084                 .flags  = IORESOURCE_IRQ,
1085         },
1086         {
1087                 .start  = AM33XX_IRQ_ICSS0_1,
1088                 .end    = AM33XX_IRQ_ICSS0_1,
1089                 .flags  = IORESOURCE_IRQ,
1090         },
1091         {
1092                 .start  = AM33XX_IRQ_ICSS0_2,
1093                 .end    = AM33XX_IRQ_ICSS0_2,
1094                 .flags  = IORESOURCE_IRQ,
1095         },
1096         {
1097                 .start  = AM33XX_IRQ_ICSS0_3,
1098                 .end    = AM33XX_IRQ_ICSS0_3,
1099                 .flags  = IORESOURCE_IRQ,
1100         },
1101         {
1102                 .start  = AM33XX_IRQ_ICSS0_4,
1103                 .end    = AM33XX_IRQ_ICSS0_4,
1104                 .flags  = IORESOURCE_IRQ,
1105         },
1106         {
1107                 .start  = AM33XX_IRQ_ICSS0_5,
1108                 .end    = AM33XX_IRQ_ICSS0_5,
1109                 .flags  = IORESOURCE_IRQ,
1110         },
1111         {
1112                 .start  = AM33XX_IRQ_ICSS0_6,
1113                 .end    = AM33XX_IRQ_ICSS0_6,
1114                 .flags  = IORESOURCE_IRQ,
1115         },
1116         {
1117                 .start  = AM33XX_IRQ_ICSS0_7,
1118                 .end    = AM33XX_IRQ_ICSS0_7,
1119                 .flags  = IORESOURCE_IRQ,
1120         },
1121 };
1123 static struct platform_device am335x_pruss_uio_dev = {
1124         .name           = "pruss_uio",
1125         .id             = -1,
1126         .num_resources  = ARRAY_SIZE(am335x_pruss_resources),
1127         .resource       = am335x_pruss_resources,
1128         .dev     =      {
1129                 .coherent_dma_mask = 0xffffffff,
1130         }
1131 };
1133 int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config)
1135         am335x_pruss_uio_dev.dev.platform_data = config;
1136         return platform_device_register(&am335x_pruss_uio_dev);
1138 #endif
1140 /*-------------------------------------------------------------------------*/
1142 static int __init omap2_init_devices(void)
1144         /*
1145          * please keep these calls, and their implementations above,
1146          * in alphabetical order so they're easier to sort through.
1147          */
1148         omap_init_audio();
1149         omap_init_mcpdm();
1150         omap_init_dmic();
1151         omap_init_camera();
1152         omap_init_mbox();
1153         omap_init_mcspi();
1154         omap_init_elm();
1155         omap_init_pmu();
1156         omap_hdq_init();
1157         omap_init_sti();
1158         omap_init_sham();
1159         omap_init_aes();
1160         omap_init_vout();
1161         am33xx_register_edma();
1162         am33xx_init_pcm();
1163 #if defined (CONFIG_SOC_OMAPAM33XX)
1164         am335x_register_pruss_uio(&am335x_pruss_uio_pdata);
1165 #endif
1166         return 0;
1168 arch_initcall(omap2_init_devices);
1170 #define AM33XX_EMAC_MDIO_FREQ           (1000000)
1172 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
1173 /* TODO : Verify the offsets */
1174 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
1175         {
1176                 .slave_reg_ofs  = 0x208,
1177                 .sliver_reg_ofs = 0xd80,
1178                 .phy_id         = "0:00",
1179         },
1180         {
1181                 .slave_reg_ofs  = 0x308,
1182                 .sliver_reg_ofs = 0xdc0,
1183                 .phy_id         = "0:01",
1184         },
1185 };
1187 static struct cpsw_platform_data am33xx_cpsw_pdata = {
1188         .ss_reg_ofs             = 0x1200,
1189         .channels               = 8,
1190         .cpdma_reg_ofs          = 0x800,
1191         .slaves                 = 2,
1192         .slave_data             = am33xx_cpsw_slaves,
1193         .ale_reg_ofs            = 0xd00,
1194         .ale_entries            = 1024,
1195         .host_port_reg_ofs      = 0x108,
1196         .hw_stats_reg_ofs       = 0x900,
1197         .bd_ram_ofs             = 0x2000,
1198         .bd_ram_size            = SZ_8K,
1199         .rx_descs               = 64,
1200         .mac_control            = BIT(5), /* MIIEN */
1201         .gigabit_en             = 1,
1202         .host_port_num          = 0,
1203         .no_bd_ram              = false,
1204         .version                = CPSW_VERSION_2,
1205 };
1207 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1208         .bus_freq       = AM33XX_EMAC_MDIO_FREQ,
1209 };
1211 static struct resource am33xx_cpsw_mdioresources[] = {
1212         {
1213                 .start  = AM33XX_CPSW_MDIO_BASE,
1214                 .end    = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1215                 .flags  = IORESOURCE_MEM,
1216         },
1217 };
1219 static struct platform_device am33xx_cpsw_mdiodevice = {
1220         .name           = "davinci_mdio",
1221         .id             = 0,
1222         .num_resources  = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1223         .resource       = am33xx_cpsw_mdioresources,
1224         .dev.platform_data = &am33xx_cpsw_mdiopdata,
1225 };
1227 static struct resource am33xx_cpsw_resources[] = {
1228         {
1229                 .start  = AM33XX_CPSW_BASE,
1230                 .end    = AM33XX_CPSW_BASE + SZ_2K - 1,
1231                 .flags  = IORESOURCE_MEM,
1232         },
1233         {
1234                 .start  = AM33XX_CPSW_SS_BASE,
1235                 .end    = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1236                 .flags  = IORESOURCE_MEM,
1237         },
1238         {
1239                 .start  = AM33XX_IRQ_CPSW_C0_RX,
1240                 .end    = AM33XX_IRQ_CPSW_C0_RX,
1241                 .flags  = IORESOURCE_IRQ,
1242         },
1243         {
1244                 .start  = AM33XX_IRQ_DMTIMER5,
1245                 .end    = AM33XX_IRQ_DMTIMER5,
1246                 .flags  = IORESOURCE_IRQ,
1247         },
1248         {
1249                 .start  = AM33XX_IRQ_DMTIMER6,
1250                 .end    = AM33XX_IRQ_DMTIMER6,
1251                 .flags  = IORESOURCE_IRQ,
1252         },
1253         {
1254                 .start  = AM33XX_IRQ_CPSW_C0,
1255                 .end    = AM33XX_IRQ_CPSW_C0,
1256                 .flags  = IORESOURCE_IRQ,
1257         },
1258 };
1260 static struct platform_device am33xx_cpsw_device = {
1261         .name           =       "cpsw",
1262         .id             =       0,
1263         .num_resources  =       ARRAY_SIZE(am33xx_cpsw_resources),
1264         .resource       =       am33xx_cpsw_resources,
1265         .dev            =       {
1266                                         .platform_data  = &am33xx_cpsw_pdata,
1267                                         .dma_mask       = &am33xx_cpsw_dmamask,
1268                                         .coherent_dma_mask = DMA_BIT_MASK(32),
1269                                 },
1270 };
1272 static unsigned char  am33xx_macid0[ETH_ALEN];
1273 static unsigned char  am33xx_macid1[ETH_ALEN];
1274 static unsigned int   am33xx_evmid;
1276 /*
1277 * am33xx_evmid_fillup - set up board evmid
1278 * @evmid - evm id which needs to be configured
1280 * This function is called to configure board evm id.
1281 * IA Motor Control EVM needs special setting of MAC PHY Id.
1282 * This function is called when IA Motor Control EVM is detected
1283 * during boot-up.
1284 */
1285 void am33xx_evmid_fillup(unsigned int evmid)
1287         am33xx_evmid = evmid;
1288         return;
1291 /*
1292 * am33xx_cpsw_macidfillup - setup mac adrresses
1293 * @eeprommacid0 - mac id 0 which needs to be configured
1294 * @eeprommacid1 - mac id 1 which needs to be configured
1296 * This function is called to configure mac addresses.
1297 * Mac addresses are read from eeprom and this function is called
1298 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1299 * In case, mac address read from eFuse are invalid, mac addresses
1300 * stored in these variable are used.
1301 */
1302 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1304         u32 i;
1306         /* Fillup these mac addresses with the mac adresses from eeprom */
1307         for (i = 0; i < ETH_ALEN; i++) {
1308                 am33xx_macid0[i] = eeprommacid0[i];
1309                 am33xx_macid1[i] = eeprommacid1[i];
1310         }
1312         return;
1315 void am33xx_cpsw_init(unsigned int gigen)
1317         u32 mac_lo, mac_hi;
1318         u32 i;
1320         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1321         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1322         am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1323         am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1324         am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1325         am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1326         am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1327         am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1329         /* Read MACID0 from eeprom if eFuse MACID is invalid */
1330         if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1331                 for (i = 0; i < ETH_ALEN; i++)
1332                         am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1333         }
1335         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1336         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1337         am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1338         am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1339         am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1340         am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1341         am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1342         am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1344         /* Read MACID1 from eeprom if eFuse MACID is invalid */
1345         if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1346                 for (i = 0; i < ETH_ALEN; i++)
1347                         am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1348         }
1350         if (am33xx_evmid == IND_AUT_MTR_EVM) {
1351                 am33xx_cpsw_slaves[0].phy_id = "0:1e";
1352                 am33xx_cpsw_slaves[1].phy_id = "0:00";
1353         }
1355         am33xx_cpsw_pdata.gigabit_en = gigen;
1357         memcpy(am33xx_cpsw_pdata.mac_addr,
1358                         am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
1359         platform_device_register(&am33xx_cpsw_mdiodevice);
1360         platform_device_register(&am33xx_cpsw_device);
1361         clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1362                         NULL, &am33xx_cpsw_device.dev);
1365 #define AM33XX_D_CAN_RAM_BASE                   0x1000
1366 #define AM33XX_D_CAN_NUM_MSG_OBJS               64
1367 #define AM33XX_CTL_DCAN_RAMINIT_OFFSET          0x644
1368 #define AM33XX_D_CAN_RAMINIT_START(n)           (0x1 << n)
1370 static void d_can_hw_raminit(unsigned int instance)
1372         u32 val;
1374         /* Read the value */
1375         val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1377         /* Modify by setting "0" */
1378         val &= ~AM33XX_D_CAN_RAMINIT_START(instance);
1379         __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1381         /* Reset to one */
1382         val |= AM33XX_D_CAN_RAMINIT_START(instance);
1383         __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1385         /* Give some time delay for transition from 0 -> 1 */
1386         udelay(1);
1389 static struct d_can_platform_data am33xx_evm_d_can0_pdata = {
1390         .d_can_offset           = 0,
1391         .d_can_ram_offset       = AM33XX_D_CAN_RAM_BASE,
1392         .num_of_msg_objs        = AM33XX_D_CAN_NUM_MSG_OBJS,
1393         .dma_support            = false,
1394         .parity_check           = false,
1395         .fck_name               = "dcan0_fck",
1396         .ick_name               = "dcan0_ick",
1397 };
1399 static struct resource am33xx_d_can0_resources[] = {
1400         {
1401                 .start  = AM33XX_D_CAN0_BASE,
1402                 .end    = AM33XX_D_CAN0_BASE + 0x3FFF,
1403                 .flags  = IORESOURCE_MEM,
1404         },
1405         {
1406                 .name   = "int0",
1407                 .start  = AM33XX_IRQ_DCAN0_0,
1408                 .end    = AM33XX_IRQ_DCAN0_0,
1409                 .flags  = IORESOURCE_IRQ,
1410         },
1411         {
1412                 .name   = "int1",
1413                 .start  = AM33XX_IRQ_DCAN0_1,
1414                 .end    = AM33XX_IRQ_DCAN0_1,
1415                 .flags  = IORESOURCE_IRQ,
1416         },
1417 };
1419 static struct platform_device am33xx_d_can0_device = {
1420         .dev            = {
1421                 .platform_data = &am33xx_evm_d_can0_pdata,
1422         },
1423         .name           = "d_can",
1424         .id             = -1,
1425         .num_resources  = ARRAY_SIZE(am33xx_d_can0_resources),
1426         .resource       = am33xx_d_can0_resources,
1427 };
1429 static struct resource am33xx_d_can1_resources[] = {
1430         {
1431                 .start  = AM33XX_D_CAN1_BASE,
1432                 .end    = AM33XX_D_CAN1_BASE + 0x3FFF,
1433                 .flags  = IORESOURCE_MEM,
1434         },
1435         {
1436                 .name   = "int0",
1437                 .start  = AM33XX_IRQ_DCAN1_0,
1438                 .end    = AM33XX_IRQ_DCAN1_0,
1439                 .flags  = IORESOURCE_IRQ,
1440         },
1441         {
1442                 .name   = "int1",
1443                 .start  = AM33XX_IRQ_DCAN1_1,
1444                 .end    = AM33XX_IRQ_DCAN1_1,
1445                 .flags  = IORESOURCE_IRQ,
1446         },
1447 };
1449 static struct d_can_platform_data am33xx_evm_d_can1_pdata = {
1450         .d_can_offset           = 0,
1451         .d_can_ram_offset       = AM33XX_D_CAN_RAM_BASE,
1452         .num_of_msg_objs        = AM33XX_D_CAN_NUM_MSG_OBJS,
1453         .dma_support            = false,
1454         .parity_check           = false,
1455         .fck_name               = "dcan1_fck",
1456         .ick_name               = "dcan1_ick",
1457 };
1459 static struct platform_device am33xx_d_can1_device = {
1460         .dev            = {
1461                 .platform_data = &am33xx_evm_d_can1_pdata,
1462         },
1463         .name           = "d_can",
1464         .id             = -1,
1465         .num_resources  = ARRAY_SIZE(am33xx_d_can1_resources),
1466         .resource       = am33xx_d_can1_resources,
1467 };
1469 void am33xx_d_can_init(unsigned int instance)
1471         switch (instance) {
1472         case 0:
1473                 d_can_hw_raminit(instance);
1474                 platform_device_register(&am33xx_d_can0_device);
1475                 break;
1476         case 1:
1477                 d_can_hw_raminit(instance);
1478                 platform_device_register(&am33xx_d_can1_device);
1479                 break;
1480         default:
1481                 break;
1482         }
1485 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1486 static int __init omap_init_wdt(void)
1488         int id = -1;
1489         struct platform_device *pdev;
1490         struct omap_hwmod *oh;
1491         char *oh_name = "wd_timer2";
1492         char *dev_name = "omap_wdt";
1494         if (!cpu_class_is_omap2())
1495                 return 0;
1497         oh = omap_hwmod_lookup(oh_name);
1498         if (!oh) {
1499                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1500                 return -EINVAL;
1501         }
1503         pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1504         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1505                                 dev_name, oh->name);
1506         return 0;
1508 subsys_initcall(omap_init_wdt);
1509 #endif