984bc62f7d74ed498d5aa30b791d8687f452b7fe
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / devices.c
1 /*
2  * linux/arch/arm/mach-omap2/devices.c
3  *
4  * OMAP2 platform device setup/initialization
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 #include <linux/gpio.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
25 #include <mach/hardware.h>
26 #include <mach/irqs.h>
27 #include <asm/mach-types.h>
28 #include <asm/mach/map.h>
29 #include <asm/pmu.h>
31 #ifdef  CONFIG_OMAP3_EDMA
32 #include <mach/edma.h>
33 #endif
35 #include <plat/tc.h>
36 #include <plat/board.h>
37 #include <plat/mcbsp.h>
38 #include <plat/mmc.h>
39 #include <plat/dma.h>
40 #include <plat/omap_hwmod.h>
41 #include <plat/omap_device.h>
42 #include <plat/omap4-keypad.h>
44 #include "mux.h"
45 #include "control.h"
46 #include "devices.h"
48 #define L3_MODULES_MAX_LEN 12
49 #define L3_MODULES 3
51 void am33xx_cpsw_init(void);
53 static int __init omap3_l3_init(void)
54 {
55         int l;
56         struct omap_hwmod *oh;
57         struct platform_device *pdev;
58         char oh_name[L3_MODULES_MAX_LEN];
60         /*
61          * To avoid code running on other OMAPs in
62          * multi-omap builds
63          */
64         if (!(cpu_is_omap34xx()))
65                 return -ENODEV;
67         l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
69         oh = omap_hwmod_lookup(oh_name);
71         if (!oh)
72                 pr_err("could not look up %s\n", oh_name);
74         pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
75                                                            NULL, 0, 0);
77         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
79         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
80 }
81 postcore_initcall(omap3_l3_init);
83 static int __init omap4_l3_init(void)
84 {
85         int l, i;
86         struct omap_hwmod *oh[3];
87         struct platform_device *pdev;
88         char oh_name[L3_MODULES_MAX_LEN];
90         /* If dtb is there, the devices will be created dynamically */
91         if (of_have_populated_dt())
92                 return -ENODEV;
94         /*
95          * To avoid code running on other OMAPs in
96          * multi-omap builds
97          */
98         if (!(cpu_is_omap44xx()))
99                 return -ENODEV;
101         for (i = 0; i < L3_MODULES; i++) {
102                 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
104                 oh[i] = omap_hwmod_lookup(oh_name);
105                 if (!(oh[i]))
106                         pr_err("could not look up %s\n", oh_name);
107         }
109         pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
110                                                      0, NULL, 0, 0);
112         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
114         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
116 postcore_initcall(omap4_l3_init);
118 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
120 static struct resource omap2cam_resources[] = {
121         {
122                 .start          = OMAP24XX_CAMERA_BASE,
123                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
124                 .flags          = IORESOURCE_MEM,
125         },
126         {
127                 .start          = INT_24XX_CAM_IRQ,
128                 .flags          = IORESOURCE_IRQ,
129         }
130 };
132 static struct platform_device omap2cam_device = {
133         .name           = "omap24xxcam",
134         .id             = -1,
135         .num_resources  = ARRAY_SIZE(omap2cam_resources),
136         .resource       = omap2cam_resources,
137 };
138 #endif
140 static struct resource omap3isp_resources[] = {
141         {
142                 .start          = OMAP3430_ISP_BASE,
143                 .end            = OMAP3430_ISP_END,
144                 .flags          = IORESOURCE_MEM,
145         },
146         {
147                 .start          = OMAP3430_ISP_CCP2_BASE,
148                 .end            = OMAP3430_ISP_CCP2_END,
149                 .flags          = IORESOURCE_MEM,
150         },
151         {
152                 .start          = OMAP3430_ISP_CCDC_BASE,
153                 .end            = OMAP3430_ISP_CCDC_END,
154                 .flags          = IORESOURCE_MEM,
155         },
156         {
157                 .start          = OMAP3430_ISP_HIST_BASE,
158                 .end            = OMAP3430_ISP_HIST_END,
159                 .flags          = IORESOURCE_MEM,
160         },
161         {
162                 .start          = OMAP3430_ISP_H3A_BASE,
163                 .end            = OMAP3430_ISP_H3A_END,
164                 .flags          = IORESOURCE_MEM,
165         },
166         {
167                 .start          = OMAP3430_ISP_PREV_BASE,
168                 .end            = OMAP3430_ISP_PREV_END,
169                 .flags          = IORESOURCE_MEM,
170         },
171         {
172                 .start          = OMAP3430_ISP_RESZ_BASE,
173                 .end            = OMAP3430_ISP_RESZ_END,
174                 .flags          = IORESOURCE_MEM,
175         },
176         {
177                 .start          = OMAP3430_ISP_SBL_BASE,
178                 .end            = OMAP3430_ISP_SBL_END,
179                 .flags          = IORESOURCE_MEM,
180         },
181         {
182                 .start          = OMAP3430_ISP_CSI2A_REGS1_BASE,
183                 .end            = OMAP3430_ISP_CSI2A_REGS1_END,
184                 .flags          = IORESOURCE_MEM,
185         },
186         {
187                 .start          = OMAP3430_ISP_CSIPHY2_BASE,
188                 .end            = OMAP3430_ISP_CSIPHY2_END,
189                 .flags          = IORESOURCE_MEM,
190         },
191         {
192                 .start          = OMAP3630_ISP_CSI2A_REGS2_BASE,
193                 .end            = OMAP3630_ISP_CSI2A_REGS2_END,
194                 .flags          = IORESOURCE_MEM,
195         },
196         {
197                 .start          = OMAP3630_ISP_CSI2C_REGS1_BASE,
198                 .end            = OMAP3630_ISP_CSI2C_REGS1_END,
199                 .flags          = IORESOURCE_MEM,
200         },
201         {
202                 .start          = OMAP3630_ISP_CSIPHY1_BASE,
203                 .end            = OMAP3630_ISP_CSIPHY1_END,
204                 .flags          = IORESOURCE_MEM,
205         },
206         {
207                 .start          = OMAP3630_ISP_CSI2C_REGS2_BASE,
208                 .end            = OMAP3630_ISP_CSI2C_REGS2_END,
209                 .flags          = IORESOURCE_MEM,
210         },
211         {
212                 .start          = INT_34XX_CAM_IRQ,
213                 .flags          = IORESOURCE_IRQ,
214         }
215 };
217 static struct platform_device omap3isp_device = {
218         .name           = "omap3isp",
219         .id             = -1,
220         .num_resources  = ARRAY_SIZE(omap3isp_resources),
221         .resource       = omap3isp_resources,
222 };
224 int omap3_init_camera(struct isp_platform_data *pdata)
226         omap3isp_device.dev.platform_data = pdata;
227         return platform_device_register(&omap3isp_device);
230 static inline void omap_init_camera(void)
232 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
233         if (cpu_is_omap24xx())
234                 platform_device_register(&omap2cam_device);
235 #endif
238 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
239                         *sdp4430_keypad_data, struct omap_board_data *bdata)
241         struct platform_device *pdev;
242         struct omap_hwmod *oh;
243         struct omap4_keypad_platform_data *keypad_data;
244         unsigned int id = -1;
245         char *oh_name = "kbd";
246         char *name = "omap4-keypad";
248         oh = omap_hwmod_lookup(oh_name);
249         if (!oh) {
250                 pr_err("Could not look up %s\n", oh_name);
251                 return -ENODEV;
252         }
254         keypad_data = sdp4430_keypad_data;
256         pdev = omap_device_build(name, id, oh, keypad_data,
257                         sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
259         if (IS_ERR(pdev)) {
260                 WARN(1, "Can't build omap_device for %s:%s.\n",
261                                                 name, oh->name);
262                 return PTR_ERR(pdev);
263         }
264         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
266         return 0;
269 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
270 static inline void omap_init_mbox(void)
272         struct omap_hwmod *oh;
273         struct platform_device *pdev;
275         oh = omap_hwmod_lookup("mailbox");
276         if (!oh) {
277                 pr_err("%s: unable to find hwmod\n", __func__);
278                 return;
279         }
281         pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
282         WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
283                                                 __func__, PTR_ERR(pdev));
285 #else
286 static inline void omap_init_mbox(void) { }
287 #endif /* CONFIG_OMAP_MBOX_FWK */
289 static inline void omap_init_sti(void) {}
291 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
293 static struct platform_device omap_pcm = {
294         .name   = "omap-pcm-audio",
295         .id     = -1,
296 };
298 /*
299  * OMAP2420 has 2 McBSP ports
300  * OMAP2430 has 5 McBSP ports
301  * OMAP3 has 5 McBSP ports
302  * OMAP4 has 4 McBSP ports
303  */
304 OMAP_MCBSP_PLATFORM_DEVICE(1);
305 OMAP_MCBSP_PLATFORM_DEVICE(2);
306 OMAP_MCBSP_PLATFORM_DEVICE(3);
307 OMAP_MCBSP_PLATFORM_DEVICE(4);
308 OMAP_MCBSP_PLATFORM_DEVICE(5);
310 static void omap_init_audio(void)
312         platform_device_register(&omap_mcbsp1);
313         platform_device_register(&omap_mcbsp2);
314         if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
315                 platform_device_register(&omap_mcbsp3);
316                 platform_device_register(&omap_mcbsp4);
317         }
318         if (cpu_is_omap243x() || cpu_is_omap34xx())
319                 platform_device_register(&omap_mcbsp5);
321         platform_device_register(&omap_pcm);
324 #else
325 static inline void omap_init_audio(void) {}
326 #endif
328 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
329                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
331 static void omap_init_mcpdm(void)
333         struct omap_hwmod *oh;
334         struct platform_device *pdev;
336         oh = omap_hwmod_lookup("mcpdm");
337         if (!oh) {
338                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
339                 return;
340         }
342         pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
343         WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
345 #else
346 static inline void omap_init_mcpdm(void) {}
347 #endif
349 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
350                 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
352 static void omap_init_dmic(void)
354         struct omap_hwmod *oh;
355         struct platform_device *pdev;
357         oh = omap_hwmod_lookup("dmic");
358         if (!oh) {
359                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
360                 return;
361         }
363         pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
364         WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
366 #else
367 static inline void omap_init_dmic(void) {}
368 #endif
370 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
372 #include <plat/mcspi.h>
374 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
376         struct platform_device *pdev;
377         char *name = "omap2_mcspi";
378         struct omap2_mcspi_platform_config *pdata;
379         static int spi_num;
380         struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
382         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
383         if (!pdata) {
384                 pr_err("Memory allocation for McSPI device failed\n");
385                 return -ENOMEM;
386         }
388         pdata->num_cs = mcspi_attrib->num_chipselect;
389         switch (oh->class->rev) {
390         case OMAP2_MCSPI_REV:
391         case OMAP3_MCSPI_REV:
392                         pdata->regs_offset = 0;
393                         break;
394         case OMAP4_MCSPI_REV:
395                         pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
396                         break;
397         default:
398                         pr_err("Invalid McSPI Revision value\n");
399                         return -EINVAL;
400         }
402         spi_num++;
403         pdev = omap_device_build(name, spi_num, oh, pdata,
404                                 sizeof(*pdata), NULL, 0, 0);
405         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
406                                 name, oh->name);
407         kfree(pdata);
408         return 0;
411 static void omap_init_mcspi(void)
413         omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
416 #else
417 static inline void omap_init_mcspi(void) {}
418 #endif
420 static struct resource omap2_pmu_resource = {
421         .start  = 3,
422         .end    = 3,
423         .flags  = IORESOURCE_IRQ,
424 };
426 static struct resource omap3_pmu_resource = {
427         .start  = INT_34XX_BENCH_MPU_EMUL,
428         .end    = INT_34XX_BENCH_MPU_EMUL,
429         .flags  = IORESOURCE_IRQ,
430 };
432 static struct platform_device omap_pmu_device = {
433         .name           = "arm-pmu",
434         .id             = ARM_PMU_DEVICE_CPU,
435         .num_resources  = 1,
436 };
438 static void omap_init_pmu(void)
440         if (cpu_is_omap24xx())
441                 omap_pmu_device.resource = &omap2_pmu_resource;
442         else if (cpu_is_omap34xx())
443                 omap_pmu_device.resource = &omap3_pmu_resource;
444         else
445                 return;
447         platform_device_register(&omap_pmu_device);
451 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
453 #ifdef CONFIG_ARCH_OMAP2
454 static struct resource omap2_sham_resources[] = {
455         {
456                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
457                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
458                 .flags  = IORESOURCE_MEM,
459         },
460         {
461                 .start  = INT_24XX_SHA1MD5,
462                 .flags  = IORESOURCE_IRQ,
463         }
464 };
465 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
466 #else
467 #define omap2_sham_resources            NULL
468 #define omap2_sham_resources_sz         0
469 #endif
471 #ifdef CONFIG_ARCH_OMAP3
472 static struct resource omap3_sham_resources[] = {
473         {
474                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
475                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
476                 .flags  = IORESOURCE_MEM,
477         },
478         {
479                 .start  = INT_34XX_SHA1MD52_IRQ,
480                 .flags  = IORESOURCE_IRQ,
481         },
482         {
483                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
484                 .flags  = IORESOURCE_DMA,
485         }
486 };
487 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
488 #else
489 #define omap3_sham_resources            NULL
490 #define omap3_sham_resources_sz         0
491 #endif
493 static struct platform_device sham_device = {
494         .name           = "omap-sham",
495         .id             = -1,
496 };
498 static void omap_init_sham(void)
500         if (cpu_is_omap24xx()) {
501                 sham_device.resource = omap2_sham_resources;
502                 sham_device.num_resources = omap2_sham_resources_sz;
503         } else if (cpu_is_omap34xx()) {
504                 sham_device.resource = omap3_sham_resources;
505                 sham_device.num_resources = omap3_sham_resources_sz;
506         } else {
507                 pr_err("%s: platform not supported\n", __func__);
508                 return;
509         }
510         platform_device_register(&sham_device);
512 #else
513 static inline void omap_init_sham(void) { }
514 #endif
516 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
518 #ifdef CONFIG_ARCH_OMAP2
519 static struct resource omap2_aes_resources[] = {
520         {
521                 .start  = OMAP24XX_SEC_AES_BASE,
522                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
523                 .flags  = IORESOURCE_MEM,
524         },
525         {
526                 .start  = OMAP24XX_DMA_AES_TX,
527                 .flags  = IORESOURCE_DMA,
528         },
529         {
530                 .start  = OMAP24XX_DMA_AES_RX,
531                 .flags  = IORESOURCE_DMA,
532         }
533 };
534 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
535 #else
536 #define omap2_aes_resources             NULL
537 #define omap2_aes_resources_sz          0
538 #endif
540 #ifdef CONFIG_ARCH_OMAP3
541 static struct resource omap3_aes_resources[] = {
542         {
543                 .start  = OMAP34XX_SEC_AES_BASE,
544                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
545                 .flags  = IORESOURCE_MEM,
546         },
547         {
548                 .start  = OMAP34XX_DMA_AES2_TX,
549                 .flags  = IORESOURCE_DMA,
550         },
551         {
552                 .start  = OMAP34XX_DMA_AES2_RX,
553                 .flags  = IORESOURCE_DMA,
554         }
555 };
556 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
557 #else
558 #define omap3_aes_resources             NULL
559 #define omap3_aes_resources_sz          0
560 #endif
562 static struct platform_device aes_device = {
563         .name           = "omap-aes",
564         .id             = -1,
565 };
567 static void omap_init_aes(void)
569         if (cpu_is_omap24xx()) {
570                 aes_device.resource = omap2_aes_resources;
571                 aes_device.num_resources = omap2_aes_resources_sz;
572         } else if (cpu_is_omap34xx()) {
573                 aes_device.resource = omap3_aes_resources;
574                 aes_device.num_resources = omap3_aes_resources_sz;
575         } else {
576                 pr_err("%s: platform not supported\n", __func__);
577                 return;
578         }
579         platform_device_register(&aes_device);
582 #else
583 static inline void omap_init_aes(void) { }
584 #endif
586 /*-------------------------------------------------------------------------*/
588 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
590 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
591                                                         *mmc_controller)
593         if ((mmc_controller->slots[0].switch_pin > 0) && \
594                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
595                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
596                                         OMAP_PIN_INPUT_PULLUP);
597         if ((mmc_controller->slots[0].gpio_wp > 0) && \
598                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
599                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
600                                         OMAP_PIN_INPUT_PULLUP);
602         omap_mux_init_signal("sdmmc_cmd", 0);
603         omap_mux_init_signal("sdmmc_clki", 0);
604         omap_mux_init_signal("sdmmc_clko", 0);
605         omap_mux_init_signal("sdmmc_dat0", 0);
606         omap_mux_init_signal("sdmmc_dat_dir0", 0);
607         omap_mux_init_signal("sdmmc_cmd_dir", 0);
608         if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
609                 omap_mux_init_signal("sdmmc_dat1", 0);
610                 omap_mux_init_signal("sdmmc_dat2", 0);
611                 omap_mux_init_signal("sdmmc_dat3", 0);
612                 omap_mux_init_signal("sdmmc_dat_dir1", 0);
613                 omap_mux_init_signal("sdmmc_dat_dir2", 0);
614                 omap_mux_init_signal("sdmmc_dat_dir3", 0);
615         }
617         /*
618          * Use internal loop-back in MMC/SDIO Module Input Clock
619          * selection
620          */
621         if (mmc_controller->slots[0].internal_clock) {
622                 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
623                 v |= (1 << 24);
624                 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
625         }
628 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
630         char *name = "mmci-omap";
632         if (!mmc_data[0]) {
633                 pr_err("%s fails: Incomplete platform data\n", __func__);
634                 return;
635         }
637         omap242x_mmc_mux(mmc_data[0]);
638         omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
639                                         INT_24XX_MMC_IRQ, mmc_data[0]);
642 #endif
644 /*-------------------------------------------------------------------------*/
646 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
647 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
648 #define OMAP_HDQ_BASE   0x480B2000
649 #endif
650 static struct resource omap_hdq_resources[] = {
651         {
652                 .start          = OMAP_HDQ_BASE,
653                 .end            = OMAP_HDQ_BASE + 0x1C,
654                 .flags          = IORESOURCE_MEM,
655         },
656         {
657                 .start          = INT_24XX_HDQ_IRQ,
658                 .flags          = IORESOURCE_IRQ,
659         },
660 };
661 static struct platform_device omap_hdq_dev = {
662         .name = "omap_hdq",
663         .id = 0,
664         .dev = {
665                 .platform_data = NULL,
666         },
667         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
668         .resource       = omap_hdq_resources,
669 };
670 static inline void omap_hdq_init(void)
672         (void) platform_device_register(&omap_hdq_dev);
674 #else
675 static inline void omap_hdq_init(void) {}
676 #endif
678 /*---------------------------------------------------------------------------*/
680 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
681         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
682 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
683 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
684 };
685 #else
686 static struct resource omap_vout_resource[2] = {
687 };
688 #endif
690 static struct platform_device omap_vout_device = {
691         .name           = "omap_vout",
692         .num_resources  = ARRAY_SIZE(omap_vout_resource),
693         .resource       = &omap_vout_resource[0],
694         .id             = -1,
695 };
696 static void omap_init_vout(void)
698         if (platform_device_register(&omap_vout_device) < 0)
699                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
701 #else
702 static inline void omap_init_vout(void) {}
703 #endif
705 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
707 #define AM33XX_TPCC_BASE                0x49000000
708 #define AM33XX_TPTC0_BASE               0x49800000
709 #define AM33XX_TPTC1_BASE               0x49900000
710 #define AM33XX_TPTC2_BASE               0x49a00000
712 #define AM33XX_SCM_BASE_EDMA            0x00000f90
714 static struct resource am33xx_edma_resources[] = {
715         {
716                 .name   = "edma_cc0",
717                 .start  = AM33XX_TPCC_BASE,
718                 .end    = AM33XX_TPCC_BASE + SZ_32K - 1,
719                 .flags  = IORESOURCE_MEM,
720         },
721         {
722                 .name   = "edma_tc0",
723                 .start  = AM33XX_TPTC0_BASE,
724                 .end    = AM33XX_TPTC0_BASE + SZ_1K - 1,
725                 .flags  = IORESOURCE_MEM,
726         },
727         {
728                 .name   = "edma_tc1",
729                 .start  = AM33XX_TPTC1_BASE,
730                 .end    = AM33XX_TPTC1_BASE + SZ_1K - 1,
731                 .flags  = IORESOURCE_MEM,
732         },
733         {
734                 .name   = "edma_tc2",
735                 .start  = AM33XX_TPTC2_BASE,
736                 .end    = AM33XX_TPTC2_BASE + SZ_1K - 1,
737                 .flags  = IORESOURCE_MEM,
738         },
739         {
740                 .name   = "edma0",
741                 .start  = AM33XX_IRQ_TPCC0_INT_PO0,
742                 .flags  = IORESOURCE_IRQ,
743         },
744         {
745                 .name   = "edma0_err",
746                 .start  = AM33XX_IRQ_TPCC0_ERRINT_PO,
747                 .flags  = IORESOURCE_IRQ,
748         },
749 };
751 static const s16 am33xx_dma_rsv_chans[][2] = {
752         /* (offset, number) */
753         {0, 2},
754         {14, 2},
755         {26, 6},
756         {48, 4},
757         {56, 8},
758         {-1, -1}
759 };
761 static const s16 am33xx_dma_rsv_slots[][2] = {
762         /* (offset, number) */
763         {0, 2},
764         {14, 2},
765         {26, 6},
766         {48, 4},
767         {56, 8},
768         {64, 127},
769         {-1, -1}
770 };
772 /* Three Transfer Controllers on AM33XX */
773 static const s8 am33xx_queue_tc_mapping[][2] = {
774         /* {event queue no, TC no} */
775         {0, 0},
776         {1, 1},
777         {2, 2},
778         {-1, -1}
779 };
781 static const s8 am33xx_queue_priority_mapping[][2] = {
782         /* {event queue no, Priority} */
783         {0, 0},
784         {1, 1},
785         {2, 2},
786         {-1, -1}
787 };
789 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
790         /* {xbar event no, Channel} */
791         {1, 12},        /* SDTXEVT1 -> MMCHS2 */
792         {2, 13},        /* SDRXEVT1 -> MMCHS2 */
793         {3, -1},
794         {4, -1},
795         {5, -1},
796         {6, -1},
797         {7, -1},
798         {8, -1},
799         {9, -1},
800         {10, -1},
801         {11, -1},
802         {12, -1},
803         {13, -1},
804         {14, -1},
805         {15, -1},
806         {16, -1},
807         {17, -1},
808         {18, -1},
809         {19, -1},
810         {20, -1},
811         {21, -1},
812         {22, -1},
813         {23, -1},
814         {24, -1},
815         {25, -1},
816         {26, -1},
817         {27, -1},
818         {28, -1},
819         {29, -1},
820         {30, -1},
821         {31, -1},
822         {-1, -1}
823 };
825 /**
826  * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
827  * according to the configuration provided
828  * @event: the event number for which mapping is required
829  * @channel: channel being activated
830  * @xbar_event_mapping: array that has the event to channel map
831  *
832  * Events that are routed by default are not mapped. Only events that
833  * are crossbar mapped are routed to available channels according to
834  * the configuration provided
835  *
836  * Returns zero on success, else negative errno.
837  */
838 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
839                         struct event_to_channel_map *xbar_event_mapping)
841         unsigned int ctrl = 0;
842         unsigned int xbar_evt_no = 0;
843         unsigned int val = 0;
844         unsigned int offset = 0;
845         unsigned int mask = 0;
847         ctrl = EDMA_CTLR(event);
848         xbar_evt_no = event - (edma_info[ctrl]->num_channels);
850         if (event < edma_info[ctrl]->num_channels) {
851                 *channel = event;
852         } else if (event < edma_info[ctrl]->num_events) {
853                 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
854                 /* confirm the range */
855                 if (*channel < EDMA_MAX_DMACH)
856                         clear_bit(*channel, edma_info[ctrl]->edma_unused);
857                 mask = (*channel)%4;
858                 offset = (*channel)/4;
859                 offset *= 4;
860                 offset += mask;
861                 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
862                                         AM33XX_SCM_BASE_EDMA + offset));
863                 val = val & (~(0xFF));
864                 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
865                 __raw_writel(val,
866                         AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
867                 return 0;
868         } else {
869                 return -EINVAL;
870         }
872         return 0;
875 static struct edma_soc_info am33xx_edma_info[] = {
876         {
877                 .n_channel              = 64,
878                 .n_region               = 4,
879                 .n_slot                 = 256,
880                 .n_tc                   = 3,
881                 .n_cc                   = 1,
882                 .rsv_chans              = am33xx_dma_rsv_chans,
883                 .rsv_slots              = am33xx_dma_rsv_slots,
884                 .queue_tc_mapping       = am33xx_queue_tc_mapping,
885                 .queue_priority_mapping = am33xx_queue_priority_mapping,
886                 .is_xbar                = 1,
887                 .n_events               = 95,
888                 .xbar_event_mapping     = am33xx_xbar_event_mapping,
889                 .map_xbar_channel       = map_xbar_event_to_channel,
890         },
891 };
893 static struct platform_device am33xx_edma_device = {
894         .name           = "edma",
895         .id             = -1,
896         .dev = {
897                 .platform_data = am33xx_edma_info,
898         },
899         .num_resources  = ARRAY_SIZE(am33xx_edma_resources),
900         .resource       = am33xx_edma_resources,
901 };
903 int __init am33xx_register_edma(void)
905         struct platform_device *pdev;
906         static struct clk *edma_clk;
908         if (cpu_is_am33xx())
909                 pdev = &am33xx_edma_device;
910         else {
911                 pr_err("%s: platform not supported\n", __func__);
912                 return -ENODEV;
913         }
915         edma_clk = clk_get(NULL, "tpcc_ick");
916         if (IS_ERR(edma_clk)) {
917                 printk(KERN_ERR "EDMA: Failed to get clock\n");
918                 return -EBUSY;
919         }
920         clk_enable(edma_clk);
921         edma_clk = clk_get(NULL, "tptc0_ick");
922         if (IS_ERR(edma_clk)) {
923                 printk(KERN_ERR "EDMA: Failed to get clock\n");
924                 return -EBUSY;
925         }
926         clk_enable(edma_clk);
927         edma_clk = clk_get(NULL, "tptc1_ick");
928         if (IS_ERR(edma_clk)) {
929                 printk(KERN_ERR "EDMA: Failed to get clock\n");
930                 return -EBUSY;
931         }
932         clk_enable(edma_clk);
933         edma_clk = clk_get(NULL, "tptc2_ick");
934         if (IS_ERR(edma_clk)) {
935                 printk(KERN_ERR "EDMA: Failed to get clock\n");
936                 return -EBUSY;
937         }
938         clk_enable(edma_clk);
940         return platform_device_register(pdev);
943 #else
944 static inline void am33xx_register_edma(void) {}
945 #endif
947 /*-------------------------------------------------------------------------*/
949 static int __init omap2_init_devices(void)
951         /*
952          * please keep these calls, and their implementations above,
953          * in alphabetical order so they're easier to sort through.
954          */
955         omap_init_audio();
956         omap_init_mcpdm();
957         omap_init_dmic();
958         omap_init_camera();
959         omap_init_mbox();
960         omap_init_mcspi();
961         omap_init_pmu();
962         omap_hdq_init();
963         omap_init_sti();
964         omap_init_sham();
965         omap_init_aes();
966         omap_init_vout();
967         am33xx_cpsw_init();
968         am33xx_register_edma();
970         return 0;
972 arch_initcall(omap2_init_devices);
974 #define AM33XX_CPSW_BASE                (0x4A100000)
975 #define AM33XX_CPSW_MDIO_BASE           (0x4A101000)
976 #define AM33XX_CPSW_SS_BASE             (0x4A101200)
977 #define AM33XX_EMAC_MDIO_FREQ           (1000000)
979 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
980 /* TODO : Verify the offsets */
981 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
982         {
983                 .slave_reg_ofs  = 0x208,
984                 .sliver_reg_ofs = 0xd80,
985                 .phy_id         = "0:00",
986         },
987         {
988                 .slave_reg_ofs  = 0x308,
989                 .sliver_reg_ofs = 0xdc0,
990                 .phy_id         = "0:01",
991         },
992 };
994 static struct cpsw_platform_data am33xx_cpsw_pdata = {
995         .ss_reg_ofs             = 0x1200,
996         .channels               = 8,
997         .cpdma_reg_ofs          = 0x800,
998         .slaves                 = 2,
999         .slave_data             = am33xx_cpsw_slaves,
1000         .ale_reg_ofs            = 0xd00,
1001         .ale_entries            = 1024,
1002         .host_port_reg_ofs      = 0x108,
1003         .hw_stats_reg_ofs       = 0x900,
1004         .bd_ram_ofs             = 0x2000,
1005         .bd_ram_size            = SZ_8K,
1006         .rx_descs               = 64,
1007         .mac_control            = BIT(5), /* MIIEN */
1008         .gigabit_en             = 1,
1009         .host_port_num          = 0,
1010         .no_bd_ram              = false,
1011         .version                = CPSW_VERSION_2,
1012 };
1014 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1015         .bus_freq       = AM33XX_EMAC_MDIO_FREQ,
1016 };
1018 static struct resource am33xx_cpsw_mdioresources[] = {
1019         {
1020                 .start  = AM33XX_CPSW_MDIO_BASE,
1021                 .end    = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1022                 .flags  = IORESOURCE_MEM,
1023         },
1024 };
1026 static struct platform_device am33xx_cpsw_mdiodevice = {
1027         .name           = "davinci_mdio",
1028         .id             = 0,
1029         .num_resources  = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1030         .resource       = am33xx_cpsw_mdioresources,
1031         .dev.platform_data = &am33xx_cpsw_mdiopdata,
1032 };
1034 static struct resource am33xx_cpsw_resources[] = {
1035         {
1036                 .start  = AM33XX_CPSW_BASE,
1037                 .end    = AM33XX_CPSW_BASE + SZ_2K - 1,
1038                 .flags  = IORESOURCE_MEM,
1039         },
1040         {
1041                 .start  = AM33XX_CPSW_SS_BASE,
1042                 .end    = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1043                 .flags  = IORESOURCE_MEM,
1044         },
1045         {
1046                 .start  = AM33XX_IRQ_CPSW_C0_RX,
1047                 .end    = AM33XX_IRQ_CPSW_C0_RX,
1048                 .flags  = IORESOURCE_IRQ,
1049         },
1050         {
1051                 .start  = AM33XX_IRQ_CPSW_RX,
1052                 .end    = AM33XX_IRQ_CPSW_RX,
1053                 .flags  = IORESOURCE_IRQ,
1054         },
1055         {
1056                 .start  = AM33XX_IRQ_CPSW_TX,
1057                 .end    = AM33XX_IRQ_CPSW_TX,
1058                 .flags  = IORESOURCE_IRQ,
1059         },
1060         {
1061                 .start  = AM33XX_IRQ_CPSW_C0,
1062                 .end    = AM33XX_IRQ_CPSW_C0,
1063                 .flags  = IORESOURCE_IRQ,
1064         },
1065 };
1067 static struct platform_device am33xx_cpsw_device = {
1068         .name           =       "cpsw",
1069         .id             =       0,
1070         .num_resources  =       ARRAY_SIZE(am33xx_cpsw_resources),
1071         .resource       =       am33xx_cpsw_resources,
1072         .dev            =       {
1073                                         .platform_data  = &am33xx_cpsw_pdata,
1074                                         .dma_mask       = &am33xx_cpsw_dmamask,
1075                                         .coherent_dma_mask = DMA_BIT_MASK(32),
1076                                 },
1077 };
1079 static unsigned char  am33xx_macid0[ETH_ALEN];
1080 static unsigned char  am33xx_macid1[ETH_ALEN];
1081 static unsigned int   am33xx_evmid;
1083 /*
1084 * am33xx_evmid_fillup - set up board evmid
1085 * @evmid - evm id which needs to be configured
1087 * This function is called to configure board evm id.
1088 * IA Motor Control EVM needs special setting of MAC PHY Id.
1089 * This function is called when IA Motor Control EVM is detected
1090 * during boot-up.
1091 */
1092 void am33xx_evmid_fillup(unsigned int evmid)
1094         am33xx_evmid = evmid;
1095         return;
1098 /*
1099 * am33xx_cpsw_macidfillup - setup mac adrresses
1100 * @eeprommacid0 - mac id 0 which needs to be configured
1101 * @eeprommacid1 - mac id 1 which needs to be configured
1103 * This function is called to configure mac addresses.
1104 * Mac addresses are read from eeprom and this function is called
1105 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1106 * In case, mac address read from eFuse are invalid, mac addresses
1107 * stored in these variable are used.
1108 */
1109 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1111         u32 i;
1113         /* Fillup these mac addresses with the mac adresses from eeprom */
1114         for (i = 0; i < ETH_ALEN; i++) {
1115                 am33xx_macid0[i] = eeprommacid0[i];
1116                 am33xx_macid1[i] = eeprommacid1[i];
1117         }
1119         return;
1122 void am33xx_cpsw_init(void)
1124         u32 mac_lo, mac_hi;
1125         u32 i;
1127         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1128         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1129         am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1130         am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1131         am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1132         am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1133         am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1134         am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1136         /* Read MACID0 from eeprom if eFuse MACID is invalid */
1137         if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1138                 for (i = 0; i < ETH_ALEN; i++)
1139                         am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1140         }
1142         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1143         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1144         am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1145         am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1146         am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1147         am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1148         am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1149         am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1151         /* Read MACID1 from eeprom if eFuse MACID is invalid */
1152         if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1153                 for (i = 0; i < ETH_ALEN; i++)
1154                         am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1155         }
1157         platform_device_register(&am33xx_cpsw_mdiodevice);
1158         platform_device_register(&am33xx_cpsw_device);
1159         clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1160                         NULL, &am33xx_cpsw_device.dev);
1164 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1165 static int __init omap_init_wdt(void)
1167         int id = -1;
1168         struct platform_device *pdev;
1169         struct omap_hwmod *oh;
1170         char *oh_name = "wd_timer2";
1171         char *dev_name = "omap_wdt";
1173         if (!cpu_class_is_omap2())
1174                 return 0;
1176         oh = omap_hwmod_lookup(oh_name);
1177         if (!oh) {
1178                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1179                 return -EINVAL;
1180         }
1182         pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1183         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1184                                 dev_name, oh->name);
1185         return 0;
1187 subsys_initcall(omap_init_wdt);
1188 #endif