aa1f0b1342cc627756ced334c92544dc9a7bb423
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / devices.c
1 /*
2  * linux/arch/arm/mach-omap2/devices.c
3  *
4  * OMAP2 platform device setup/initialization
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 #include <linux/gpio.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
25 #include <mach/hardware.h>
26 #include <mach/irqs.h>
27 #include <mach/board-am335xevm.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/map.h>
30 #include <asm/pmu.h>
32 #ifdef  CONFIG_OMAP3_EDMA
33 #include <mach/edma.h>
34 #endif
36 #include <asm/hardware/asp.h>
38 #include <plat/tc.h>
39 #include <plat/board.h>
40 #include <plat/mcbsp.h>
41 #include <plat/mmc.h>
42 #include <plat/dma.h>
43 #include <plat/omap_hwmod.h>
44 #include <plat/omap_device.h>
45 #include <plat/omap4-keypad.h>
47 /* LCD controller similar DA8xx */
48 #include <video/da8xx-fb.h>
50 #include "mux.h"
51 #include "control.h"
52 #include "devices.h"
54 #define L3_MODULES_MAX_LEN 12
55 #define L3_MODULES 3
57 static int __init omap3_l3_init(void)
58 {
59         int l;
60         struct omap_hwmod *oh;
61         struct platform_device *pdev;
62         char oh_name[L3_MODULES_MAX_LEN];
64         /*
65          * To avoid code running on other OMAPs in
66          * multi-omap builds
67          */
68         if (!(cpu_is_omap34xx()))
69                 return -ENODEV;
71         l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
73         oh = omap_hwmod_lookup(oh_name);
75         if (!oh)
76                 pr_err("could not look up %s\n", oh_name);
78         pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
79                                                            NULL, 0, 0);
81         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
83         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
84 }
85 postcore_initcall(omap3_l3_init);
87 static int __init omap4_l3_init(void)
88 {
89         int l, i;
90         struct omap_hwmod *oh[3];
91         struct platform_device *pdev;
92         char oh_name[L3_MODULES_MAX_LEN];
94         /* If dtb is there, the devices will be created dynamically */
95         if (of_have_populated_dt())
96                 return -ENODEV;
98         /*
99          * To avoid code running on other OMAPs in
100          * multi-omap builds
101          */
102         if (!(cpu_is_omap44xx()))
103                 return -ENODEV;
105         for (i = 0; i < L3_MODULES; i++) {
106                 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
108                 oh[i] = omap_hwmod_lookup(oh_name);
109                 if (!(oh[i]))
110                         pr_err("could not look up %s\n", oh_name);
111         }
113         pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
114                                                      0, NULL, 0, 0);
116         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
118         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
120 postcore_initcall(omap4_l3_init);
122 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
124 static struct resource omap2cam_resources[] = {
125         {
126                 .start          = OMAP24XX_CAMERA_BASE,
127                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
128                 .flags          = IORESOURCE_MEM,
129         },
130         {
131                 .start          = INT_24XX_CAM_IRQ,
132                 .flags          = IORESOURCE_IRQ,
133         }
134 };
136 static struct platform_device omap2cam_device = {
137         .name           = "omap24xxcam",
138         .id             = -1,
139         .num_resources  = ARRAY_SIZE(omap2cam_resources),
140         .resource       = omap2cam_resources,
141 };
142 #endif
143 #define L4_PER_LCDC_PHYS        0x4830E000
145 static struct resource am33xx_lcdc_resources[] = {
146         [0] = { /* registers */
147                 .start  = L4_PER_LCDC_PHYS,
148                 .end    = L4_PER_LCDC_PHYS + SZ_4K - 1,
149                 .flags  = IORESOURCE_MEM,
150         },
151         [1] = { /* interrupt */
152                 .start  = AM33XX_IRQ_LCD,
153                 .end    = AM33XX_IRQ_LCD,
154                 .flags  = IORESOURCE_IRQ,
155         },
156 };
158 static struct platform_device am33xx_lcdc_device = {
159         .name           = "da8xx_lcdc",
160         .id             = 0,
161         .num_resources  = ARRAY_SIZE(am33xx_lcdc_resources),
162         .resource       = am33xx_lcdc_resources,
163 };
165 void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
167         int ret;
169         am33xx_lcdc_device.dev.platform_data = pdata;
171         ret = platform_device_register(&am33xx_lcdc_device);
172         if (ret)
173                 pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n",
174                                 ret);
178 #if defined(CONFIG_SND_AM335X_SOC_EVM) || \
179                                 defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
180 static struct resource am335x_mcasp1_resource[] = {
181         {
182                 .name = "mcasp1",
183                 .start = AM33XX_ASP1_BASE,
184                 .end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
185                 .flags = IORESOURCE_MEM,
186         },
187         /* TX event */
188         {
189                 .start = AM33XX_DMA_MCASP1_X,
190                 .end = AM33XX_DMA_MCASP1_X,
191                 .flags = IORESOURCE_DMA,
192         },
193         /* RX event */
194         {
195                 .start = AM33XX_DMA_MCASP1_R,
196                 .end = AM33XX_DMA_MCASP1_R,
197                 .flags = IORESOURCE_DMA,
198         },
199 };
201 static struct platform_device am335x_mcasp1_device = {
202         .name = "davinci-mcasp",
203         .id = 1,
204         .num_resources = ARRAY_SIZE(am335x_mcasp1_resource),
205         .resource = am335x_mcasp1_resource,
206 };
208 void __init am335x_register_mcasp1(struct snd_platform_data *pdata)
210         am335x_mcasp1_device.dev.platform_data = pdata;
211         platform_device_register(&am335x_mcasp1_device);
214 #else
215 void __init am335x_register_mcasp1(struct snd_platform_data *pdata) {}
216 #endif
218 #if (defined(CONFIG_SND_AM33XX_SOC) || (defined(CONFIG_SND_AM33XX_SOC_MODULE)))
219 struct platform_device am33xx_pcm_device = {
220         .name           = "davinci-pcm-audio",
221         .id             = -1,
222 };
224 static void am33xx_init_pcm(void)
226         platform_device_register(&am33xx_pcm_device);
229 #else
230 static inline void am33xx_init_pcm(void) {}
231 #endif
233 static struct resource omap3isp_resources[] = {
234         {
235                 .start          = OMAP3430_ISP_BASE,
236                 .end            = OMAP3430_ISP_END,
237                 .flags          = IORESOURCE_MEM,
238         },
239         {
240                 .start          = OMAP3430_ISP_CCP2_BASE,
241                 .end            = OMAP3430_ISP_CCP2_END,
242                 .flags          = IORESOURCE_MEM,
243         },
244         {
245                 .start          = OMAP3430_ISP_CCDC_BASE,
246                 .end            = OMAP3430_ISP_CCDC_END,
247                 .flags          = IORESOURCE_MEM,
248         },
249         {
250                 .start          = OMAP3430_ISP_HIST_BASE,
251                 .end            = OMAP3430_ISP_HIST_END,
252                 .flags          = IORESOURCE_MEM,
253         },
254         {
255                 .start          = OMAP3430_ISP_H3A_BASE,
256                 .end            = OMAP3430_ISP_H3A_END,
257                 .flags          = IORESOURCE_MEM,
258         },
259         {
260                 .start          = OMAP3430_ISP_PREV_BASE,
261                 .end            = OMAP3430_ISP_PREV_END,
262                 .flags          = IORESOURCE_MEM,
263         },
264         {
265                 .start          = OMAP3430_ISP_RESZ_BASE,
266                 .end            = OMAP3430_ISP_RESZ_END,
267                 .flags          = IORESOURCE_MEM,
268         },
269         {
270                 .start          = OMAP3430_ISP_SBL_BASE,
271                 .end            = OMAP3430_ISP_SBL_END,
272                 .flags          = IORESOURCE_MEM,
273         },
274         {
275                 .start          = OMAP3430_ISP_CSI2A_REGS1_BASE,
276                 .end            = OMAP3430_ISP_CSI2A_REGS1_END,
277                 .flags          = IORESOURCE_MEM,
278         },
279         {
280                 .start          = OMAP3430_ISP_CSIPHY2_BASE,
281                 .end            = OMAP3430_ISP_CSIPHY2_END,
282                 .flags          = IORESOURCE_MEM,
283         },
284         {
285                 .start          = OMAP3630_ISP_CSI2A_REGS2_BASE,
286                 .end            = OMAP3630_ISP_CSI2A_REGS2_END,
287                 .flags          = IORESOURCE_MEM,
288         },
289         {
290                 .start          = OMAP3630_ISP_CSI2C_REGS1_BASE,
291                 .end            = OMAP3630_ISP_CSI2C_REGS1_END,
292                 .flags          = IORESOURCE_MEM,
293         },
294         {
295                 .start          = OMAP3630_ISP_CSIPHY1_BASE,
296                 .end            = OMAP3630_ISP_CSIPHY1_END,
297                 .flags          = IORESOURCE_MEM,
298         },
299         {
300                 .start          = OMAP3630_ISP_CSI2C_REGS2_BASE,
301                 .end            = OMAP3630_ISP_CSI2C_REGS2_END,
302                 .flags          = IORESOURCE_MEM,
303         },
304         {
305                 .start          = INT_34XX_CAM_IRQ,
306                 .flags          = IORESOURCE_IRQ,
307         }
308 };
310 static struct platform_device omap3isp_device = {
311         .name           = "omap3isp",
312         .id             = -1,
313         .num_resources  = ARRAY_SIZE(omap3isp_resources),
314         .resource       = omap3isp_resources,
315 };
317 int omap3_init_camera(struct isp_platform_data *pdata)
319         omap3isp_device.dev.platform_data = pdata;
320         return platform_device_register(&omap3isp_device);
323 static inline void omap_init_camera(void)
325 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
326         if (cpu_is_omap24xx())
327                 platform_device_register(&omap2cam_device);
328 #endif
331 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
332                         *sdp4430_keypad_data, struct omap_board_data *bdata)
334         struct platform_device *pdev;
335         struct omap_hwmod *oh;
336         struct omap4_keypad_platform_data *keypad_data;
337         unsigned int id = -1;
338         char *oh_name = "kbd";
339         char *name = "omap4-keypad";
341         oh = omap_hwmod_lookup(oh_name);
342         if (!oh) {
343                 pr_err("Could not look up %s\n", oh_name);
344                 return -ENODEV;
345         }
347         keypad_data = sdp4430_keypad_data;
349         pdev = omap_device_build(name, id, oh, keypad_data,
350                         sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
352         if (IS_ERR(pdev)) {
353                 WARN(1, "Can't build omap_device for %s:%s.\n",
354                                                 name, oh->name);
355                 return PTR_ERR(pdev);
356         }
357         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
359         return 0;
362 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
363 static inline void omap_init_mbox(void)
365         struct omap_hwmod *oh;
366         struct platform_device *pdev;
368         oh = omap_hwmod_lookup("mailbox");
369         if (!oh) {
370                 pr_err("%s: unable to find hwmod\n", __func__);
371                 return;
372         }
374         pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
375         WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
376                                                 __func__, PTR_ERR(pdev));
378 #else
379 static inline void omap_init_mbox(void) { }
380 #endif /* CONFIG_OMAP_MBOX_FWK */
382 static inline void omap_init_sti(void) {}
384 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
386 static struct platform_device omap_pcm = {
387         .name   = "omap-pcm-audio",
388         .id     = -1,
389 };
391 /*
392  * OMAP2420 has 2 McBSP ports
393  * OMAP2430 has 5 McBSP ports
394  * OMAP3 has 5 McBSP ports
395  * OMAP4 has 4 McBSP ports
396  */
397 OMAP_MCBSP_PLATFORM_DEVICE(1);
398 OMAP_MCBSP_PLATFORM_DEVICE(2);
399 OMAP_MCBSP_PLATFORM_DEVICE(3);
400 OMAP_MCBSP_PLATFORM_DEVICE(4);
401 OMAP_MCBSP_PLATFORM_DEVICE(5);
403 static void omap_init_audio(void)
405         platform_device_register(&omap_mcbsp1);
406         platform_device_register(&omap_mcbsp2);
407         if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
408                 platform_device_register(&omap_mcbsp3);
409                 platform_device_register(&omap_mcbsp4);
410         }
411         if (cpu_is_omap243x() || cpu_is_omap34xx())
412                 platform_device_register(&omap_mcbsp5);
414         platform_device_register(&omap_pcm);
417 #else
418 static inline void omap_init_audio(void) {}
419 #endif
421 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
422                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
424 static void omap_init_mcpdm(void)
426         struct omap_hwmod *oh;
427         struct platform_device *pdev;
429         oh = omap_hwmod_lookup("mcpdm");
430         if (!oh) {
431                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
432                 return;
433         }
435         pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
436         WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
438 #else
439 static inline void omap_init_mcpdm(void) {}
440 #endif
442 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
443                 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
445 static void omap_init_dmic(void)
447         struct omap_hwmod *oh;
448         struct platform_device *pdev;
450         oh = omap_hwmod_lookup("dmic");
451         if (!oh) {
452                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
453                 return;
454         }
456         pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
457         WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
459 #else
460 static inline void omap_init_dmic(void) {}
461 #endif
463 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
465 #include <plat/mcspi.h>
467 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
469         struct platform_device *pdev;
470         char *name = "omap2_mcspi";
471         struct omap2_mcspi_platform_config *pdata;
472         static int spi_num;
473         struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
475         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
476         if (!pdata) {
477                 pr_err("Memory allocation for McSPI device failed\n");
478                 return -ENOMEM;
479         }
481         pdata->num_cs = mcspi_attrib->num_chipselect;
482         switch (oh->class->rev) {
483         case OMAP2_MCSPI_REV:
484         case OMAP3_MCSPI_REV:
485                         pdata->regs_offset = 0;
486                         break;
487         case OMAP4_MCSPI_REV:
488                         pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
489                         break;
490         default:
491                         pr_err("Invalid McSPI Revision value\n");
492                         return -EINVAL;
493         }
495         spi_num++;
496         pdev = omap_device_build(name, spi_num, oh, pdata,
497                                 sizeof(*pdata), NULL, 0, 0);
498         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
499                                 name, oh->name);
500         kfree(pdata);
501         return 0;
504 static void omap_init_mcspi(void)
506         omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
509 #else
510 static inline void omap_init_mcspi(void) {}
511 #endif
513 #ifdef CONFIG_SOC_OMAPAM33XX
515 static int omap_elm_init(struct omap_hwmod *oh, void *unused)
517         struct platform_device *pdev;
518         char *name = "omap2_elm";
519         static int elm_num;
522         elm_num++;
523         pdev = omap_device_build(name, elm_num, oh, NULL,
524                                 0,      NULL,
525                                 0, 0);
526         return 0;
529 static void omap_init_elm(void)
532         omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL);
535 #else
536 static void omap_init_elm(void) {}
537 #endif
540 static struct resource omap2_pmu_resource = {
541         .start  = 3,
542         .end    = 3,
543         .flags  = IORESOURCE_IRQ,
544 };
546 static struct resource omap3_pmu_resource = {
547         .start  = INT_34XX_BENCH_MPU_EMUL,
548         .end    = INT_34XX_BENCH_MPU_EMUL,
549         .flags  = IORESOURCE_IRQ,
550 };
552 static struct platform_device omap_pmu_device = {
553         .name           = "arm-pmu",
554         .id             = ARM_PMU_DEVICE_CPU,
555         .num_resources  = 1,
556 };
558 static void omap_init_pmu(void)
560         if (cpu_is_omap24xx())
561                 omap_pmu_device.resource = &omap2_pmu_resource;
562         else if (cpu_is_omap34xx())
563                 omap_pmu_device.resource = &omap3_pmu_resource;
564         else
565                 return;
567         platform_device_register(&omap_pmu_device);
571 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
573 #ifdef CONFIG_ARCH_OMAP2
574 static struct resource omap2_sham_resources[] = {
575         {
576                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
577                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
578                 .flags  = IORESOURCE_MEM,
579         },
580         {
581                 .start  = INT_24XX_SHA1MD5,
582                 .flags  = IORESOURCE_IRQ,
583         }
584 };
585 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
586 #else
587 #define omap2_sham_resources            NULL
588 #define omap2_sham_resources_sz         0
589 #endif
591 #ifdef CONFIG_ARCH_OMAP3
592 static struct resource omap3_sham_resources[] = {
593         {
594                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
595                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
596                 .flags  = IORESOURCE_MEM,
597         },
598         {
599                 .start  = INT_34XX_SHA1MD52_IRQ,
600                 .flags  = IORESOURCE_IRQ,
601         },
602         {
603                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
604                 .flags  = IORESOURCE_DMA,
605         }
606 };
607 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
608 #else
609 #define omap3_sham_resources            NULL
610 #define omap3_sham_resources_sz         0
611 #endif
613 static struct platform_device sham_device = {
614         .name           = "omap-sham",
615         .id             = -1,
616 };
618 static void omap_init_sham(void)
620         if (cpu_is_omap24xx()) {
621                 sham_device.resource = omap2_sham_resources;
622                 sham_device.num_resources = omap2_sham_resources_sz;
623         } else if (cpu_is_omap34xx()) {
624                 sham_device.resource = omap3_sham_resources;
625                 sham_device.num_resources = omap3_sham_resources_sz;
626         } else {
627                 pr_err("%s: platform not supported\n", __func__);
628                 return;
629         }
630         platform_device_register(&sham_device);
632 #else
633 static inline void omap_init_sham(void) { }
634 #endif
636 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
638 #ifdef CONFIG_ARCH_OMAP2
639 static struct resource omap2_aes_resources[] = {
640         {
641                 .start  = OMAP24XX_SEC_AES_BASE,
642                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
643                 .flags  = IORESOURCE_MEM,
644         },
645         {
646                 .start  = OMAP24XX_DMA_AES_TX,
647                 .flags  = IORESOURCE_DMA,
648         },
649         {
650                 .start  = OMAP24XX_DMA_AES_RX,
651                 .flags  = IORESOURCE_DMA,
652         }
653 };
654 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
655 #else
656 #define omap2_aes_resources             NULL
657 #define omap2_aes_resources_sz          0
658 #endif
660 #ifdef CONFIG_ARCH_OMAP3
661 static struct resource omap3_aes_resources[] = {
662         {
663                 .start  = OMAP34XX_SEC_AES_BASE,
664                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
665                 .flags  = IORESOURCE_MEM,
666         },
667         {
668                 .start  = OMAP34XX_DMA_AES2_TX,
669                 .flags  = IORESOURCE_DMA,
670         },
671         {
672                 .start  = OMAP34XX_DMA_AES2_RX,
673                 .flags  = IORESOURCE_DMA,
674         }
675 };
676 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
677 #else
678 #define omap3_aes_resources             NULL
679 #define omap3_aes_resources_sz          0
680 #endif
682 static struct platform_device aes_device = {
683         .name           = "omap-aes",
684         .id             = -1,
685 };
687 static void omap_init_aes(void)
689         if (cpu_is_omap24xx()) {
690                 aes_device.resource = omap2_aes_resources;
691                 aes_device.num_resources = omap2_aes_resources_sz;
692         } else if (cpu_is_omap34xx()) {
693                 aes_device.resource = omap3_aes_resources;
694                 aes_device.num_resources = omap3_aes_resources_sz;
695         } else {
696                 pr_err("%s: platform not supported\n", __func__);
697                 return;
698         }
699         platform_device_register(&aes_device);
702 #else
703 static inline void omap_init_aes(void) { }
704 #endif
706 /*-------------------------------------------------------------------------*/
708 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
710 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
711                                                         *mmc_controller)
713         if ((mmc_controller->slots[0].switch_pin > 0) && \
714                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
715                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
716                                         OMAP_PIN_INPUT_PULLUP);
717         if ((mmc_controller->slots[0].gpio_wp > 0) && \
718                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
719                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
720                                         OMAP_PIN_INPUT_PULLUP);
722         omap_mux_init_signal("sdmmc_cmd", 0);
723         omap_mux_init_signal("sdmmc_clki", 0);
724         omap_mux_init_signal("sdmmc_clko", 0);
725         omap_mux_init_signal("sdmmc_dat0", 0);
726         omap_mux_init_signal("sdmmc_dat_dir0", 0);
727         omap_mux_init_signal("sdmmc_cmd_dir", 0);
728         if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
729                 omap_mux_init_signal("sdmmc_dat1", 0);
730                 omap_mux_init_signal("sdmmc_dat2", 0);
731                 omap_mux_init_signal("sdmmc_dat3", 0);
732                 omap_mux_init_signal("sdmmc_dat_dir1", 0);
733                 omap_mux_init_signal("sdmmc_dat_dir2", 0);
734                 omap_mux_init_signal("sdmmc_dat_dir3", 0);
735         }
737         /*
738          * Use internal loop-back in MMC/SDIO Module Input Clock
739          * selection
740          */
741         if (mmc_controller->slots[0].internal_clock) {
742                 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
743                 v |= (1 << 24);
744                 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
745         }
748 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
750         char *name = "mmci-omap";
752         if (!mmc_data[0]) {
753                 pr_err("%s fails: Incomplete platform data\n", __func__);
754                 return;
755         }
757         omap242x_mmc_mux(mmc_data[0]);
758         omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
759                                         INT_24XX_MMC_IRQ, mmc_data[0]);
762 #endif
764 /*-------------------------------------------------------------------------*/
766 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
767 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
768 #define OMAP_HDQ_BASE   0x480B2000
769 #endif
770 static struct resource omap_hdq_resources[] = {
771         {
772                 .start          = OMAP_HDQ_BASE,
773                 .end            = OMAP_HDQ_BASE + 0x1C,
774                 .flags          = IORESOURCE_MEM,
775         },
776         {
777                 .start          = INT_24XX_HDQ_IRQ,
778                 .flags          = IORESOURCE_IRQ,
779         },
780 };
781 static struct platform_device omap_hdq_dev = {
782         .name = "omap_hdq",
783         .id = 0,
784         .dev = {
785                 .platform_data = NULL,
786         },
787         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
788         .resource       = omap_hdq_resources,
789 };
790 static inline void omap_hdq_init(void)
792         (void) platform_device_register(&omap_hdq_dev);
794 #else
795 static inline void omap_hdq_init(void) {}
796 #endif
798 /*---------------------------------------------------------------------------*/
800 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
801         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
802 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
803 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
804 };
805 #else
806 static struct resource omap_vout_resource[2] = {
807 };
808 #endif
810 static struct platform_device omap_vout_device = {
811         .name           = "omap_vout",
812         .num_resources  = ARRAY_SIZE(omap_vout_resource),
813         .resource       = &omap_vout_resource[0],
814         .id             = -1,
815 };
816 static void omap_init_vout(void)
818         if (platform_device_register(&omap_vout_device) < 0)
819                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
821 #else
822 static inline void omap_init_vout(void) {}
823 #endif
825 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
827 #define AM33XX_TPCC_BASE                0x49000000
828 #define AM33XX_TPTC0_BASE               0x49800000
829 #define AM33XX_TPTC1_BASE               0x49900000
830 #define AM33XX_TPTC2_BASE               0x49a00000
832 #define AM33XX_SCM_BASE_EDMA            0x00000f90
834 static struct resource am33xx_edma_resources[] = {
835         {
836                 .name   = "edma_cc0",
837                 .start  = AM33XX_TPCC_BASE,
838                 .end    = AM33XX_TPCC_BASE + SZ_32K - 1,
839                 .flags  = IORESOURCE_MEM,
840         },
841         {
842                 .name   = "edma_tc0",
843                 .start  = AM33XX_TPTC0_BASE,
844                 .end    = AM33XX_TPTC0_BASE + SZ_1K - 1,
845                 .flags  = IORESOURCE_MEM,
846         },
847         {
848                 .name   = "edma_tc1",
849                 .start  = AM33XX_TPTC1_BASE,
850                 .end    = AM33XX_TPTC1_BASE + SZ_1K - 1,
851                 .flags  = IORESOURCE_MEM,
852         },
853         {
854                 .name   = "edma_tc2",
855                 .start  = AM33XX_TPTC2_BASE,
856                 .end    = AM33XX_TPTC2_BASE + SZ_1K - 1,
857                 .flags  = IORESOURCE_MEM,
858         },
859         {
860                 .name   = "edma0",
861                 .start  = AM33XX_IRQ_TPCC0_INT_PO0,
862                 .flags  = IORESOURCE_IRQ,
863         },
864         {
865                 .name   = "edma0_err",
866                 .start  = AM33XX_IRQ_TPCC0_ERRINT_PO,
867                 .flags  = IORESOURCE_IRQ,
868         },
869 };
871 static const s16 am33xx_dma_rsv_chans[][2] = {
872         /* (offset, number) */
873         {0, 2},
874         {14, 2},
875         {26, 6},
876         {48, 4},
877         {56, 8},
878         {-1, -1}
879 };
881 static const s16 am33xx_dma_rsv_slots[][2] = {
882         /* (offset, number) */
883         {0, 2},
884         {14, 2},
885         {26, 6},
886         {48, 4},
887         {56, 8},
888         {64, 127},
889         {-1, -1}
890 };
892 /* Three Transfer Controllers on AM33XX */
893 static const s8 am33xx_queue_tc_mapping[][2] = {
894         /* {event queue no, TC no} */
895         {0, 0},
896         {1, 1},
897         {2, 2},
898         {-1, -1}
899 };
901 static const s8 am33xx_queue_priority_mapping[][2] = {
902         /* {event queue no, Priority} */
903         {0, 0},
904         {1, 1},
905         {2, 2},
906         {-1, -1}
907 };
909 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
910         /* {xbar event no, Channel} */
911         {1, 12},        /* SDTXEVT1 -> MMCHS2 */
912         {2, 13},        /* SDRXEVT1 -> MMCHS2 */
913         {3, -1},
914         {4, -1},
915         {5, -1},
916         {6, -1},
917         {7, -1},
918         {8, -1},
919         {9, -1},
920         {10, -1},
921         {11, -1},
922         {12, -1},
923         {13, -1},
924         {14, -1},
925         {15, -1},
926         {16, -1},
927         {17, -1},
928         {18, -1},
929         {19, -1},
930         {20, -1},
931         {21, -1},
932         {22, -1},
933         {23, -1},
934         {24, -1},
935         {25, -1},
936         {26, -1},
937         {27, -1},
938         {28, -1},
939         {29, -1},
940         {30, -1},
941         {31, -1},
942         {-1, -1}
943 };
945 /**
946  * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
947  * according to the configuration provided
948  * @event: the event number for which mapping is required
949  * @channel: channel being activated
950  * @xbar_event_mapping: array that has the event to channel map
951  *
952  * Events that are routed by default are not mapped. Only events that
953  * are crossbar mapped are routed to available channels according to
954  * the configuration provided
955  *
956  * Returns zero on success, else negative errno.
957  */
958 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
959                         struct event_to_channel_map *xbar_event_mapping)
961         unsigned int ctrl = 0;
962         unsigned int xbar_evt_no = 0;
963         unsigned int val = 0;
964         unsigned int offset = 0;
965         unsigned int mask = 0;
967         ctrl = EDMA_CTLR(event);
968         xbar_evt_no = event - (edma_info[ctrl]->num_channels);
970         if (event < edma_info[ctrl]->num_channels) {
971                 *channel = event;
972         } else if (event < edma_info[ctrl]->num_events) {
973                 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
974                 /* confirm the range */
975                 if (*channel < EDMA_MAX_DMACH)
976                         clear_bit(*channel, edma_info[ctrl]->edma_unused);
977                 mask = (*channel)%4;
978                 offset = (*channel)/4;
979                 offset *= 4;
980                 offset += mask;
981                 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
982                                         AM33XX_SCM_BASE_EDMA + offset));
983                 val = val & (~(0xFF));
984                 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
985                 __raw_writel(val,
986                         AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
987                 return 0;
988         } else {
989                 return -EINVAL;
990         }
992         return 0;
995 static struct edma_soc_info am33xx_edma_info[] = {
996         {
997                 .n_channel              = 64,
998                 .n_region               = 4,
999                 .n_slot                 = 256,
1000                 .n_tc                   = 3,
1001                 .n_cc                   = 1,
1002                 .rsv_chans              = am33xx_dma_rsv_chans,
1003                 .rsv_slots              = am33xx_dma_rsv_slots,
1004                 .queue_tc_mapping       = am33xx_queue_tc_mapping,
1005                 .queue_priority_mapping = am33xx_queue_priority_mapping,
1006                 .is_xbar                = 1,
1007                 .n_events               = 95,
1008                 .xbar_event_mapping     = am33xx_xbar_event_mapping,
1009                 .map_xbar_channel       = map_xbar_event_to_channel,
1010         },
1011 };
1013 static struct platform_device am33xx_edma_device = {
1014         .name           = "edma",
1015         .id             = -1,
1016         .dev = {
1017                 .platform_data = am33xx_edma_info,
1018         },
1019         .num_resources  = ARRAY_SIZE(am33xx_edma_resources),
1020         .resource       = am33xx_edma_resources,
1021 };
1023 int __init am33xx_register_edma(void)
1025         struct platform_device *pdev;
1026         static struct clk *edma_clk;
1028         if (cpu_is_am33xx())
1029                 pdev = &am33xx_edma_device;
1030         else {
1031                 pr_err("%s: platform not supported\n", __func__);
1032                 return -ENODEV;
1033         }
1035         edma_clk = clk_get(NULL, "tpcc_ick");
1036         if (IS_ERR(edma_clk)) {
1037                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1038                 return -EBUSY;
1039         }
1040         clk_enable(edma_clk);
1041         edma_clk = clk_get(NULL, "tptc0_ick");
1042         if (IS_ERR(edma_clk)) {
1043                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1044                 return -EBUSY;
1045         }
1046         clk_enable(edma_clk);
1047         edma_clk = clk_get(NULL, "tptc1_ick");
1048         if (IS_ERR(edma_clk)) {
1049                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1050                 return -EBUSY;
1051         }
1052         clk_enable(edma_clk);
1053         edma_clk = clk_get(NULL, "tptc2_ick");
1054         if (IS_ERR(edma_clk)) {
1055                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1056                 return -EBUSY;
1057         }
1058         clk_enable(edma_clk);
1060         return platform_device_register(pdev);
1063 #else
1064 static inline void am33xx_register_edma(void) {}
1065 #endif
1067 /*-------------------------------------------------------------------------*/
1069 static int __init omap2_init_devices(void)
1071         /*
1072          * please keep these calls, and their implementations above,
1073          * in alphabetical order so they're easier to sort through.
1074          */
1075         omap_init_audio();
1076         omap_init_mcpdm();
1077         omap_init_dmic();
1078         omap_init_camera();
1079         omap_init_mbox();
1080         omap_init_mcspi();
1081         omap_init_elm();
1082         omap_init_pmu();
1083         omap_hdq_init();
1084         omap_init_sti();
1085         omap_init_sham();
1086         omap_init_aes();
1087         omap_init_vout();
1088         am33xx_register_edma();
1089         am33xx_init_pcm();
1091         return 0;
1093 arch_initcall(omap2_init_devices);
1095 #define AM33XX_CPSW_BASE                (0x4A100000)
1096 #define AM33XX_CPSW_MDIO_BASE           (0x4A101000)
1097 #define AM33XX_CPSW_SS_BASE             (0x4A101200)
1098 #define AM33XX_EMAC_MDIO_FREQ           (1000000)
1100 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
1101 /* TODO : Verify the offsets */
1102 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
1103         {
1104                 .slave_reg_ofs  = 0x208,
1105                 .sliver_reg_ofs = 0xd80,
1106                 .phy_id         = "0:00",
1107         },
1108         {
1109                 .slave_reg_ofs  = 0x308,
1110                 .sliver_reg_ofs = 0xdc0,
1111                 .phy_id         = "0:01",
1112         },
1113 };
1115 static struct cpsw_platform_data am33xx_cpsw_pdata = {
1116         .ss_reg_ofs             = 0x1200,
1117         .channels               = 8,
1118         .cpdma_reg_ofs          = 0x800,
1119         .slaves                 = 2,
1120         .slave_data             = am33xx_cpsw_slaves,
1121         .ale_reg_ofs            = 0xd00,
1122         .ale_entries            = 1024,
1123         .host_port_reg_ofs      = 0x108,
1124         .hw_stats_reg_ofs       = 0x900,
1125         .bd_ram_ofs             = 0x2000,
1126         .bd_ram_size            = SZ_8K,
1127         .rx_descs               = 64,
1128         .mac_control            = BIT(5), /* MIIEN */
1129         .gigabit_en             = 1,
1130         .host_port_num          = 0,
1131         .no_bd_ram              = false,
1132         .version                = CPSW_VERSION_2,
1133 };
1135 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1136         .bus_freq       = AM33XX_EMAC_MDIO_FREQ,
1137 };
1139 static struct resource am33xx_cpsw_mdioresources[] = {
1140         {
1141                 .start  = AM33XX_CPSW_MDIO_BASE,
1142                 .end    = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1143                 .flags  = IORESOURCE_MEM,
1144         },
1145 };
1147 static struct platform_device am33xx_cpsw_mdiodevice = {
1148         .name           = "davinci_mdio",
1149         .id             = 0,
1150         .num_resources  = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1151         .resource       = am33xx_cpsw_mdioresources,
1152         .dev.platform_data = &am33xx_cpsw_mdiopdata,
1153 };
1155 static struct resource am33xx_cpsw_resources[] = {
1156         {
1157                 .start  = AM33XX_CPSW_BASE,
1158                 .end    = AM33XX_CPSW_BASE + SZ_2K - 1,
1159                 .flags  = IORESOURCE_MEM,
1160         },
1161         {
1162                 .start  = AM33XX_CPSW_SS_BASE,
1163                 .end    = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1164                 .flags  = IORESOURCE_MEM,
1165         },
1166         {
1167                 .start  = AM33XX_IRQ_CPSW_C0_RX,
1168                 .end    = AM33XX_IRQ_CPSW_C0_RX,
1169                 .flags  = IORESOURCE_IRQ,
1170         },
1171         {
1172                 .start  = AM33XX_IRQ_CPSW_RX,
1173                 .end    = AM33XX_IRQ_CPSW_RX,
1174                 .flags  = IORESOURCE_IRQ,
1175         },
1176         {
1177                 .start  = AM33XX_IRQ_CPSW_TX,
1178                 .end    = AM33XX_IRQ_CPSW_TX,
1179                 .flags  = IORESOURCE_IRQ,
1180         },
1181         {
1182                 .start  = AM33XX_IRQ_CPSW_C0,
1183                 .end    = AM33XX_IRQ_CPSW_C0,
1184                 .flags  = IORESOURCE_IRQ,
1185         },
1186 };
1188 static struct platform_device am33xx_cpsw_device = {
1189         .name           =       "cpsw",
1190         .id             =       0,
1191         .num_resources  =       ARRAY_SIZE(am33xx_cpsw_resources),
1192         .resource       =       am33xx_cpsw_resources,
1193         .dev            =       {
1194                                         .platform_data  = &am33xx_cpsw_pdata,
1195                                         .dma_mask       = &am33xx_cpsw_dmamask,
1196                                         .coherent_dma_mask = DMA_BIT_MASK(32),
1197                                 },
1198 };
1200 static unsigned char  am33xx_macid0[ETH_ALEN];
1201 static unsigned char  am33xx_macid1[ETH_ALEN];
1202 static unsigned int   am33xx_evmid;
1204 /*
1205 * am33xx_evmid_fillup - set up board evmid
1206 * @evmid - evm id which needs to be configured
1208 * This function is called to configure board evm id.
1209 * IA Motor Control EVM needs special setting of MAC PHY Id.
1210 * This function is called when IA Motor Control EVM is detected
1211 * during boot-up.
1212 */
1213 void am33xx_evmid_fillup(unsigned int evmid)
1215         am33xx_evmid = evmid;
1216         return;
1219 /*
1220 * am33xx_cpsw_macidfillup - setup mac adrresses
1221 * @eeprommacid0 - mac id 0 which needs to be configured
1222 * @eeprommacid1 - mac id 1 which needs to be configured
1224 * This function is called to configure mac addresses.
1225 * Mac addresses are read from eeprom and this function is called
1226 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1227 * In case, mac address read from eFuse are invalid, mac addresses
1228 * stored in these variable are used.
1229 */
1230 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1232         u32 i;
1234         /* Fillup these mac addresses with the mac adresses from eeprom */
1235         for (i = 0; i < ETH_ALEN; i++) {
1236                 am33xx_macid0[i] = eeprommacid0[i];
1237                 am33xx_macid1[i] = eeprommacid1[i];
1238         }
1240         return;
1243 void am33xx_cpsw_init(unsigned int gigen)
1245         u32 mac_lo, mac_hi;
1246         u32 i;
1248         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1249         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1250         am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1251         am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1252         am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1253         am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1254         am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1255         am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1257         /* Read MACID0 from eeprom if eFuse MACID is invalid */
1258         if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1259                 for (i = 0; i < ETH_ALEN; i++)
1260                         am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1261         }
1263         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1264         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1265         am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1266         am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1267         am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1268         am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1269         am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1270         am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1272         /* Read MACID1 from eeprom if eFuse MACID is invalid */
1273         if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1274                 for (i = 0; i < ETH_ALEN; i++)
1275                         am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1276         }
1278         if (am33xx_evmid == IND_AUT_MTR_EVM) {
1279                 am33xx_cpsw_slaves[0].phy_id = "0:1e";
1280                 am33xx_cpsw_slaves[1].phy_id = "0:00";
1281         }
1283         am33xx_cpsw_pdata.gigabit_en = gigen;
1285         memcpy(am33xx_cpsw_pdata.mac_addr,
1286                         am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
1287         platform_device_register(&am33xx_cpsw_mdiodevice);
1288         platform_device_register(&am33xx_cpsw_device);
1289         clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1290                         NULL, &am33xx_cpsw_device.dev);
1294 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1295 static int __init omap_init_wdt(void)
1297         int id = -1;
1298         struct platform_device *pdev;
1299         struct omap_hwmod *oh;
1300         char *oh_name = "wd_timer2";
1301         char *dev_name = "omap_wdt";
1303         if (!cpu_class_is_omap2())
1304                 return 0;
1306         oh = omap_hwmod_lookup(oh_name);
1307         if (!oh) {
1308                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1309                 return -EINVAL;
1310         }
1312         pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1313         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1314                                 dev_name, oh->name);
1315         return 0;
1317 subsys_initcall(omap_init_wdt);
1318 #endif